[PATCH] liteeth: LiteX Ethernet device
LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic network device that is commonly used in LiteX designs.
Signed-off-by: Joel Stanley joel@jms.id.au --- include/linux/litex.h | 83 ++++++++++++++++ drivers/net/liteeth.c | 214 ++++++++++++++++++++++++++++++++++++++++++ drivers/net/Kconfig | 5 + drivers/net/Makefile | 1 + 4 files changed, 303 insertions(+) create mode 100644 include/linux/litex.h create mode 100644 drivers/net/liteeth.c
diff --git a/include/linux/litex.h b/include/linux/litex.h new file mode 100644 index 000000000000..f2edb86d5f44 --- /dev/null +++ b/include/linux/litex.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Common LiteX header providing + * helper functions for accessing CSRs. + * + * Copyright (C) 2019-2020 Antmicro <www.antmicro.com> + */ + +#ifndef _LINUX_LITEX_H +#define _LINUX_LITEX_H + +#include <linux/io.h> + +static inline void _write_litex_subregister(u32 val, void __iomem *addr) +{ + writel((u32 __force)cpu_to_le32(val), addr); +} + +static inline u32 _read_litex_subregister(void __iomem *addr) +{ + return le32_to_cpu((__le32 __force)readl(addr)); +} + +/* + * LiteX SoC Generator, depending on the configuration, can split a single + * logical CSR (Control&Status Register) into a series of consecutive physical + * registers. + * + * For example, in the configuration with 8-bit CSR Bus, a 32-bit aligned, + * 32-bit wide logical CSR will be laid out as four 32-bit physical + * subregisters, each one containing one byte of meaningful data. + * + * For Linux support, upstream LiteX enforces a 32-bit wide CSR bus, which + * means that only larger-than-32-bit CSRs will be split across multiple + * subregisters (e.g., a 64-bit CSR will be spread across two consecutive + * 32-bit subregisters). + * + * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus + */ + +static inline void litex_write8(void __iomem *reg, u8 val) +{ + _write_litex_subregister(val, reg); +} + +static inline void litex_write16(void __iomem *reg, u16 val) +{ + _write_litex_subregister(val, reg); +} + +static inline void litex_write32(void __iomem *reg, u32 val) +{ + _write_litex_subregister(val, reg); +} + +static inline void litex_write64(void __iomem *reg, u64 val) +{ + _write_litex_subregister(val >> 32, reg); + _write_litex_subregister(val, reg + 4); +} + +static inline u8 litex_read8(void __iomem *reg) +{ + return _read_litex_subregister(reg); +} + +static inline u16 litex_read16(void __iomem *reg) +{ + return _read_litex_subregister(reg); +} + +static inline u32 litex_read32(void __iomem *reg) +{ + return _read_litex_subregister(reg); +} + +static inline u64 litex_read64(void __iomem *reg) +{ + return ((u64)_read_litex_subregister(reg) << 32) | + _read_litex_subregister(reg + 4); +} + +#endif /* _LINUX_LITEX_H */ diff --git a/drivers/net/liteeth.c b/drivers/net/liteeth.c new file mode 100644 index 000000000000..5da713a9c7a1 --- /dev/null +++ b/drivers/net/liteeth.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * LiteX Liteeth Ethernet + * + * Copyright 2021 Joel Stanley joel@jms.id.au, IBM Corp. + */ + +#include <linux/litex.h> + +#include <dm.h> +#include <dm/device_compat.h> +#include <net.h> + +#define LITEETH_WRITER_SLOT 0x00 +#define LITEETH_WRITER_LENGTH 0x04 +#define LITEETH_WRITER_ERRORS 0x08 +#define LITEETH_WRITER_EV_STATUS 0x0C +#define LITEETH_WRITER_EV_PENDING 0x10 +#define LITEETH_WRITER_EV_ENABLE 0x14 +#define LITEETH_READER_START 0x18 +#define LITEETH_READER_READY 0x1C +#define LITEETH_READER_LEVEL 0x20 +#define LITEETH_READER_SLOT 0x24 +#define LITEETH_READER_LENGTH 0x28 +#define LITEETH_READER_EV_STATUS 0x2C +#define LITEETH_READER_EV_PENDING 0x30 +#define LITEETH_READER_EV_ENABLE 0x34 +#define LITEETH_PREAMBLE_CRC 0x38 +#define LITEETH_PREAMBLE_ERRORS 0x3C +#define LITEETH_CRC_ERRORS 0x40 + +struct liteeth { + struct udevice *dev; + + void __iomem *base; + u32 slot_size; + + /* Tx */ + u32 tx_slot; + u32 num_tx_slots; + void __iomem *tx_base; + + /* Rx */ + u32 rx_slot; + u32 num_rx_slots; + void __iomem *rx_base; +}; + +static int liteeth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct liteeth *priv = dev_get_priv(dev); + u8 rx_slot; + int len; + + if (!litex_read8(priv->base + LITEETH_WRITER_EV_PENDING)) { + debug("liteeth: No packet ready\n"); + return -EPERM; + } + + rx_slot = litex_read8(priv->base + LITEETH_WRITER_SLOT); + len = litex_read32(priv->base + LITEETH_WRITER_LENGTH); + + debug("%s: slot %d len 0x%x\n", __func__, rx_slot, len); + + *packetp = priv->rx_base + rx_slot * priv->slot_size; + + return len; +} + +static int liteeth_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct liteeth *priv = dev_get_priv(dev); + + litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1); + + return 0; +} + +static int liteeth_start(struct udevice *dev) +{ + struct liteeth *priv = dev_get_priv(dev); + + /* Clear pending events */ + litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1); + litex_write8(priv->base + LITEETH_READER_EV_PENDING, 1); + + /* Enable events */ + litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 1); + litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 1); + + return 0; +} + +static void liteeth_stop(struct udevice *dev) +{ + struct liteeth *priv = dev_get_priv(dev); + + litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 0); + litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 0); +} + +static int liteeth_send(struct udevice *dev, void *packet, int len) +{ + struct liteeth *priv = dev_get_priv(dev); + void __iomem *txbuffer; + + if (!litex_read8(priv->base + LITEETH_READER_READY)) { + printf("liteeth: reader not ready\n"); + return -EPERM; + } + + /* Reject oversize packets */ + if (unlikely(len > priv->slot_size)) + return -EPERM; + + txbuffer = priv->tx_base + priv->tx_slot * priv->slot_size; + memcpy_toio(txbuffer, packet, len); + litex_write8(priv->base + LITEETH_READER_SLOT, priv->tx_slot); + litex_write16(priv->base + LITEETH_READER_LENGTH, len); + litex_write8(priv->base + LITEETH_READER_START, 1); + + priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots; + + return 0; +} + +static void liteeth_setup_slots(struct liteeth *priv) +{ + int err; + + err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,rx-slots", &priv->num_rx_slots); + if (err) { + dev_dbg(priv->dev, "unable to get litex,rx-slots, using 2\n"); + priv->num_rx_slots = 2; + } + + err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,tx-slots", &priv->num_tx_slots); + if (err) { + dev_dbg(priv->dev, "unable to get litex,tx-slots, using 2\n"); + priv->num_tx_slots = 2; + } + + err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,slot-size", &priv->slot_size); + if (err) { + dev_dbg(priv->dev, "unable to get litex,slot-size, using 0x800\n"); + priv->slot_size = 0x800; + } +} + +static int liteeth_remove(struct udevice *dev) +{ + liteeth_stop(dev); + + return 0; +} + +static const struct eth_ops liteeth_ops = { + .start = liteeth_start, + .stop = liteeth_stop, + .send = liteeth_send, + .recv = liteeth_recv, + .free_pkt = liteeth_free_pkt, +}; + +static int liteeth_of_to_plat(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct liteeth *priv = dev_get_priv(dev); + void __iomem *buf_base; + + pdata->iobase = dev_read_addr(dev); + + priv->dev = dev; + + priv->base = dev_remap_addr_name(dev, "mac"); + if (!priv->base) { + dev_err(dev, "failed to map registers\n"); + return -EINVAL; + } + + buf_base = dev_remap_addr_name(dev, "buffer"); + if (!buf_base) { + dev_err(dev, "failed to map buffer\n"); + return -EINVAL; + } + + liteeth_setup_slots(priv); + + /* Rx slots */ + priv->rx_base = buf_base; + priv->rx_slot = 0; + + /* Tx slots come after Rx slots */ + priv->tx_base = buf_base + priv->num_rx_slots * priv->slot_size; + priv->tx_slot = 0; + + return 0; +} + +static const struct udevice_id liteeth_ids[] = { + { .compatible = "litex,liteeth" }, + {} +}; + +U_BOOT_DRIVER(liteeth) = { + .name = "liteeth", + .id = UCLASS_ETH, + .of_match = liteeth_ids, + .of_to_plat = liteeth_of_to_plat, + .plat_auto = sizeof(struct eth_pdata), + .remove = liteeth_remove, + .ops = &liteeth_ops, + .priv_auto = sizeof(struct liteeth), +}; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 52dc9e4f0f6d..95420bd4a140 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -460,6 +460,11 @@ config LPC32XX_ETH depends on ARCH_LPC32XX default y
+config LITEETH + bool "LiteX LiteEth Ethernet MAC" + help + Driver for the LiteEth Ethernet MAC from LiteX. + config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 054ec68470db..770107296c62 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_KSZ9477) += ksz9477.o +obj-$(CONFIG_LITEETH) += liteeth.o obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
On Wed, Aug 10, 2022 at 7:30 AM Joel Stanley joel@jms.id.au wrote:
LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic network device that is commonly used in LiteX designs.
Signed-off-by: Joel Stanley joel@jms.id.au
include/linux/litex.h | 83 ++++++++++++++++ drivers/net/liteeth.c | 214 ++++++++++++++++++++++++++++++++++++++++++ drivers/net/Kconfig | 5 + drivers/net/Makefile | 1 + 4 files changed, 303 insertions(+) create mode 100644 include/linux/litex.h create mode 100644 drivers/net/liteeth.c
diff --git a/include/linux/litex.h b/include/linux/litex.h new file mode 100644 index 000000000000..f2edb86d5f44 --- /dev/null +++ b/include/linux/litex.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Common LiteX header providing
- helper functions for accessing CSRs.
- Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
- */
+#ifndef _LINUX_LITEX_H +#define _LINUX_LITEX_H
+#include <linux/io.h>
+static inline void _write_litex_subregister(u32 val, void __iomem *addr) +{
writel((u32 __force)cpu_to_le32(val), addr);+}
+static inline u32 _read_litex_subregister(void __iomem *addr) +{
return le32_to_cpu((__le32 __force)readl(addr));+}
+/*
- LiteX SoC Generator, depending on the configuration, can split a single
- logical CSR (Control&Status Register) into a series of consecutive physical
- registers.
- For example, in the configuration with 8-bit CSR Bus, a 32-bit aligned,
- 32-bit wide logical CSR will be laid out as four 32-bit physical
- subregisters, each one containing one byte of meaningful data.
- For Linux support, upstream LiteX enforces a 32-bit wide CSR bus, which
- means that only larger-than-32-bit CSRs will be split across multiple
- subregisters (e.g., a 64-bit CSR will be spread across two consecutive
- 32-bit subregisters).
- For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
- */
+static inline void litex_write8(void __iomem *reg, u8 val) +{
_write_litex_subregister(val, reg);+}
+static inline void litex_write16(void __iomem *reg, u16 val) +{
_write_litex_subregister(val, reg);+}
+static inline void litex_write32(void __iomem *reg, u32 val) +{
_write_litex_subregister(val, reg);+}
+static inline void litex_write64(void __iomem *reg, u64 val) +{
_write_litex_subregister(val >> 32, reg);_write_litex_subregister(val, reg + 4);+}
+static inline u8 litex_read8(void __iomem *reg) +{
return _read_litex_subregister(reg);+}
+static inline u16 litex_read16(void __iomem *reg) +{
return _read_litex_subregister(reg);+}
+static inline u32 litex_read32(void __iomem *reg) +{
return _read_litex_subregister(reg);+}
+static inline u64 litex_read64(void __iomem *reg) +{
return ((u64)_read_litex_subregister(reg) << 32) |_read_litex_subregister(reg + 4);+}
+#endif /* _LINUX_LITEX_H */ diff --git a/drivers/net/liteeth.c b/drivers/net/liteeth.c new file mode 100644 index 000000000000..5da713a9c7a1 --- /dev/null +++ b/drivers/net/liteeth.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- LiteX Liteeth Ethernet
- Copyright 2021 Joel Stanley joel@jms.id.au, IBM Corp.
- */
+#include <linux/litex.h>
+#include <dm.h> +#include <dm/device_compat.h> +#include <net.h>
+#define LITEETH_WRITER_SLOT 0x00 +#define LITEETH_WRITER_LENGTH 0x04 +#define LITEETH_WRITER_ERRORS 0x08 +#define LITEETH_WRITER_EV_STATUS 0x0C +#define LITEETH_WRITER_EV_PENDING 0x10 +#define LITEETH_WRITER_EV_ENABLE 0x14 +#define LITEETH_READER_START 0x18 +#define LITEETH_READER_READY 0x1C +#define LITEETH_READER_LEVEL 0x20 +#define LITEETH_READER_SLOT 0x24 +#define LITEETH_READER_LENGTH 0x28 +#define LITEETH_READER_EV_STATUS 0x2C +#define LITEETH_READER_EV_PENDING 0x30 +#define LITEETH_READER_EV_ENABLE 0x34 +#define LITEETH_PREAMBLE_CRC 0x38 +#define LITEETH_PREAMBLE_ERRORS 0x3C +#define LITEETH_CRC_ERRORS 0x40
+struct liteeth {
struct udevice *dev;void __iomem *base;u32 slot_size;/* Tx */u32 tx_slot;u32 num_tx_slots;void __iomem *tx_base;/* Rx */u32 rx_slot;u32 num_rx_slots;void __iomem *rx_base;+};
+static int liteeth_recv(struct udevice *dev, int flags, uchar **packetp) +{
struct liteeth *priv = dev_get_priv(dev);u8 rx_slot;int len;if (!litex_read8(priv->base + LITEETH_WRITER_EV_PENDING)) {debug("liteeth: No packet ready\n");return -EPERM;}rx_slot = litex_read8(priv->base + LITEETH_WRITER_SLOT);len = litex_read32(priv->base + LITEETH_WRITER_LENGTH);debug("%s: slot %d len 0x%x\n", __func__, rx_slot, len);*packetp = priv->rx_base + rx_slot * priv->slot_size;return len;+}
+static int liteeth_free_pkt(struct udevice *dev, uchar *packet, int length) +{
struct liteeth *priv = dev_get_priv(dev);litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1);return 0;+}
+static int liteeth_start(struct udevice *dev) +{
struct liteeth *priv = dev_get_priv(dev);/* Clear pending events */litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1);litex_write8(priv->base + LITEETH_READER_EV_PENDING, 1);/* Enable events */litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 1);litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 1);return 0;+}
+static void liteeth_stop(struct udevice *dev) +{
struct liteeth *priv = dev_get_priv(dev);litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 0);litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 0);+}
+static int liteeth_send(struct udevice *dev, void *packet, int len) +{
struct liteeth *priv = dev_get_priv(dev);void __iomem *txbuffer;if (!litex_read8(priv->base + LITEETH_READER_READY)) {printf("liteeth: reader not ready\n");return -EPERM;}/* Reject oversize packets */if (unlikely(len > priv->slot_size))return -EPERM;txbuffer = priv->tx_base + priv->tx_slot * priv->slot_size;memcpy_toio(txbuffer, packet, len);litex_write8(priv->base + LITEETH_READER_SLOT, priv->tx_slot);litex_write16(priv->base + LITEETH_READER_LENGTH, len);litex_write8(priv->base + LITEETH_READER_START, 1);priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots;return 0;+}
+static void liteeth_setup_slots(struct liteeth *priv) +{
int err;err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,rx-slots", &priv->num_rx_slots);if (err) {dev_dbg(priv->dev, "unable to get litex,rx-slots, using 2\n");priv->num_rx_slots = 2;}err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,tx-slots", &priv->num_tx_slots);if (err) {dev_dbg(priv->dev, "unable to get litex,tx-slots, using 2\n");priv->num_tx_slots = 2;}err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,slot-size", &priv->slot_size);if (err) {dev_dbg(priv->dev, "unable to get litex,slot-size, using 0x800\n");priv->slot_size = 0x800;}+}
+static int liteeth_remove(struct udevice *dev) +{
liteeth_stop(dev);return 0;+}
+static const struct eth_ops liteeth_ops = {
.start = liteeth_start,.stop = liteeth_stop,.send = liteeth_send,.recv = liteeth_recv,.free_pkt = liteeth_free_pkt,+};
+static int liteeth_of_to_plat(struct udevice *dev) +{
struct eth_pdata *pdata = dev_get_plat(dev);struct liteeth *priv = dev_get_priv(dev);void __iomem *buf_base;pdata->iobase = dev_read_addr(dev);priv->dev = dev;priv->base = dev_remap_addr_name(dev, "mac");if (!priv->base) {dev_err(dev, "failed to map registers\n");return -EINVAL;}buf_base = dev_remap_addr_name(dev, "buffer");if (!buf_base) {dev_err(dev, "failed to map buffer\n");return -EINVAL;}liteeth_setup_slots(priv);/* Rx slots */priv->rx_base = buf_base;priv->rx_slot = 0;/* Tx slots come after Rx slots */priv->tx_base = buf_base + priv->num_rx_slots * priv->slot_size;priv->tx_slot = 0;return 0;+}
+static const struct udevice_id liteeth_ids[] = {
{ .compatible = "litex,liteeth" },{}+};
+U_BOOT_DRIVER(liteeth) = {
.name = "liteeth",.id = UCLASS_ETH,.of_match = liteeth_ids,.of_to_plat = liteeth_of_to_plat,.plat_auto = sizeof(struct eth_pdata),.remove = liteeth_remove,.ops = &liteeth_ops,.priv_auto = sizeof(struct liteeth),+}; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 52dc9e4f0f6d..95420bd4a140 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -460,6 +460,11 @@ config LPC32XX_ETH depends on ARCH_LPC32XX default y
+config LITEETH
bool "LiteX LiteEth Ethernet MAC"helpDriver for the LiteEth Ethernet MAC from LiteX.config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 054ec68470db..770107296c62 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_KSZ9477) += ksz9477.o +obj-$(CONFIG_LITEETH) += liteeth.o obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o -- 2.35.1
Reviewed-by: Ramon Fried rfried.dev@gmail.com
On 8/10/22 00:29, Joel Stanley wrote:
LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic network device that is commonly used in LiteX designs.
Signed-off-by: Joel Stanley joel@jms.id.au
include/linux/litex.h | 83 ++++++++++++++++ drivers/net/liteeth.c | 214 ++++++++++++++++++++++++++++++++++++++++++ drivers/net/Kconfig | 5 + drivers/net/Makefile | 1 + 4 files changed, 303 insertions(+) create mode 100644 include/linux/litex.h create mode 100644 drivers/net/liteeth.c
diff --git a/include/linux/litex.h b/include/linux/litex.h new file mode 100644 index 000000000000..f2edb86d5f44 --- /dev/null +++ b/include/linux/litex.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Common LiteX header providing
- helper functions for accessing CSRs.
- Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
- */
+#ifndef _LINUX_LITEX_H +#define _LINUX_LITEX_H
+#include <linux/io.h>
+static inline void _write_litex_subregister(u32 val, void __iomem *addr) +{
- writel((u32 __force)cpu_to_le32(val), addr);
+}
+static inline u32 _read_litex_subregister(void __iomem *addr) +{
- return le32_to_cpu((__le32 __force)readl(addr));
+}
+/*
- LiteX SoC Generator, depending on the configuration, can split a single
- logical CSR (Control&Status Register) into a series of consecutive physical
- registers.
- For example, in the configuration with 8-bit CSR Bus, a 32-bit aligned,
- 32-bit wide logical CSR will be laid out as four 32-bit physical
- subregisters, each one containing one byte of meaningful data.
- For Linux support, upstream LiteX enforces a 32-bit wide CSR bus, which
- means that only larger-than-32-bit CSRs will be split across multiple
- subregisters (e.g., a 64-bit CSR will be spread across two consecutive
- 32-bit subregisters).
- For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
- */
+static inline void litex_write8(void __iomem *reg, u8 val) +{
- _write_litex_subregister(val, reg);
+}
+static inline void litex_write16(void __iomem *reg, u16 val) +{
- _write_litex_subregister(val, reg);
+}
+static inline void litex_write32(void __iomem *reg, u32 val) +{
- _write_litex_subregister(val, reg);
+}
+static inline void litex_write64(void __iomem *reg, u64 val) +{
- _write_litex_subregister(val >> 32, reg);
- _write_litex_subregister(val, reg + 4);
+}
+static inline u8 litex_read8(void __iomem *reg) +{
- return _read_litex_subregister(reg);
+}
+static inline u16 litex_read16(void __iomem *reg) +{
- return _read_litex_subregister(reg);
+}
+static inline u32 litex_read32(void __iomem *reg) +{
- return _read_litex_subregister(reg);
+}
+static inline u64 litex_read64(void __iomem *reg) +{
- return ((u64)_read_litex_subregister(reg) << 32) |
_read_litex_subregister(reg + 4);+}
+#endif /* _LINUX_LITEX_H */ diff --git a/drivers/net/liteeth.c b/drivers/net/liteeth.c new file mode 100644 index 000000000000..5da713a9c7a1 --- /dev/null +++ b/drivers/net/liteeth.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- LiteX Liteeth Ethernet
- Copyright 2021 Joel Stanley joel@jms.id.au, IBM Corp.
- */
+#include <linux/litex.h>
+#include <dm.h> +#include <dm/device_compat.h> +#include <net.h>
+#define LITEETH_WRITER_SLOT 0x00 +#define LITEETH_WRITER_LENGTH 0x04 +#define LITEETH_WRITER_ERRORS 0x08 +#define LITEETH_WRITER_EV_STATUS 0x0C +#define LITEETH_WRITER_EV_PENDING 0x10 +#define LITEETH_WRITER_EV_ENABLE 0x14 +#define LITEETH_READER_START 0x18 +#define LITEETH_READER_READY 0x1C +#define LITEETH_READER_LEVEL 0x20 +#define LITEETH_READER_SLOT 0x24 +#define LITEETH_READER_LENGTH 0x28 +#define LITEETH_READER_EV_STATUS 0x2C +#define LITEETH_READER_EV_PENDING 0x30 +#define LITEETH_READER_EV_ENABLE 0x34 +#define LITEETH_PREAMBLE_CRC 0x38 +#define LITEETH_PREAMBLE_ERRORS 0x3C +#define LITEETH_CRC_ERRORS 0x40
+struct liteeth {
- struct udevice *dev;
- void __iomem *base;
- u32 slot_size;
- /* Tx */
- u32 tx_slot;
- u32 num_tx_slots;
- void __iomem *tx_base;
- /* Rx */
- u32 rx_slot;
- u32 num_rx_slots;
- void __iomem *rx_base;
+};
+static int liteeth_recv(struct udevice *dev, int flags, uchar **packetp) +{
- struct liteeth *priv = dev_get_priv(dev);
- u8 rx_slot;
- int len;
- if (!litex_read8(priv->base + LITEETH_WRITER_EV_PENDING)) {
debug("liteeth: No packet ready\n");return -EPERM;
Shouldn't this be -EAGAIN?
- }
- rx_slot = litex_read8(priv->base + LITEETH_WRITER_SLOT);
- len = litex_read32(priv->base + LITEETH_WRITER_LENGTH);
- debug("%s: slot %d len 0x%x\n", __func__, rx_slot, len);
- *packetp = priv->rx_base + rx_slot * priv->slot_size;
- return len;
+}
+static int liteeth_free_pkt(struct udevice *dev, uchar *packet, int length) +{
- struct liteeth *priv = dev_get_priv(dev);
- litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1);
- return 0;
+}
+static int liteeth_start(struct udevice *dev) +{
- struct liteeth *priv = dev_get_priv(dev);
- /* Clear pending events */
- litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1);
- litex_write8(priv->base + LITEETH_READER_EV_PENDING, 1);
- /* Enable events */
- litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 1);
- litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 1);
- return 0;
+}
+static void liteeth_stop(struct udevice *dev) +{
- struct liteeth *priv = dev_get_priv(dev);
- litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 0);
- litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 0);
+}
+static int liteeth_send(struct udevice *dev, void *packet, int len) +{
- struct liteeth *priv = dev_get_priv(dev);
- void __iomem *txbuffer;
- if (!litex_read8(priv->base + LITEETH_READER_READY)) {
printf("liteeth: reader not ready\n");return -EPERM;
ditto, but I guess it doesn't matter here since the return value is thrown away
- }
- /* Reject oversize packets */
- if (unlikely(len > priv->slot_size))
return -EPERM;
I would expect -EMSGSIZE
--Sean
- txbuffer = priv->tx_base + priv->tx_slot * priv->slot_size;
- memcpy_toio(txbuffer, packet, len);
- litex_write8(priv->base + LITEETH_READER_SLOT, priv->tx_slot);
- litex_write16(priv->base + LITEETH_READER_LENGTH, len);
- litex_write8(priv->base + LITEETH_READER_START, 1);
- priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots;
- return 0;
+}
+static void liteeth_setup_slots(struct liteeth *priv) +{
- int err;
- err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,rx-slots", &priv->num_rx_slots);
- if (err) {
dev_dbg(priv->dev, "unable to get litex,rx-slots, using 2\n");priv->num_rx_slots = 2;- }
- err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,tx-slots", &priv->num_tx_slots);
- if (err) {
dev_dbg(priv->dev, "unable to get litex,tx-slots, using 2\n");priv->num_tx_slots = 2;- }
- err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,slot-size", &priv->slot_size);
- if (err) {
dev_dbg(priv->dev, "unable to get litex,slot-size, using 0x800\n");priv->slot_size = 0x800;- }
+}
+static int liteeth_remove(struct udevice *dev) +{
- liteeth_stop(dev);
- return 0;
+}
+static const struct eth_ops liteeth_ops = {
- .start = liteeth_start,
- .stop = liteeth_stop,
- .send = liteeth_send,
- .recv = liteeth_recv,
- .free_pkt = liteeth_free_pkt,
+};
+static int liteeth_of_to_plat(struct udevice *dev) +{
- struct eth_pdata *pdata = dev_get_plat(dev);
- struct liteeth *priv = dev_get_priv(dev);
- void __iomem *buf_base;
- pdata->iobase = dev_read_addr(dev);
- priv->dev = dev;
- priv->base = dev_remap_addr_name(dev, "mac");
- if (!priv->base) {
dev_err(dev, "failed to map registers\n");return -EINVAL;- }
- buf_base = dev_remap_addr_name(dev, "buffer");
- if (!buf_base) {
dev_err(dev, "failed to map buffer\n");return -EINVAL;- }
- liteeth_setup_slots(priv);
- /* Rx slots */
- priv->rx_base = buf_base;
- priv->rx_slot = 0;
- /* Tx slots come after Rx slots */
- priv->tx_base = buf_base + priv->num_rx_slots * priv->slot_size;
- priv->tx_slot = 0;
- return 0;
+}
+static const struct udevice_id liteeth_ids[] = {
- { .compatible = "litex,liteeth" },
- {}
+};
+U_BOOT_DRIVER(liteeth) = {
- .name = "liteeth",
- .id = UCLASS_ETH,
- .of_match = liteeth_ids,
- .of_to_plat = liteeth_of_to_plat,
- .plat_auto = sizeof(struct eth_pdata),
- .remove = liteeth_remove,
- .ops = &liteeth_ops,
- .priv_auto = sizeof(struct liteeth),
+}; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 52dc9e4f0f6d..95420bd4a140 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -460,6 +460,11 @@ config LPC32XX_ETH depends on ARCH_LPC32XX default y
+config LITEETH
- bool "LiteX LiteEth Ethernet MAC"
- help
Driver for the LiteEth Ethernet MAC from LiteX.- config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X
diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 054ec68470db..770107296c62 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_KSZ9477) += ksz9477.o +obj-$(CONFIG_LITEETH) += liteeth.o obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
On Sun, 18 Sept 2022 at 15:50, Sean Anderson seanga2@gmail.com wrote:
On 8/10/22 00:29, Joel Stanley wrote:
LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic network device that is commonly used in LiteX designs.
+static int liteeth_recv(struct udevice *dev, int flags, uchar **packetp) +{
struct liteeth *priv = dev_get_priv(dev);u8 rx_slot;int len;if (!litex_read8(priv->base + LITEETH_WRITER_EV_PENDING)) {debug("liteeth: No packet ready\n");return -EPERM;Shouldn't this be -EAGAIN?
Your suggestion makes more sense. I think I copied another driver with these return codes, perhaps ftgmac100.
I'll respin with EAGAIN and EMSGSIZE.
Cheers,
Joel
participants (3)
-
Joel Stanley -
Ramon Fried -
Sean Anderson