[U-Boot] [PATCH 1/2] mtd: spi: Add SYS_SPI_BLOCK_SIZE to Kconfig

From: Tien Fong Chee tien.fong.chee@intel.com
Different SPI flash has different block erase size configuration, it can be configured as block erase size or sub-block erase size, so SYS_SPI_BLOCK_SIZE is created to provide UBI a consistent block reading. UBI block reading would be eventually translated to offset access into SPI regardless how the block erase size is configured on SPI. This would made the UBI transparent from SPI layer.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com --- drivers/mtd/spi/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index d3b007a731..ea3779c521 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -196,4 +196,11 @@ config SPI_FLASH_MTD
If unsure, say N
+config SYS_SPI_BLOCK_SIZE + hex "SPI chip eraseblock size for UBI reading" + depends on SPL_SPI_FLASH_SUPPORT + default 65536 + help + Number of data bytes in a physical eraseblock for UBI reading. + endmenu # menu "SPI Flash Support"

From: Tien Fong Chee tien.fong.chee@intel.com
Adding UBI support for SPI flash.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com --- common/spl/spl_ubi.c | 11 ++++++++++- drivers/mtd/spi/sf-uclass.c | 30 ++++++++++++++++++++++++++++++ include/spi_flash.h | 10 ++++++++++ 3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c index 0cb5080882..40a449b42b 100644 --- a/common/spl/spl_ubi.c +++ b/common/spl/spl_ubi.c @@ -9,6 +9,8 @@ #include <nand.h> #include <onenand_uboot.h> #include <ubispl.h> +#include <spi.h> +#include <spi_flash.h> #include <spl.h>
int spl_ubi_load_image(struct spl_image_info *spl_image, @@ -33,6 +35,12 @@ int spl_ubi_load_image(struct spl_image_info *spl_image, info.peb_size = CONFIG_SYS_ONENAND_BLOCK_SIZE; break; #endif +#ifdef CONFIG_SPL_SPI_FLASH_SUPPORT + case BOOT_DEVICE_SPI: + info.read = spi_flash_read_block; + info.peb_size = CONFIG_SYS_SPI_BLOCK_SIZE; + break; +#endif default: goto out; } @@ -82,6 +90,7 @@ out: #endif return ret; } -/* Use priorty 0 so that Ubi will override NAND and ONENAND methods */ +/* Use priorty 0 so that Ubi will override SPI, NAND and ONENAND methods */ +SPL_LOAD_IMAGE_METHOD("SPI", 0, BOOT_DEVICE_SPI, spl_ubi_load_image); SPL_LOAD_IMAGE_METHOD("NAND", 0, BOOT_DEVICE_NAND, spl_ubi_load_image); SPL_LOAD_IMAGE_METHOD("OneNAND", 0, BOOT_DEVICE_ONENAND, spl_ubi_load_image); diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index 719a2fd23a..45b6dd9e52 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -12,6 +12,36 @@
DECLARE_GLOBAL_DATA_PTR;
+/** + * spi_flash_read_block - Read data from physical eraseblock into a buffer + * @block: Number of the physical eraseblock + * @offset: Data offset from the start of @peb + * @len: Data size to read + * @buf: Address of the destination buffer + * @return 0 if OK, -ve on error + */ +int spi_flash_read_block(int block, int offset, int len, void *buf) +{ + struct udevice *dev; + + int ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS, + CONFIG_SF_DEFAULT_SPEED, + CONFIG_SF_DEFAULT_MODE, &dev); + if (ret) { + printf("Failed to initialize SPI flash at "); + printf("%u:%u (error %d)\n",CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS, ret); + return ret; + } + + dev_get_uclass_priv(dev); + + return log_ret(sf_get_ops(dev)->read(dev, + CONFIG_SYS_SPI_BLOCK_SIZE * + block + offset, len, buf)); +} + int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len, void *buf) { return log_ret(sf_get_ops(dev)->read(dev, offset, len, buf)); diff --git a/include/spi_flash.h b/include/spi_flash.h index 55b4721813..f6eefdc5c8 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -102,6 +102,16 @@ int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len); */ int spl_flash_get_sw_write_prot(struct udevice *dev);
+/** + * spi_flash_read_block - Read data from physical eraseblock into a buffer + * @block: Number of the physical eraseblock + * @offset: Data offset from the start of @peb + * @len: Data size to read + * @buf: Address of the destination buffer + * @return 0 if OK, -ve on error + */ +int spi_flash_read_block(int block, int offset, int len, void *dst); + int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, unsigned int max_hz, unsigned int spi_mode, struct udevice **devp);

On Mon, 2019-07-29 at 15:48 +0800, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
Adding UBI support for SPI flash.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
common/spl/spl_ubi.c | 11 ++++++++++- drivers/mtd/spi/sf-uclass.c | 30 ++++++++++++++++++++++++++++++ include/spi_flash.h | 10 ++++++++++ 3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c index 0cb5080882..40a449b42b 100644 --- a/common/spl/spl_ubi.c +++ b/common/spl/spl_ubi.c
[...]
Any comment?
THanks.

On Mon, 2019-07-29 at 15:48 +0800, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
Different SPI flash has different block erase size configuration, it can be configured as block erase size or sub-block erase size, so SYS_SPI_BLOCK_SIZE is created to provide UBI a consistent block reading. UBI block reading would be eventually translated to offset access into SPI regardless how the block erase size is configured on SPI. This would made the UBI transparent from SPI layer.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
drivers/mtd/spi/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index d3b007a731..ea3779c521 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -196,4 +196,11 @@ config SPI_FLASH_MTD If unsure, say N +config SYS_SPI_BLOCK_SIZE
- hex "SPI chip eraseblock size for UBI reading"
- depends on SPL_SPI_FLASH_SUPPORT
- default 65536
- help
- Number of data bytes in a physical eraseblock for UBI
reading.
endmenu # menu "SPI Flash Support"
Any comment?
Thanks.

On 8/22/19 9:40 AM, Chee, Tien Fong wrote:
On Mon, 2019-07-29 at 15:48 +0800, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
Different SPI flash has different block erase size configuration, it can be configured as block erase size or sub-block erase size, so SYS_SPI_BLOCK_SIZE is created to provide UBI a consistent block reading. UBI block reading would be eventually translated to offset access into SPI regardless how the block erase size is configured on SPI. This would made the UBI transparent from SPI layer.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
drivers/mtd/spi/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index d3b007a731..ea3779c521 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -196,4 +196,11 @@ config SPI_FLASH_MTD If unsure, say N +config SYS_SPI_BLOCK_SIZE
- hex "SPI chip eraseblock size for UBI reading"
- depends on SPL_SPI_FLASH_SUPPORT
- default 65536
- help
- Number of data bytes in a physical eraseblock for UBI
reading.
endmenu # menu "SPI Flash Support"
Any comment?
UBI is able to obtain underlying media erase block size from the MTD subsystem, just let it do that. Besides, any such compile-time config would fail the next time you change the SPI NOR (e.g. because it's EOL), as that would force you to rebuild U-Boot, which might ultimately not be possible.

On Thu, 2019-08-22 at 09:54 +0200, Marek Vasut wrote:
On 8/22/19 9:40 AM, Chee, Tien Fong wrote:
On Mon, 2019-07-29 at 15:48 +0800, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
Different SPI flash has different block erase size configuration, it can be configured as block erase size or sub-block erase size, so SYS_SPI_BLOCK_SIZE is created to provide UBI a consistent block reading. UBI block reading would be eventually translated to offset access into SPI regardless how the block erase size is configured on SPI. This would made the UBI transparent from SPI layer.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
drivers/mtd/spi/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index d3b007a731..ea3779c521 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -196,4 +196,11 @@ config SPI_FLASH_MTD If unsure, say N +config SYS_SPI_BLOCK_SIZE
- hex "SPI chip eraseblock size for UBI reading"
- depends on SPL_SPI_FLASH_SUPPORT
- default 65536
- help
- Number of data bytes in a physical eraseblock for UBI
reading.
endmenu # menu "SPI Flash Support"
Any comment?
UBI is able to obtain underlying media erase block size from the MTD subsystem, just let it do that. Besides, any such compile-time config would fail the next time you change the SPI NOR (e.g. because it's EOL), as that would force you to rebuild U-Boot, which might ultimately not be possible.
Okay, let me check how to get this info from MTD. If you have some ideas, you can let me know too :) .

On 8/23/19 5:29 AM, Chee, Tien Fong wrote:
On Thu, 2019-08-22 at 09:54 +0200, Marek Vasut wrote:
On 8/22/19 9:40 AM, Chee, Tien Fong wrote:
On Mon, 2019-07-29 at 15:48 +0800, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
Different SPI flash has different block erase size configuration, it can be configured as block erase size or sub-block erase size, so SYS_SPI_BLOCK_SIZE is created to provide UBI a consistent block reading. UBI block reading would be eventually translated to offset access into SPI regardless how the block erase size is configured on SPI. This would made the UBI transparent from SPI layer.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
drivers/mtd/spi/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index d3b007a731..ea3779c521 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -196,4 +196,11 @@ config SPI_FLASH_MTD If unsure, say N +config SYS_SPI_BLOCK_SIZE
- hex "SPI chip eraseblock size for UBI reading"
- depends on SPL_SPI_FLASH_SUPPORT
- default 65536
- help
- Number of data bytes in a physical eraseblock for UBI
reading.
endmenu # menu "SPI Flash Support"
Any comment?
UBI is able to obtain underlying media erase block size from the MTD subsystem, just let it do that. Besides, any such compile-time config would fail the next time you change the SPI NOR (e.g. because it's EOL), as that would force you to rebuild U-Boot, which might ultimately not be possible.
Okay, let me check how to get this info from MTD. If you have some ideas, you can let me know too :) .
It should all be there already, since you can already attach UBI on SPI NOR from U-Boot.
participants (3)
-
Chee, Tien Fong
-
Marek Vasut
-
tien.fong.chee@intel.com