[U-Boot] [PATCH v6 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox
From: Fabio Estevam fabio.estevam@freescale.com
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com Acked-by: Stefan Roese sr@denx.de --- Changes since v5: - Add Stefan's Ack Changes since v4: - None
drivers/net/fec_mxc.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4cefda4..56178d4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR; */ #define FEC_XFER_TIMEOUT 5000
+/* + * The standard 32-byte DMA alignment does not work on mx6solox, which requires + * 64-byte alignment in the DMA RX FEC buffer. + * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also + * satisfies the alignment on other SoCs (32-bytes) + */ +#define FEC_DMA_RX_MINALIGN 64 + #ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif @@ -286,7 +294,7 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) * Reload the RX descriptors with default values and wipe * the RX buffers. */ - size = roundup(dsize, ARCH_DMA_MINALIGN); + size = roundup(dsize, FEC_DMA_RX_MINALIGN); for (i = 0; i < count; i++) { data = (uint8_t *)fec->rbd_base[i].data_pointer; memset(data, 0, dsize); @@ -881,9 +889,9 @@ static int fec_alloc_descs(struct fec_priv *fec) /* Allocate RX buffers. */
/* Maximum RX buffer size. */ - size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN); + size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); for (i = 0; i < FEC_RBD_NUM; i++) { - data = memalign(ARCH_DMA_MINALIGN, size); + data = memalign(FEC_DMA_RX_MINALIGN, size); if (!data) { printf("%s: error allocating rxbuf %d\n", __func__, i); goto err_ring;
From: Fabio Estevam fabio.estevam@freescale.com
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail.
As explained by Ye Li:
"The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version."
Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs.
No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- Changes since v5: - Put explanation why we need to poll READY bit after TDAR into the code
drivers/net/fec_mxc.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 6afc827..bdd8108 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -719,13 +719,36 @@ static int fec_send(struct eth_device *dev, void *packet, int length) break; }
- if (!timeout) + if (!timeout) { ret = -EINVAL; + goto out; + }
- invalidate_dcache_range(addr, addr + size); - if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) + /* + * The TDAR bit is cleared when the descriptors are all out from TX + * but on mx6solox we noticed that the READY bit is still not cleared + * right after TDAR. + * These are two distinct signals, and in IC simulation, we found that + * TDAR always gets cleared prior than the READY bit of last BD becomes + * cleared. + * In mx6solox, we use a later version of FEC IP. It looks like that + * this intrinsic behaviour of TDAR bit has changed in this newer FEC + * version. + * + * Fix this by polling the READY bit of BD after the TDAR polling, + * which covers the mx6solox case and does not harm the other SoCs. + */ + timeout = FEC_XFER_TIMEOUT; + while (--timeout) { + invalidate_dcache_range(addr, addr + size); + if (!(readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)) + break; + } + + if (!timeout) ret = -EINVAL;
+out: debug("fec_send: status 0x%x index %d ret %i\n", readw(&fec->tbd_base[fec->tbd_index].status), fec->tbd_index, ret);
On Saturday, August 23, 2014 at 02:41:50 PM, Fabio Estevam wrote:
From: Fabio Estevam fabio.estevam@freescale.com
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com Acked-by: Stefan Roese sr@denx.de
Changes since v5:
- Add Stefan's Ack
Changes since v4:
- None
drivers/net/fec_mxc.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4cefda4..56178d4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR; */ #define FEC_XFER_TIMEOUT 5000
+/*
- The standard 32-byte DMA alignment does not work on mx6solox, which
requires + * 64-byte alignment in the DMA RX FEC buffer.
- Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and
also + * satisfies the alignment on other SoCs (32-bytes)
- */
+#define FEC_DMA_RX_MINALIGN 64
#ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif @@ -286,7 +294,7 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) * Reload the RX descriptors with default values and wipe * the RX buffers. */
- size = roundup(dsize, ARCH_DMA_MINALIGN);
- size = roundup(dsize, FEC_DMA_RX_MINALIGN);
This $size here is used only by the cache flushing functions. We agreed in the previous iterations, that the cacheline is 32b on MX6SX . This change is pointless unless ARCH_DMA_MINALIGN != 32 on MX6SX. Is that right ? [...]
Best regards, Marek Vasut
On Mon, Aug 25, 2014 at 5:02 AM, Marek Vasut marex@denx.de wrote:
This $size here is used only by the cache flushing functions. We agreed in the previous iterations, that the cacheline is 32b on MX6SX . This change is pointless unless ARCH_DMA_MINALIGN != 32 on MX6SX. Is that right ?
Yes, you are right. The cacheline on mx6sx is 32 bytes. It is only the RX buffers that need 64-bytes alignment.
Will fix this in v7.
Thanks
participants (2)
-
Fabio Estevam -
Marek Vasut