Since there are lots of difference between kirkwood and armada series, it is better to seperate them but still keep the most common file shared by all marvell platform in the mv-common configure file.

This patch move the kirkwood only driver definitoin in mv-common to the <soc_name>/config.h.

This patch is tested with compilation for armada100 and guruplug.

Signed-off-by: Lei Wen leiwen@marvell.com --- arch/arm/include/asm/arch-armada100/config.h | 50 +++++++++ arch/arm/include/asm/arch-kirkwood/config.h | 145 +++++++++++++++++++++++++ include/configs/aspenite.h | 1 + include/configs/mv-common.h | 147 ++++---------------------- 4 files changed, 217 insertions(+), 126 deletions(-) create mode 100644 arch/arm/include/asm/arch-armada100/config.h create mode 100644 arch/arm/include/asm/arch-kirkwood/config.h

diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h new file mode 100644 index 0000000..02d72b4 --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/config.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2011 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Lei Wen leiwen@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * This file should be included in board config header file. + * + * It supports common definitions for Armada100 platform + */ + +#ifndef _ARMD1_CONFIG_H +#define _ARMD1_CONFIG_H + +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ + +#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ +#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ +#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ +#define MV_MFPR_BASE ARMD1_MFPR_BASE +#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE +#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register + represents UART Unit Enable */ +/* + * There is no internal RAM in ARMADA100, using DRAM + * TBD: dcache to be used for this + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) +#define CONFIG_NR_DRAM_BANKS_MAX 2 + +#endif /* _ARMD1_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h new file mode 100644 index 0000000..71ba464 --- /dev/null +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2011 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Lei Wen leiwen@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * This file should be included in board config header file. + * + * It supports common definitions for Kirkwood platform + */ + +#ifndef _KW_CONFIG_H +#define _KW_CONFIG_H + +#if defined (CONFIG_KW88F6281) +#include <asm/arch/kw88f6281.h> +#elif defined (CONFIG_KW88F6192) +#include <asm/arch/kw88f6192.h> +#else +#error "SOC Name not defined" +#endif /* CONFIG_KW88F6281 */ + +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ + +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ +#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ + +/* + * By default kwbimage.cfg from board specific folder is used + * If for some board, different configuration file need to be used, + * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file + */ +#ifndef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg +#endif /* CONFIG_SYS_KWD_CONFIG */ + +/* Kirkwood has 2k of Security SRAM, use it for SP */ +#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 +#define CONFIG_NR_DRAM_BANKS_MAX 2 + +#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE +#define MV_UART_CONSOLE_BASE KW_UART0_BASE +#define MV_SATA_BASE KW_SATA_BASE +#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET +#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET + +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_KIRKWOOD +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ +#define NAND_ALLOW_ERASE_ALL 1 +#endif + +/* + * SPI Flash configuration + */ +#ifdef CONFIG_CMD_SF +#define CONFIG_HARD_SPI 1 +#define CONFIG_KIRKWOOD_SPI 1 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */ +#endif + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI_KIRKWOOD +#define CONFIG_EHCI_IS_TDI +#endif /* CONFIG_CMD_USB */ + +/* + * IDE Support on SATA ports + */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_CMD_EXT2 +#define CONFIG_MVSATA_IDE +#define CONFIG_IDE_PREINIT +#define CONFIG_MVSATA_IDE_USE_PORT1 +/* Needs byte-swapping for ATA data register */ +#define CONFIG_IDE_SWAP_IO +/* Data, registers and alternate blocks are at the same offset */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) +#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) +#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) +/* Each 8-bit ATA register is aligned to a 4-bytes address */ +#define CONFIG_SYS_ATA_STRIDE 4 +/* Controller supports 48-bits LBA addressing */ +#define CONFIG_LBA48 +/* CONFIG_CMD_IDE requires some #defines for ATA registers */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 2 +/* ATA registers base is at SATA controller base */ +#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE +#endif /* CONFIG_CMD_IDE */ + +/* + * I2C related stuff + */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_I2C_MVTWSI +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#endif /* _KW_CONFIG_H */ diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h index 706365f..48706cb 100644 --- a/include/configs/aspenite.h +++ b/include/configs/aspenite.h @@ -53,6 +53,7 @@ * to enable certain macros */ #include "mv-common.h" +#undef CONFIG_ARCH_MISC_INIT

/* * Environment variables configurations diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 97b6971..6a6a321 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -33,58 +33,13 @@ #ifndef _MV_COMMON_H #define _MV_COMMON_H

+/* ====> Include platform Common Definations */ +#include <asm/arch/config.h> + /* * High Level Configuration Options (easy to change) */ #define CONFIG_MARVELL 1 -#define CONFIG_ARM926EJS 1 /* Basic Architecture */ - -/* ====> Kirkwood Platform Common Definations */ -#if defined(CONFIG_KIRKWOOD) -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ - -/* - * By default kwbimage.cfg from board specific folder is used - * If for some board, different configuration file need to be used, - * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file - */ -#ifndef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg -#endif /* CONFIG_SYS_KWD_CONFIG */ - -/* Kirkwood has 2k of Security SRAM, use it for SP */ -#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 -#define CONFIG_NR_DRAM_BANKS_MAX 2 - -#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE -#define MV_UART_CONSOLE_BASE KW_UART0_BASE -#define MV_SATA_BASE KW_SATA_BASE -#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET -#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET - -/* ====> ARMADA100 Platform Common Definations */ -#elif defined (CONFIG_ARMADA100) - -#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ -#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ -#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ -#define MV_MFPR_BASE ARMD1_MFPR_BASE -#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE -#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register - represents UART Unit Enable */ -/* - * There is no internal RAM in ARMADA100, using DRAM - * TBD: dcache to be used for this - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) -#define CONFIG_NR_DRAM_BANKS_MAX 2 - -#else -#error "Unsupported SoC Platform..." -#endif

/* * Custom CONFIG_SYS_TEXT_BASE can be done in <board>.h @@ -138,31 +93,6 @@ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */

/* - * NAND configuration - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ -#define NAND_ALLOW_ERASE_ALL 1 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ -#endif - -/* - * SPI Flash configuration - */ -#ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH 1 -#define CONFIG_HARD_SPI 1 -#define CONFIG_KIRKWOOD_SPI 1 -#define CONFIG_SPI_FLASH_MACRONIX 1 -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */ -#endif - -/* * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */ @@ -176,9 +106,7 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ -#ifndef CONFIG_ARMADA100 /* will be removed latter */ #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#endif /* CONFIG_ARMADA100 */ #define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */ #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ #define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ @@ -199,27 +127,29 @@ #endif #endif /* CONFIG_NR_DRAM_BANKS */

+/* ====> Include driver Common Definations */ /* - * Ethernet Driver configuration + * Common NAND configuration */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ -#endif /* CONFIG_CMD_NET */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* + * Common SPI Flash configuration + */ +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH 1 +#define CONFIG_SPI_FLASH_MACRONIX 1 +#endif

/* - * USB/EHCI + * Common USB/EHCI configuration */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_KIRKWOOD -#define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION #define CONFIG_ISO_PARTITION @@ -227,44 +157,9 @@ #endif /* CONFIG_CMD_USB */

/* - * IDE Support on SATA ports - */ -#ifdef CONFIG_CMD_IDE -#define __io -#define CONFIG_CMD_EXT2 -#define CONFIG_MVSATA_IDE -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT1 -/* Needs byte-swapping for ATA data register */ -#define CONFIG_IDE_SWAP_IO -/* Data, registers and alternate blocks are at the same offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) -#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) -#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) -/* Each 8-bit ATA register is aligned to a 4-bytes address */ -#define CONFIG_SYS_ATA_STRIDE 4 -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 -/* CONFIG_CMD_IDE requires some #defines for ATA registers */ -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE 2 -/* ATA registers base is at SATA controller base */ -#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE -#endif /* CONFIG_CMD_IDE */ - -/* - * I2C related stuff - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MVTWSI -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - -/* * File system */ -#ifndef CONFIG_ARMADA100 /* will be removed latter */ +#ifdef CONFIG_SYS_MVFS #define CONFIG_CMD_EXT2 #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_FAT @@ -275,6 +170,6 @@ #define CONFIG_MTD_PARTITIONS #define CONFIG_CMD_MTDPARTS #define CONFIG_LZO -#endif /* CONFIG_ARMADA100 */ +#endif

#endif /* _MV_COMMON_H */

Pantheon Family processors are highly integrated SoCs based on Sheeva_88SV331x-v5 PJ1 cpu core. Ref: http://www.marvell.com/products/processors/communications/marvell_pantheon_9...

SoC versions Supported: 1) PANTHEON920 (TD) 2) PANTHEON910 (TTC)

Signed-off-by: Lei Wen leiwen@marvell.com --- arch/arm/cpu/arm926ejs/pantheon/Makefile | 46 ++++++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 78 ++++++++++ arch/arm/cpu/arm926ejs/pantheon/dram.c | 130 ++++++++++++++++ arch/arm/cpu/arm926ejs/pantheon/timer.c | 204 +++++++++++++++++++++++++ arch/arm/include/asm/arch-pantheon/config.h | 44 ++++++ arch/arm/include/asm/arch-pantheon/cpu.h | 79 ++++++++++ arch/arm/include/asm/arch-pantheon/pantheon.h | 54 +++++++ 7 files changed, 635 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/pantheon/Makefile create mode 100644 arch/arm/cpu/arm926ejs/pantheon/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/pantheon/dram.c create mode 100644 arch/arm/cpu/arm926ejs/pantheon/timer.c create mode 100644 arch/arm/include/asm/arch-pantheon/config.h create mode 100644 arch/arm/include/asm/arch-pantheon/cpu.h create mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h

diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile new file mode 100644 index 0000000..ab94985 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pantheon/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2011 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Lei Wen leiwen@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS-y = cpu.o timer.o dram.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c new file mode 100644 index 0000000..9ddc77c --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2011 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Lei Wen leiwen@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/arch/pantheon.h> +#include <asm/io.h> + +#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1)) +#define SET_MRVL_ID (1<<8) +#define L2C_RAM_SEL (1<<4) + +int arch_cpu_init(void) +{ + u32 val; + struct panthcpu_registers *cpuregs = + (struct panthcpu_registers*) PANTHEON_CPU_BASE; + + struct panthapb_registers *apbclkres = + (struct panthapb_registers*) PANTHEON_APBC_BASE; + + struct panthmpmu_registers *mpmu = + (struct panthmpmu_registers*) PANTHEON_MPMU_BASE; + + /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */ + val = readl(&cpuregs->cpu_conf); + val = val | SET_MRVL_ID; + writel(val, &cpuregs->cpu_conf); + + /* Turn on clock gating (PMUM_CCGR) */ + writel(0xFFFFFFFF, &mpmu->ccgr); + + /* Turn on clock gating (PMUM_ACGR) */ + writel(0xFFFFFFFF, &mpmu->acgr); + + /* Turn on uart2 clock */ + writel(UARTCLK14745KHZ, &apbclkres->uart0); + + /* Enable GPIO clock */ + writel(APBC_APBCLK, &apbclkres->gpio); + + icache_enable(); + + return 0; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + u32 id; + struct panthcpu_registers *cpuregs = + (struct panthcpu_registers*) PANTHEON_CPU_BASE; + + id = readl(&cpuregs->chip_id); + printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10)); + return 0; +} +#endif diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c new file mode 100644 index 0000000..ca38f53 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pantheon/dram.c @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2011 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Lei Wen leiwen@marvell.com, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/arch/pantheon.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Pantheon DRAM controller supports upto 8 banks + * for chip select 0 and 1 + */ + +/* + * DDR Memory Control Registers + * Refer Datasheet 4.4 + */ +struct panthddr_map_registers { + u32 cs; /* Memory Address Map Register -CS */ + u32 pad[3]; +}; + +struct panthddr_registers { + u8 pad[0x100 - 0x000]; + struct panthddr_map_registers mmap[2]; +}; + +/* + * panth_sdram_base - reads SDRAM Base Address Register + */ +u32 panth_sdram_base(int chip_sel) +{ + struct panthddr_registers *ddr_regs = + (struct panthddr_registers *)PANTHEON_DRAM_BASE; + u32 result = 0; + u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); + + if (!CS_valid) + return 0; + + result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000; + return result; +} + +/* + * panth_sdram_size - reads SDRAM size + */ +u32 panth_sdram_size(int chip_sel) +{ + struct panthddr_registers *ddr_regs = + (struct panthddr_registers *)PANTHEON_DRAM_BASE; + u32 result = 0; + u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); + + if (!CS_valid) + return 0; + + result = readl(&ddr_regs->mmap[chip_sel].cs); + result = (result >> 16) & 0xF; + if (result < 0x7) { + printf("Unknown DRAM Size\n"); + return -1; + } else { + return ((0x8 << (result - 0x7)) * 1024 * 1024); + } +} + +#ifndef CONFIG_SYS_BOARD_DRAM_INIT +int dram_init(void) +{ + int i; + + gd->ram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = panth_sdram_base(i); + gd->bd->bi_dram[i].size = panth_sdram_size(i); + /* + * It is assumed that all memory banks are consecutive + * and without gaps. + * If the gap is found, ram_size will be reported for + * consecutive memory only + */ + if (gd->bd->bi_dram[i].start != gd->ram_size) + break; + + gd->ram_size += gd->bd->bi_dram[i].size; + + } + + for (; i < CONFIG_NR_DRAM_BANKS; i++) { + /* If above loop terminated prematurely, we need to set + * remaining banks' start address & size as 0. Otherwise other + * u-boot functions and Linux kernel gets wrong values which + * could result in crash */ + gd->bd->bi_dram[i].start = 0; + gd->bd->bi_dram[i].size = 0; + } + return 0; +} + +/* + * If this function is not defined here, + * board.c alters dram bank zero configuration defined above. + */ +void dram_init_banksize(void) +{ + dram_init(); +} +#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c new file mode 100644 index 0000000..e100a44 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pantheon/timer.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2011 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Lei Wen leiwen@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/arch/pantheon.h> + +/* + * Timer registers + * Refer 6.2.9 in Datasheet + */ +struct panthtmr_registers { + u32 clk_ctrl; /* Timer clk control reg */ + u32 match[9]; /* Timer match registers */ + u32 count[3]; /* Timer count registers */ + u32 status[3]; + u32 ie[3]; + u32 preload[3]; /* Timer preload value */ + u32 preload_ctrl[3]; + u32 wdt_match_en; + u32 wdt_match_r; + u32 wdt_val; + u32 wdt_sts; + u32 icr[3]; + u32 wdt_icr; + u32 cer; /* Timer count enable reg */ + u32 cmr; + u32 ilr[3]; + u32 wcr; + u32 wfar; + u32 wsar; + u32 cvwr[3]; +}; + +#define TIMER 0 /* Use TIMER 0 */ +/* Each timer has 3 match registers */ +#define MATCH_CMP(x) ((3 * TIMER) + x) +#define TIMER_LOAD_VAL 0xffffffff +#define COUNT_RD_REQ 0x1 + +DECLARE_GLOBAL_DATA_PTR; +/* Using gd->tbu from timestamp and gd->tbl for lastdec */ + +/* For preventing risk of instability in reading counter value, + * first set read request to register cvwr and then read same + * register after it captures counter value. + */ +ulong read_timer(void) +{ + struct panthtmr_registers *panthtimers = + (struct panthtmr_registers *) PANTHEON_TIMER_BASE; + volatile int loop=100; + + writel(COUNT_RD_REQ, &panthtimers->cvwr); + while (loop--); + return(readl(&panthtimers->cvwr)); +} + +void reset_timer_masked(void) +{ + /* reset time */ + gd->tbl = read_timer(); + gd->tbu = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = read_timer(); + + if (now >= gd->tbl) { + /* normal mode */ + gd->tbu += now - gd->tbl; + } else { + /* we have an overflow ... */ + gd->tbu += now + TIMER_LOAD_VAL - gd->tbl; + } + gd->tbl = now; + + return gd->tbu; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - + base); +} + +void set_timer(ulong t) +{ + gd->tbu = t; +} + +void __udelay(unsigned long usec) +{ + ulong delayticks; + ulong endtime; + + delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000)); + endtime = get_timer_masked() + delayticks; + + while (get_timer_masked() < endtime); +} + +/* + * init the Timer + */ +int timer_init(void) +{ + struct panthapb_registers *apb1clkres = + (struct panthapb_registers *) PANTHEON_APBC_BASE; + struct panthtmr_registers *panthtimers = + (struct panthtmr_registers *) PANTHEON_TIMER_BASE; + + /* Enable Timer clock at 3.25 MHZ */ + writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers); + + /* load value into timer */ + writel(0x0, &panthtimers->clk_ctrl); + /* Use Timer 0 Match Resiger 0 */ + writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]); + /* Preload value is 0 */ + writel(0x0, &panthtimers->preload[TIMER]); + /* Enable match comparator 0 for Timer 0 */ + writel(0x1, &panthtimers->preload_ctrl[TIMER]); + + /* Enable timer 0 */ + writel(0x1, &panthtimers->cer); + /* init the gd->tbu and gd->tbl value */ + reset_timer_masked(); + + return 0; +} + +#define MPMU_APRR_WDTR (1<<4) +#define TMR_WFAR 0xbaba /* WDT Register First key */ +#define TMP_WSAR 0xeb10 /* WDT Register Second key */ + +/* + * This function uses internal Watchdog Timer + * based reset mechanism. + * Steps to write watchdog registers (protected access) + * 1. Write key value to TMR_WFAR reg. + * 2. Write key value to TMP_WSAR reg. + * 3. Perform write operation. + */ +void reset_cpu (unsigned long ignored) +{ + struct panthmpmu_registers *mpmu = + (struct panthmpmu_registers *) PANTHEON_MPMU_BASE; + struct panthtmr_registers *panthtimers = + (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE; + u32 val; + + /* negate hardware reset to the WDT after system reset */ + val = readl(&mpmu->aprr); + val = val | MPMU_APRR_WDTR; + writel(val, &mpmu->aprr); + + /* reset/enable WDT clock */ + writel(APBC_APBCLK, &mpmu->wdtpcr); + + /* clear previous WDT status */ + writel(TMR_WFAR, &panthtimers->wfar); + writel(TMP_WSAR, &panthtimers->wsar); + writel(0, &panthtimers->wdt_sts); + + /* set match counter */ + writel(TMR_WFAR, &panthtimers->wfar); + writel(TMP_WSAR, &panthtimers->wsar); + writel(0xf, &panthtimers->wdt_match_r); + + /* enable WDT reset */ + writel(TMR_WFAR, &panthtimers->wfar); + writel(TMP_WSAR, &panthtimers->wsar); + writel(0x3, &panthtimers->wdt_match_en); + + /*enable functional WDT clock */ + writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr); +} diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h new file mode 100644 index 0000000..8c9734d --- /dev/null +++ b/arch/arm/include/asm/arch-pantheon/config.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2011 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Lei Wen leiwen@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _PANTHEON_CONFIG_H +#define _PANTHEON_CONFIG_H + +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ + +#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ +#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ +#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ +#define MV_MFPR_BASE PANTHEON_MFPR_BASE +#define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE +#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register + represents UART Unit Enable */ +/* + * There is no internal RAM in ARMADA100, using DRAM + * TBD: dcache to be used for this + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) +#define CONFIG_NR_DRAM_BANKS_MAX 2 + +#endif /* _PANTHEON_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h new file mode 100644 index 0000000..30f4393 --- /dev/null +++ b/arch/arm/include/asm/arch-pantheon/cpu.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2011 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Lei Wen leiwen@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _PANTHEON_CPU_H +#define _PANTHEON_CPU_H + +#include <asm/io.h> +#include <asm/system.h> + +/* + * Main Power Management (MPMU) Registers + * Refer Register Datasheet 9.1 + */ +struct panthmpmu_registers { + u8 pad0[0x0024]; + u32 ccgr; /*0x0024*/ + u8 pad1[0x0200 - 0x024 - 4]; + u32 wdtpcr; /*0x0200*/ + u8 pad2[0x1020 - 0x200 - 4]; + u32 aprr; /*0x1020*/ + u32 acgr; /*0x1024*/ +}; + +/* + * APB Clock Reset/Control Registers + * Refer Register Datasheet 6.14 + */ +struct panthapb_registers { + u32 uart0; /*0x000*/ + u32 uart1; /*0x004*/ + u32 gpio; /*0x008*/ + u8 pad0[0x034 - 0x08 - 4]; + u32 timers; /*0x034*/ +}; + +/* + * CPU Interface Registers + * Refer Register Datasheet 4.3 + */ +struct panthcpu_registers { + u32 chip_id; /* Chip Id Reg */ + u32 pad; + u32 cpu_conf; /* CPU Conf Reg */ + u32 pad1; + u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ + u32 pad2; + u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ + u32 mcb_conf; /* MCB Conf Reg */ + u32 sys_boot_ctl; /* Sytem Boot Control */ +}; + +/* + * Functions + */ +u32 panth_sdram_base(int); +u32 panth_sdram_size(int); + +#endif /* _PANTHEON_CPU_H */ diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h new file mode 100644 index 0000000..e4ed087 --- /dev/null +++ b/arch/arm/include/asm/arch-pantheon/pantheon.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2011 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Lei Wen leiwen@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _PANTHEON_H +#define _PANTHEON_H + +#ifndef __ASSEMBLY__ +#include <asm/types.h> +#include <asm/io.h> +#endif /* __ASSEMBLY__ */ + +#include <asm/arch/cpu.h> + +/* Common APB clock register bit definitions */ +#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ +#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ +#define APBC_RST (1<<2) /* Reset Generation */ +/* Functional Clock Selection Mask */ +#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) + +/* Register Base Addresses */ +#define PANTHEON_DRAM_BASE 0xB0000000 +#define PANTHEON_TIMER_BASE 0xD4014000 +#define PANTHEON_WD_TIMER_BASE 0xD4080000 +#define PANTHEON_APBC_BASE 0xD4015000 +#define PANTHEON_UART1_BASE 0xD4017000 +#define PANTHEON_UART2_BASE 0xD4018000 +#define PANTHEON_GPIO_BASE 0xD4019000 +#define PANTHEON_MFPR_BASE 0xD401E000 +#define PANTHEON_MPMU_BASE 0xD4050000 +#define PANTHEON_CPU_BASE 0xD4282C00 + +#endif /* _PANTHEON_H */

This patch adds the support MFP support for Marvell PANTHEON SoCs

Signed-off-by: Lei Wen leiwen@marvell.com --- arch/arm/include/asm/arch-pantheon/mfp.h | 42 ++++++++++++++++++++++++++++++ drivers/gpio/mvmfp.c | 2 + 2 files changed, 44 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-pantheon/mfp.h

diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h new file mode 100644 index 0000000..170dcbb --- /dev/null +++ b/arch/arm/include/asm/arch-pantheon/mfp.h @@ -0,0 +1,42 @@ +/* + * Based on arch/arm/include/asm/arch-armada100/mfp.h + * (C) Copyright 2011 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Lei Wen leiwen@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __PANTHEON_MFP_H +#define __PANTHEON_MFP_H + +/* + * Frequently used MFP Configuration macros for all PANTHEON family of +SoCs + * + * offset, pull,pF, drv,dF, edge,eF ,afn,aF + */ +/* UART2 */ +#define MFP47_UART2_RXD MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM +#define MFP48_UART2_TXD MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM + +/* More macros can be defined here... */ + +#define MFP_PIN_MAX 117 +#endif diff --git a/drivers/gpio/mvmfp.c b/drivers/gpio/mvmfp.c index 5646ed4..e7830c6 100644 --- a/drivers/gpio/mvmfp.c +++ b/drivers/gpio/mvmfp.c @@ -28,6 +28,8 @@ #include <asm/arch/mfp.h> #ifdef CONFIG_ARMADA100 #include <asm/arch/armada100.h> +#elif defined(CONFIG_PANTHEON) +#include <asm/arch/pantheon.h> #else #error Unsupported SoC... #endif