[PATCH v3 1/3] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host
Add USB 2.0 host nodes and PHYs.
Co-developed-by: William Wu william.wu@rock-chips.com Signed-off-by: William Wu william.wu@rock-chips.com Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- Changes in v2,v3: - none
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 169 ++++++++++++++++++++++++ 1 file changed, 169 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 2386edf90deb..e1d240baf35d 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -4,6 +4,9 @@ */
#include "rk3588-u-boot.dtsi" +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h>
/ { aliases { @@ -13,6 +16,105 @@ chosen { u-boot,spl-boot-order = &sdmmc; }; + + vcc5v0_host: vcc5v0-host-regulator { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + usb_host0_ehci: usb@fc800000 { + compatible = "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; };
&sdmmc { @@ -20,3 +122,70 @@ u-boot,dm-spl; status = "okay"; }; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&usb_host0_ehci { + companion = <&usb_host0_ohci>; + phys = <&u2phy2_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb_host0_ohci { + phys = <&u2phy2_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy2_grf { + status = "okay"; +}; + +&u2phy2 { + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; + clock-output-names = "usb480m_phy2"; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host1_ehci { + companion = <&usb_host1_ohci>; + phys = <&u2phy3_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb_host1_ohci { + phys = <&u2phy3_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy3_grf { + status = "okay"; +}; + +&u2phy3 { + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; + clock-output-names = "usb480m_phy3"; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; +
Add initial support for the rk3588 PHY variant. The driver now looks for phy-supply and enables/disables the vbus accordingly. The lookup for the host-port reg inside the struct now does a do {} while() instead of a while() {} in order to allow a first check for reg == 0.
Co-developed-by: Frank Wang frank.wang@rock-chips.com Signed-off-by: Frank Wang frank.wang@rock-chips.com Signed-off-by: Eugen Hristev eugen.hristev@collabora.com Tested-by: Vasily Khoruzhick anarsoul@gmail.com # rk3568-based board Tested-by: Xavier Drudis Ferran xdrudis@tinet.cat # rk3399 rock pi 4B+ --- Changes in v3: - add handling of -EBUSY and -EALREADY for regulator return Changes in v2: - add handling of -EACCES
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 109 +++++++++++++++++- 1 file changed, 104 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 55e1dbcfef7e..75c50670524e 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -13,6 +13,7 @@ #include <dm/device_compat.h> #include <dm/lists.h> #include <generic-phy.h> +#include <power/regulator.h> #include <reset.h> #include <syscon.h> #include <asm/gpio.h> @@ -61,6 +62,7 @@ struct rockchip_usb2phy_cfg { struct rockchip_usb2phy { void *reg_base; struct clk phyclk; + struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; const struct rockchip_usb2phy_cfg *phy_cfg; };
@@ -86,11 +88,34 @@ struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct phy *phy) return &phy_cfg->port_cfgs[phy->id]; }
+static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy) +{ + struct udevice *parent = phy->dev->parent; + struct rockchip_usb2phy *priv = dev_get_priv(parent); + struct udevice *vbus = NULL; + + if (phy->id == USB2PHY_PORT_HOST) + vbus = priv->vbus_supply[USB2PHY_PORT_HOST]; + + return vbus; +} + static int rockchip_usb2phy_power_on(struct phy *phy) { struct udevice *parent = dev_get_parent(phy->dev); struct rockchip_usb2phy *priv = dev_get_priv(parent); const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy); + struct udevice *vbus = NULL; + int ret; + + vbus = rockchip_usb2phy_check_vbus(phy); + if (vbus) { + ret = regulator_set_enable(vbus, true); + if (ret && ret != -EALREADY) { + dev_err(phy->dev, "vbus enable failed: %d\n", ret); + return ret; + } + }
property_enable(priv->reg_base, &port_cfg->phy_sus, false);
@@ -105,6 +130,17 @@ static int rockchip_usb2phy_power_off(struct phy *phy) struct udevice *parent = dev_get_parent(phy->dev); struct rockchip_usb2phy *priv = dev_get_priv(parent); const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy); + struct udevice *vbus = NULL; + int ret; + + vbus = rockchip_usb2phy_check_vbus(phy); + if (vbus) { + ret = regulator_set_enable(vbus, false); + if (ret && ret != -EACCES && ret != -EBUSY) { + dev_info(phy->dev, "vbus disable failed: %d\n", ret); + return ret; + } + }
property_enable(priv->reg_base, &port_cfg->phy_sus, true);
@@ -149,13 +185,20 @@ static int rockchip_usb2phy_of_xlate(struct phy *phy, struct ofnode_phandle_args *args) { const char *name = phy->dev->name; + struct udevice *parent = phy->dev->parent; + struct rockchip_usb2phy *priv = dev_get_priv(parent);
- if (!strcasecmp(name, "host-port")) + if (!strcasecmp(name, "host-port")) { phy->id = USB2PHY_PORT_HOST; - else if (!strcasecmp(name, "otg-port")) + device_get_supply_regulator(phy->dev, "phy-supply", + &priv->vbus_supply[USB2PHY_PORT_HOST]); + } else if (!strcasecmp(name, "otg-port")) { phy->id = USB2PHY_PORT_OTG; - else + device_get_supply_regulator(phy->dev, "phy-supply", + &priv->vbus_supply[USB2PHY_PORT_OTG]); + } else { dev_err(phy->dev, "improper %s device\n", name); + }
return 0; } @@ -201,14 +244,14 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
/* find out a proper config which can be matched with dt. */ index = 0; - while (phy_cfgs[index].reg) { + do { if (phy_cfgs[index].reg == reg) { priv->phy_cfg = &phy_cfgs[index]; break; }
++index; - } + } while (phy_cfgs[index].reg);
if (!priv->phy_cfg) { dev_err(dev, "failed find proper phy-cfg\n"); @@ -348,6 +391,58 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { { /* sentinel */ } };
+static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { + { + .reg = 0x0000, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x000c, 11, 11, 0, 1 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, + } + }, + }, + { + .reg = 0x4000, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x000c, 11, 11, 0, 0 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, + } + }, + }, + { + .reg = 0x8000, + .port_cfgs = { + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0008, 2, 2, 0, 1 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, + } + }, + }, + { + .reg = 0xc000, + .port_cfgs = { + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0008, 2, 2, 0, 1 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, + } + }, + }, + { /* sentinel */ } +}; + static const struct udevice_id rockchip_usb2phy_ids[] = { { .compatible = "rockchip,rk3399-usb2phy", @@ -357,6 +452,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs, }, + { + .compatible = "rockchip,rk3588-usb2phy", + .data = (ulong)&rk3588_phy_cfgs, + }, { /* sentinel */ } };
Hi Eugen,
On 2023-03-31 11:40, Eugen Hristev wrote:
Add initial support for the rk3588 PHY variant. The driver now looks for phy-supply and enables/disables the vbus accordingly.
Maybe this should be added to core phy uclass to closer match linux?
Look like e.g. meson phy drivers also handle a phy-supply and could also benefit from having this in phy uclass instead of in each phy driver.
Regards, Jonas
The lookup for the host-port reg inside the struct now does a do {} while() instead of a while() {} in order to allow a first check for reg == 0.
Co-developed-by: Frank Wang frank.wang@rock-chips.com Signed-off-by: Frank Wang frank.wang@rock-chips.com Signed-off-by: Eugen Hristev eugen.hristev@collabora.com Tested-by: Vasily Khoruzhick anarsoul@gmail.com # rk3568-based board Tested-by: Xavier Drudis Ferran xdrudis@tinet.cat # rk3399 rock pi 4B+
Changes in v3:
- add handling of -EBUSY and -EALREADY for regulator return
Changes in v2:
- add handling of -EACCES
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 109 +++++++++++++++++- 1 file changed, 104 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 55e1dbcfef7e..75c50670524e 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -13,6 +13,7 @@ #include <dm/device_compat.h> #include <dm/lists.h> #include <generic-phy.h> +#include <power/regulator.h> #include <reset.h> #include <syscon.h> #include <asm/gpio.h> @@ -61,6 +62,7 @@ struct rockchip_usb2phy_cfg { struct rockchip_usb2phy { void *reg_base; struct clk phyclk;
- struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; const struct rockchip_usb2phy_cfg *phy_cfg;
};
@@ -86,11 +88,34 @@ struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct phy *phy) return &phy_cfg->port_cfgs[phy->id]; }
+static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy) +{
- struct udevice *parent = phy->dev->parent;
- struct rockchip_usb2phy *priv = dev_get_priv(parent);
- struct udevice *vbus = NULL;
- if (phy->id == USB2PHY_PORT_HOST)
vbus = priv->vbus_supply[USB2PHY_PORT_HOST];- return vbus;
+}
static int rockchip_usb2phy_power_on(struct phy *phy) { struct udevice *parent = dev_get_parent(phy->dev); struct rockchip_usb2phy *priv = dev_get_priv(parent); const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
struct udevice *vbus = NULL;
int ret;
vbus = rockchip_usb2phy_check_vbus(phy);
if (vbus) {
ret = regulator_set_enable(vbus, true);if (ret && ret != -EALREADY) {dev_err(phy->dev, "vbus enable failed: %d\n", ret);return ret;}}
property_enable(priv->reg_base, &port_cfg->phy_sus, false);
@@ -105,6 +130,17 @@ static int rockchip_usb2phy_power_off(struct phy *phy) struct udevice *parent = dev_get_parent(phy->dev); struct rockchip_usb2phy *priv = dev_get_priv(parent); const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
struct udevice *vbus = NULL;
int ret;
vbus = rockchip_usb2phy_check_vbus(phy);
if (vbus) {
ret = regulator_set_enable(vbus, false);if (ret && ret != -EACCES && ret != -EBUSY) {dev_info(phy->dev, "vbus disable failed: %d\n", ret);return ret;}}
property_enable(priv->reg_base, &port_cfg->phy_sus, true);
@@ -149,13 +185,20 @@ static int rockchip_usb2phy_of_xlate(struct phy *phy, struct ofnode_phandle_args *args) { const char *name = phy->dev->name;
- struct udevice *parent = phy->dev->parent;
- struct rockchip_usb2phy *priv = dev_get_priv(parent);
- if (!strcasecmp(name, "host-port"))
- if (!strcasecmp(name, "host-port")) { phy->id = USB2PHY_PORT_HOST;
- else if (!strcasecmp(name, "otg-port"))
device_get_supply_regulator(phy->dev, "phy-supply",&priv->vbus_supply[USB2PHY_PORT_HOST]);- } else if (!strcasecmp(name, "otg-port")) { phy->id = USB2PHY_PORT_OTG;
- else
device_get_supply_regulator(phy->dev, "phy-supply",&priv->vbus_supply[USB2PHY_PORT_OTG]);} else { dev_err(phy->dev, "improper %s device\n", name);
}
return 0;
} @@ -201,14 +244,14 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
/* find out a proper config which can be matched with dt. */ index = 0;
- while (phy_cfgs[index].reg) {
do { if (phy_cfgs[index].reg == reg) { priv->phy_cfg = &phy_cfgs[index]; break; }
++index;
- }
} while (phy_cfgs[index].reg);
if (!priv->phy_cfg) { dev_err(dev, "failed find proper phy-cfg\n");
@@ -348,6 +391,58 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { { /* sentinel */ } };
+static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
- {
.reg = 0x0000,.port_cfgs = {[USB2PHY_PORT_OTG] = {.phy_sus = { 0x000c, 11, 11, 0, 1 },.ls_det_en = { 0x0080, 0, 0, 0, 1 },.ls_det_st = { 0x0084, 0, 0, 0, 1 },.ls_det_clr = { 0x0088, 0, 0, 0, 1 },.utmi_ls = { 0x00c0, 10, 9, 0, 1 },}},- },
- {
.reg = 0x4000,.port_cfgs = {[USB2PHY_PORT_OTG] = {.phy_sus = { 0x000c, 11, 11, 0, 0 },.ls_det_en = { 0x0080, 0, 0, 0, 1 },.ls_det_st = { 0x0084, 0, 0, 0, 1 },.ls_det_clr = { 0x0088, 0, 0, 0, 1 },.utmi_ls = { 0x00c0, 10, 9, 0, 1 },}},- },
- {
.reg = 0x8000,.port_cfgs = {[USB2PHY_PORT_HOST] = {.phy_sus = { 0x0008, 2, 2, 0, 1 },.ls_det_en = { 0x0080, 0, 0, 0, 1 },.ls_det_st = { 0x0084, 0, 0, 0, 1 },.ls_det_clr = { 0x0088, 0, 0, 0, 1 },.utmi_ls = { 0x00c0, 10, 9, 0, 1 },}},- },
- {
.reg = 0xc000,.port_cfgs = {[USB2PHY_PORT_HOST] = {.phy_sus = { 0x0008, 2, 2, 0, 1 },.ls_det_en = { 0x0080, 0, 0, 0, 1 },.ls_det_st = { 0x0084, 0, 0, 0, 1 },.ls_det_clr = { 0x0088, 0, 0, 0, 1 },.utmi_ls = { 0x00c0, 10, 9, 0, 1 },}},- },
- { /* sentinel */ }
+};
static const struct udevice_id rockchip_usb2phy_ids[] = { { .compatible = "rockchip,rk3399-usb2phy", @@ -357,6 +452,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs, },
- {
.compatible = "rockchip,rk3588-usb2phy",.data = (ulong)&rk3588_phy_cfgs,- }, { /* sentinel */ }
};
On 4/2/23 14:04, Jonas Karlman wrote:
Hi Eugen,
On 2023-03-31 11:40, Eugen Hristev wrote:
Add initial support for the rk3588 PHY variant. The driver now looks for phy-supply and enables/disables the vbus accordingly.
Maybe this should be added to core phy uclass to closer match linux?
Look like e.g. meson phy drivers also handle a phy-supply and could also benefit from having this in phy uclass instead of in each phy driver.
This can be done yes. I can try it.
Regards, Jonas
Enable USB command, USB drivers, PHY and regulators, for USB host operations.
Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- configs/rock5b-rk3588_defconfig | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index f3026c7ea166..c4b3bd65147f 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -41,12 +41,13 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -61,7 +62,9 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 @@ -69,4 +72,17 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYSRESET=y # CONFIG_BINMAN_FDT is not set +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y CONFIG_ERRNO_STR=y
Hi Eugen,
On 2023-03-31 11:40, Eugen Hristev wrote:
Add USB 2.0 host nodes and PHYs.
Co-developed-by: William Wu william.wu@rock-chips.com Signed-off-by: William Wu william.wu@rock-chips.com Signed-off-by: Eugen Hristev eugen.hristev@collabora.com
Changes in v2,v3:
- none
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 169 ++++++++++++++++++++++++ 1 file changed, 169 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 2386edf90deb..e1d240baf35d 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -4,6 +4,9 @@ */
#include "rk3588-u-boot.dtsi" +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h>
/ { aliases { @@ -13,6 +16,105 @@ chosen { u-boot,spl-boot-order = &sdmmc; };
- vcc5v0_host: vcc5v0-host-regulator {
u-boot,dm-pre-reloc;compatible = "regulator-fixed";regulator-name = "vcc5v0_host";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;enable-active-high;gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_host_en>;vin-supply = <&vcc5v0_sys>;- };
- usb_host0_ehci: usb@fc800000 {
compatible = "generic-ehci";reg = <0x0 0xfc800000 0x0 0x40000>;interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host0_ohci: usb@fc840000 {
compatible = "generic-ohci";reg = <0x0 0xfc840000 0x0 0x40000>;interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host1_ehci: usb@fc880000 {
compatible = "generic-ehci";reg = <0x0 0xfc880000 0x0 0x40000>;interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host1_ohci: usb@fc8c0000 {
compatible = "generic-ohci";reg = <0x0 0xfc8c0000 0x0 0x40000>;interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon","simple-mfd";reg = <0x0 0xfd5d8000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy2: usb2-phy@8000 {compatible = "rockchip,rk3588-usb2phy";reg = <0x8000 0x10>;interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";#clock-cells = <0>;status = "disabled";u2phy2_host: host-port {#phy-cells = <0>;status = "disabled";};};- };
- usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon","simple-mfd";reg = <0x0 0xfd5dc000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy3: usb2-phy@c000 {compatible = "rockchip,rk3588-usb2phy";reg = <0xc000 0x10>;interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";#clock-cells = <0>;status = "disabled";u2phy3_host: host-port {#phy-cells = <0>;status = "disabled";};};- };
Most of these nodes could be added to the soc u-boot dtsi and not the board specific file. Also wondering if some of the reset and clock related properties below are board specific or soc specific and can go into the above soc nodes directly.
Are there any patches in the works to add these nodes to linux dt?
Regards, Jonas
};
&sdmmc { @@ -20,3 +122,70 @@ u-boot,dm-spl; status = "okay"; };
+&pinctrl {
- usb {
vcc5v0_host_en: vcc5v0-host-en {rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+&usb_host0_ehci {
- companion = <&usb_host0_ohci>;
- phys = <&u2phy2_host>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usb_host0_ohci {
- phys = <&u2phy2_host>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usb2phy2_grf {
- status = "okay";
+};
+&u2phy2 {
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
- reset-names = "phy", "apb";
- clock-output-names = "usb480m_phy2";
- status = "okay";
+};
+&u2phy2_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
+&usb_host1_ehci {
- companion = <&usb_host1_ohci>;
- phys = <&u2phy3_host>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usb_host1_ohci {
- phys = <&u2phy3_host>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usb2phy3_grf {
- status = "okay";
+};
+&u2phy3 {
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
- reset-names = "phy", "apb";
- clock-output-names = "usb480m_phy3";
- status = "okay";
+};
+&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
On 4/2/23 14:00, Jonas Karlman wrote:
Hi Eugen,
On 2023-03-31 11:40, Eugen Hristev wrote:
Add USB 2.0 host nodes and PHYs.
Co-developed-by: William Wu william.wu@rock-chips.com Signed-off-by: William Wu william.wu@rock-chips.com Signed-off-by: Eugen Hristev eugen.hristev@collabora.com
Changes in v2,v3:
none
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 169 ++++++++++++++++++++++++ 1 file changed, 169 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 2386edf90deb..e1d240baf35d 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -4,6 +4,9 @@ */
#include "rk3588-u-boot.dtsi" +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h>
/ { aliases { @@ -13,6 +16,105 @@ chosen { u-boot,spl-boot-order = &sdmmc; };
- vcc5v0_host: vcc5v0-host-regulator {
u-boot,dm-pre-reloc;compatible = "regulator-fixed";regulator-name = "vcc5v0_host";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;enable-active-high;gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_host_en>;vin-supply = <&vcc5v0_sys>;- };
- usb_host0_ehci: usb@fc800000 {
compatible = "generic-ehci";reg = <0x0 0xfc800000 0x0 0x40000>;interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host0_ohci: usb@fc840000 {
compatible = "generic-ohci";reg = <0x0 0xfc840000 0x0 0x40000>;interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host1_ehci: usb@fc880000 {
compatible = "generic-ehci";reg = <0x0 0xfc880000 0x0 0x40000>;interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host1_ohci: usb@fc8c0000 {
compatible = "generic-ohci";reg = <0x0 0xfc8c0000 0x0 0x40000>;interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon","simple-mfd";reg = <0x0 0xfd5d8000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy2: usb2-phy@8000 {compatible = "rockchip,rk3588-usb2phy";reg = <0x8000 0x10>;interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";#clock-cells = <0>;status = "disabled";u2phy2_host: host-port {#phy-cells = <0>;status = "disabled";};};- };
- usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon","simple-mfd";reg = <0x0 0xfd5dc000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy3: usb2-phy@c000 {compatible = "rockchip,rk3588-usb2phy";reg = <0xc000 0x10>;interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";#clock-cells = <0>;status = "disabled";u2phy3_host: host-port {#phy-cells = <0>;status = "disabled";};};- };
Most of these nodes could be added to the soc u-boot dtsi and not the board specific file. Also wondering if some of the reset and clock related properties below are board specific or soc specific and can go into the above soc nodes directly.
That is right, but , it would spread all the -u-boot.dtsi nodes into a lot of files. So I kept them here to have them all in one place. I can move them if you think it's better.
Are there any patches in the works to add these nodes to linux dt?
From what I know, yes, the patches are in the works, but I cannot say for sure when they will be sent/accepted
Regards, Jonas
};
&sdmmc { @@ -20,3 +122,70 @@ u-boot,dm-spl; status = "okay"; };
+&pinctrl {
- usb {
vcc5v0_host_en: vcc5v0-host-en {rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+&usb_host0_ehci {
- companion = <&usb_host0_ohci>;
- phys = <&u2phy2_host>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usb_host0_ohci {
- phys = <&u2phy2_host>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usb2phy2_grf {
- status = "okay";
+};
+&u2phy2 {
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
- reset-names = "phy", "apb";
- clock-output-names = "usb480m_phy2";
- status = "okay";
+};
+&u2phy2_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
+&usb_host1_ehci {
- companion = <&usb_host1_ohci>;
- phys = <&u2phy3_host>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usb_host1_ohci {
- phys = <&u2phy3_host>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usb2phy3_grf {
- status = "okay";
+};
+&u2phy3 {
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
- reset-names = "phy", "apb";
- clock-output-names = "usb480m_phy3";
- status = "okay";
+};
+&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
On 2023-04-03 13:28, Eugen Hristev wrote:
On 4/2/23 14:00, Jonas Karlman wrote:
Hi Eugen,
On 2023-03-31 11:40, Eugen Hristev wrote:
Add USB 2.0 host nodes and PHYs.
Co-developed-by: William Wu william.wu@rock-chips.com Signed-off-by: William Wu william.wu@rock-chips.com Signed-off-by: Eugen Hristev eugen.hristev@collabora.com
Changes in v2,v3:
none
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 169 ++++++++++++++++++++++++ 1 file changed, 169 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 2386edf90deb..e1d240baf35d 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -4,6 +4,9 @@ */
#include "rk3588-u-boot.dtsi" +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h>
/ { aliases { @@ -13,6 +16,105 @@ chosen { u-boot,spl-boot-order = &sdmmc; };
- vcc5v0_host: vcc5v0-host-regulator {
u-boot,dm-pre-reloc;compatible = "regulator-fixed";regulator-name = "vcc5v0_host";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;enable-active-high;gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_host_en>;vin-supply = <&vcc5v0_sys>;- };
- usb_host0_ehci: usb@fc800000 {
compatible = "generic-ehci";reg = <0x0 0xfc800000 0x0 0x40000>;interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host0_ohci: usb@fc840000 {
compatible = "generic-ohci";reg = <0x0 0xfc840000 0x0 0x40000>;interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host1_ehci: usb@fc880000 {
compatible = "generic-ehci";reg = <0x0 0xfc880000 0x0 0x40000>;interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host1_ohci: usb@fc8c0000 {
compatible = "generic-ohci";reg = <0x0 0xfc8c0000 0x0 0x40000>;interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon","simple-mfd";reg = <0x0 0xfd5d8000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy2: usb2-phy@8000 {compatible = "rockchip,rk3588-usb2phy";reg = <0x8000 0x10>;interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";#clock-cells = <0>;status = "disabled";u2phy2_host: host-port {#phy-cells = <0>;status = "disabled";};};- };
- usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon","simple-mfd";reg = <0x0 0xfd5dc000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy3: usb2-phy@c000 {compatible = "rockchip,rk3588-usb2phy";reg = <0xc000 0x10>;interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";#clock-cells = <0>;status = "disabled";u2phy3_host: host-port {#phy-cells = <0>;status = "disabled";};};- };
Most of these nodes could be added to the soc u-boot dtsi and not the board specific file. Also wondering if some of the reset and clock related properties below are board specific or soc specific and can go into the above soc nodes directly.
That is right, but , it would spread all the -u-boot.dtsi nodes into a lot of files. So I kept them here to have them all in one place. I can move them if you think it's better.
I think it is preferably that nodes likely to end up in main soc dtsi is temporarily placed in soc u-boot dtsi file. At least until proper finalized nodes can be synced from linux-next.
That way other rk3588 boards more easily can benefit from these nodes.
Are there any patches in the works to add these nodes to linux dt?
From what I know, yes, the patches are in the works, but I cannot say for sure when they will be sent/accepted
Great, thanks.
Regards, Jonas
Regards, Jonas
};
&sdmmc { @@ -20,3 +122,70 @@ u-boot,dm-spl; status = "okay"; };
+&pinctrl {
- usb {
vcc5v0_host_en: vcc5v0-host-en {rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+&usb_host0_ehci {
- companion = <&usb_host0_ohci>;
- phys = <&u2phy2_host>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usb_host0_ohci {
- phys = <&u2phy2_host>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usb2phy2_grf {
- status = "okay";
+};
+&u2phy2 {
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
- reset-names = "phy", "apb";
- clock-output-names = "usb480m_phy2";
- status = "okay";
+};
+&u2phy2_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
+&usb_host1_ehci {
- companion = <&usb_host1_ohci>;
- phys = <&u2phy3_host>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usb_host1_ohci {
- phys = <&u2phy3_host>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usb2phy3_grf {
- status = "okay";
+};
+&u2phy3 {
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
- reset-names = "phy", "apb";
- clock-output-names = "usb480m_phy3";
- status = "okay";
+};
+&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
participants (2)
-
Eugen Hristev -
Jonas Karlman