The instruction and data cache line sizes of Andes core are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so the SYS_CACHELINE_SIZE is enabled with a default value.

Signed-off-by: Yu Chien Peter Lin peterlin@andestech.com --- arch/riscv/cpu/andesv5/Kconfig | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig index f311291aed..e3efb0de8f 100644 --- a/arch/riscv/cpu/andesv5/Kconfig +++ b/arch/riscv/cpu/andesv5/Kconfig @@ -1,6 +1,7 @@ config RISCV_NDS bool select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)