[PATCH 00/21] Finish migration to DM_ETH

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[PATCH v2] crypto/fsl: Add support...

Tom Rini

2 Aug 2022 2 Aug '22

1:33 p.m.

As I've noted before, with v2022.07 being released, we have gone 2 years past the DM_ETH migration deadline. What this series does is a few things: - Remove some boards that either lack DM migration at all, or lack OF_CONTROL. DM migration has had an explicit deadline, and OF_CONTROL an implict one. - Remove some un-migrated ethernet drivers. I had reached out in private to some people about this and they had hoped to have done the conversion by now. Unfortunately, here we now are. - Perform some minor forceful migrations on boards. These boards use OF_CONTROL and drivers which use DM_ETH, so I am hopeful that just removing or guarding the code here is fine and works. - Disable networkgin on some other boards. Unlike boards in the above case, it looks like the board code itself needs some updates, as was done on the platforms that have already been migrated. - Finally, select DM_ETH for all NETDEVICES and update dependencies.

This series depends on https://patchwork.ozlabs.org/project/uboot/patch/8ae444f17dc5db69a1da809875a... being applied and in practical terms depennds on my current outstanding Kconfig migrations as well.

-- Tom

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Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 01/21] Convert CONFIG_SYS_FDT_PAD to Kconfig

This converts the following to Kconfig: CONFIG_SYS_FDT_PAD

diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 9db2cee99423..7a80fe0dfdeb 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -23,10 +23,6 @@ #include <asm/io.h> #include <tee/optee.h>

-#ifndef CONFIG_SYS_FDT_PAD -#define CONFIG_SYS_FDT_PAD 0x3000 -#endif - /* adding a ramdisk needs 0x44 bytes in version 2008.10 */ #define FDT_RAMDISK_OVERHEAD 0x80

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 1ba48e587215..11a3db590259 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -299,7 +299,6 @@

#define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)

#ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index f5e07a929fc5..a5461d7fc685 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -413,8 +413,6 @@ #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08

#define CONFIG_SYS_DPAA_FMAN - -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 7983a71953d4..560083c5b315 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -388,8 +388,6 @@

#define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME - -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_FMAN_ENET diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 9d43d87338a9..fc068c94a9ea 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -411,8 +411,6 @@ #define CONFIG_SYS_DPAA_DCE #define CONFIG_SYS_DPAA_RMAN /* RMan */ #define CONFIG_SYS_INTERLAKEN - -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 9a9920a88055..056e2d1925ba 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -365,8 +365,6 @@ #define CONFIG_SYS_DPAA_DCE #define CONFIG_SYS_DPAA_RMAN /* RMan */ #define CONFIG_SYS_INTERLAKEN - -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 4280c2df1fab..bba82f1e0cd3 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -368,8 +368,6 @@ #define CONFIG_SYS_DPAA_DCE #define CONFIG_SYS_DPAA_RMAN #define CONFIG_SYS_INTERLAKEN - -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 5f3fd89c21bb..7e65b2b6aa22 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -293,7 +293,6 @@

#define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)

#ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 589ba615dd6d..0d470c4b4a13 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -385,8 +385,6 @@ int get_scl(void); #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME

-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - /* Qman / Bman */ /* RGMII (FM1@DTESC5) is local managemant interface */ #define CONFIG_SYS_RGMII2_PHY_ADDR 0x11 diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 43f30fd70f71..1fb1d05eba36 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -114,8 +114,6 @@ #define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 - -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif #endif

diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 2e48ea0f8aad..e5fb111f1b88 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -87,7 +87,6 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #endif -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif

/* Miscellaneous configurable options */ diff --git a/lib/Kconfig b/lib/Kconfig index 7dd777b56a79..074801278598 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -743,6 +743,16 @@ config OF_LIBFDT_OVERLAY help This enables the FDT library (libfdt) overlay support.

+config SYS_FDT_PAD + hex "Maximum size of the FDT memory area passeed to the OS" + depends on OF_LIBFDT + default 0x13000 if FMAN_ENET || QE || U_QE + default 0x3000 + help + During OS boot, we allocate a region of memory within the bootmap + for the FDT. This is the size that we will expand the FDT that we + are using will be extended to be, in bytes. + config SPL_OF_LIBFDT bool "Enable the FDT library for SPL" depends on SPL_LIBGENERIC_SUPPORT

-- 2.25.1

Simon Glass

2:41 p.m.

New subject: [PATCH 01/21] Convert CONFIG_SYS_FDT_PAD to Kconfig

On Tue, 2 Aug 2022 at 05:35, Tom Rini trini@konsulko.com wrote:

...

This converts the following to Kconfig: CONFIG_SYS_FDT_PAD

Signed-off-by: Tom Rini trini@konsulko.com

boot/image-fdt.c | 4 ---- include/configs/P2041RDB.h | 1 - include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 2 -- include/configs/T208xQDS.h | 2 -- include/configs/T208xRDB.h | 2 -- include/configs/T4240RDB.h | 2 -- include/configs/corenet_ds.h | 1 - include/configs/kmcent2.h | 2 -- include/configs/ls1043a_common.h | 2 -- include/configs/ls1046a_common.h | 1 - lib/Kconfig | 10 ++++++++++ 12 files changed, 10 insertions(+), 21 deletions(-)

Reviewed-by: Simon Glass sjg@chromium.org

Tom Rini

13 Aug 13 Aug

3:42 a.m.

New subject: [PATCH 01/21] Convert CONFIG_SYS_FDT_PAD to Kconfig

On Tue, Aug 02, 2022 at 07:33:27AM -0400, Tom Rini wrote:

...

This converts the following to Kconfig: CONFIG_SYS_FDT_PAD

Signed-off-by: Tom Rini trini@konsulko.com Reviewed-by: Simon Glass sjg@chromium.org

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 02/21] ppc: Remove ids8313 board

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Heiko Schocher hs@denx.de Signed-off-by: Tom Rini trini@konsulko.com --- arch/powerpc/cpu/mpc83xx/Kconfig | 7 - board/ids/ids8313/Kconfig | 12 -- board/ids/ids8313/MAINTAINERS | 6 - board/ids/ids8313/Makefile | 9 -- board/ids/ids8313/ids8313.c | 216 ---------------------------- configs/ids8313_defconfig | 216 ---------------------------- include/configs/ids8313.h | 237 ------------------------------- 7 files changed, 703 deletions(-) delete mode 100644 board/ids/ids8313/Kconfig delete mode 100644 board/ids/ids8313/MAINTAINERS delete mode 100644 board/ids/ids8313/Makefile delete mode 100644 board/ids/ids8313/ids8313.c delete mode 100644 configs/ids8313_defconfig delete mode 100644 include/configs/ids8313.h

diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 9a31604ba3e6..9d24f029b397 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -26,12 +26,6 @@ config TARGET_MPC837XERDB select BOARD_EARLY_INIT_F select SYS_83XX_DDR_USES_CS0

-config TARGET_IDS8313 - bool "Support ids8313" - select ARCH_MPC8313 - select DM - imply CMD_DM - config TARGET_KMETER1 bool "Support kmeter1" select VENDOR_KM @@ -212,7 +206,6 @@ config FSL_ELBC bool

source "board/freescale/mpc837xerdb/Kconfig" -source "board/ids/ids8313/Kconfig" source "board/gdsys/mpc8308/Kconfig"

endmenu diff --git a/board/ids/ids8313/Kconfig b/board/ids/ids8313/Kconfig deleted file mode 100644 index d165b4be7a12..000000000000 --- a/board/ids/ids8313/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IDS8313 - -config SYS_BOARD - default "ids8313" - -config SYS_VENDOR - default "ids" - -config SYS_CONFIG_NAME - default "ids8313" - -endif diff --git a/board/ids/ids8313/MAINTAINERS b/board/ids/ids8313/MAINTAINERS deleted file mode 100644 index c5b2f9ed0a3a..000000000000 --- a/board/ids/ids8313/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -IDS8313 BOARD -M: Heiko Schocher hs@denx.de -S: Maintained -F: board/ids/ids8313/ -F: include/configs/ids8313.h -F: configs/ids8313_defconfig diff --git a/board/ids/ids8313/Makefile b/board/ids/ids8313/Makefile deleted file mode 100644 index 91e4ad6f124a..000000000000 --- a/board/ids/ids8313/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2013 -# Heiko Schocher, DENX Software Engineering, hs@denx.de - -obj-y = ids8313.o diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c deleted file mode 100644 index 48aea71be637..000000000000 --- a/board/ids/ids8313/ids8313.c +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (c) 2011 IDS GmbH, Germany - * ids8313.c - ids8313 board support. - * - * Sergej Stepanov ste@ids.de - * Based on board/freescale/mpc8313erdb/mpc8313erdb.c - */ - -#include <common.h> -#include <fdt_support.h> -#include <init.h> -#include <mpc83xx.h> -#include <spi.h> -#include <asm/bitops.h> -#include <asm/global_data.h> -#include <linux/delay.h> -#include <linux/libfdt.h> - -DECLARE_GLOBAL_DATA_PTR; -/** CPLD contains the info about: - * - board type: *pCpld & 0xF0 - * - hw-revision: *pCpld & 0x0F - * - cpld-revision: *pCpld+1 - */ -int checkboard(void) -{ - char *pcpld = (char *)CONFIG_SYS_CPLD_BASE; - u8 u8Vers = readb(pcpld); - u8 u8Revs = readb(pcpld + 1); - - printf("Board: "); - switch (u8Vers & 0xF0) { - case '\x40': - printf("CU73X"); - break; - case '\x50': - printf("CC73X"); - break; - default: - printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs); - return 0; - } - printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n", - u8Vers & 0x0F, u8Revs & 0xFF); - return 0; -} - -/* - * fixed sdram init - */ -int fixed_sdram(unsigned long config) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_SDRAM_SIZE; - -#ifndef CONFIG_SYS_RAMBOOT - u32 msize_log2 = __ilog2(msize); - - out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); - out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); - out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); - sync(); - - /* - * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], - * or the DDR2 controller may fail to initialize correctly. - */ - udelay(50000); - - out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); - out_be32(&im->ddr.cs_config[0], config); - - /* currently we use only one CS, so disable the other banks */ - out_be32(&im->ddr.cs_config[1], 0); - out_be32(&im->ddr.cs_config[2], 0); - out_be32(&im->ddr.cs_config[3], 0); - - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); - - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); - - out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); - sync(); - udelay(300); - - /* enable DDR controller */ - setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); - /* now check the real size */ - disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); - enable_addr_trans(); -#endif - return msize; -} - -static int setup_sdram(void) -{ - u32 msize = CONFIG_SYS_SDRAM_SIZE; - long int size_01, size_02; - - size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG); - size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256); - - if (size_01 > size_02) - msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG); - else - msize = size_02; - - return msize; -} - -int dram_init(void) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - fsl_lbc_t *lbc = &im->im_lbc; - u32 msize = 0; - - if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) - return -ENXIO; - - msize = setup_sdram(); - - out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF)); - out_be32(&lbc->mrtpr, 0x20000000); - sync(); - - gd->ram_size = msize; - - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif - -/* gpio mask for spi_cs */ -#define IDSCPLD_SPI_CS_MASK 0x00000001 -/* spi_cs multiplexed through cpld */ -#define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf) - -#if defined(CONFIG_MISC_INIT_R) -/* srp umcr mask for rts */ -#define IDSUMCR_RTS_MASK 0x04 -int misc_init_r(void) -{ - /*srp*/ - duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0]; - duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1]; - - gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; - - /* deactivate spi_cs channels */ - out_8(spi_base, 0); - /* deactivate the spi_cs */ - setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK); - /*srp - deactivate rts*/ - out_8(&uart1->umcr, IDSUMCR_RTS_MASK); - out_8(&uart2->umcr, IDSUMCR_RTS_MASK); - - - gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE; - return 0; -} -#endif - -#ifdef CONFIG_MPC8XXX_SPI -/* - * The following are used to control the SPI chip selects - */ -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && ((cs >= 0) && (cs <= 2)); -} - -void spi_cs_activate(struct spi_slave *slave) -{ - gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; - - /* select the spi_cs channel */ - out_8(spi_base, 1 << slave->cs); - /* activate the spi_cs */ - clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; - - /* select the spi_cs channel */ - out_8(spi_base, 1 << slave->cs); - /* deactivate the spi_cs */ - setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); -} -#endif diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig deleted file mode 100644 index 1f0a86469702..000000000000 --- a/configs/ids8313_defconfig +++ /dev/null @@ -1,216 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF00000 -CONFIG_SYS_MALLOC_LEN=0x800000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_BOOTCOUNT_ADDR=0x9 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_ENV_ADDR=0xFFFC0000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_IDS8313=y -CONFIG_CORE_PLL_RATIO_2_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="INITRAM" -CONFIG_BAT1_BASE=0xFD000000 -CONFIG_BAT1_LENGTH_256_KBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_GUARDED=y -CONFIG_BAT1_DCACHE_GUARDED=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="FLASH" -CONFIG_BAT2_BASE=0xFF800000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_GUARDED=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="IMMR" -CONFIG_BAT5_BASE=0xF0000000 -CONFIG_BAT5_LENGTH_128_MBYTES=y -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_ICACHE_INHIBITED=y -CONFIG_BAT5_ICACHE_GUARDED=y -CONFIG_BAT5_DCACHE_INHIBITED=y -CONFIG_BAT5_DCACHE_GUARDED=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="NAND_MRAM_CPLD" -CONFIG_BAT6_BASE=0xE0000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_GUARDED=y -CONFIG_BAT6_DCACHE_GUARDED=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_NAND_LBLAWBAR_PRELIM_1=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFF800000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_8_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xE1000000 -CONFIG_LBLAW1_NAME="NAND" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_LBLAW2=y -CONFIG_LBLAW2_BASE=0xE2000000 -CONFIG_LBLAW2_NAME="MRAM" -CONFIG_LBLAW2_LENGTH_128_KBYTES=y -CONFIG_LBLAW3=y -CONFIG_LBLAW3_BASE=0xE3000000 -CONFIG_LBLAW3_NAME="CPLD" -CONFIG_LBLAW3_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFF800000 -CONFIG_OR0_AM_8_MBYTES=y -CONFIG_OR0_SCY_10=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="NAND" -CONFIG_BR1_OR1_BASE=0xE1000000 -CONFIG_BR1_ERRORCHECKING_BOTH=y -CONFIG_BR1_MACHINE_FCM=y -CONFIG_OR1_SCY_4=y -CONFIG_OR1_PGS_LARGE=y -CONFIG_OR1_CSCT_8_CYCLE=y -CONFIG_OR1_CST_ONE_CLOCK=y -CONFIG_OR1_CHT_TWO_CLOCK=y -CONFIG_OR1_RST_ONE_CLOCK=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_ELBC_BR2_OR2=y -CONFIG_BR2_OR2_NAME="MRAM" -CONFIG_BR2_OR2_BASE=0xE2000000 -CONFIG_OR2_AM_128_KBYTES=y -CONFIG_OR2_SCY_7=y -CONFIG_OR2_CSNT_EARLIER=y -CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y -CONFIG_OR2_TRLX_RELAXED=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="CPLD" -CONFIG_BR3_OR3_BASE=0xE3000000 -CONFIG_OR3_SCY_1=y -CONFIG_OR3_CSNT_EARLIER=y -CONFIG_OR3_TRLX_RELAXED=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_LCRR_EADC_1=y -CONFIG_LCRR_CLKDIV_2=y -CONFIG_SYS_BARGSIZE=1024 -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=1 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n" -CONFIG_AUTOBOOT_DELAY_STR="ids" -CONFIG_BOOT_RETRY=y -CONFIG_BOOT_RETRY_TIME=900 -CONFIG_BOOT_RETRY_MIN=30 -CONFIG_RESET_TO_RETRY=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run boot_cramfs" -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_CBSIZE=1024 -CONFIG_SYS_BOOTM_LEN=0x800000 -CONFIG_CMD_IMLS=y -CONFIG_CMD_ENV_FLAGS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_CMD_NAND_TRIMFFS=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=ff800000.flash,nand0=e1000000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:7m(dum),768k(BOOT-BIN),128k(BOOT-ENV),128k(BOOT-REDENV);e1000000.flash:-(ubi)" -CONFIG_CMD_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR_REDUND=0xFFFE0000 -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="ids8313/uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="TSEC1" -CONFIG_VERSION_VARIABLE=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_I2C=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xFF800801 -CONFIG_SYS_OR0_PRELIM=0xFF8008A7 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE1000C21 -CONFIG_SYS_OR1_PRELIM=0xFFFF87CE -CONFIG_SYS_BR2_PRELIM_BOOL=y -CONFIG_SYS_BR2_PRELIM=0xE2000801 -CONFIG_SYS_OR2_PRELIM=0xFFFE0C74 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xE3000801 -CONFIG_SYS_OR3_PRELIM=0xFFFF8814 -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=400000 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_MAX_FLASH_SECT=128 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_ELBC=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -# CONFIG_PCI is not set -CONFIG_RTC_PCF8563=y -CONFIG_SYS_NS16550=y -CONFIG_WATCHDOG=y -CONFIG_JFFS2_NAND=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h deleted file mode 100644 index e89b800b7eeb..000000000000 --- a/include/configs/ids8313.h +++ /dev/null @@ -1,237 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (c) 2011 IDS GmbH, Germany - * Sergej Stepanov ste@ids.de - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - */ - -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) - -#define CONFIG_HWCONFIG - -/* - * Definitions for initial stack pointer and data area (in DCACHE ) - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ - -/* - * Internal Definitions - */ -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* - * Manually set up DDR parameters, - * as this board has not the SPD connected to I2C. - */ -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ - 0x00010000 |\ - CSCONFIG_ROW_BIT_13 |\ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ - CSCONFIG_BANK_BIT_3) - -#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ -#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ - (3 << TIMING_CFG0_WRT_SHIFT) |\ - (3 << TIMING_CFG0_RRT_SHIFT) |\ - (3 << TIMING_CFG0_WWT_SHIFT) |\ - (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_MRS_CYC_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ - (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\ - (4 << TIMING_CFG1_ACTTORW_SHIFT) |\ - (7 << TIMING_CFG1_CASLAT_SHIFT) |\ - (4 << TIMING_CFG1_REFREC_SHIFT) |\ - (4 << TIMING_CFG1_WRREC_SHIFT) |\ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\ - (2 << TIMING_CFG1_WRTORD_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ - (5 << TIMING_CFG2_CPO_SHIFT) |\ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\ - (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\ - (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\ - (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) - -#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\ - (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - -#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\ - SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\ - SDRAM_CFG_DBW_32 |\ - SDRAM_CFG_SDRAM_TYPE_DDR2) - -#define CONFIG_SYS_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\ - (0x0242 << SDRAM_MODE_SD_SHIFT)) -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\ - DDRCDR_PZ_NOMZ |\ - DDRCDR_NZ_NOMZ |\ - DDRCDR_ODT |\ - DDRCDR_M_ODR |\ - DDRCDR_Q_DRN) - -/* - * on-board devices - */ -#define CONFIG_TSEC1 -#define CONFIG_TSEC2 - -/* - * NOR FLASH setup - */ -#define CONFIG_FLASH_SHOW_PROGRESS 50 - -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#define CONFIG_SYS_FLASH_SIZE 8 - -/* - * NAND FLASH setup - */ -#define CONFIG_SYS_NAND_BASE 0xE1000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_CACHE_PAGES 64 - - -/* - * MRAM setup - */ -#define CONFIG_SYS_MRAM_BASE 0xE2000000 -#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */ - -/* - * CPLD setup - */ -#define CONFIG_SYS_CPLD_BASE 0xE3000000 - -/* - * HW-Watchdog - */ -#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF - -/* - * I2C setup - */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * Ethernet setup - */ -#ifdef CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x1 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC1_PHYIDX 0 -#endif - -#ifdef CONFIG_TSEC2 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC2_PHY_ADDR 0x3 -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC2_PHYIDX 0 -#endif - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) - -#define CONFIG_SYS_SCCR_USBDRCM 3 - -/* - * U-Boot environment setup - */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Environment Configuration - */ - -#define CONFIG_NETDEV eth1 -#define CONFIG_HOSTNAME "ids8313" -#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx" -#define CONFIG_UBOOTPATH "ids8313/u-boot.bin" -#define CONFIG_FDTFILE "ids8313/ids8313.dtb" -#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" - -/* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_LOADS_ECHO -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -/* mtdparts command line support */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" __stringify(CONFIG_NETDEV) "\0" \ - "ethprime=TSEC1\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot ${loadaddr} ${uboot}; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +${filesize}; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +${filesize}; " \ - "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ - " ${filesize}; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +${filesize}; " \ - "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ - " ${filesize}\0" \ - "console=ttyS0\0" \ - "fdtaddr=0x780000\0" \ - "kernel_addr=ff800000\0" \ - "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \ - "setbootargs=setenv bootargs " \ - "root=${rootdev} rw console=${console}," \ - "${baudrate} ${othbootargs}\0" \ - "setipargs=setenv bootargs root=${rootdev} rw " \ - "nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off " \ - "console=${console},${baudrate} ${othbootargs}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "\0" - -/* UBI Support */ - -#endif /* __CONFIG_H */

-- 2.25.1

Heiko Schocher

1:45 p.m.

New subject: [PATCH 02/21] ppc: Remove ids8313 board

Hello Tom,

On 02.08.22 13:33, Tom Rini wrote:

...

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Heiko Schocher hs@denx.de Signed-off-by: Tom Rini trini@konsulko.com

arch/powerpc/cpu/mpc83xx/Kconfig | 7 - board/ids/ids8313/Kconfig | 12 -- board/ids/ids8313/MAINTAINERS | 6 - board/ids/ids8313/Makefile | 9 -- board/ids/ids8313/ids8313.c | 216 ---------------------------- configs/ids8313_defconfig | 216 ---------------------------- include/configs/ids8313.h | 237 ------------------------------- 7 files changed, 703 deletions(-) delete mode 100644 board/ids/ids8313/Kconfig delete mode 100644 board/ids/ids8313/MAINTAINERS delete mode 100644 board/ids/ids8313/Makefile delete mode 100644 board/ids/ids8313/ids8313.c delete mode 100644 configs/ids8313_defconfig delete mode 100644 include/configs/ids8313.h

Acked-by: Heiko Schocher hs@denx.de

bye, Heiko

-- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: hs@denx.de

Tom Rini

13 Aug 13 Aug

3:42 a.m.

New subject: [PATCH 02/21] ppc: Remove ids8313 board

On Tue, Aug 02, 2022 at 07:33:28AM -0400, Tom Rini wrote:

...

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Heiko Schocher hs@denx.de Signed-off-by: Tom Rini trini@konsulko.com Acked-by: Heiko Schocher hs@denx.de

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 03/21] arm: Remove snapper9260 board

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Simon Glass sjg@chromium.org Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-at91/Kconfig | 10 -- board/bluewater/snapper9260/Kconfig | 12 -- board/bluewater/snapper9260/MAINTAINERS | 7 - board/bluewater/snapper9260/Makefile | 9 -- board/bluewater/snapper9260/snapper9260.c | 154 ---------------------- configs/snapper9260_defconfig | 58 -------- configs/snapper9g20_defconfig | 57 -------- include/configs/snapper9260.h | 80 ----------- 8 files changed, 387 deletions(-) delete mode 100644 board/bluewater/snapper9260/Kconfig delete mode 100644 board/bluewater/snapper9260/MAINTAINERS delete mode 100644 board/bluewater/snapper9260/Makefile delete mode 100644 board/bluewater/snapper9260/snapper9260.c delete mode 100644 configs/snapper9260_defconfig delete mode 100644 configs/snapper9g20_defconfig delete mode 100644 include/configs/snapper9260.h

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 11bfd5afe745..094c9891f648 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -79,15 +79,6 @@ config TARGET_ETHERNUT5 bool "Ethernut5 board" select AT91SAM9XE

-config TARGET_SNAPPER9260 - bool "Support snapper9260" - select AT91SAM9260 - select AT91_WANTS_COMMON_PHY - select DM - select DM_GPIO - select DM_SERIAL - imply CMD_DM - config TARGET_GURNARD bool "Support gurnard" select AT91SAM9G45 @@ -364,7 +355,6 @@ source "board/atmel/sama5d3xek/Kconfig" source "board/atmel/sama5d4_xplained/Kconfig" source "board/atmel/sama5d4ek/Kconfig" source "board/bluewater/gurnard/Kconfig" -source "board/bluewater/snapper9260/Kconfig" source "board/calao/usb_a9263/Kconfig" source "board/egnite/ethernut5/Kconfig" source "board/esd/meesc/Kconfig" diff --git a/board/bluewater/snapper9260/Kconfig b/board/bluewater/snapper9260/Kconfig deleted file mode 100644 index b8e9cbc58559..000000000000 --- a/board/bluewater/snapper9260/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SNAPPER9260 - -config SYS_BOARD - default "snapper9260" - -config SYS_VENDOR - default "bluewater" - -config SYS_CONFIG_NAME - default "snapper9260" - -endif diff --git a/board/bluewater/snapper9260/MAINTAINERS b/board/bluewater/snapper9260/MAINTAINERS deleted file mode 100644 index 1f8f4d6988f5..000000000000 --- a/board/bluewater/snapper9260/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -SNAPPER9260 BOARD -M: Simon Glass sjg@chromium.org -S: Maintained -F: board/bluewater/snapper9260/ -F: include/configs/snapper9260.h -F: configs/snapper9260_defconfig -F: configs/snapper9g20_defconfig diff --git a/board/bluewater/snapper9260/Makefile b/board/bluewater/snapper9260/Makefile deleted file mode 100644 index 842abf4eeeb5..000000000000 --- a/board/bluewater/snapper9260/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2011 Bluewater Systems -# Ryan Mallon ryan@bluewatersys.com - -obj-y += snapper9260.o diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c deleted file mode 100644 index df53a651c395..000000000000 --- a/board/bluewater/snapper9260/snapper9260.c +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Bluewater Systems Snapper 9260/9G20 modules - * - * (C) Copyright 2011 Bluewater Systems - * Author: Andre Renaud andre@bluewatersys.com - * Author: Ryan Mallon ryan@bluewatersys.com - */ - -#include <common.h> -#include <dm.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <asm/mach-types.h> -#include <asm/arch/at91sam9260_matrix.h> -#include <asm/arch/at91sam9_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> -#include <asm/arch/atmel_serial.h> -#include <net.h> -#include <netdev.h> -#include <i2c.h> -#include <pca953x.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* IO Expander pins */ -#define IO_EXP_ETH_RESET (0 << 1) -#define IO_EXP_ETH_POWER (1 << 1) - -static void macb_hw_init(void) -{ - struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; - - at91_periph_clk_enable(ATMEL_ID_EMAC0); - - /* Disable pull-ups to prevent PHY going into test mode */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA18), - &pioa->pudr); - - /* Power down ethernet */ - pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT); - pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1); - - /* Hold ethernet in reset */ - pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT); - pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0); - - /* Enable ethernet power */ - pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0); - - at91_phy_reset(); - - /* Bring the ethernet out of reset */ - pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1); - - /* The phy internal reset take 21ms */ - udelay(21 * 1000); - - /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA18), - &pioa->puer); - - at91_macb_hw_init(); -} - -static void nand_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - unsigned long csa; - - /* Enable CS3 as NAND/SmartMedia */ - csa = readl(&matrix->ebicsa); - csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; - writel(csa, &matrix->ebicsa); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | - AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(3), - &smc->cs[3].mode); - - /* Configure RDY/BSY */ - gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy"); - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); - - /* Enable NandFlash */ - gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce"); - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); -} - -int board_init(void) -{ - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - - /* The mach-type is the same for both Snapper 9260 and 9G20 */ - gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260; - - /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - /* Initialise peripherals */ - at91_seriald_hw_init(); - i2c_set_bus_num(0); - nand_hw_init(); - macb_hw_init(); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f); -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); - return 0; -} - -void reset_phy(void) -{ -} - -static struct atmel_serial_plat at91sam9260_serial_plat = { - .base_addr = ATMEL_BASE_DBGU, -}; - -U_BOOT_DRVINFO(at91sam9260_serial) = { - .name = "serial_atmel", - .plat = &at91sam9260_serial_plat, -}; diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig deleted file mode 100644 index 9fb55dc9af36..000000000000 --- a/configs/snapper9260_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_AT91=y -CONFIG_SYS_TEXT_BASE=0x21f00000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_SNAPPER9260=y -CONFIG_AT91_GPIO_PULLUP=y -CONFIG_ATMEL_LEGACY=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_SYS_LOAD_ADDR=0x23000000 -CONFIG_FIT=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 ip=any" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Snapper> " -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=282 -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_NAND=y -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -# CONFIG_CMD_MDIO is not set -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RETRY_COUNT=20 -CONFIG_TFTP_PORT=y -CONFIG_TFTP_TSIZE=y -CONFIG_AT91_GPIO=y -CONFIG_CMD_PCA953X=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x7F -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -# CONFIG_SYS_NAND_USE_FLASH_BBT is not set -CONFIG_NAND_ATMEL=y -CONFIG_MACB=y -CONFIG_RMII=y -CONFIG_ATMEL_USART=y diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig deleted file mode 100644 index aa765c417793..000000000000 --- a/configs/snapper9g20_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_AT91=y -CONFIG_SYS_TEXT_BASE=0x21f00000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_SNAPPER9260=y -CONFIG_AT91_GPIO_PULLUP=y -CONFIG_ATMEL_LEGACY=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_SYS_LOAD_ADDR=0x23000000 -CONFIG_FIT=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 ip=any" -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=276 -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_NAND=y -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -# CONFIG_CMD_MDIO is not set -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RETRY_COUNT=20 -CONFIG_TFTP_PORT=y -CONFIG_TFTP_TSIZE=y -CONFIG_AT91_GPIO=y -CONFIG_CMD_PCA953X=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x7F -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -# CONFIG_SYS_NAND_USE_FLASH_BBT is not set -CONFIG_NAND_ATMEL=y -CONFIG_MACB=y -CONFIG_RMII=y -CONFIG_ATMEL_USART=y diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h deleted file mode 100644 index 7adb349f9a54..000000000000 --- a/include/configs/snapper9260.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Bluewater Systems Snapper 9260 and 9G20 modules - * - * (C) Copyright 2011 Bluewater Systems - * Author: Andre Renaud andre@bluewatersys.com - * Author: Ryan Mallon ryan@bluewatersys.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SoC type is defined in boards.cfg */ -#include <asm/hardware.h> -#include <linux/sizes.h> - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 - -/* CPU */ - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 - -/* Mem test settings */ - -/* NAND Flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 - -/* GPIOs and IO expander */ -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } - -/* UARTs/Serial console */ -#ifndef CONFIG_DM_SERIAL -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS -#endif - -/* I2C - Bit-bashed */ -#define CONFIG_SOFT_I2C_READ_REPEATED_START -#define I2C_INIT do { \ - at91_set_gpio_output(AT91_PIN_PA23, 1); \ - at91_set_gpio_output(AT91_PIN_PA24, 1); \ - at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ - at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ - } while (0) -#define I2C_SOFT_DECLARATIONS -#define I2C_ACTIVE -#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1); -#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23); -#define I2C_SDA(bit) do { \ - if (bit) { \ - at91_set_gpio_input(AT91_PIN_PA23, 1); \ - } else { \ - at91_set_gpio_output(AT91_PIN_PA23, 1); \ - at91_set_gpio_value(AT91_PIN_PA23, bit); \ - } \ - } while (0) -#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) -#define I2C_DELAY udelay(2) - -/* Boot options */ - -/* Environment settings */ - -/* Console settings */ - -#endif /* __CONFIG_H */

-- 2.25.1

Simon Glass

8 Aug 8 Aug

9:26 p.m.

New subject: [PATCH 03/21] arm: Remove snapper9260 board

On Tue, 2 Aug 2022 at 05:34, Tom Rini trini@konsulko.com wrote:

...

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Simon Glass sjg@chromium.org Signed-off-by: Tom Rini trini@konsulko.com

arch/arm/mach-at91/Kconfig | 10 -- board/bluewater/snapper9260/Kconfig | 12 -- board/bluewater/snapper9260/MAINTAINERS | 7 - board/bluewater/snapper9260/Makefile | 9 -- board/bluewater/snapper9260/snapper9260.c | 154 ---------------------- configs/snapper9260_defconfig | 58 -------- configs/snapper9g20_defconfig | 57 -------- include/configs/snapper9260.h | 80 ----------- 8 files changed, 387 deletions(-) delete mode 100644 board/bluewater/snapper9260/Kconfig delete mode 100644 board/bluewater/snapper9260/MAINTAINERS delete mode 100644 board/bluewater/snapper9260/Makefile delete mode 100644 board/bluewater/snapper9260/snapper9260.c delete mode 100644 configs/snapper9260_defconfig delete mode 100644 configs/snapper9g20_defconfig delete mode 100644 include/configs/snapper9260.h

Reviewed-by: Simon Glass sjg@chromium.org

Tom Rini

13 Aug 13 Aug

3:42 a.m.

New subject: [PATCH 03/21] arm: Remove snapper9260 board

On Tue, Aug 02, 2022 at 07:33:29AM -0400, Tom Rini wrote:

...

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Simon Glass sjg@chromium.org Signed-off-by: Tom Rini trini@konsulko.com Reviewed-by: Simon Glass sjg@chromium.org

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 04/21] arm: Remove mx28evk board

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Fabio Estevam festevam@gmail.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/dts/Makefile | 1 - arch/arm/dts/imx28-evk.dts | 360 ------------------------ arch/arm/mach-imx/mxs/Kconfig | 5 - board/freescale/mx28evk/Kconfig | 15 - board/freescale/mx28evk/MAINTAINERS | 10 - board/freescale/mx28evk/Makefile | 10 - board/freescale/mx28evk/README | 62 ---- board/freescale/mx28evk/iomux.c | 205 -------------- board/freescale/mx28evk/mx28evk.c | 74 ----- configs/mx28evk_auart_console_defconfig | 59 ---- configs/mx28evk_defconfig | 68 ----- configs/mx28evk_nand_defconfig | 62 ---- configs/mx28evk_spi_defconfig | 57 ---- include/configs/mx28evk.h | 183 ------------ 14 files changed, 1171 deletions(-) delete mode 100644 arch/arm/dts/imx28-evk.dts delete mode 100644 board/freescale/mx28evk/Kconfig delete mode 100644 board/freescale/mx28evk/MAINTAINERS delete mode 100644 board/freescale/mx28evk/Makefile delete mode 100644 board/freescale/mx28evk/README delete mode 100644 board/freescale/mx28evk/iomux.c delete mode 100644 board/freescale/mx28evk/mx28evk.c delete mode 100644 configs/mx28evk_auart_console_defconfig delete mode 100644 configs/mx28evk_defconfig delete mode 100644 configs/mx28evk_nand_defconfig delete mode 100644 configs/mx28evk_spi_defconfig delete mode 100644 include/configs/mx28evk.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ceaa39e4b4d6..5c1a61a01c2f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -741,7 +741,6 @@ dtb-$(CONFIG_TARGET_MX23_OLINUXINO) += \ imx23-olinuxino.dtb

dtb-$(CONFIG_MX28) += \ - imx28-evk.dtb \ imx28-xea.dtb

dtb-$(CONFIG_MX51) += \ diff --git a/arch/arm/dts/imx28-evk.dts b/arch/arm/dts/imx28-evk.dts deleted file mode 100644 index 7e2b0f198dfa..000000000000 --- a/arch/arm/dts/imx28-evk.dts +++ /dev/null @@ -1,360 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Copyright 2012 Freescale Semiconductor, Inc. - -/dts-v1/; -#include "imx28.dtsi" - -/ { - model = "Freescale i.MX28 Evaluation Kit"; - compatible = "fsl,imx28-evk", "fsl,imx28"; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vddio_sd0: regulator-vddio-sd0 { - compatible = "regulator-fixed"; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 28 0>; - }; - - reg_fec_3v3: regulator-fec-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fec-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 15 0>; - }; - - reg_usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 9 0>; - enable-active-high; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 8 0>; - enable-active-high; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 0>; - enable-active-high; - }; - - reg_can_3v3: regulator-can-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 13 0>; - enable-active-high; - }; - - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <&reg_lcd_3v3>; - avdd-supply = <&reg_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; - - apb@80000000 { - apbh@80000000 { - nand-controller@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg - &gpmi_pins_evk>; - status = "okay"; - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - wp-gpios = <&gpio2 12 0>; - vmmc-supply = <&reg_vddio_sd0>; - status = "okay"; - }; - - ssp1: spi@80012000 { - compatible = "fsl,imx28-mmc"; - bus-width = <8>; - wp-gpios = <&gpio0 28 0>; - }; - - ssp2: spi@80014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP1_CMD__GPIO_2_13 - MX28_PAD_SSP1_DATA3__GPIO_2_15 - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - MX28_PAD_SSP1_SCK__GPIO_2_12 - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_LCD_RESET__GPIO_3_30 - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_AUART2_TX__GPIO_3_9 - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - led_pin_gpio3_5: led_gpio3_5@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - gpmi_pins_evk: gpmi-nand-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE1N__GPMI_CE1N - MX28_PAD_GPMI_RDY1__GPMI_READY1 - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - lcdif_pins_evk: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_evk>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - can0: can@80032000 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <&reg_can_3v3>; - status = "okay"; - }; - - can1: can@80034000 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - xceiver-supply = <&reg_can_3v3>; - status = "okay"; - }; - }; - - apbx@80040000 { - saif0: saif@80042000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; - }; - - saif1: saif@80046000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - fsl,ave-ctrl = <4>; - fsl,ave-delay = <2>; - fsl,settling = <10>; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <&reg_3p3v>; - VDDIO-supply = <&reg_3p3v>; - clocks = <&saif0>; - }; - - at24@51 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x51>; - }; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - uart-has-rtscts; - status = "okay"; - }; - - auart3: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pins_a>; - vbus-supply = <&reg_usb0_vbus>; - status = "okay"; - }; - - usb1: usb@80090000 { - vbus-supply = <&reg_usb1_vbus>; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-supply = <&reg_fec_3v3>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - - sound { - compatible = "fsl,imx28-evk-sgtl5000", - "fsl,mxs-audio-sgtl5000"; - model = "imx28-evk-sgtl5000"; - saif-controllers = <&saif0 &saif1>; - audio-codec = <&sgtl5000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_gpio3_5>; - - user { - label = "Heartbeat"; - gpios = <&gpio3 5 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - backlight_display: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index b2026a3758a5..60518a7957ed 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -39,10 +39,6 @@ choice prompt "MX28 board select" optional

-config TARGET_MX28EVK - bool "Support mx28evk" - select BOARD_EARLY_INIT_F - config TARGET_XEA bool "Support XEA"

@@ -51,7 +47,6 @@ endchoice config SYS_SOC default "mxs"

-source "board/freescale/mx28evk/Kconfig" source "board/liebherr/xea/Kconfig"

endif diff --git a/board/freescale/mx28evk/Kconfig b/board/freescale/mx28evk/Kconfig deleted file mode 100644 index 39777bd70fae..000000000000 --- a/board/freescale/mx28evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX28EVK - -config SYS_BOARD - default "mx28evk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "mx28evk" - -endif diff --git a/board/freescale/mx28evk/MAINTAINERS b/board/freescale/mx28evk/MAINTAINERS deleted file mode 100644 index c565010ccf6b..000000000000 --- a/board/freescale/mx28evk/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -MX28EVK BOARD -M: Fabio Estevam festevam@gmail.com -S: Maintained -F: board/freescale/mx28evk/ -F: arch/arm/dts/imx28-evk.dts -F: include/configs/mx28evk.h -F: configs/mx28evk_defconfig -F: configs/mx28evk_auart_console_defconfig -F: configs/mx28evk_nand_defconfig -F: configs/mx28evk_spi_defconfig diff --git a/board/freescale/mx28evk/Makefile b/board/freescale/mx28evk/Makefile deleted file mode 100644 index 057760433da9..000000000000 --- a/board/freescale/mx28evk/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_SPL_BUILD -obj-y := mx28evk.o -else -obj-y := iomux.o -endif diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README deleted file mode 100644 index d32f0efb3326..000000000000 --- a/board/freescale/mx28evk/README +++ /dev/null @@ -1,62 +0,0 @@ -FREESCALE MX28EVK -================== - -Supported hardware: MX28EVK rev C and D are supported in U-Boot. - -Files of the MX28EVK port --------------------------- - -arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28 -arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28 -board/freescale/mx28evk/ - MX28EVK board specific files -include/configs/mx28evk.h - MX28EVK configuration file - -Jumper configuration ---------------------- - -To boot MX28EVK from an SD card, set the boot mode DIP switches as: - - * Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42) - * JTAG PSWITCH RESET: To the right (reset disabled) - * Battery Source: Down - * Wall 5V: Up - * VDD 5V: To the left (off) - * Hold Button: Down (off) - -To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as: - - * Boot Mode Select: 0 0 1 0 (Boot from SSP2) - * JTAG PSWITCH RESET: To the right (reset disabled) - * Battery Source: Down - * Wall 5V: Up - * VDD 5V: To the left (off) - * Hold Button: Down (off) - -Environment Storage -------------------- - -There are three targets for mx28evk: - -"make mx28evk_config" - store environment variables into MMC - -or - -"make mx28evk_nand_config" - store environment variables into NAND flash - -or - -"make mx28evk_spi_config" - store environment variables into SPI NOR flash - -Choose the target accordingly. - -Note: The mx28evk board does not come with a NAND flash populated from the -factory. It comes with an empty slot (U23), which allows the insertion of a -48-pin TSOP flash device. - -mx28evk does not come with SPI NOR flash populated from the factory either. -It is possible to solder a SOIC memory on U49 or use a DIP8 on J89. -To get SPI communication to work R320, R321,R322 and C178 need to be populated. -Look in the schematics for the proper component values. - -Follow the instructions from doc/imx/common/mxs.txt to generate a bootable -SD card or to generate a binary to be flashed into SPI NOR. diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c deleted file mode 100644 index cc0c85885446..000000000000 --- a/board/freescale/mx28evk/iomux.c +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale MX28EVK IOMUX setup - * - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* write protect */ - MX28_PAD_SSP1_SCK__GPIO_2_12, - /* MMC0 slot power enable */ - MX28_PAD_PWM3__GPIO_3_28 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - -#ifdef CONFIG_NAND_MXS - /* GPMI NAND */ - MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDN__GPMI_RDN | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, -#endif - - /* FEC0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, - /* FEC0 Enable */ - MX28_PAD_SSP1_DATA3__GPIO_2_15 | - (MXS_PAD_12MA | MXS_PAD_3V3), - /* FEC0 Reset */ - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - - /* FEC1 */ - MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, - - /* EMI */ - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - - /* SPI2 (for SPI flash) */ - MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_SS0__SSP2_D3 | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* LCD */ - MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, - MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, - MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD, - MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD, - MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD, - MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */ - MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */ -}; - -#define HW_DRAM_CTL29 (0x74 >> 2) -#define CS_MAP 0xf -#define COLUMN_SIZE 0x2 -#define ADDR_PINS 0x1 -#define APREBIT 0xa - -#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ - ADDR_PINS << 8 | APREBIT) - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c deleted file mode 100644 index 88c3bf36089c..000000000000 --- a/board/freescale/mx28evk/mx28evk.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale MX28EVK board - * - * (C) Copyright 2011 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam fabio.estevam@freescale.com - * - * Based on m28evk.c: - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx28.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <linux/delay.h> -#include <linux/mii.h> -#include <miiphy.h> -#include <netdev.h> -#include <errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - /* SSP2 clock at 160MHz */ - mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); - -#ifdef CONFIG_CMD_USB - mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); - mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 | - MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL); - gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1); -#endif - - /* Power on LCD */ - gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1); - - /* Set contrast to maximum */ - gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig deleted file mode 100644 index b9c85d616079..000000000000 --- a/configs/mx28evk_auart_console_defconfig +++ /dev/null @@ -1,59 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_IMX_CONFIG="" -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x42000000 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_BSS_LIMIT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_SPLASH_SCREEN=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig deleted file mode 100644 index bdfad9fec622..000000000000 --- a/configs/mx28evk_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x40000 -CONFIG_IMX_CONFIG="" -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx28-evk" -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x42000000 -CONFIG_FIT=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_BSS_LIMIT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_DM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_VERSION_VARIABLE=y -# CONFIG_NET is not set -CONFIG_DM=y -CONFIG_SPL_DM=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MXS=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_SPLASH_SCREEN=y diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig deleted file mode 100644 index 136c1d60699b..000000000000 --- a/configs/mx28evk_nand_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_IMX_CONFIG="" -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x380000 -CONFIG_SYS_LOAD_ADDR=0x42000000 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_BSS_LIMIT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_SPLASH_SCREEN=y -CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig deleted file mode 100644 index ab8c34c8b164..000000000000 --- a/configs/mx28evk_spi_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX28=y -CONFIG_SYS_TEXT_BASE=0x40002000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x4000 -CONFIG_IMX_CONFIG="" -CONFIG_SPL_TEXT_BASE=0x00001000 -CONFIG_TARGET_MX28EVK=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_SYS_LOAD_ADDR=0x42000000 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NO_BSS_LIMIT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" -CONFIG_CMD_UBI=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_VERSION_VARIABLE=y -CONFIG_MXS_GPIO=y -CONFIG_MMC_MXS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_MII=y -CONFIG_CONS_INDEX=0 -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_SPLASH_SCREEN=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h deleted file mode 100644 index 9f3ac48b70a2..000000000000 --- a/include/configs/mx28evk.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Freescale Semiconductor, Inc. - * Author: Fabio Estevam fabio.estevam@freescale.com - * - * Based on m28evk.h: - * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com - * on behalf of DENX Software Engineering GmbH - */ -#ifndef __CONFIGS_MX28EVK_H__ -#define __CONFIGS_MX28EVK_H__ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* UBI and NAND partitioning */ - -/* RTC */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_MXS -#endif - -/* USB */ - -/* Framebuffer support */ -#ifdef CONFIG_DM_VIDEO -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) -#endif - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ubifs_file=filesystem.ubifs\0" \ - "update_nand_full_filename=u-boot.nand\0" \ - "update_nand_firmware_filename=u-boot.sb\0" \ - "update_nand_firmware_maxsz=0x100000\0" \ - "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ - "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ - "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \ - "nand device 0 ; " \ - "nand info ; " \ - "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ - "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ - "update_nand_firmware_full=" /* Update FCB, DBBT and FW */ \ - "if tftp ${update_nand_full_filename} ; then " \ - "run update_nand_get_fcb_size ; " \ - "nand scrub -y 0x0 ${filesize} ; " \ - "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \ - "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ - "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ - "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ - "fi\0" \ - "update_nand_firmware=" /* Update only firmware */ \ - "if tftp ${update_nand_firmware_filename} ; then " \ - "run update_nand_get_fcb_size ; " \ - "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \ - "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \ - "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \ - "nand erase ${fcb_sz} ${fw_sz} ; " \ - "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ - "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ - "fi\0" \ - "update_nand_kernel=" /* Update kernel */ \ - "mtdparts default; " \ - "nand erase.part kernel; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "nand write ${loadaddr} kernel ${filesize}\0" \ - "update_nand_fdt=" /* Update fdt */ \ - "mtdparts default; " \ - "nand erase.part fdt; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${fdt_file}; " \ - "nand write ${loadaddr} fdt ${filesize}\0" \ - "update_nand_filesystem=" /* Update filesystem */ \ - "mtdparts default; " \ - "nand erase.part filesystem; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${ubifs_file}; " \ - "ubi part filesystem; " \ - "ubi create filesystem; " \ - "ubi write ${loadaddr} filesystem ${filesize}\0" \ - "nandargs=setenv bootargs console=${console_mainline},${baudrate} " \ - "rootfstype=ubifs ubi.mtd=6 root=ubi0_0 ${mtdparts}\0" \ - "nandboot=" /* Boot from NAND */ \ - "mtdparts default; " \ - "run nandargs; " \ - "nand read ${loadaddr} kernel 0x00400000; " \ - "if test ${boot_fdt} = yes; then " \ - "nand read ${fdt_addr} fdt 0x00080000; " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = no; then " \ - "bootz; " \ - "else " \ - "echo "ERROR: Set boot_fdt to yes or no."; " \ - "fi; " \ - "fi\0" \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console_fsl=ttyAM0\0" \ - "console_mainline=ttyAMA0\0" \ - "fdt_file=imx28-evk.dtb\0" \ - "fdt_addr=0x41000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ - "mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console_mainline},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;" \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_MX28EVK_H__ */

-- 2.25.1

Fabio Estevam

3 Aug 3 Aug

1:08 a.m.

New subject: [PATCH 04/21] arm: Remove mx28evk board

On Tue, Aug 2, 2022 at 8:34 AM Tom Rini trini@konsulko.com wrote:

...

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

This is not correct.

The only missing DM migration is the DM_SERIAL one, which is due on v2023.04.

So NACK to this patch.

Fabio Estevam

1:11 a.m.

New subject: [PATCH 04/21] arm: Remove mx28evk board

On Tue, Aug 2, 2022 at 8:08 PM Fabio Estevam festevam@gmail.com wrote:

...

On Tue, Aug 2, 2022 at 8:34 AM Tom Rini trini@konsulko.com wrote:

...
This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

This is not correct.

The only missing DM migration is the DM_SERIAL one, which is due on v2023.04.

So NACK to this patch.

It is OK to remove all mx28evk defconfigs, except the mx28evk_defconfig.

Tom Rini

3:57 a.m.

New subject: [PATCH 04/21] arm: Remove mx28evk board

On Tue, Aug 02, 2022 at 08:11:49PM -0300, Fabio Estevam wrote:

...

On Tue, Aug 2, 2022 at 8:08 PM Fabio Estevam festevam@gmail.com wrote:

...
On Tue, Aug 2, 2022 at 8:34 AM Tom Rini trini@konsulko.com wrote:

...
This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

This is not correct.

The only missing DM migration is the DM_SERIAL one, which is due on v2023.04.

So NACK to this patch.

It is OK to remove all mx28evk defconfigs, except the mx28evk_defconfig.

I feel like I asked someone to do that before, and they're still there. Can you please then? Thanks.

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 05/21] arm: Remove edminiv2 board

This board is not converted to use CONFIG_DM, well passed the migration deadline. Remove it.

Cc: Simon Guinot simon.guinot@sequanux.org Signed-off-by: Tom Rini trini@konsulko.com --- This is also the last orion5x board, if you don't wish to migrate this platform I'll follow-up with a larger removal patch. --- arch/arm/mach-orion5x/Kconfig | 13 --- board/LaCie/edminiv2/Kconfig | 12 --- board/LaCie/edminiv2/MAINTAINERS | 6 -- board/LaCie/edminiv2/Makefile | 10 --- board/LaCie/edminiv2/edminiv2.c | 57 ------------- configs/edminiv2_defconfig | 72 ----------------- include/configs/edminiv2.h | 134 ------------------------------- 7 files changed, 304 deletions(-) delete mode 100644 board/LaCie/edminiv2/Kconfig delete mode 100644 board/LaCie/edminiv2/MAINTAINERS delete mode 100644 board/LaCie/edminiv2/Makefile delete mode 100644 board/LaCie/edminiv2/edminiv2.c delete mode 100644 configs/edminiv2_defconfig delete mode 100644 include/configs/edminiv2.h

diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index b8b45a048ca3..e677211b2e91 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -6,21 +6,8 @@ config 88F5182 config FEROCEON bool

-choice - prompt "Marvell Orion board select" - optional - -config TARGET_EDMINIV2 - bool "LaCie Ethernet Disk mini V2" - select 88F5182 - select FEROCEON - select SUPPORT_SPL - -endchoice - config SYS_SOC default "orion5x"

-source "board/LaCie/edminiv2/Kconfig"

endif diff --git a/board/LaCie/edminiv2/Kconfig b/board/LaCie/edminiv2/Kconfig deleted file mode 100644 index ac3fe3fbcb3e..000000000000 --- a/board/LaCie/edminiv2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_EDMINIV2 - -config SYS_BOARD - default "edminiv2" - -config SYS_VENDOR - default "LaCie" - -config SYS_CONFIG_NAME - default "edminiv2" - -endif diff --git a/board/LaCie/edminiv2/MAINTAINERS b/board/LaCie/edminiv2/MAINTAINERS deleted file mode 100644 index 055afd0e766f..000000000000 --- a/board/LaCie/edminiv2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -EDMINIV2 BOARD -M: Simon Guinot simon.guinot@sequanux.org -S: Maintained -F: board/LaCie/edminiv2/ -F: include/configs/edminiv2.h -F: configs/edminiv2_defconfig diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile deleted file mode 100644 index 5252c2b0e60e..000000000000 --- a/board/LaCie/edminiv2/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net -# -# Based on original Kirkwood support which is -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com - -obj-y := edminiv2.o ../common/common.o diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c deleted file mode 100644 index 9c066a283c99..000000000000 --- a/board/LaCie/edminiv2/edminiv2.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#include <common.h> -#include <miiphy.h> -#include <net.h> -#include <asm/arch/orion5x.h> -#include <asm/global_data.h> -#include "../common/common.h" -#include <spl.h> -#include <ns16550.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* arch number of board */ - gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2; - - /* boot parameter start at 256th byte of RAM base */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; - - return 0; -} - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{ - mv_phy_88e1116_init("egiga0", 8); -} -#endif /* CONFIG_RESET_PHY_R */ - -/* - * SPL serial setup and NOR boot device selection - */ - -#ifdef CONFIG_SPL_BUILD - -void spl_board_init(void) -{ - preloader_console_init(); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_NOR; -} - -#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig deleted file mode 100644 index 1cd0ac020b2a..000000000000 --- a/configs/edminiv2_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_ORION5X=y -CONFIG_SYS_TEXT_BASE=0x00800000 -CONFIG_SYS_MALLOC_LEN=0x40000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-orion5x/u-boot-spl.lds" -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x2000 -CONFIG_SPL_TEXT_BASE=0xffff0000 -CONFIG_TARGET_EDMINIV2=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_IDENT_STRING=" EDMiniV2" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_ENV_ADDR=0xFFF84000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf40 -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y -CONFIG_RESET_PHY_R=y -CONFIG_SPL_MAX_SIZE=0xfff0 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x20000 -CONFIG_SPL_BSS_MAX_SIZE=0x1ffff -CONFIG_SPL_BOARD_INIT=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0x20000 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x40000 -CONFIG_SYS_SPL_MALLOC_SIZE=0x1ffff -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="EDMiniV2> " -CONFIG_SYS_PBSIZE=1051 -CONFIG_CMD_IMLS=y -CONFIG_CMD_IDE=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT2=y -CONFIG_ISO_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_SYS_IDE_MAXBUS=1 -CONFIG_SYS_IDE_MAXDEVICE=1 -CONFIG_SYS_ATA_BASE_ADDR=0xf1080000 -CONFIG_SYS_ATA_STRIDE=4 -CONFIG_SYS_ATA_DATA_OFFSET=0x100 -CONFIG_SYS_ATA_REG_OFFSET=0x100 -CONFIG_SYS_ATA_ALT_OFFSET=0x100 -CONFIG_SYS_ATA_IDE0_OFFSET=0x4000 -CONFIG_LBA48=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_MAX_FLASH_SECT=11 -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h deleted file mode 100644 index d2f1cd5d5c8c..000000000000 --- a/include/configs/edminiv2.h +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Albert ARIBAUD albert.u.boot@aribaud.net - * - * Based on original Kirkwood support which is - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar prafulla@marvell.com - */ - -#ifndef _CONFIG_EDMINIV2_H -#define _CONFIG_EDMINIV2_H - -/* - * SPL - */ - -#define CONFIG_SYS_UBOOT_BASE 0xfff90000 -#define CONFIG_SYS_UBOOT_START 0x00800000 - -/* - * High Level Configuration Options (easy to change) - */ - -#include <asm/arch/orion5x.h> -/* - * CLKs configurations - */ - -/* - * Board-specific values for Orion5x MPP low level init: - * - MPPs 12 to 15 are SATA LEDs (mode 5) - * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for - * MPP16 to MPP19, mode 0 for others - */ - -#define ORION5X_MPP0_7 0x00000003 -#define ORION5X_MPP8_15 0x55550000 -#define ORION5X_MPP16_23 0x00005555 - -/* - * Board-specific values for Orion5x GPIO low level init: - * - GPIO3 is input (RTC interrupt) - * - GPIO16 is Power LED control (0 = on, 1 = off) - * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) - * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) - * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) - * - GPIO22 is SATA disk power status () - * - GPIO23 is supply status for SATA disk () - * - GPIO24 is supply control for board (write 1 to power off) - * Last GPIO is 25, further bits are supposed to be 0. - * Enable mask has ones for INPUT, 0 for OUTPUT. - * Default is LED ON, board ON :) - */ - -#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca -#define ORION5X_GPIO_OUT_VALUE 0x00000000 -#define ORION5X_GPIO_IN_POLARITY 0x000000d0 - -/* - * NS16550 Configuration - */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } - -/* - * FLASH configuration - */ - -#define CONFIG_SYS_FLASH_BASE 0xfff80000 - -/* auto boot */ - -/* - * Network - */ - -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ -#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ -#define CONFIG_PHY_BASE_ADR 0x8 -#endif - -/* - * IDE - */ -#ifdef CONFIG_IDE -#define __io -/* Data, registers and alternate blocks are at the same offset */ -/* Each 8-bit ATA register is aligned to a 4-bytes address */ -/* A single bus, a single device */ -/* ATA registers base is at SATA controller base */ -/* ATA bus 0 is orion5x port 1 on ED Mini V2 */ -/* end of IDE defines */ -#endif /* CMD_IDE */ - -/* - * Common USB/EHCI configuration - */ -#ifdef CONFIG_CMD_USB -#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE -#endif /* CONFIG_CMD_USB */ - -/* - * I2C related stuff - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE -#endif - -/* - * Environment variables configurations - */ - -/* Enable command line editing */ - -/* provide extensive help */ - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0 - -#endif /* _CONFIG_EDMINIV2_H */

-- 2.25.1

Simon Glass

5 Aug 5 Aug

6:48 p.m.

New subject: [PATCH 05/21] arm: Remove edminiv2 board

On Tue, 2 Aug 2022 at 05:35, Tom Rini trini@konsulko.com wrote:

...

This board is not converted to use CONFIG_DM, well passed the migration deadline. Remove it.

Cc: Simon Guinot simon.guinot@sequanux.org Signed-off-by: Tom Rini trini@konsulko.com

This is also the last orion5x board, if you don't wish to migrate this platform I'll follow-up with a larger removal patch.

arch/arm/mach-orion5x/Kconfig | 13 --- board/LaCie/edminiv2/Kconfig | 12 --- board/LaCie/edminiv2/MAINTAINERS | 6 -- board/LaCie/edminiv2/Makefile | 10 --- board/LaCie/edminiv2/edminiv2.c | 57 ------------- configs/edminiv2_defconfig | 72 ----------------- include/configs/edminiv2.h | 134 ------------------------------- 7 files changed, 304 deletions(-) delete mode 100644 board/LaCie/edminiv2/Kconfig delete mode 100644 board/LaCie/edminiv2/MAINTAINERS delete mode 100644 board/LaCie/edminiv2/Makefile delete mode 100644 board/LaCie/edminiv2/edminiv2.c delete mode 100644 configs/edminiv2_defconfig delete mode 100644 include/configs/edminiv2.h

Reviewed-by: Simon Glass sjg@chromium.org

This is getting in the way of BLK tidy-ups too.

Tom Rini

21 Aug 21 Aug

4:42 a.m.

New subject: [PATCH 05/21] arm: Remove edminiv2 board

On Tue, Aug 02, 2022 at 07:33:31AM -0400, Tom Rini wrote:

...

This board is not converted to use CONFIG_DM, well passed the migration deadline. Remove it.

Cc: Simon Guinot simon.guinot@sequanux.org Signed-off-by: Tom Rini trini@konsulko.com Reviewed-by: Simon Glass sjg@chromium.org

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 06/21] arm: Remove cm_t335 board

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Igor Grinberg grinberg@compulab.co.il Cc: Nikita Kiryanov nikita@compulab.co.il Cc: Uri Mashiach uri.mashiach@compulab.co.il Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-omap2/Kconfig | 1 - arch/arm/mach-omap2/am33xx/Kconfig | 7 -- board/compulab/cm_t335/Kconfig | 15 --- board/compulab/cm_t335/MAINTAINERS | 6 -- board/compulab/cm_t335/Makefile | 8 -- board/compulab/cm_t335/cm_t335.c | 166 ----------------------------- board/compulab/cm_t335/mux.c | 116 -------------------- board/compulab/cm_t335/spl.c | 116 -------------------- board/compulab/cm_t335/u-boot.lds | 110 ------------------- configs/cm_t335_defconfig | 83 --------------- include/configs/cm_t335.h | 98 ----------------- 11 files changed, 726 deletions(-) delete mode 100644 board/compulab/cm_t335/Kconfig delete mode 100644 board/compulab/cm_t335/MAINTAINERS delete mode 100644 board/compulab/cm_t335/Makefile delete mode 100644 board/compulab/cm_t335/cm_t335.c delete mode 100644 board/compulab/cm_t335/mux.c delete mode 100644 board/compulab/cm_t335/spl.c delete mode 100644 board/compulab/cm_t335/u-boot.lds delete mode 100644 configs/cm_t335_defconfig delete mode 100644 include/configs/cm_t335.h

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index fa4104747673..914d43b04965 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -207,7 +207,6 @@ source "board/siemens/rut/Kconfig" source "board/ti/ti816x/Kconfig" source "board/ti/am43xx/Kconfig" source "board/ti/am335x/Kconfig" -source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" source "board/phytec/phycore_am335x_r2/Kconfig"

diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index bd6b08655260..987ab367ece3 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -125,13 +125,6 @@ config TARGET_CHILIBOARD select DM_SERIAL imply CMD_DM

-config TARGET_CM_T335 - bool "Support cm_t335" - select DM - select DM_GPIO - select DM_SERIAL - imply CMD_DM - config TARGET_DRACO bool "Support draco" select BOARD_LATE_INIT diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig deleted file mode 100644 index 683efde76443..000000000000 --- a/board/compulab/cm_t335/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_CM_T335 - -config SYS_BOARD - default "cm_t335" - -config SYS_VENDOR - default "compulab" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "cm_t335" - -endif diff --git a/board/compulab/cm_t335/MAINTAINERS b/board/compulab/cm_t335/MAINTAINERS deleted file mode 100644 index 5fb922c68b02..000000000000 --- a/board/compulab/cm_t335/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CM_T335 BOARD -M: Igor Grinberg grinberg@compulab.co.il -S: Maintained -F: board/compulab/cm_t335/ -F: include/configs/cm_t335.h -F: configs/cm_t335_defconfig diff --git a/board/compulab/cm_t335/Makefile b/board/compulab/cm_t335/Makefile deleted file mode 100644 index 34f671311865..000000000000 --- a/board/compulab/cm_t335/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/ -# -# Author: Ilya Ledvich ilya@compulab.co.il - -obj-y += cm_t335.o -obj-$(CONFIG_SPL_BUILD) += mux.o spl.o diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c deleted file mode 100644 index 1d4a3aceef54..000000000000 --- a/board/compulab/cm_t335/cm_t335.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Board functions for Compulab CM-T335 board - * - * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ - * - * Author: Ilya Ledvich ilya@compulab.co.il - */ - -#include <common.h> -#include <env.h> -#include <errno.h> -#include <miiphy.h> -#include <net.h> -#include <status_led.h> -#include <cpsw.h> -#include <asm/global_data.h> -#include <linux/delay.h> - -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware_am33xx.h> -#include <asm/io.h> -#include <asm/gpio.h> - -#include "../common/eeprom.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Basic board specific setup. Pinmux has been handled already. - */ -int board_init(void) -{ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - gpmc_init(); - -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF); -#endif - return 0; -} - -#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - return; -} - -static struct cpsw_slave_data cpsw_slave = { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_RGMII, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = &cpsw_slave, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -/* PHY reset GPIO */ -#define GPIO_PHY_RST GPIO_PIN(3, 7) - -static void board_phy_init(void) -{ - gpio_request(GPIO_PHY_RST, "phy_rst"); - gpio_direction_output(GPIO_PHY_RST, 0); - mdelay(2); - gpio_set_value(GPIO_PHY_RST, 1); - mdelay(2); -} - -static void get_efuse_mac_addr(uchar *enetaddr) -{ - uint32_t mac_hi, mac_lo; - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - enetaddr[0] = mac_hi & 0xFF; - enetaddr[1] = (mac_hi & 0xFF00) >> 8; - enetaddr[2] = (mac_hi & 0xFF0000) >> 16; - enetaddr[3] = (mac_hi & 0xFF000000) >> 24; - enetaddr[4] = mac_lo & 0xFF; - enetaddr[5] = (mac_lo & 0xFF00) >> 8; -} - -/* - * Routine: handle_mac_address - * Description: prepare MAC address for on-board Ethernet. - */ -static int handle_mac_address(void) -{ - uchar enetaddr[6]; - int rv; - - rv = eth_env_get_enetaddr("ethaddr", enetaddr); - if (rv) - return 0; - - rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); - if (rv) - get_efuse_mac_addr(enetaddr); - - if (!is_valid_ethaddr(enetaddr)) - return -1; - - return eth_env_set_enetaddr("ethaddr", enetaddr); -} - -#define AR8051_PHY_DEBUG_ADDR_REG 0x1d -#define AR8051_PHY_DEBUG_DATA_REG 0x1e -#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 -#define AR8051_RGMII_TX_CLK_DLY 0x100 - -int board_eth_init(struct bd_info *bis) -{ - int rv, n = 0; - const char *devname; - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - rv = handle_mac_address(); - if (rv) - printf("No MAC address found!\n"); - - writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); - - board_phy_init(); - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - else - n += rv; - - /* - * CPSW RGMII Internal Delay Mode is not supported in all PVT - * operating points. So we must set the TX clock delay feature - * in the AR8051 PHY. Since we only support a single ethernet - * device, we only do this for the first instance. - */ - devname = miiphy_get_current_dev(); - - miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, - AR8051_DEBUG_RGMII_CLK_DLY_REG); - miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, - AR8051_RGMII_TX_CLK_DLY); - return n; -} -#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */ diff --git a/board/compulab/cm_t335/mux.c b/board/compulab/cm_t335/mux.c deleted file mode 100644 index 1c326bd1b6f6..000000000000 --- a/board/compulab/cm_t335/mux.c +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Pinmux configuration for Compulab CM-T335 board - * - * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ - * - * Author: Ilya Ledvich ilya@compulab.co.il - */ - -#include <common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware.h> -#include <asm/arch/mux.h> -#include <asm/io.h> - -static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, - {-1}, -}; - -static struct module_pin_mux uart1_pin_mux[] = { - {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, - {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)}, - {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)}, - {-1}, -}; - -static struct module_pin_mux mmc0_pin_mux[] = { - {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {-1}, -}; - -static struct module_pin_mux i2c0_pin_mux[] = { - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, - {-1}, -}; - -static struct module_pin_mux i2c1_pin_mux[] = { - /* I2C_DATA */ - {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, - /* I2C_SCLK */ - {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)}, - {-1}, -}; - -static struct module_pin_mux rgmii1_pin_mux[] = { - {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ - {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ - {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ - {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ - {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ - {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ - {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ - {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ - {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ - {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ - {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ - {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ - {-1}, -}; - -static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ - {-1}, -}; - -static struct module_pin_mux eth_phy_rst_pin_mux[] = { - {OFFSET(emu0), (MODE(7) | PULLUDDIS)}, /* GPIO3_7 */ - {-1}, -}; - -static struct module_pin_mux status_led_pin_mux[] = { - {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)}, /* GPIO2_0 */ - {-1}, -}; - -void set_uart_mux_conf(void) -{ - configure_module_pin_mux(uart0_pin_mux); - configure_module_pin_mux(uart1_pin_mux); -} - -void set_mux_conf_regs(void) -{ - configure_module_pin_mux(i2c0_pin_mux); - configure_module_pin_mux(i2c1_pin_mux); - configure_module_pin_mux(rgmii1_pin_mux); - configure_module_pin_mux(eth_phy_rst_pin_mux); - configure_module_pin_mux(mmc0_pin_mux); - configure_module_pin_mux(nand_pin_mux); - configure_module_pin_mux(status_led_pin_mux); -} diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c deleted file mode 100644 index 33264dfa71fc..000000000000 --- a/board/compulab/cm_t335/spl.c +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SPL specific code for Compulab CM-T335 board - * - * Board functions for Compulab CM-T335 board - * - * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ - * - * Author: Ilya Ledvich ilya@compulab.co.il - */ - -#include <common.h> -#include <cpu_func.h> -#include <errno.h> -#include <init.h> -#include <log.h> - -#include <asm/arch/ddr_defs.h> -#include <asm/arch/clock.h> -#include <asm/arch/clocks_am33xx.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/hardware_am33xx.h> -#include <linux/sizes.h> - -const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, - .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, - .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, - .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, - .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, -}; - -static const struct ddr_data ddr3_data = { - .datardsratio0 = MT41J128MJT125_RD_DQS, - .datawdsratio0 = MT41J128MJT125_WR_DQS, - .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, - .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, -}; - -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = MT41J128MJT125_RATIO, - .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, - - .cmd1csratio = MT41J128MJT125_RATIO, - .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, - - .cmd2csratio = MT41J128MJT125_RATIO, - .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = MT41J128MJT125_EMIF_SDCFG, - .ref_ctrl = MT41J128MJT125_EMIF_SDREF, - .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, - .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, - .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, - .zq_config = MT41J128MJT125_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | - PHY_EN_DYN_PWRDN, -}; - -const struct dpll_params dpll_ddr = { -/* M N M2 M3 M4 M5 M6 */ - 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1}; - -void am33xx_spl_board_init(void) -{ - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - /* Get the frequency */ - dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); - - /* Set CORE Frequencies to OPP100 */ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - - /* Set MPU Frequency to what we detected now that voltages are set */ - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); -} - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - -static void probe_sdram_size(long size) -{ - switch (size) { - case SZ_512M: - ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG; - break; - case SZ_256M: - ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG; - break; - case SZ_128M: - ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG; - break; - default: - puts("Failed configuring DRAM, resetting...\n\n"); - reset_cpu(); - } - debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); - config_ddr(303, &ioregs, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -} - -void sdram_init(void) -{ - long size = SZ_1G; - - do { - size = size / 2; - probe_sdram_size(size); - } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size); - - return; -} diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds deleted file mode 100644 index 49938804611c..000000000000 --- a/board/compulab/cm_t335/u-boot.lds +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2004-2008 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.__image_copy_start) - *(.vectors) - CPUDIR/start.o (.text*) - board/compulab/cm_t335/built-in.o (.text*) - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - . = .; - - . = ALIGN(4); - __u_boot_list : { - KEEP(*(SORT(__u_boot_list*))); - } - - . = ALIGN(4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - .hash : { *(.hash*) } - - .end : - { - *(.__end) - } - - _image_binary_end = .; - - /* - * Deprecated: this MMU section is used by pxa at present but - * should not be used by new boards/CPUs. - */ - . = ALIGN(4096); - .mmutable : { - *(.mmutable) - } - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _image_binary_end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig deleted file mode 100644 index f1b4b622cbd5..000000000000 --- a/configs/cm_t335_defconfig +++ /dev/null @@ -1,83 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x300000 -CONFIG_AM33XX=y -CONFIG_TARGET_CM_T335=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 -CONFIG_TIMESTAMP=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NAND_BASE=y -CONFIG_SPL_POWER=y -CONFIG_SPL_WATCHDOG=y -# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set -CONFIG_SYS_PROMPT="CM-T335 # " -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=1051 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_EEPROM_LAYOUT=y -CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_BOOTP_DNS2=y -CONFIG_SYS_DISABLE_AUTOLOAD=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:2m(spl),1m(u-boot),1m(u-boot-env),1m(dtb),4m(splash),6m(kernel),-(rootfs)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NET_RETRY_COUNT=10 -CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_CMD_PCA953X=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS_GPIO=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=64 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000 -CONFIG_PHY_ATHEROS=y -CONFIG_MII=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h deleted file mode 100644 index 84b4271c36fa..000000000000 --- a/include/configs/cm_t335.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Config file for Compulab CM-T335 board - * - * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ - * - * Author: Ilya Ledvich ilya@compulab.co.il - */ - -#ifndef __CONFIG_CM_T335_H -#define __CONFIG_CM_T335_H - -#include <configs/ti_am335x_common.h> - -#undef CONFIG_MAX_RAM_BANK_SIZE -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */ - -/* Clock Defines */ -#define V_OSCK 25000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define MMCARGS \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ - "mmcrootfstype=ext4\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" - -#define NANDARGS \ - "nandroot=ubi0:rootfs rw\0" \ - "nandrootfstype=ubifs\0" \ - "nandargs=setenv bootargs console=${console} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype} " \ - "ubi.mtd=${rootfs_name}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nboot ${loadaddr} nand0 900000; " \ - "bootm ${loadaddr}\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=82000000\0" \ - "console=ttyO0,115200n8\0" \ - "rootfs_name=rootfs\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - MMCARGS \ - NANDARGS - -/* Serial console configuration */ - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ - -/* I2C Configuration */ - -/* SPL */ - -/* Network. */ - -/* NAND support */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -/* GPIO pin + bank to pin ID mapping */ -#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin) - -/* Status LED */ -/* Status LED polarity is inversed, so init it in the "off" state */ - -/* EEPROM */ - -/* - * Enable PCA9555 at I2C0-0x26. - * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command. - */ -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x26 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} } - -#endif /* __CONFIG_CM_T335_H */

-- 2.25.1

Tom Rini

21 Aug 21 Aug

4:42 a.m.

New subject: [PATCH 06/21] arm: Remove cm_t335 board

On Tue, Aug 02, 2022 at 07:33:32AM -0400, Tom Rini wrote:

...

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Igor Grinberg grinberg@compulab.co.il Cc: Nikita Kiryanov nikita@compulab.co.il Cc: Uri Mashiach uri.mashiach@compulab.co.il Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 07/21] arm: Remove armadillo-800eva board

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-rmobile/Kconfig.32 | 4 - board/atmark-techno/armadillo-800eva/Kconfig | 12 - .../armadillo-800eva/MAINTAINERS | 6 - board/atmark-techno/armadillo-800eva/Makefile | 5 - .../armadillo-800eva/armadillo-800eva.c | 327 ------------------ configs/armadillo-800eva_defconfig | 54 --- include/configs/armadillo-800eva.h | 61 ---- 7 files changed, 469 deletions(-) delete mode 100644 board/atmark-techno/armadillo-800eva/Kconfig delete mode 100644 board/atmark-techno/armadillo-800eva/MAINTAINERS delete mode 100644 board/atmark-techno/armadillo-800eva/Makefile delete mode 100644 board/atmark-techno/armadillo-800eva/armadillo-800eva.c delete mode 100644 configs/armadillo-800eva_defconfig delete mode 100644 include/configs/armadillo-800eva.h

diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index ea98bb00f3ba..27db7940e370 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -50,9 +50,6 @@ choice prompt "Renesas ARM SoCs board select" optional

-config TARGET_ARMADILLO_800EVA - bool "armadillo 800 eva board" - config TARGET_BLANCHE bool "Blanche board" select DM @@ -156,7 +153,6 @@ config QOS_PRI_GFX

endchoice

-source "board/atmark-techno/armadillo-800eva/Kconfig" source "board/renesas/blanche/Kconfig" source "board/renesas/gose/Kconfig" source "board/renesas/koelsch/Kconfig" diff --git a/board/atmark-techno/armadillo-800eva/Kconfig b/board/atmark-techno/armadillo-800eva/Kconfig deleted file mode 100644 index cd37dd4861dd..000000000000 --- a/board/atmark-techno/armadillo-800eva/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ARMADILLO_800EVA - -config SYS_BOARD - default "armadillo-800eva" - -config SYS_VENDOR - default "atmark-techno" - -config SYS_CONFIG_NAME - default "armadillo-800eva" - -endif diff --git a/board/atmark-techno/armadillo-800eva/MAINTAINERS b/board/atmark-techno/armadillo-800eva/MAINTAINERS deleted file mode 100644 index 6f547d82ecb0..000000000000 --- a/board/atmark-techno/armadillo-800eva/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ARMADILLO-800EVA BOARD -M: Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com -S: Maintained -F: board/atmark-techno/armadillo-800eva/ -F: include/configs/armadillo-800eva.h -F: configs/armadillo-800eva_defconfig diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile deleted file mode 100644 index 7e01cb6794a0..000000000000 --- a/board/atmark-techno/armadillo-800eva/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com - -obj-y += armadillo-800eva.o diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c deleted file mode 100644 index c1c3dfd3deb3..000000000000 --- a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c +++ /dev/null @@ -1,327 +0,0 @@ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <malloc.h> -#include <asm/global_data.h> -#include <asm/processor.h> -#include <asm/mach-types.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/rmobile.h> - -#define s_init_wait(cnt) \ - ({ \ - volatile u32 i = 0x10000 * cnt; \ - while (i > 0) \ - i--; \ - }) - -#define USBCR1 0xE605810A - -void s_init(void) -{ - struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE; - struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE; - struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE; - struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE; - struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE; - struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE; - - /* Watchdog init */ - writew(0xA500, &rwdt0->rwtcsra0); - writew(0xA500, &rwdt1->rwtcsra0); - - /* CPG */ - writel(0xFF800080, &cpg->rmstpcr4); - writel(0xFF800080, &cpg->smstpcr4); - - /* USB clock */ - writel(0x00000080, &cpg->usbckcr); - s_init_wait(1); - - /* USBCR1 */ - writew(0x0710, USBCR1); - - /* FRQCR */ - writel(0x00000000, &cpg->frqcrb); - writel(0x62030533, &cpg->frqcra); - writel(0x208A354E, &cpg->frqcrc); - writel(0x80331050, &cpg->frqcrb); - s_init_wait(1); - - writel(0x00000000, &cpg->frqcrd); - s_init_wait(1); - - /* SUBClk */ - writel(0x0000010B, &cpg->subckcr); - - /* PLL */ - writel(0x00004004, &cpg->pllc01cr); - s_init_wait(1); - - writel(0xa0000000, &cpg->pllc2cr); - s_init_wait(2); - - /* BSC */ - writel(0x0000001B, &bsc->cmncr); - - writel(0x20000000, &dbsc->dbcmd); - writel(0x10009C40, &dbsc->dbcmd); - s_init_wait(1); - - writel(0x00000007, &dbsc->dbkind); - writel(0x0E030A02, &dbsc->dbconf0); - writel(0x00000001, &dbsc->dbphytype); - writel(0x00000000, &dbsc->dbbl); - writel(0x00000006, &dbsc->dbtr0); - writel(0x00000005, &dbsc->dbtr1); - writel(0x00000000, &dbsc->dbtr2); - writel(0x00000006, &dbsc->dbtr3); - writel(0x00080006, &dbsc->dbtr4); - writel(0x00000015, &dbsc->dbtr5); - writel(0x0000000f, &dbsc->dbtr6); - writel(0x00000004, &dbsc->dbtr7); - writel(0x00000018, &dbsc->dbtr8); - writel(0x00000006, &dbsc->dbtr9); - writel(0x00000006, &dbsc->dbtr10); - writel(0x0000000F, &dbsc->dbtr11); - writel(0x0000000D, &dbsc->dbtr12); - writel(0x000000A0, &dbsc->dbtr13); - writel(0x000A0003, &dbsc->dbtr14); - writel(0x00000003, &dbsc->dbtr15); - writel(0x40005005, &dbsc->dbtr16); - writel(0x0C0C0000, &dbsc->dbtr17); - writel(0x00000200, &dbsc->dbtr18); - writel(0x00000040, &dbsc->dbtr19); - writel(0x00000001, &dbsc->dbrnk0); - writel(0x00000110, &dbsc->dbdficnt); - writel(0x00000101, &ddrp->funcctrl); - writel(0x00000001, &ddrp->dllctrl); - writel(0x00000186, &ddrp->zqcalctrl); - writel(0xB3440051, &ddrp->zqodtctrl); - writel(0x94449443, &ddrp->rdctrl); - writel(0x000000C0, &ddrp->rdtmg); - writel(0x00000101, &ddrp->fifoinit); - writel(0x02060506, &ddrp->outctrl); - writel(0x00004646, &ddrp->dqcalofs1); - writel(0x00004646, &ddrp->dqcalofs2); - writel(0x800000aa, &ddrp->dqcalexp); - writel(0x00000000, &ddrp->dllctrl); - writel(0x00000000, DDRPNCNT); - - writel(0x0000000C, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00000002, DDRPNCNT); - - writel(0x0000000C, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00000187, &ddrp->zqcalctrl); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00000010, &dbsc->dbdficnt); - writel(0x02060507, &ddrp->outctrl); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x21009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x00009C40, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x11000044, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x2A000000, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x2B000000, &dbsc->dbcmd); - readl(&dbsc->dbwait); - - writel(0x29000004, &dbsc->dbcmd); - readl(&dbsc->dbwait); - - writel(0x28001520, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x03000200, &dbsc->dbcmd); - readl(&dbsc->dbwait); - s_init_wait(1); - - writel(0x000001FF, &dbsc->dbrfcnf0); - writel(0x00010C30, &dbsc->dbrfcnf1); - writel(0x00000000, &dbsc->dbrfcnf2); - - writel(0x00000001, &dbsc->dbrfen); - writel(0x00000001, &dbsc->dbacen); - - /* BSC */ - writel(0x00410400, &bsc->cs0bcr); - writel(0x00410400, &bsc->cs2bcr); - writel(0x00410400, &bsc->cs5bbcr); - writel(0x02CB0400, &bsc->cs6abcr); - - writel(0x00000440, &bsc->cs0wcr); - writel(0x00000440, &bsc->cs2wcr); - writel(0x00000240, &bsc->cs5bwcr); - writel(0x00000240, &bsc->cs6awcr); - - writel(0x00000005, &bsc->rbwtcnt); - writel(0x00000002, &bsc->cs0wcr2); - writel(0x00000002, &bsc->cs2wcr2); - writel(0x00000002, &bsc->cs4wcr2); -} - -#define GPIO_ICCR (0xE60581A0) -#define ICCR_15BIT (1 << 15) /* any time 1 */ -#define IIC0_CONTA (1 << 7) -#define IIC0_CONTB (1 << 6) -#define IIC1_CONTA (1 << 5) -#define IIC1_CONTB (1 << 4) -#define IIC0_PS33E (1 << 1) -#define IIC1_PS33E (1 << 0) -#define GPIO_ICCR_DATA \ - (ICCR_15BIT | \ - IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \ - IIC1_CONTB | IIC0_PS33E | IIC1_PS33E) - -#define MSTPCR1 0xE6150134 -#define TMU0_MSTP125 (1 << 25) -#define I2C0_MSTP116 (1 << 16) - -#define MSTPCR3 0xE615013C -#define I2C1_MSTP323 (1 << 23) -#define GETHER_MSTP309 (1 << 9) - -#define GPIO_SCIFA1_TXD (0xE60520C4) -#define GPIO_SCIFA1_RXD (0xE60520C3) - -int board_early_init_f(void) -{ - /* TMU */ - clrbits_le32(MSTPCR1, TMU0_MSTP125); - - /* GETHER */ - clrbits_le32(MSTPCR3, GETHER_MSTP309); - - /* I2C 0/1 */ - clrbits_le32(MSTPCR1, I2C0_MSTP116); - clrbits_le32(MSTPCR3, I2C1_MSTP323); - - /* SCIFA1 */ - writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */ - writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */ - - /* IICCR */ - writew(GPIO_ICCR_DATA, GPIO_ICCR); - - return 0; -} - -DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - /* board id for linux */ - gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO800EVA; - /* adress of boot parameters */ - gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100; - - /* Init PFC controller */ - r8a7740_pinmux_init(); - - /* GETHER Enable */ - gpio_request(GPIO_FN_ET_CRS, NULL); - gpio_request(GPIO_FN_ET_MDC, NULL); - gpio_request(GPIO_FN_ET_MDIO, NULL); - gpio_request(GPIO_FN_ET_TX_ER, NULL); - gpio_request(GPIO_FN_ET_RX_ER, NULL); - gpio_request(GPIO_FN_ET_ERXD0, NULL); - gpio_request(GPIO_FN_ET_ERXD1, NULL); - gpio_request(GPIO_FN_ET_ERXD2, NULL); - gpio_request(GPIO_FN_ET_ERXD3, NULL); - gpio_request(GPIO_FN_ET_TX_CLK, NULL); - gpio_request(GPIO_FN_ET_TX_EN, NULL); - gpio_request(GPIO_FN_ET_ETXD0, NULL); - gpio_request(GPIO_FN_ET_ETXD1, NULL); - gpio_request(GPIO_FN_ET_ETXD2, NULL); - gpio_request(GPIO_FN_ET_ETXD3, NULL); - gpio_request(GPIO_FN_ET_PHY_INT, NULL); - gpio_request(GPIO_FN_ET_COL, NULL); - gpio_request(GPIO_FN_ET_RX_DV, NULL); - gpio_request(GPIO_FN_ET_RX_CLK, NULL); - - gpio_request(GPIO_PORT18, NULL); /* PHY_RST */ - gpio_direction_output(GPIO_PORT18, 1); - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - - return 0; -} - -int board_late_init(void) -{ - return 0; -} - -void reset_cpu(void) -{ -} diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig deleted file mode 100644 index 6a67c60dd425..000000000000 --- a/configs/armadillo-800eva_defconfig +++ /dev/null @@ -1,54 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -# CONFIG_SYS_THUMB_BUILD is not set -CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0xE80C0000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_ARCH_RMOBILE_BOARD_STRING="Armadillo-800EVA Board" -CONFIG_R8A7740=y -CONFIG_TARGET_ARMADILLO_800EVA=y -CONFIG_SYS_CLK_FREQ=50000000 -CONFIG_SYS_LOAD_ADDR=0x44000000 -CONFIG_ENV_ADDR=0x40000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xe8083000 -CONFIG_SYS_MONITOR_BASE=0x00000000 -CONFIG_BOOTDELAY=3 -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=256 -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_LOADB is not set -CONFIG_CMD_SDRAM=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_CMD_SLEEP is not set -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_MMC is not set -CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y -CONFIG_PHY_SMSC=y -CONFIG_SH_ETHER=y -CONFIG_SCIF_CONSOLE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h deleted file mode 100644 index da02a96889bc..000000000000 --- a/include/configs/armadillo-800eva.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the bonito board - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#ifndef __ARMADILLO_800EVA_H -#define __ARMADILLO_800EVA_H - -#define CONFIG_SH_GPIO_PFC - -#include <asm/arch/rmobile.h> - -#define BOARD_LATE_INIT - -#define CONFIG_TMU_TIMER -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4) - -/* STACK */ -#define STACK_AREA_SIZE 0xC000 -#define LOW_LEVEL_MERAM_STACK \ - (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) - -/* MEMORY */ -#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000 -#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define SCIF0_BASE 0xe6c40000 -#define SCIF1_BASE 0xe6c50000 -#define SCIF2_BASE 0xe6c60000 -#define SCIF4_BASE 0xe6c80000 -#define CONFIG_SCIF_A - -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* FLASH */ -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } - -/* ENV setting */ - -/* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x0 -#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000 -#define CONFIG_SH_ETHER_SH7734_MII (0x01) -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII - -#endif /* __ARMADILLO_800EVA_H */

-- 2.25.1

Tom Rini

21 Aug 21 Aug

4:42 a.m.

New subject: [PATCH 07/21] arm: Remove armadillo-800eva board

On Tue, Aug 02, 2022 at 07:33:33AM -0400, Tom Rini wrote:

...

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 08/21] arm: Remove kzm9g board

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com Cc: Tetsuyuki Kobayashi koba@kmckk.co.jp Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-rmobile/Kconfig.32 | 4 - board/kmc/kzm9g/Kconfig | 12 - board/kmc/kzm9g/MAINTAINERS | 7 - board/kmc/kzm9g/Makefile | 6 - board/kmc/kzm9g/kzm9g.c | 373 ------------------------------- configs/kzm9g_defconfig | 47 ---- include/configs/kzm9g.h | 57 ----- 7 files changed, 506 deletions(-) delete mode 100644 board/kmc/kzm9g/Kconfig delete mode 100644 board/kmc/kzm9g/MAINTAINERS delete mode 100644 board/kmc/kzm9g/Makefile delete mode 100644 board/kmc/kzm9g/kzm9g.c delete mode 100644 configs/kzm9g_defconfig delete mode 100644 include/configs/kzm9g.h

diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index 27db7940e370..a07eff71dfe7 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -83,9 +83,6 @@ config TARGET_LAGER select SPL_USE_TINY_PRINTF imply CMD_DM

-config TARGET_KZM9G - bool "KZM9D board" - config TARGET_ALT bool "Alt board" select DM @@ -157,7 +154,6 @@ source "board/renesas/blanche/Kconfig" source "board/renesas/gose/Kconfig" source "board/renesas/koelsch/Kconfig" source "board/renesas/lager/Kconfig" -source "board/kmc/kzm9g/Kconfig" source "board/renesas/alt/Kconfig" source "board/renesas/silk/Kconfig" source "board/renesas/porter/Kconfig" diff --git a/board/kmc/kzm9g/Kconfig b/board/kmc/kzm9g/Kconfig deleted file mode 100644 index f163efd9892b..000000000000 --- a/board/kmc/kzm9g/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KZM9G - -config SYS_BOARD - default "kzm9g" - -config SYS_VENDOR - default "kmc" - -config SYS_CONFIG_NAME - default "kzm9g" - -endif diff --git a/board/kmc/kzm9g/MAINTAINERS b/board/kmc/kzm9g/MAINTAINERS deleted file mode 100644 index 411efd1e31e0..000000000000 --- a/board/kmc/kzm9g/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -KZM9G BOARD -M: Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com -M: Tetsuyuki Kobayashi koba@kmckk.co.jp -S: Maintained -F: board/kmc/kzm9g/ -F: include/configs/kzm9g.h -F: configs/kzm9g_defconfig diff --git a/board/kmc/kzm9g/Makefile b/board/kmc/kzm9g/Makefile deleted file mode 100644 index aebe9f3546ef..000000000000 --- a/board/kmc/kzm9g/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com -# (C) Copyright 2012 Renesas Solutions Corp. - -obj-y := kzm9g.o diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c deleted file mode 100644 index dccf4691afa8..000000000000 --- a/board/kmc/kzm9g/kzm9g.c +++ /dev/null @@ -1,373 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com - * (C) Copyright 2012 Renesas Solutions Corp. - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <netdev.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define CS0BCR_D (0x06C00400) -#define CS4BCR_D (0x16c90400) -#define CS0WCR_D (0x55062C42) -#define CS4WCR_D (0x1e071dc3) - -#define CMNCR_BROMMD0 (1 << 21) -#define CMNCR_BROMMD1 (1 << 22) -#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1) -#define VCLKCR1_D (0x27) - -#define SMSTPCR1_CMT0 (1 << 24) -#define SMSTPCR1_I2C0 (1 << 16) -#define SMSTPCR3_USB (1 << 22) -#define SMSTPCR3_I2C1 (1 << 23) - -#define PORT32CR (0xE6051020) -#define PORT33CR (0xE6051021) -#define PORT34CR (0xE6051022) -#define PORT35CR (0xE6051023) - -static int cmp_loop(u32 *addr, u32 data, u32 cmp) -{ - int err = -1; - int timeout = 100; - u32 value; - - while (timeout > 0) { - value = readl(addr); - if ((value & data) == cmp) { - err = 0; - break; - } - timeout--; - } - - return err; -} - -/* SBSC Init function */ -static void sbsc_init(struct sh73a0_sbsc *sbsc) -{ - writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0); - writel(0x5, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - writel(0xacc90159, &sbsc->sdcr0); - writel(0x00010059, &sbsc->sdcr1); - writel(0x50874114, &sbsc->sdwcrc0); - writel(0x33199b37, &sbsc->sdwcrc1); - writel(0x008f2313, &sbsc->sdwcrc2); - writel(0x31020707, &sbsc->sdwcr00); - writel(0x0017040a, &sbsc->sdwcr01); - writel(0x31020707, &sbsc->sdwcr10); - writel(0x0017040a, &sbsc->sdwcr11); - writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */ - writel(0x30000000, &sbsc->sdwcr2); - - writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr); - cmp_loop(&sbsc->sdpcr, 0x80, 0x80); - - writel(0x00002710, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - writel(0x0000003f, &sbsc->sdmracr0); - writel(0x0, SDMRA1A); - writel(0x000001f4, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - writel(0x0000ff0a, &sbsc->sdmracr0); - if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) - writel(0x0, SDMRA3A); - else - writel(0x0, SDMRA3B); - - writel(0x00000032, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) { - writel(0x00002201, &sbsc->sdmracr0); - writel(0x0, SDMRA1A); - writel(0x00000402, &sbsc->sdmracr0); - writel(0x0, SDMRA1A); - writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ - writel(0x0, SDMRA1A); - writel(0x0, SDMRA2A); - } else { - writel(0x00002201, &sbsc->sdmracr0); - writel(0x0, SDMRA1B); - writel(0x00000402, &sbsc->sdmracr0); - writel(0x0, SDMRA1B); - writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ - writel(0x0, SDMRA1B); - writel(0x0, SDMRA2B); - } - - writel(0x88800004, &sbsc->sdmrtmpcr); - writel(0x00000004, &sbsc->sdmrtmpmsk); - writel(0xa55a0032, &sbsc->rtcor); - writel(0xa55a000c, &sbsc->rtcorh); - writel(0xa55a2048, &sbsc->rtcsr); - writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0); - writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1); - writel(0xfff20000, &sbsc->zqccr); - - /* SCBS2 only */ - if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) { - writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0); - writel(0xa5390000, &sbsc->dphycnt1); - writel(0x00001200, &sbsc->dphycnt0); - writel(0x07ce0000, &sbsc->dphycnt1); - writel(0x00001247, &sbsc->dphycnt0); - cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000); - writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0); - } -} - -void s_init(void) -{ - struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE; - struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; - struct sh73a0_sbsc_cpg_srcr *cpg_srcr = - (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; - struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE; - struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE; - struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; - struct sh73a0_hpb_bscr *hpb_bscr = - (struct sh73a0_hpb_bscr *)HPBSCR_BASE; - - /* Watchdog init */ - writew(0xA507, &rwdt->rwtcsra0); - - /* Secure control register Init */ - #define LIFEC_SEC_SRC_BIT (1 << 15) - writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC); - - clrbits_le32(&cpg->smstpcr3, (1 << 15)); - clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); - clrbits_le32(&cpg->smstpcr2, (1 << 18)); - clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); - writel(0x0, &cpg->pllecr); - - cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); - cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); - - writel(0x2D000000, &cpg->pll0cr); - writel(0x17100000, &cpg->pll1cr); - writel(0x96235880, &cpg->frqcrb); - cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); - - writel(0xB, &cpg->flckcr); - clrbits_le32(&cpg->smstpcr0, (1 << 1)); - - clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); - writel(0x0514, &hpb_bscr->smgpiotime); - writel(0x0514, &hpb_bscr->smcmt2time); - writel(0x0514, &hpb_bscr->smcpgtime); - writel(0x0514, &hpb_bscr->smsysctime); - - writel(0x00092000, &cpg->dvfscr4); - writel(0x000000DC, &cpg->dvfscr5); - writel(0x0, &cpg->pllecr); - cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); - - /* FRQCR Init */ - writel(0x0012453C, &cpg->frqcra); - writel(0x80431350, &cpg->frqcrb); /* ETM TRCLK 78MHz */ - cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); - writel(0x00000B0B, &cpg->frqcrd); - cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); - - /* Clock Init */ - writel(0x00000003, PCLKCR); - writel(0x0000012F, &cpg->vclkcr1); - writel(0x00000119, &cpg->vclkcr2); - writel(0x00000119, &cpg->vclkcr3); - writel(0x00000002, &cpg->zbckcr); - writel(0x00000005, &cpg->flckcr); - writel(0x00000080, &cpg->sd0ckcr); - writel(0x00000080, &cpg->sd1ckcr); - writel(0x00000080, &cpg->sd2ckcr); - writel(0x0000003F, &cpg->fsiackcr); - writel(0x0000003F, &cpg->fsibckcr); - writel(0x00000080, &cpg->subckcr); - writel(0x0000000B, &cpg->spuackcr); - writel(0x0000000B, &cpg->spuvckcr); - writel(0x0000013F, &cpg->msuckcr); - writel(0x00000080, &cpg->hsickcr); - writel(0x0000003F, &cpg->mfck1cr); - writel(0x0000003F, &cpg->mfck2cr); - writel(0x00000107, &cpg->dsitckcr); - writel(0x00000313, &cpg->dsi0pckcr); - writel(0x0000130D, &cpg->dsi1pckcr); - writel(0x2A800E0E, &cpg->dsi0phycr); - writel(0x1E000000, &cpg->pll0cr); - writel(0x2D000000, &cpg->pll0cr); - writel(0x17100000, &cpg->pll1cr); - writel(0x27000080, &cpg->pll2cr); - writel(0x1D000000, &cpg->pll3cr); - writel(0x00080000, &cpg->pll0stpcr); - writel(0x000120C0, &cpg->pll1stpcr); - writel(0x00012000, &cpg->pll2stpcr); - writel(0x00000030, &cpg->pll3stpcr); - - writel(0x0000000B, &cpg->pllecr); - cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00); - - writel(0x000120F0, &cpg->dvfscr3); - writel(0x00000020, &cpg->mpmode); - writel(0x0000028A, &cpg->vrefcr); - writel(0xE4628087, &cpg->rmstpcr0); - writel(0xFFFFFFFF, &cpg->rmstpcr1); - writel(0x53FFFFFF, &cpg->rmstpcr2); - writel(0xFFFFFFFF, &cpg->rmstpcr3); - writel(0x00800D3D, &cpg->rmstpcr4); - writel(0xFFFFF3FF, &cpg->rmstpcr5); - writel(0x00000000, &cpg->smstpcr2); - writel(0x00040000, &cpg_srcr->srcr2); - - clrbits_le32(&cpg->pllecr, (1 << 3)); - cmp_loop(&cpg->pllecr, 0x00000800, 0x0); - - writel(0x00000001, &hpb->hpbctrl6); - cmp_loop(&hpb->hpbctrl6, 0x1, 0x1); - - writel(0x00001414, &cpg->frqcrd); - cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); - - writel(0x1d000000, &cpg->pll3cr); - setbits_le32(&cpg->pllecr, (1 << 3)); - cmp_loop(&cpg->pllecr, 0x800, 0x800); - - /* SBSC1 Init*/ - sbsc_init(sbsc1); - - /* SBSC2 Init*/ - sbsc_init(sbsc2); - - writel(0x00000b0b, &cpg->frqcrd); - cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); - writel(0xfffffffc, &cpg->cpgxxcs4); -} - -int board_early_init_f(void) -{ - struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; - struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE; - struct sh73a0_sbsc_cpg_srcr *cpg_srcr = - (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; - - writel(CS0BCR_D, &bsc->cs0bcr); - writel(CS4BCR_D, &bsc->cs4bcr); - writel(CS0WCR_D, &bsc->cs0wcr); - writel(CS4WCR_D, &bsc->cs4wcr); - - clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD); - - clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); - clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); - writel(VCLKCR1_D, &cpg->vclkcr1); - - /* Setup SCIF4 / workaround */ - writeb(0x12, PORT32CR); - writeb(0x22, PORT33CR); - writeb(0x12, PORT34CR); - writeb(0x22, PORT35CR); - - return 0; -} - -void adjust_core_voltage(void) -{ - u8 data; - - data = 0x35; - i2c_set_bus_num(0); - i2c_write(0x40, 3, 1, &data, 1); -} - -int board_init(void) -{ - adjust_core_voltage(); - sh73a0_pinmux_init(); - - /* SCIFA 4 */ - gpio_request(GPIO_FN_SCIFA4_TXD, NULL); - gpio_request(GPIO_FN_SCIFA4_RXD, NULL); - gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); - gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); - - /* Ethernet/SMSC */ - gpio_request(GPIO_PORT224, NULL); - gpio_direction_input(GPIO_PORT224); - - /* SMSC/USB */ - gpio_request(GPIO_FN_CS4_, NULL); - - /* MMCIF */ - gpio_request(GPIO_FN_MMCCLK0, NULL); - gpio_request(GPIO_FN_MMCCMD0_PU, NULL); - gpio_request(GPIO_FN_MMCD0_0_PU, NULL); - gpio_request(GPIO_FN_MMCD0_1_PU, NULL); - gpio_request(GPIO_FN_MMCD0_2_PU, NULL); - gpio_request(GPIO_FN_MMCD0_3_PU, NULL); - gpio_request(GPIO_FN_MMCD0_4_PU, NULL); - gpio_request(GPIO_FN_MMCD0_5_PU, NULL); - gpio_request(GPIO_FN_MMCD0_6_PU, NULL); - gpio_request(GPIO_FN_MMCD0_7_PU, NULL); - - /* SDHI */ - gpio_request(GPIO_FN_SDHIWP0, NULL); - gpio_request(GPIO_FN_SDHICD0, NULL); - gpio_request(GPIO_FN_SDHICMD0, NULL); - gpio_request(GPIO_FN_SDHICLK0, NULL); - gpio_request(GPIO_FN_SDHID0_3, NULL); - gpio_request(GPIO_FN_SDHID0_2, NULL); - gpio_request(GPIO_FN_SDHID0_1, NULL); - gpio_request(GPIO_FN_SDHID0_0, NULL); - gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); - gpio_request(GPIO_PORT15, NULL); - gpio_direction_output(GPIO_PORT15, 1); - - /* I2C */ - gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); - gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); - gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); - gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); - - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - int ret = 0; -#ifdef CONFIG_SMC911X - ret = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return ret; -} - -void reset_cpu(void) -{ - /* Soft Power On Reset */ - writel((1 << 31), RESCNT2); -} diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig deleted file mode 100644 index 58191c114c54..000000000000 --- a/configs/kzm9g_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -# CONFIG_SYS_THUMB_BUILD is not set -CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_SYS_MALLOC_LEN=0x60000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_ARCH_RMOBILE_BOARD_STRING="KMC KZM-A9-GT" -CONFIG_TARGET_KZM9G=y -CONFIG_SYS_LOAD_ADDR=0x43000000 -CONFIG_ENV_ADDR=0x40000 -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/null console=ttySC4,115200" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="KZM-A9-GT# " -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=256 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_NFS_TIMEOUT=10000 -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SH=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x10000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_SCIF_CONSOLE=y -# CONFIG_FAT_WRITE is not set -CONFIG_OF_LIBFDT=y diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h deleted file mode 100644 index 602c1c539190..000000000000 --- a/include/configs/kzm9g.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#ifndef __KZM9G_H -#define __KZM9G_H - -#define CONFIG_SH73A0 - -#include <asm/arch/rmobile.h> - -/* MEMORY */ -#define KZM_SDRAM_BASE (0x40000000) -#define PHYS_SDRAM KZM_SDRAM_BASE -#define PHYS_SDRAM_SIZE (512 * 1024 * 1024) - -/* NOR Flash */ -#define KZM_FLASH_BASE (0x00000000) -#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) - -/* prompt */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ - -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000) -#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) -#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) -#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) - -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 - -/* FLASH */ -#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */ - -/* Timeout for Flash erase operations (in ms) */ -/* Timeout for Flash write operations (in ms) */ -/* Timeout for Flash set sector lock bit operations (in ms) */ -/* Timeout for Flash clear lock bit operations (in ms) */ - -/* GPIO / PFC */ -#define CONFIG_SH_GPIO_PFC - -/* Clock */ -#define CONFIG_GLOBAL_TIMER -#define CONFIG_SYS_CPU_CLK (1196000000) -#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ - -#endif /* __KZM9G_H */

-- 2.25.1

Tom Rini

21 Aug 21 Aug

4:42 a.m.

New subject: [PATCH 08/21] arm: Remove kzm9g board

On Tue, Aug 02, 2022 at 07:33:34AM -0400, Tom Rini wrote:

...

This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com Cc: Tetsuyuki Kobayashi koba@kmckk.co.jp Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 09/21] net: Remove smc91111 ethernet driver

This driver has not been converted to DM_ETH. The migration deadline passed 2 years ago.

Cc: Linus Walleij linus.walleij@linaro.org Cc: David Feng fenghua@phytium.com.cn Cc: Liviu Dudau liviu.dudau@foss.arm.com Cc: Andre Przywara andre.przywara@arm.com Signed-off-by: Tom Rini trini@konsulko.com --- README | 14 - board/armltd/integrator/integrator.c | 3 - board/armltd/vexpress64/vexpress64.c | 3 - drivers/net/Makefile | 1 - drivers/net/smc91111.c | 1307 ------------------------- drivers/net/smc91111.h | 632 ------------ examples/standalone/Makefile | 1 - examples/standalone/smc91111_eeprom.c | 372 ------- include/configs/integratorcp.h | 8 - include/configs/vexpress_aemv8.h | 6 - 10 files changed, 2347 deletions(-) delete mode 100644 drivers/net/smc91111.c delete mode 100644 drivers/net/smc91111.h delete mode 100644 examples/standalone/smc91111_eeprom.c

diff --git a/README b/README index a6c306149c73..98185af62463 100644 --- a/README +++ b/README @@ -565,20 +565,6 @@ The following options need to be configured: CONFIG_LAN91C96_USE_32_BIT Define this to enable 32 bit addressing

- CONFIG_SMC91111 - Support for SMSC's LAN91C111 chip - - CONFIG_SMC91111_BASE - Define this to hold the physical address - of the device (I/O space) - - CONFIG_SMC_USE_32_BIT - Define this if data bus is 32 bits - - CONFIG_SMC_USE_IOFUNCS - Define this to use i/o functions instead of macros - (some hardware wont work with macros) - CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT Define this if you have more then 3 PHYs.

diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index e734ceae8890..4959a7fd6dcf 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -179,9 +179,6 @@ extern void dram_query(void); int board_eth_init(struct bd_info *bis) { int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif return rc; } #endif diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 709ebf3fb085..05a7a25c32ec 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -200,9 +200,6 @@ int board_eth_init(struct bd_info *bis) { int rc = 0; #ifndef CONFIG_DM_ETH -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif #ifdef CONFIG_SMC911X rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); #endif diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 9536af11946f..ac9818107e7e 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -78,7 +78,6 @@ obj-$(CONFIG_RTL8139) += rtl8139.o obj-$(CONFIG_RTL8169) += rtl8169.o obj-$(CONFIG_SH_ETHER) += sh_eth.o obj-$(CONFIG_SJA1105) += sja1105.o -obj-$(CONFIG_SMC91111) += smc91111.o obj-$(CONFIG_SMC911X) += smc911x.o obj-$(CONFIG_SNI_AVE) += sni_ave.o obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c deleted file mode 100644 index 61d7f3df69ee..000000000000 --- a/drivers/net/smc91111.c +++ /dev/null @@ -1,1307 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*------------------------------------------------------------------------ - . smc91111.c - . This is a driver for SMSC's 91C111 single-chip Ethernet device. - . - . (C) Copyright 2002 - . Sysgo Real-Time Solutions, GmbH <www.elinos.com> - . Rolf Offermanns rof@sysgo.de - . - . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) - . Developed by Simple Network Magic Corporation (SNMC) - . Copyright (C) 1996 by Erik Stahlman (ES) - . - . - . Information contained in this file was obtained from the LAN91C111 - . manual from SMC. To get a copy, if you really want one, you can find - . information under www.smsc.com. - . - . - . "Features" of the SMC chip: - . Integrated PHY/MAC for 10/100BaseT Operation - . Supports internal and external MII - . Integrated 8K packet memory - . EEPROM interface for configuration - . - . Arguments: - . io = for the base address - . irq = for the IRQ - . - . author: - . Erik Stahlman ( erik@vt.edu ) - . Daris A Nevil ( dnevil@snmc.com ) - . - . - . Hardware multicast code from Peter Cammaert ( pc@denkart.be ) - . - . Sources: - . o SMSC LAN91C111 databook (www.smsc.com) - . o smc9194.c by Erik Stahlman - . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) - . - . History: - . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. - . 10/17/01 Marco Hasewinkel Modify for DNP/1110 - . 07/25/01 Woojung Huh Modify for ADS Bitsy - . 04/25/01 Daris A Nevil Initial public release through SMSC - . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111 - ----------------------------------------------------------------------------*/ - -#include <common.h> -#include <command.h> -#include <config.h> -#include <malloc.h> -#include <linux/delay.h> -#include "smc91111.h" -#include <net.h> - -/* Use power-down feature of the chip */ -#define POWER_DOWN 0 - -#define NO_AUTOPROBE - -#define SMC_DEBUG 0 - -#if SMC_DEBUG > 1 -static const char version[] = - "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n"; -#endif - -/* Autonegotiation timeout in seconds */ -#ifndef CONFIG_SMC_AUTONEG_TIMEOUT -#define CONFIG_SMC_AUTONEG_TIMEOUT 10 -#endif - -/*------------------------------------------------------------------------ - . - . Configuration options, for the experienced user to change. - . - -------------------------------------------------------------------------*/ - -/* - . Wait time for memory to be free. This probably shouldn't be - . tuned that much, as waiting for this means nothing else happens - . in the system -*/ -#define MEMORY_WAIT_TIME 16 - - -#if (SMC_DEBUG > 2 ) -#define PRINTK3(args...) printf(args) -#else -#define PRINTK3(args...) -#endif - -#if SMC_DEBUG > 1 -#define PRINTK2(args...) printf(args) -#else -#define PRINTK2(args...) -#endif - -#ifdef SMC_DEBUG -#define PRINTK(args...) printf(args) -#else -#define PRINTK(args...) -#endif - - -/*------------------------------------------------------------------------ - . - . The internal workings of the driver. If you are changing anything - . here with the SMC stuff, you should have the datasheet and know - . what you are doing. - . - -------------------------------------------------------------------------*/ - -/* Memory sizing constant */ -#define LAN91C111_MEMORY_MULTIPLIER (1024*2) - -#ifndef CONFIG_SMC91111_BASE -#error "SMC91111 Base address must be passed to initialization funciton" -/* #define CONFIG_SMC91111_BASE 0x20000300 */ -#endif - -#define SMC_DEV_NAME "SMC91111" -#define SMC_PHY_ADDR 0x0000 -#define SMC_ALLOC_MAX_TRY 5 -#define SMC_TX_TIMEOUT 30 - -#define SMC_PHY_CLOCK_DELAY 1000 - -#define ETH_ZLEN 60 - -#ifdef CONFIG_SMC_USE_32_BIT -#define USE_32_BIT 1 -#else -#undef USE_32_BIT -#endif - -#ifdef SHARED_RESOURCES -extern void swap_to(int device_id); -#else -# define swap_to(x) -#endif - -#ifndef CONFIG_SMC91111_EXT_PHY -static void smc_phy_configure(struct eth_device *dev); -#endif /* !CONFIG_SMC91111_EXT_PHY */ - -/* - ------------------------------------------------------------ - . - . Internal routines - . - ------------------------------------------------------------ -*/ - -#ifdef CONFIG_SMC_USE_IOFUNCS -/* - * input and output functions - * - * Implemented due to inx,outx macros accessing the device improperly - * and putting the device into an unkown state. - * - * For instance, on Sharp LPD7A400 SDK, affects were chip memory - * could not be free'd (hence the alloc failures), duplicate packets, - * packets being corrupt (shifted) on the wire, etc. Switching to the - * inx,outx functions fixed this problem. - */ - -static inline word SMC_inw(struct eth_device *dev, dword offset) -{ - word v; - v = *((volatile word*)(dev->iobase + offset)); - barrier(); *(volatile u32*)(0xc0000000); - return v; -} - -static inline void SMC_outw(struct eth_device *dev, word value, dword offset) -{ - *((volatile word*)(dev->iobase + offset)) = value; - barrier(); *(volatile u32*)(0xc0000000); -} - -static inline byte SMC_inb(struct eth_device *dev, dword offset) -{ - word _w; - - _w = SMC_inw(dev, offset & ~((dword)1)); - return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); -} - -static inline void SMC_outb(struct eth_device *dev, byte value, dword offset) -{ - word _w; - - _w = SMC_inw(dev, offset & ~((dword)1)); - if (offset & 1) - *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) = - (value<<8) | (_w & 0x00ff); - else - *((volatile word*)(dev->iobase + offset)) = - value | (_w & 0xff00); -} - -static inline void SMC_insw(struct eth_device *dev, dword offset, - volatile uchar* buf, dword len) -{ - volatile word *p = (volatile word *)buf; - - while (len-- > 0) { - *p++ = SMC_inw(dev, offset); - barrier(); - *((volatile u32*)(0xc0000000)); - } -} - -static inline void SMC_outsw(struct eth_device *dev, dword offset, - uchar* buf, dword len) -{ - volatile word *p = (volatile word *)buf; - - while (len-- > 0) { - SMC_outw(dev, *p++, offset); - barrier(); - *(volatile u32*)(0xc0000000); - } -} -#endif /* CONFIG_SMC_USE_IOFUNCS */ - -/* - . A rather simple routine to print out a packet for debugging purposes. -*/ -#if SMC_DEBUG > 2 -static void print_packet( byte *, int ); -#endif - -#define tx_done(dev) 1 - -static int poll4int (struct eth_device *dev, byte mask, int timeout) -{ - int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; - int is_timeout = 0; - word old_bank = SMC_inw (dev, BSR_REG); - - PRINTK2 ("Polling...\n"); - SMC_SELECT_BANK (dev, 2); - while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) { - if (get_timer (0) >= tmo) { - is_timeout = 1; - break; - } - } - - /* restore old bank selection */ - SMC_SELECT_BANK (dev, old_bank); - - if (is_timeout) - return 1; - else - return 0; -} - -/* Only one release command at a time, please */ -static inline void smc_wait_mmu_release_complete (struct eth_device *dev) -{ - int count = 0; - - /* assume bank 2 selected */ - while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { - udelay(1); /* Wait until not busy */ - if (++count > 200) - break; - } -} - -/* - . Function: smc_reset( void ) - . Purpose: - . This sets the SMC91111 chip to its normal state, hopefully from whatever - . mess that any other DOS driver has put it in. - . - . Maybe I should reset more registers to defaults in here? SOFTRST should - . do that for me. - . - . Method: - . 1. send a SOFT RESET - . 2. wait for it to finish - . 3. enable autorelease mode - . 4. reset the memory management unit - . 5. clear all interrupts - . -*/ -static void smc_reset (struct eth_device *dev) -{ - PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); - - /* This resets the registers mostly to defaults, but doesn't - affect EEPROM. That seems unnecessary */ - SMC_SELECT_BANK (dev, 0); - SMC_outw (dev, RCR_SOFTRST, RCR_REG); - - /* Setup the Configuration Register */ - /* This is necessary because the CONFIG_REG is not affected */ - /* by a soft reset */ - - SMC_SELECT_BANK (dev, 1); -#if defined(CONFIG_SMC91111_EXT_PHY) - SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); -#else - SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG); -#endif - - - /* Release from possible power-down state */ - /* Configuration register is not affected by Soft Reset */ - SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN, - CONFIG_REG); - - SMC_SELECT_BANK (dev, 0); - - /* this should pause enough for the chip to be happy */ - udelay(10); - - /* Disable transmit and receive functionality */ - SMC_outw (dev, RCR_CLEAR, RCR_REG); - SMC_outw (dev, TCR_CLEAR, TCR_REG); - - /* set the control register */ - SMC_SELECT_BANK (dev, 1); - SMC_outw (dev, CTL_DEFAULT, CTL_REG); - - /* Reset the MMU */ - SMC_SELECT_BANK (dev, 2); - smc_wait_mmu_release_complete (dev); - SMC_outw (dev, MC_RESET, MMU_CMD_REG); - while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) - udelay(1); /* Wait until not busy */ - - /* Note: It doesn't seem that waiting for the MMU busy is needed here, - but this is a place where future chipsets _COULD_ break. Be wary - of issuing another MMU command right after this */ - - /* Disable all interrupts */ - SMC_outb (dev, 0, IM_REG); -} - -/* - . Function: smc_enable - . Purpose: let the chip talk to the outside work - . Method: - . 1. Enable the transmitter - . 2. Enable the receiver - . 3. Enable interrupts -*/ -static void smc_enable(struct eth_device *dev) -{ - PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); - SMC_SELECT_BANK( dev, 0 ); - /* see the header file for options in TCR/RCR DEFAULT*/ - SMC_outw( dev, TCR_DEFAULT, TCR_REG ); - SMC_outw( dev, RCR_DEFAULT, RCR_REG ); - - /* clear MII_DIS */ -/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ -} - -/* - . Function: smc_halt - . Purpose: closes down the SMC91xxx chip. - . Method: - . 1. zero the interrupt mask - . 2. clear the enable receive flag - . 3. clear the enable xmit flags - . - . TODO: - . (1) maybe utilize power down mode. - . Why not yet? Because while the chip will go into power down mode, - . the manual says that it will wake up in response to any I/O requests - . in the register space. Empirical results do not show this working. -*/ -static void smc_halt(struct eth_device *dev) -{ - PRINTK2("%s: smc_halt\n", SMC_DEV_NAME); - - /* no more interrupts for me */ - SMC_SELECT_BANK( dev, 2 ); - SMC_outb( dev, 0, IM_REG ); - - /* and tell the card to stay away from that nasty outside world */ - SMC_SELECT_BANK( dev, 0 ); - SMC_outb( dev, RCR_CLEAR, RCR_REG ); - SMC_outb( dev, TCR_CLEAR, TCR_REG ); - - swap_to(FLASH); -} - - -/* - . Function: smc_send(struct net_device * ) - . Purpose: - . This sends the actual packet to the SMC9xxx chip. - . - . Algorithm: - . First, see if a saved_skb is available. - . ( this should NOT be called if there is no 'saved_skb' - . Now, find the packet number that the chip allocated - . Point the data pointers at it in memory - . Set the length word in the chip's memory - . Dump the packet to chip memory - . Check if a last byte is needed ( odd length packet ) - . if so, set the control flag right - . Tell the card to send it - . Enable the transmit interrupt, so I know if it failed - . Free the kernel data if I actually sent it. -*/ -static int smc_send(struct eth_device *dev, void *packet, int packet_length) -{ - byte packet_no; - byte *buf; - int length; - int numPages; - int try = 0; - int time_out; - byte status; - byte saved_pnr; - word saved_ptr; - - /* save PTR and PNR registers before manipulation */ - SMC_SELECT_BANK (dev, 2); - saved_pnr = SMC_inb( dev, PN_REG ); - saved_ptr = SMC_inw( dev, PTR_REG ); - - PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); - - length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; - - /* allocate memory - ** The MMU wants the number of pages to be the number of 256 bytes - ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) - ** - ** The 91C111 ignores the size bits, but the code is left intact - ** for backwards and future compatibility. - ** - ** Pkt size for allocating is data length +6 (for additional status - ** words, length and ctl!) - ** - ** If odd size then last byte is included in this header. - */ - numPages = ((length & 0xfffe) + 6); - numPages >>= 8; /* Divide by 256 */ - - if (numPages > 7) { - printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); - return 0; - } - - /* now, try to allocate the memory */ - SMC_SELECT_BANK (dev, 2); - SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG); - - /* FIXME: the ALLOC_INT bit never gets set * - * so the following will always give a * - * memory allocation error. * - * same code works in armboot though * - * -ro - */ - -again: - try++; - time_out = MEMORY_WAIT_TIME; - do { - status = SMC_inb (dev, SMC91111_INT_REG); - if (status & IM_ALLOC_INT) { - /* acknowledge the interrupt */ - SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG); - break; - } - } while (--time_out); - - if (!time_out) { - PRINTK2 ("%s: memory allocation, try %d failed ...\n", - SMC_DEV_NAME, try); - if (try < SMC_ALLOC_MAX_TRY) - goto again; - else - return 0; - } - - PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", - SMC_DEV_NAME, try); - - buf = (byte *) packet; - - /* If I get here, I _know_ there is a packet slot waiting for me */ - packet_no = SMC_inb (dev, AR_REG); - if (packet_no & AR_FAILED) { - /* or isn't there? BAD CHIP! */ - printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); - return 0; - } - - /* we have a packet address, so tell the card to use it */ - SMC_outb (dev, packet_no, PN_REG); - - /* do not write new ptr value if Write data fifo not empty */ - while ( saved_ptr & PTR_NOTEMPTY ) - printf ("Write data fifo not empty!\n"); - - /* point to the beginning of the packet */ - SMC_outw (dev, PTR_AUTOINC, PTR_REG); - - PRINTK3 ("%s: Trying to xmit packet of length %x\n", - SMC_DEV_NAME, length); - -#if SMC_DEBUG > 2 - printf ("Transmitting Packet\n"); - print_packet (buf, length); -#endif - - /* send the packet length ( +6 for status, length and ctl byte ) - and the status word ( set to zeros ) */ -#ifdef USE_32_BIT - SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG); -#else - SMC_outw (dev, 0, SMC91111_DATA_REG); - /* send the packet length ( +6 for status words, length, and ctl */ - SMC_outw (dev, (length + 6), SMC91111_DATA_REG); -#endif - - /* send the actual data - . I _think_ it's faster to send the longs first, and then - . mop up by sending the last word. It depends heavily - . on alignment, at least on the 486. Maybe it would be - . a good idea to check which is optimal? But that could take - . almost as much time as is saved? - */ -#ifdef USE_32_BIT - SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); - if (length & 0x2) - SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), - SMC91111_DATA_REG); -#else - SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); -#endif /* USE_32_BIT */ - - /* Send the last byte, if there is one. */ - if ((length & 1) == 0) { - SMC_outw (dev, 0, SMC91111_DATA_REG); - } else { - SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); - } - - /* and let the chipset deal with it */ - SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); - - /* poll for TX INT */ - /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */ - /* poll for TX_EMPTY INT - autorelease enabled */ - if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { - /* sending failed */ - PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); - - /* release packet */ - /* no need to release, MMU does that now */ - - /* wait for MMU getting ready (low) */ - while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { - udelay(10); - } - - PRINTK2 ("MMU ready\n"); - - - return 0; - } else { - /* ack. int */ - SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG); - /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ - PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, - length); - - /* release packet */ - /* no need to release, MMU does that now */ - - /* wait for MMU getting ready (low) */ - while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { - udelay(10); - } - - PRINTK2 ("MMU ready\n"); - - - } - - /* restore previously saved registers */ - SMC_outb( dev, saved_pnr, PN_REG ); - SMC_outw( dev, saved_ptr, PTR_REG ); - - return length; -} - -static int smc_write_hwaddr(struct eth_device *dev) -{ - int i; - - swap_to(ETHERNET); - SMC_SELECT_BANK (dev, 1); -#ifdef USE_32_BIT - for (i = 0; i < 6; i += 2) { - word address; - - address = dev->enetaddr[i + 1] << 8; - address |= dev->enetaddr[i]; - SMC_outw(dev, address, (ADDR0_REG + i)); - } -#else - for (i = 0; i < 6; i++) - SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i)); -#endif - swap_to(FLASH); - return 0; -} - -/* - * Open and Initialize the board - * - * Set up everything, reset the card, etc .. - * - */ -static int smc_init(struct eth_device *dev, struct bd_info *bd) -{ - swap_to(ETHERNET); - - PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME); - - /* reset the hardware */ - smc_reset (dev); - smc_enable (dev); - - /* Configure the PHY */ -#ifndef CONFIG_SMC91111_EXT_PHY - smc_phy_configure (dev); -#endif - - /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ -/* SMC_SELECT_BANK(dev, 0); */ -/* SMC_outw(dev, 0, RPC_REG); */ - - printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr); - - return 0; -} - -/*------------------------------------------------------------- - . - . smc_rcv - receive a packet from the card - . - . There is ( at least ) a packet waiting to be read from - . chip-memory. - . - . o Read the status - . o If an error, record it - . o otherwise, read in the packet - -------------------------------------------------------------- -*/ -static int smc_rcv(struct eth_device *dev) -{ - int packet_number; - word status; - word packet_length; - int is_error = 0; -#ifdef USE_32_BIT - dword stat_len; -#endif - byte saved_pnr; - word saved_ptr; - - SMC_SELECT_BANK(dev, 2); - /* save PTR and PTR registers */ - saved_pnr = SMC_inb( dev, PN_REG ); - saved_ptr = SMC_inw( dev, PTR_REG ); - - packet_number = SMC_inw( dev, RXFIFO_REG ); - - if ( packet_number & RXFIFO_REMPTY ) { - - return 0; - } - - PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); - /* start reading from the start of the packet */ - SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); - - /* First two words are status and packet_length */ -#ifdef USE_32_BIT - stat_len = SMC_inl(dev, SMC91111_DATA_REG); - status = stat_len & 0xffff; - packet_length = stat_len >> 16; -#else - status = SMC_inw( dev, SMC91111_DATA_REG ); - packet_length = SMC_inw( dev, SMC91111_DATA_REG ); -#endif - - packet_length &= 0x07ff; /* mask off top bits */ - - PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ); - - if ( !(status & RS_ERRORS ) ){ - /* Adjust for having already read the first two words */ - packet_length -= 4; /*4; */ - - - /* set odd length for bug in LAN91C111, */ - /* which never sets RS_ODDFRAME */ - /* TODO ? */ - - -#ifdef USE_32_BIT - PRINTK3(" Reading %d dwords (and %d bytes)\n", - packet_length >> 2, packet_length & 3 ); - /* QUESTION: Like in the TX routine, do I want - to send the DWORDs or the bytes first, or some - mixture. A mixture might improve already slow PIO - performance */ - SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0], - packet_length >> 2); - /* read the left over bytes */ - if (packet_length & 3) { - int i; - - byte *tail = (byte *)(net_rx_packets[0] + - (packet_length & ~3)); - dword leftover = SMC_inl(dev, SMC91111_DATA_REG); - for (i=0; i<(packet_length & 3); i++) - *tail++ = (byte) (leftover >> (8*i)) & 0xff; - } -#else - PRINTK3(" Reading %d words and %d byte(s)\n", - (packet_length >> 1 ), packet_length & 1 ); - SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0], - packet_length >> 1); - -#endif /* USE_32_BIT */ - -#if SMC_DEBUG > 2 - printf("Receiving Packet\n"); - print_packet(net_rx_packets[0], packet_length); -#endif - } else { - /* error ... */ - /* TODO ? */ - is_error = 1; - } - - while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) - udelay(1); /* Wait until not busy */ - - /* error or good, tell the card to get rid of this packet */ - SMC_outw( dev, MC_RELEASE, MMU_CMD_REG ); - - while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) - udelay(1); /* Wait until not busy */ - - /* restore saved registers */ - SMC_outb( dev, saved_pnr, PN_REG ); - SMC_outw( dev, saved_ptr, PTR_REG ); - - if (!is_error) { - /* Pass the packet up to the protocol layers. */ - net_process_received_packet(net_rx_packets[0], packet_length); - return packet_length; - } else { - return 0; - } - -} - - -#if 0 -/*------------------------------------------------------------ - . Modify a bit in the LAN91C111 register set - .-------------------------------------------------------------*/ -static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, - unsigned int bit, int val) -{ - word regval; - - SMC_SELECT_BANK( dev, bank ); - - regval = SMC_inw( dev, reg ); - if (val) - regval |= bit; - else - regval &= ~bit; - - SMC_outw( dev, regval, 0 ); - return(regval); -} - - -/*------------------------------------------------------------ - . Retrieve a bit in the LAN91C111 register set - .-------------------------------------------------------------*/ -static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit) -{ - SMC_SELECT_BANK( dev, bank ); - if ( SMC_inw( dev, reg ) & bit) - return(1); - else - return(0); -} - - -/*------------------------------------------------------------ - . Modify a LAN91C111 register (word access only) - .-------------------------------------------------------------*/ -static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val) -{ - SMC_SELECT_BANK( dev, bank ); - SMC_outw( dev, val, reg ); -} - - -/*------------------------------------------------------------ - . Retrieve a LAN91C111 register (word access only) - .-------------------------------------------------------------*/ -static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg) -{ - SMC_SELECT_BANK( dev, bank ); - return(SMC_inw( dev, reg )); -} - -#endif /* 0 */ - -/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */ - -#if (SMC_DEBUG > 2 ) - -/*------------------------------------------------------------ - . Debugging function for viewing MII Management serial bitstream - .-------------------------------------------------------------*/ -static void smc_dump_mii_stream (byte * bits, int size) -{ - int i; - - printf ("BIT#:"); - for (i = 0; i < size; ++i) { - printf ("%d", i % 10); - } - - printf ("\nMDOE:"); - for (i = 0; i < size; ++i) { - if (bits[i] & MII_MDOE) - printf ("1"); - else - printf ("0"); - } - - printf ("\nMDO :"); - for (i = 0; i < size; ++i) { - if (bits[i] & MII_MDO) - printf ("1"); - else - printf ("0"); - } - - printf ("\nMDI :"); - for (i = 0; i < size; ++i) { - if (bits[i] & MII_MDI) - printf ("1"); - else - printf ("0"); - } - - printf ("\n"); -} -#endif - -/*------------------------------------------------------------ - . Reads a register from the MII Management serial interface - .-------------------------------------------------------------*/ -#ifndef CONFIG_SMC91111_EXT_PHY -static word smc_read_phy_register (struct eth_device *dev, byte phyreg) -{ - int oldBank; - int i; - byte mask; - word mii_reg; - byte bits[64]; - int clk_idx = 0; - int input_idx; - word phydata; - byte phyaddr = SMC_PHY_ADDR; - - /* 32 consecutive ones on MDO to establish sync */ - for (i = 0; i < 32; ++i) - bits[clk_idx++] = MII_MDOE | MII_MDO; - - /* Start code <01> */ - bits[clk_idx++] = MII_MDOE; - bits[clk_idx++] = MII_MDOE | MII_MDO; - - /* Read command <10> */ - bits[clk_idx++] = MII_MDOE | MII_MDO; - bits[clk_idx++] = MII_MDOE; - - /* Output the PHY address, msb first */ - mask = (byte) 0x10; - for (i = 0; i < 5; ++i) { - if (phyaddr & mask) - bits[clk_idx++] = MII_MDOE | MII_MDO; - else - bits[clk_idx++] = MII_MDOE; - - /* Shift to next lowest bit */ - mask >>= 1; - } - - /* Output the phy register number, msb first */ - mask = (byte) 0x10; - for (i = 0; i < 5; ++i) { - if (phyreg & mask) - bits[clk_idx++] = MII_MDOE | MII_MDO; - else - bits[clk_idx++] = MII_MDOE; - - /* Shift to next lowest bit */ - mask >>= 1; - } - - /* Tristate and turnaround (2 bit times) */ - bits[clk_idx++] = 0; - /*bits[clk_idx++] = 0; */ - - /* Input starts at this bit time */ - input_idx = clk_idx; - - /* Will input 16 bits */ - for (i = 0; i < 16; ++i) - bits[clk_idx++] = 0; - - /* Final clock bit */ - bits[clk_idx++] = 0; - - /* Save the current bank */ - oldBank = SMC_inw (dev, BANK_SELECT); - - /* Select bank 3 */ - SMC_SELECT_BANK (dev, 3); - - /* Get the current MII register value */ - mii_reg = SMC_inw (dev, MII_REG); - - /* Turn off all MII Interface bits */ - mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); - - /* Clock all 64 cycles */ - for (i = 0; i < sizeof bits; ++i) { - /* Clock Low - output data */ - SMC_outw (dev, mii_reg | bits[i], MII_REG); - udelay(SMC_PHY_CLOCK_DELAY); - - - /* Clock Hi - input data */ - SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); - udelay(SMC_PHY_CLOCK_DELAY); - bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; - } - - /* Return to idle state */ - /* Set clock to low, data to low, and output tristated */ - SMC_outw (dev, mii_reg, MII_REG); - udelay(SMC_PHY_CLOCK_DELAY); - - /* Restore original bank select */ - SMC_SELECT_BANK (dev, oldBank); - - /* Recover input data */ - phydata = 0; - for (i = 0; i < 16; ++i) { - phydata <<= 1; - - if (bits[input_idx++] & MII_MDI) - phydata |= 0x0001; - } - -#if (SMC_DEBUG > 2 ) - printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", - phyaddr, phyreg, phydata); - smc_dump_mii_stream (bits, sizeof bits); -#endif - - return (phydata); -} - - -/*------------------------------------------------------------ - . Writes a register to the MII Management serial interface - .-------------------------------------------------------------*/ -static void smc_write_phy_register (struct eth_device *dev, byte phyreg, - word phydata) -{ - int oldBank; - int i; - word mask; - word mii_reg; - byte bits[65]; - int clk_idx = 0; - byte phyaddr = SMC_PHY_ADDR; - - /* 32 consecutive ones on MDO to establish sync */ - for (i = 0; i < 32; ++i) - bits[clk_idx++] = MII_MDOE | MII_MDO; - - /* Start code <01> */ - bits[clk_idx++] = MII_MDOE; - bits[clk_idx++] = MII_MDOE | MII_MDO; - - /* Write command <01> */ - bits[clk_idx++] = MII_MDOE; - bits[clk_idx++] = MII_MDOE | MII_MDO; - - /* Output the PHY address, msb first */ - mask = (byte) 0x10; - for (i = 0; i < 5; ++i) { - if (phyaddr & mask) - bits[clk_idx++] = MII_MDOE | MII_MDO; - else - bits[clk_idx++] = MII_MDOE; - - /* Shift to next lowest bit */ - mask >>= 1; - } - - /* Output the phy register number, msb first */ - mask = (byte) 0x10; - for (i = 0; i < 5; ++i) { - if (phyreg & mask) - bits[clk_idx++] = MII_MDOE | MII_MDO; - else - bits[clk_idx++] = MII_MDOE; - - /* Shift to next lowest bit */ - mask >>= 1; - } - - /* Tristate and turnaround (2 bit times) */ - bits[clk_idx++] = 0; - bits[clk_idx++] = 0; - - /* Write out 16 bits of data, msb first */ - mask = 0x8000; - for (i = 0; i < 16; ++i) { - if (phydata & mask) - bits[clk_idx++] = MII_MDOE | MII_MDO; - else - bits[clk_idx++] = MII_MDOE; - - /* Shift to next lowest bit */ - mask >>= 1; - } - - /* Final clock bit (tristate) */ - bits[clk_idx++] = 0; - - /* Save the current bank */ - oldBank = SMC_inw (dev, BANK_SELECT); - - /* Select bank 3 */ - SMC_SELECT_BANK (dev, 3); - - /* Get the current MII register value */ - mii_reg = SMC_inw (dev, MII_REG); - - /* Turn off all MII Interface bits */ - mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); - - /* Clock all cycles */ - for (i = 0; i < sizeof bits; ++i) { - /* Clock Low - output data */ - SMC_outw (dev, mii_reg | bits[i], MII_REG); - udelay(SMC_PHY_CLOCK_DELAY); - - - /* Clock Hi - input data */ - SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); - udelay(SMC_PHY_CLOCK_DELAY); - bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; - } - - /* Return to idle state */ - /* Set clock to low, data to low, and output tristated */ - SMC_outw (dev, mii_reg, MII_REG); - udelay(SMC_PHY_CLOCK_DELAY); - - /* Restore original bank select */ - SMC_SELECT_BANK (dev, oldBank); - -#if (SMC_DEBUG > 2 ) - printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", - phyaddr, phyreg, phydata); - smc_dump_mii_stream (bits, sizeof bits); -#endif -} -#endif /* !CONFIG_SMC91111_EXT_PHY */ - - -/*------------------------------------------------------------ - . Configures the specified PHY using Autonegotiation. Calls - . smc_phy_fixed() if the user has requested a certain config. - .-------------------------------------------------------------*/ -#ifndef CONFIG_SMC91111_EXT_PHY -static void smc_phy_configure (struct eth_device *dev) -{ - int timeout; - word my_phy_caps; /* My PHY capabilities */ - word my_ad_caps; /* My Advertised capabilities */ - word status = 0; /*;my status = 0 */ - - PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME); - - /* Reset the PHY, setting all other bits to zero */ - smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST); - - /* Wait for the reset to complete, or time out */ - timeout = 6; /* Wait up to 3 seconds */ - while (timeout--) { - if (!(smc_read_phy_register (dev, PHY_CNTL_REG) - & PHY_CNTL_RST)) { - /* reset complete */ - break; - } - - mdelay(500); /* wait 500 millisecs */ - } - - if (timeout < 1) { - printf ("%s:PHY reset timed out\n", SMC_DEV_NAME); - goto smc_phy_configure_exit; - } - - /* Read PHY Register 18, Status Output */ - /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */ - - /* Enable PHY Interrupts (for register 18) */ - /* Interrupts listed here are disabled */ - smc_write_phy_register (dev, PHY_MASK_REG, 0xffff); - - /* Configure the Receive/Phy Control register */ - SMC_SELECT_BANK (dev, 0); - SMC_outw (dev, RPC_DEFAULT, RPC_REG); - - /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ - my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG); - my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ - - if (my_phy_caps & PHY_STAT_CAP_T4) - my_ad_caps |= PHY_AD_T4; - - if (my_phy_caps & PHY_STAT_CAP_TXF) - my_ad_caps |= PHY_AD_TX_FDX; - - if (my_phy_caps & PHY_STAT_CAP_TXH) - my_ad_caps |= PHY_AD_TX_HDX; - - if (my_phy_caps & PHY_STAT_CAP_TF) - my_ad_caps |= PHY_AD_10_FDX; - - if (my_phy_caps & PHY_STAT_CAP_TH) - my_ad_caps |= PHY_AD_10_HDX; - - /* Update our Auto-Neg Advertisement Register */ - smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps); - - /* Read the register back. Without this, it appears that when */ - /* auto-negotiation is restarted, sometimes it isn't ready and */ - /* the link does not come up. */ - smc_read_phy_register(dev, PHY_AD_REG); - - PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); - PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); - - /* Restart auto-negotiation process in order to advertise my caps */ - smc_write_phy_register (dev, PHY_CNTL_REG, - PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); - - /* Wait for the auto-negotiation to complete. This may take from */ - /* 2 to 3 seconds. */ - /* Wait for the reset to complete, or time out */ - timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; - while (timeout--) { - - status = smc_read_phy_register (dev, PHY_STAT_REG); - if (status & PHY_STAT_ANEG_ACK) { - /* auto-negotiate complete */ - break; - } - - mdelay(500); /* wait 500 millisecs */ - - /* Restart auto-negotiation if remote fault */ - if (status & PHY_STAT_REM_FLT) { - printf ("%s: PHY remote fault detected\n", - SMC_DEV_NAME); - - /* Restart auto-negotiation */ - printf ("%s: PHY restarting auto-negotiation\n", - SMC_DEV_NAME); - smc_write_phy_register (dev, PHY_CNTL_REG, - PHY_CNTL_ANEG_EN | - PHY_CNTL_ANEG_RST | - PHY_CNTL_SPEED | - PHY_CNTL_DPLX); - } - } - - if (timeout < 1) { - printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME); - } - - /* Fail if we detected an auto-negotiate remote fault */ - if (status & PHY_STAT_REM_FLT) { - printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME); - } - - /* Re-Configure the Receive/Phy Control register */ - SMC_outw (dev, RPC_DEFAULT, RPC_REG); - -smc_phy_configure_exit: ; - -} -#endif /* !CONFIG_SMC91111_EXT_PHY */ - - -#if SMC_DEBUG > 2 -static void print_packet( byte * buf, int length ) -{ - int i; - int remainder; - int lines; - - printf("Packet of length %d \n", length ); - -#if SMC_DEBUG > 3 - lines = length / 16; - remainder = length % 16; - - for ( i = 0; i < lines ; i ++ ) { - int cur; - - for ( cur = 0; cur < 8; cur ++ ) { - byte a, b; - - a = *(buf ++ ); - b = *(buf ++ ); - printf("%02x%02x ", a, b ); - } - printf("\n"); - } - for ( i = 0; i < remainder/2 ; i++ ) { - byte a, b; - - a = *(buf ++ ); - b = *(buf ++ ); - printf("%02x%02x ", a, b ); - } - printf("\n"); -#endif -} -#endif - -int smc91111_initialize(u8 dev_num, phys_addr_t base_addr) -{ - struct smc91111_priv *priv; - struct eth_device *dev; - int i; - - priv = malloc(sizeof(*priv)); - if (!priv) - return 0; - dev = malloc(sizeof(*dev)); - if (!dev) { - free(priv); - return 0; - } - - memset(dev, 0, sizeof(*dev)); - priv->dev_num = dev_num; - dev->priv = priv; - dev->iobase = base_addr; - - swap_to(ETHERNET); - SMC_SELECT_BANK(dev, 1); - for (i = 0; i < 6; ++i) - dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i)); - swap_to(FLASH); - - dev->init = smc_init; - dev->halt = smc_halt; - dev->send = smc_send; - dev->recv = smc_rcv; - dev->write_hwaddr = smc_write_hwaddr; - sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num); - - eth_register(dev); - return 0; -} diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h deleted file mode 100644 index f2ba34474598..000000000000 --- a/drivers/net/smc91111.h +++ /dev/null @@ -1,632 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*------------------------------------------------------------------------ - . smc91111.h - macros for the LAN91C111 Ethernet Driver - . - . (C) Copyright 2002 - . Sysgo Real-Time Solutions, GmbH <www.elinos.com> - . Rolf Offermanns rof@sysgo.de - . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) - . Developed by Simple Network Magic Corporation (SNMC) - . Copyright (C) 1996 by Erik Stahlman (ES) - . - . This file contains register information and access macros for - . the LAN91C111 single chip ethernet controller. It is a modified - . version of the smc9194.h file. - . - . Information contained in this file was obtained from the LAN91C111 - . manual from SMC. To get a copy, if you really want one, you can find - . information under www.smsc.com. - . - . Authors - . Erik Stahlman ( erik@vt.edu ) - . Daris A Nevil ( dnevil@snmc.com ) - . - . History - . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device - . - ---------------------------------------------------------------------------*/ -#ifndef _SMC91111_H_ -#define _SMC91111_H_ - -#include <asm/types.h> -#include <config.h> -#include <net.h> - -/* - * This function may be called by the board specific initialisation code - * in order to override the default mac address. - */ - -void smc_set_mac_addr (const unsigned char *addr); - - -/* I want some simple types */ - -typedef unsigned char byte; -typedef unsigned short word; -typedef unsigned long int dword; - -struct smc91111_priv{ - u8 dev_num; -}; - -/* - . DEBUGGING LEVELS - . - . 0 for normal operation - . 1 for slightly more details - . >2 for various levels of increasingly useless information - . 2 for interrupt tracking, status flags - . 3 for packet info - . 4 for complete packet dumps -*/ -/*#define SMC_DEBUG 0 */ - -/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ - -#define SMC_IO_EXTENT 16 - -#if defined(CONFIG_MS7206SE) -#define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); }) -#define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r))) -#define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01)))) -#define SMC_insw(a, r, b, l) \ - do { \ - int __i; \ - word *__b2 = (word *)(b); \ - for (__i = 0; __i < (l); __i++) { \ - *__b2++ = SWAB7206(SMC_inw(a, r)); \ - } \ - } while (0) -#define SMC_outw(a, d, r) (*((volatile word *)((a)->iobase+(r))) = d) -#define SMC_outb(a, d, r) ({ word __d = (byte)(d); \ - word __w = SMC_inw((a), ((r)&(~1))); \ - if (((r) & 1)) \ - __w = (__w & 0x00ff) | (__d << 8); \ - else \ - __w = (__w & 0xff00) | (__d); \ - SMC_outw((a), __w, ((r)&(~1))); \ - }) -#define SMC_outsw(a, r, b, l) \ - do { \ - int __i; \ - word *__b2 = (word *)(b); \ - for (__i = 0; __i < (l); __i++) { \ - SMC_outw(a, SWAB7206(*__b2), r); \ - __b2++; \ - } \ - } while (0) -#else - -#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ -/* - * We have only 16 Bit PCMCIA access on Socket 0 - */ - -#if CONFIG_ARM64 -#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) -#else -#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) -#endif -#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) - -#if CONFIG_ARM64 -#define SMC_outw(a, d, r) \ - (*((volatile word*)((a)->iobase+((dword)(r)))) = d) -#else -#define SMC_outw(a, d, r) \ - (*((volatile word*)((a)->iobase+(r))) = d) -#endif -#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ - word __w = SMC_inw((a),(r)&~1); \ - __w &= ((r)&1) ? 0x00FF : 0xFF00; \ - __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw((a),__w,(r)&~1); \ - }) -#if 0 -#define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l)) -#else -#define SMC_outsw(a,r,b,l) ({ int __i; \ - word *__b2; \ - __b2 = (word *) b; \ - for (__i = 0; __i < l; __i++) { \ - SMC_outw((a), *(__b2 + __i), r); \ - } \ - }) -#endif - -#if 0 -#define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l)) -#else -#define SMC_insw(a,r,b,l) ({ int __i ; \ - word *__b2; \ - __b2 = (word *) b; \ - for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw((a),(r)); \ - SMC_inw((a),0); \ - }; \ - }) -#endif - -#endif /* CONFIG_SMC_USE_IOFUNCS */ - -#if defined(CONFIG_SMC_USE_32_BIT) - -#ifdef CONFIG_XSENGINE -#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) -#else -#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) -#endif - -#define SMC_insl(a,r,b,l) ({ int __i ; \ - dword *__b2; \ - __b2 = (dword *) b; \ - for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inl((a),(r)); \ - SMC_inl((a),0); \ - }; \ - }) - -#ifdef CONFIG_XSENGINE -#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) -#else -#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) -#endif -#define SMC_outsl(a,r,b,l) ({ int __i; \ - dword *__b2; \ - __b2 = (dword *) b; \ - for (__i = 0; __i < l; __i++) { \ - SMC_outl((a), *(__b2 + __i), r); \ - } \ - }) - -#endif /* CONFIG_SMC_USE_32_BIT */ - -#endif - -/*--------------------------------------------------------------- - . - . A description of the SMSC registers is probably in order here, - . although for details, the SMC datasheet is invaluable. - . - . Basically, the chip has 4 banks of registers ( 0 to 3 ), which - . are accessed by writing a number into the BANK_SELECT register - . ( I also use a SMC_SELECT_BANK macro for this ). - . - . The banks are configured so that for most purposes, bank 2 is all - . that is needed for simple run time tasks. - -----------------------------------------------------------------------*/ - -/* - . Bank Select Register: - . - . yyyy yyyy 0000 00xx - . xx = bank number - . yyyy yyyy = 0x33, for identification purposes. -*/ -#define BANK_SELECT 14 - -/* Transmit Control Register */ -/* BANK 0 */ -#define TCR_REG 0x0000 /* transmit control register */ -#define TCR_ENABLE 0x0001 /* When 1 we can transmit */ -#define TCR_LOOP 0x0002 /* Controls output pin LBK */ -#define TCR_FORCOL 0x0004 /* When 1 will force a collision */ -#define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ -#define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ -#define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ -#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ -#define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ -#define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ -#define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ - -#define TCR_CLEAR 0 /* do NOTHING */ -/* the default settings for the TCR register : */ -/* QUESTION: do I want to enable padding of short packets ? */ -#define TCR_DEFAULT TCR_ENABLE - - -/* EPH Status Register */ -/* BANK 0 */ -#define EPH_STATUS_REG 0x0002 -#define ES_TX_SUC 0x0001 /* Last TX was successful */ -#define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ -#define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ -#define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ -#define ES_16COL 0x0010 /* 16 Collisions Reached */ -#define ES_SQET 0x0020 /* Signal Quality Error Test */ -#define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ -#define ES_TXDEFR 0x0080 /* Transmit Deferred */ -#define ES_LATCOL 0x0200 /* Late collision detected on last tx */ -#define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ -#define ES_EXC_DEF 0x0800 /* Excessive Deferral */ -#define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ -#define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ -#define ES_TXUNRN 0x8000 /* Tx Underrun */ - - -/* Receive Control Register */ -/* BANK 0 */ -#define RCR_REG 0x0004 -#define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ -#define RCR_PRMS 0x0002 /* Enable promiscuous mode */ -#define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ -#define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ -#define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ -#define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ -#define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ -#define RCR_SOFTRST 0x8000 /* resets the chip */ - -/* the normal settings for the RCR register : */ -#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) -#define RCR_CLEAR 0x0 /* set it to a base state */ - -/* Counter Register */ -/* BANK 0 */ -#define COUNTER_REG 0x0006 - -/* Memory Information Register */ -/* BANK 0 */ -#define MIR_REG 0x0008 - -/* Receive/Phy Control Register */ -/* BANK 0 */ -#define RPC_REG 0x000A -#define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ -#define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ -#define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ -#define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ -#define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ -#define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ -#define RPC_LED_RES (0x01) /* LED = Reserved */ -#define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ -#define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ -#define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ -#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ -#define RPC_LED_TX (0x06) /* LED = TX packet occurred */ -#define RPC_LED_RX (0x07) /* LED = RX packet occurred */ -#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) -/* buggy schematic: LEDa -> yellow, LEDb --> green */ -#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ - | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ - | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) -#else -/* SMSC reference design: LEDa --> green, LEDb --> yellow */ -#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ - | (RPC_LED_100_10 << RPC_LSXA_SHFT) \ - | (RPC_LED_TX_RX << RPC_LSXB_SHFT) ) -#endif - -/* Bank 0 0x000C is reserved */ - -/* Bank Select Register */ -/* All Banks */ -#define BSR_REG 0x000E - - -/* Configuration Reg */ -/* BANK 1 */ -#define CONFIG_REG 0x0000 -#define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ -#define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ -#define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ -#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */ - -/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ -#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) - - -/* Base Address Register */ -/* BANK 1 */ -#define BASE_REG 0x0002 - - -/* Individual Address Registers */ -/* BANK 1 */ -#define ADDR0_REG 0x0004 -#define ADDR1_REG 0x0006 -#define ADDR2_REG 0x0008 - - -/* General Purpose Register */ -/* BANK 1 */ -#define GP_REG 0x000A - - -/* Control Register */ -/* BANK 1 */ -#define CTL_REG 0x000C -#define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ -#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ -#define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ -#define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ -#define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ -#define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ -#define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ -#define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ -#define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/ - -/* MMU Command Register */ -/* BANK 2 */ -#define MMU_CMD_REG 0x0000 -#define MC_BUSY 1 /* When 1 the last release has not completed */ -#define MC_NOP (0<<5) /* No Op */ -#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ -#define MC_RESET (2<<5) /* Reset MMU to initial state */ -#define MC_REMOVE (3<<5) /* Remove the current rx packet */ -#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ -#define MC_FREEPKT (5<<5) /* Release packet in PNR register */ -#define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ -#define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ - - -/* Packet Number Register */ -/* BANK 2 */ -#define PN_REG 0x0002 - - -/* Allocation Result Register */ -/* BANK 2 */ -#define AR_REG 0x0003 -#define AR_FAILED 0x80 /* Alocation Failed */ - - -/* RX FIFO Ports Register */ -/* BANK 2 */ -#define RXFIFO_REG 0x0004 /* Must be read as a word */ -#define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */ - - -/* TX FIFO Ports Register */ -/* BANK 2 */ -#define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ -#define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ - - -/* Pointer Register */ -/* BANK 2 */ -#define PTR_REG 0x0006 -#define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ -#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ -#define PTR_READ 0x2000 /* When 1 the operation is a read */ -#define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ - - -/* Data Register */ -/* BANK 2 */ -#define SMC91111_DATA_REG 0x0008 - - -/* Interrupt Status/Acknowledge Register */ -/* BANK 2 */ -#define SMC91111_INT_REG 0x000C - - -/* Interrupt Mask Register */ -/* BANK 2 */ -#define IM_REG 0x000D -#define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ -#define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ -#define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ -#define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ -#define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ -#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ -#define IM_TX_INT 0x02 /* Transmit Interrrupt */ -#define IM_RCV_INT 0x01 /* Receive Interrupt */ - - -/* Multicast Table Registers */ -/* BANK 3 */ -#define MCAST_REG1 0x0000 -#define MCAST_REG2 0x0002 -#define MCAST_REG3 0x0004 -#define MCAST_REG4 0x0006 - - -/* Management Interface Register (MII) */ -/* BANK 3 */ -#define MII_REG 0x0008 -#define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ -#define MII_MDOE 0x0008 /* MII Output Enable */ -#define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ -#define MII_MDI 0x0002 /* MII Input, pin MDI */ -#define MII_MDO 0x0001 /* MII Output, pin MDO */ - - -/* Revision Register */ -/* BANK 3 */ -#define REV_REG 0x000A /* ( hi: chip id low: rev # ) */ - - -/* Early RCV Register */ -/* BANK 3 */ -/* this is NOT on SMC9192 */ -#define ERCV_REG 0x000C -#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ -#define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ - -/* External Register */ -/* BANK 7 */ -#define EXT_REG 0x0000 - - -#define CHIP_9192 3 -#define CHIP_9194 4 -#define CHIP_9195 5 -#define CHIP_9196 6 -#define CHIP_91100 7 -#define CHIP_91100FD 8 -#define CHIP_91111FD 9 - -#if 0 -static const char * chip_ids[ 15 ] = { - NULL, NULL, NULL, - /* 3 */ "SMC91C90/91C92", - /* 4 */ "SMC91C94", - /* 5 */ "SMC91C95", - /* 6 */ "SMC91C96", - /* 7 */ "SMC91C100", - /* 8 */ "SMC91C100FD", - /* 9 */ "SMC91C111", - NULL, NULL, - NULL, NULL, NULL}; -#endif - -/* - . Transmit status bits -*/ -#define TS_SUCCESS 0x0001 -#define TS_LOSTCAR 0x0400 -#define TS_LATCOL 0x0200 -#define TS_16COL 0x0010 - -/* - . Receive status bits -*/ -#define RS_ALGNERR 0x8000 -#define RS_BRODCAST 0x4000 -#define RS_BADCRC 0x2000 -#define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ -#define RS_TOOLONG 0x0800 -#define RS_TOOSHORT 0x0400 -#define RS_MULTICAST 0x0001 -#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) - - -/* PHY Types */ -enum { - PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */ - PHY_LAN83C180 -}; - - -/* PHY Register Addresses (LAN91C111 Internal PHY) */ - -/* PHY Control Register */ -#define PHY_CNTL_REG 0x00 -#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ -#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ -#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ -#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ -#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ -#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ -#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ -#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ -#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ - -/* PHY Status Register */ -#define PHY_STAT_REG 0x01 -#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ -#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ -#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ -#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ -#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ -#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ -#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ -#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ -#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ -#define PHY_STAT_LINK 0x0004 /* 1=valid link */ -#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ -#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ - -/* PHY Identifier Registers */ -#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ -#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ - -/* PHY Auto-Negotiation Advertisement Register */ -#define PHY_AD_REG 0x04 -#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ -#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ -#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ -#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ -#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ -#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ -#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ -#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ -#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ - -/* PHY Auto-negotiation Remote End Capability Register */ -#define PHY_RMT_REG 0x05 -/* Uses same bit definitions as PHY_AD_REG */ - -/* PHY Configuration Register 1 */ -#define PHY_CFG1_REG 0x10 -#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ -#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ -#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ -#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ -#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ -#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ -#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ -#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ -#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ -#define PHY_CFG1_TLVL_MASK 0x003C -#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ - - -/* PHY Configuration Register 2 */ -#define PHY_CFG2_REG 0x11 -#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ -#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ -#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ -#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ - -/* PHY Status Output (and Interrupt status) Register */ -#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ -#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ -#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ -#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ -#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ -#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ -#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ -#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ -#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ -#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ -#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ - -/* PHY Interrupt/Status Mask Register */ -#define PHY_MASK_REG 0x13 /* Interrupt Mask */ -/* Uses the same bit definitions as PHY_INT_REG */ - - -/*------------------------------------------------------------------------- - . I define some macros to make it easier to do somewhat common - . or slightly complicated, repeated tasks. - --------------------------------------------------------------------------*/ - -/* select a register bank, 0 to 3 */ - -#define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); } - -/* this enables an interrupt in the interrupt mask register */ -#define SMC_ENABLE_INT(a,x) {\ - unsigned char mask;\ - SMC_SELECT_BANK((a),2);\ - mask = SMC_inb((a), IM_REG );\ - mask |= (x);\ - SMC_outb( (a), mask, IM_REG ); \ -} - -/* this disables an interrupt from the interrupt mask register */ - -#define SMC_DISABLE_INT(a,x) {\ - unsigned char mask;\ - SMC_SELECT_BANK(2);\ - mask = SMC_inb( (a), IM_REG );\ - mask &= ~(x);\ - SMC_outb( (a), mask, IM_REG ); \ -} - -/*---------------------------------------------------------------------- - . Define the interrupts that I want to receive from the card - . - . I want: - . IM_EPH_INT, for nasty errors - . IM_RCV_INT, for happy received packets - . IM_RX_OVRN_INT, because I have to kick the receiver - . IM_MDINT, for PHY Register 18 Status Changes - --------------------------------------------------------------------------*/ -#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \ - IM_MDINT) - -#endif /* _SMC_91111_H_ */ diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index d4be0c7350dc..5b48a9d43c62 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -4,7 +4,6 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de.

extra-y := hello_world -extra-$(CONFIG_SMC91111) += smc91111_eeprom extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2 extra-$(CONFIG_PPC) += sched

diff --git a/examples/standalone/smc91111_eeprom.c b/examples/standalone/smc91111_eeprom.c deleted file mode 100644 index bf7e93064309..000000000000 --- a/examples/standalone/smc91111_eeprom.c +++ /dev/null @@ -1,372 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2004 - * Robin Getz rgetz@blacfin.uclinux.org - * - * Heavily borrowed from the following peoples GPL'ed software: - * - Wolfgang Denk, DENX Software Engineering, wd@denx.de - * Das U-Boot - * - Ladislav Michl ladis@linux-mips.org - * A rejected patch on the U-Boot mailing list - */ - -#include <common.h> -#include <exports.h> -#include <linux/delay.h> -#include "../drivers/net/smc91111.h" - -#ifndef SMC91111_EEPROM_INIT -# define SMC91111_EEPROM_INIT() -#endif - -#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE -#define EEPROM 0x1 -#define MAC 0x2 -#define UNKNOWN 0x4 - -void dump_reg (struct eth_device *dev); -void dump_eeprom (struct eth_device *dev); -int write_eeprom_reg (struct eth_device *dev, int value, int reg); -void copy_from_eeprom (struct eth_device *dev); -void print_MAC (struct eth_device *dev); -int read_eeprom_reg (struct eth_device *dev, int reg); -void print_macaddr (struct eth_device *dev); - -int smc91111_eeprom(int argc, char *const argv[]) -{ - int c, i, j, done, line, reg, value, start, what; - char input[50]; - - struct eth_device dev; - dev.iobase = CONFIG_SMC91111_BASE; - - /* Print the ABI version */ - app_startup (argv); - if (XF_VERSION != (int) get_version ()) { - printf ("Expects ABI version %d\n", XF_VERSION); - printf ("Actual U-Boot ABI version %d\n", - (int) get_version ()); - printf ("Can't run\n\n"); - return (0); - } - - SMC91111_EEPROM_INIT(); - - if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) { - printf ("Can't find SMSC91111\n"); - return (0); - } - - done = 0; - what = UNKNOWN; - printf ("\n"); - while (!done) { - /* print the prompt */ - printf ("SMC91111> "); - line = 0; - i = 0; - start = 1; - while (!line) { - /* Wait for a keystroke */ - while (!tstc ()); - - c = getc (); - /* Make Uppercase */ - if (c >= 'Z') - c -= ('a' - 'A'); - /* printf(" |%02x| ",c); */ - - switch (c) { - case '\r': /* Enter */ - case '\n': - input[i] = 0; - puts ("\r\n"); - line = 1; - break; - case '\0': /* nul */ - continue; - - case 0x03: /* ^C - break */ - input[0] = 0; - i = 0; - line = 1; - done = 1; - break; - - case 0x5F: - case 0x08: /* ^H - backspace */ - case 0x7F: /* DEL - backspace */ - if (i > 0) { - puts ("\b \b"); - i--; - } - break; - default: - if (start) { - if ((c == 'W') || (c == 'D') - || (c == 'M') || (c == 'C') - || (c == 'P')) { - putc (c); - input[i] = c; - if (i <= 45) - i++; - start = 0; - } - } else { - if ((c >= '0' && c <= '9') - || (c >= 'A' && c <= 'F') - || (c == 'E') || (c == 'M') - || (c == ' ')) { - putc (c); - input[i] = c; - if (i <= 45) - i++; - break; - } - } - break; - } - } - - for (; i < 49; i++) - input[i] = 0; - - switch (input[0]) { - case ('W'): - /* Line should be w reg value */ - i = 0; - reg = 0; - value = 0; - /* Skip to the next space or end) */ - while ((input[i] != ' ') && (input[i] != 0)) - i++; - - if (input[i] != 0) - i++; - - /* Are we writing to EEPROM or MAC */ - switch (input[i]) { - case ('E'): - what = EEPROM; - break; - case ('M'): - what = MAC; - break; - default: - what = UNKNOWN; - break; - } - - /* skip to the next space or end */ - while ((input[i] != ' ') && (input[i] != 0)) - i++; - if (input[i] != 0) - i++; - - /* Find register to write into */ - j = 0; - while ((input[i] != ' ') && (input[i] != 0)) { - j = input[i] - 0x30; - if (j >= 0xA) { - j -= 0x07; - } - reg = (reg * 0x10) + j; - i++; - } - - while ((input[i] != ' ') && (input[i] != 0)) - i++; - - if (input[i] != 0) - i++; - else - what = UNKNOWN; - - /* Get the value to write */ - j = 0; - while ((input[i] != ' ') && (input[i] != 0)) { - j = input[i] - 0x30; - if (j >= 0xA) { - j -= 0x07; - } - value = (value * 0x10) + j; - i++; - } - - switch (what) { - case 1: - printf ("Writing EEPROM register %02x with %04x\n", reg, value); - write_eeprom_reg (&dev, value, reg); - break; - case 2: - printf ("Writing MAC register bank %i, reg %02x with %04x\n", reg >> 4, reg & 0xE, value); - SMC_SELECT_BANK (&dev, reg >> 4); - SMC_outw (&dev, value, reg & 0xE); - break; - default: - printf ("Wrong\n"); - break; - } - break; - case ('D'): - dump_eeprom (&dev); - break; - case ('M'): - dump_reg (&dev); - break; - case ('C'): - copy_from_eeprom (&dev); - break; - case ('P'): - print_macaddr (&dev); - break; - default: - break; - } - - } - - return (0); -} - -void copy_from_eeprom (struct eth_device *dev) -{ - int i; - - SMC_SELECT_BANK (dev, 1); - SMC_outw (dev, (SMC_inw (dev, CTL_REG) & !CTL_EEPROM_SELECT) | - CTL_RELOAD, CTL_REG); - i = 100; - while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --i) - udelay(100); - if (i == 0) { - printf ("Timeout Refreshing EEPROM registers\n"); - } else { - printf ("EEPROM contents copied to MAC\n"); - } - -} - -void print_macaddr (struct eth_device *dev) -{ - int i, j, k, mac[6]; - - printf ("Current MAC Address in SMSC91111 "); - SMC_SELECT_BANK (dev, 1); - for (i = 0; i < 5; i++) { - printf ("%02x:", SMC_inb (dev, ADDR0_REG + i)); - } - - printf ("%02x\n", SMC_inb (dev, ADDR0_REG + 5)); - - i = 0; - for (j = 0x20; j < 0x23; j++) { - k = read_eeprom_reg (dev, j); - mac[i] = k & 0xFF; - i++; - mac[i] = k >> 8; - i++; - } - - printf ("Current MAC Address in EEPROM "); - for (i = 0; i < 5; i++) - printf ("%02x:", mac[i]); - printf ("%02x\n", mac[5]); - -} -void dump_eeprom (struct eth_device *dev) -{ - int j, k; - - printf ("IOS2-0 "); - for (j = 0; j < 8; j++) { - printf ("%03x ", j); - } - printf ("\n"); - - for (k = 0; k < 4; k++) { - if (k == 0) - printf ("CONFIG "); - if (k == 1) - printf ("BASE "); - if ((k == 2) || (k == 3)) - printf (" "); - for (j = 0; j < 0x20; j += 4) { - printf ("%02x:%04x ", j + k, - read_eeprom_reg (dev, j + k)); - } - printf ("\n"); - } - - for (j = 0x20; j < 0x40; j++) { - if ((j & 0x07) == 0) - printf ("\n"); - printf ("%02x:%04x ", j, read_eeprom_reg (dev, j)); - } - printf ("\n"); - -} - -int read_eeprom_reg (struct eth_device *dev, int reg) -{ - int timeout; - - SMC_SELECT_BANK (dev, 2); - SMC_outw (dev, reg, PTR_REG); - - SMC_SELECT_BANK (dev, 1); - SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | - CTL_RELOAD, CTL_REG); - timeout = 100; - while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout) - udelay(100); - if (timeout == 0) { - printf ("Timeout Reading EEPROM register %02x\n", reg); - return 0; - } - - return SMC_inw (dev, GP_REG); - -} - -int write_eeprom_reg (struct eth_device *dev, int value, int reg) -{ - int timeout; - - SMC_SELECT_BANK (dev, 2); - SMC_outw (dev, reg, PTR_REG); - - SMC_SELECT_BANK (dev, 1); - SMC_outw (dev, value, GP_REG); - SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | - CTL_STORE, CTL_REG); - timeout = 100; - while ((SMC_inw (dev, CTL_REG) & CTL_STORE) && --timeout) - udelay(100); - if (timeout == 0) { - printf ("Timeout Writing EEPROM register %02x\n", reg); - return 0; - } - - return 1; - -} - -void dump_reg (struct eth_device *dev) -{ - int i, j; - - printf (" "); - for (j = 0; j < 4; j++) { - printf ("Bank%i ", j); - } - printf ("\n"); - for (i = 0; i < 0xF; i += 2) { - printf ("%02x ", i); - for (j = 0; j < 4; j++) { - SMC_SELECT_BANK (dev, j); - printf ("%04x ", SMC_inw (dev, i)); - } - printf ("\n"); - } -} diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 2752152f68ee..7b9a5b1c5415 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -19,14 +19,6 @@ /* Integrator CP-specific configuration */ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */

-/* - * Hardware drivers - */ -#define CONFIG_SMC91111 -#define CONFIG_SMC_USE_32_BIT -#define CONFIG_SMC91111_BASE 0xC8000000 -#undef CONFIG_SMC91111_EXT_PHY - #define CONFIG_SERVERIP 192.168.1.100 #define CONFIG_IPADDR 192.168.1.104

diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 077428f50040..0c11b6b3331e 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -84,12 +84,6 @@ #endif #endif /* !CONFIG_GICV3 */

-#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && !defined(CONFIG_DM_ETH) -/* The Vexpress64 BASE_FVP simulator uses SMSC91C111 */ -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000) -#endif - /* PL011 Serial Configuration */ #ifdef CONFIG_TARGET_VEXPRESS64_JUNO #define CONFIG_PL011_CLOCK 7372800

-- 2.25.1

Ramon Fried

6 Aug 6 Aug

7:47 p.m.

New subject: [PATCH 09/21] net: Remove smc91111 ethernet driver

On Tue, Aug 2, 2022 at 2:37 PM Tom Rini trini@konsulko.com wrote:

...

This driver has not been converted to DM_ETH. The migration deadline passed 2 years ago.

Cc: Linus Walleij linus.walleij@linaro.org Cc: David Feng fenghua@phytium.com.cn Cc: Liviu Dudau liviu.dudau@foss.arm.com Cc: Andre Przywara andre.przywara@arm.com Signed-off-by: Tom Rini trini@konsulko.com

README | 14 - board/armltd/integrator/integrator.c | 3 - board/armltd/vexpress64/vexpress64.c | 3 - drivers/net/Makefile | 1 - drivers/net/smc91111.c | 1307 ------------------------- drivers/net/smc91111.h | 632 ------------ examples/standalone/Makefile | 1 - examples/standalone/smc91111_eeprom.c | 372 ------- include/configs/integratorcp.h | 8 - include/configs/vexpress_aemv8.h | 6 - 10 files changed, 2347 deletions(-) delete mode 100644 drivers/net/smc91111.c delete mode 100644 drivers/net/smc91111.h delete mode 100644 examples/standalone/smc91111_eeprom.c

diff --git a/README b/README index a6c306149c73..98185af62463 100644 --- a/README +++ b/README @@ -565,20 +565,6 @@ The following options need to be configured: CONFIG_LAN91C96_USE_32_BIT Define this to enable 32 bit addressing
          CONFIG_SMC91111
          Support for SMSC's LAN91C111 chip
                  CONFIG_SMC91111_BASE
                  Define this to hold the physical address
                  of the device (I/O space)
                  CONFIG_SMC_USE_32_BIT
                  Define this if data bus is 32 bits
                  CONFIG_SMC_USE_IOFUNCS
                  Define this to use i/o functions instead of macros
                  (some hardware wont work with macros)
                  CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
                  Define this if you have more then 3 PHYs.
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index e734ceae8890..4959a7fd6dcf 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -179,9 +179,6 @@ extern void dram_query(void); int board_eth_init(struct bd_info *bis) { int rc = 0; -#ifdef CONFIG_SMC91111
  rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif return rc; } #endif diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 709ebf3fb085..05a7a25c32ec 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -200,9 +200,6 @@ int board_eth_init(struct bd_info *bis) { int rc = 0; #ifndef CONFIG_DM_ETH -#ifdef CONFIG_SMC91111
  rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif #ifdef CONFIG_SMC911X rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); #endif diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 9536af11946f..ac9818107e7e 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -78,7 +78,6 @@ obj-$(CONFIG_RTL8139) += rtl8139.o obj-$(CONFIG_RTL8169) += rtl8169.o obj-$(CONFIG_SH_ETHER) += sh_eth.o obj-$(CONFIG_SJA1105) += sja1105.o -obj-$(CONFIG_SMC91111) += smc91111.o obj-$(CONFIG_SMC911X) += smc911x.o obj-$(CONFIG_SNI_AVE) += sni_ave.o obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c deleted file mode 100644 index 61d7f3df69ee..000000000000 --- a/drivers/net/smc91111.c +++ /dev/null @@ -1,1307 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*------------------------------------------------------------------------

. smc91111.c

. This is a driver for SMSC's 91C111 single-chip Ethernet device.

.

. (C) Copyright 2002

. Sysgo Real-Time Solutions, GmbH <www.elinos.com>

. Rolf Offermanns rof@sysgo.de

.

. Copyright (C) 2001 Standard Microsystems Corporation (SMSC)

. Developed by Simple Network Magic Corporation (SNMC)

. Copyright (C) 1996 by Erik Stahlman (ES)

.

.

. Information contained in this file was obtained from the LAN91C111

. manual from SMC. To get a copy, if you really want one, you can find

. information under www.smsc.com.

.

.

. "Features" of the SMC chip:

. Integrated PHY/MAC for 10/100BaseT Operation

. Supports internal and external MII

. Integrated 8K packet memory

. EEPROM interface for configuration

.

. Arguments:

. io = for the base address

. irq = for the IRQ

.

. author:

. Erik Stahlman ( erik@vt.edu )

. Daris A Nevil ( dnevil@snmc.com )

.

.

. Hardware multicast code from Peter Cammaert ( pc@denkart.be )

.

. Sources:

. o SMSC LAN91C111 databook (www.smsc.com)

. o smc9194.c by Erik Stahlman

. o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )

.

. History:

. 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.

. 10/17/01 Marco Hasewinkel Modify for DNP/1110

. 07/25/01 Woojung Huh Modify for ADS Bitsy

. 04/25/01 Daris A Nevil Initial public release through SMSC

. 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111

----------------------------------------------------------------------------*/

-#include <common.h> -#include <command.h> -#include <config.h> -#include <malloc.h> -#include <linux/delay.h> -#include "smc91111.h" -#include <net.h>

-/* Use power-down feature of the chip */ -#define POWER_DOWN 0

-#define NO_AUTOPROBE

-#define SMC_DEBUG 0

-#if SMC_DEBUG > 1 -static const char version[] =
  "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
-#endif

-/* Autonegotiation timeout in seconds */ -#ifndef CONFIG_SMC_AUTONEG_TIMEOUT -#define CONFIG_SMC_AUTONEG_TIMEOUT 10 -#endif

-/*------------------------------------------------------------------------

.

. Configuration options, for the experienced user to change.

.

-------------------------------------------------------------------------*/

-/*

. Wait time for memory to be free. This probably shouldn't be

. tuned that much, as waiting for this means nothing else happens

. in the system

-*/ -#define MEMORY_WAIT_TIME 16

-#if (SMC_DEBUG > 2 ) -#define PRINTK3(args...) printf(args) -#else -#define PRINTK3(args...) -#endif

-#if SMC_DEBUG > 1 -#define PRINTK2(args...) printf(args) -#else -#define PRINTK2(args...) -#endif

-#ifdef SMC_DEBUG -#define PRINTK(args...) printf(args) -#else -#define PRINTK(args...) -#endif

-/*------------------------------------------------------------------------

.

. The internal workings of the driver. If you are changing anything

. here with the SMC stuff, you should have the datasheet and know

. what you are doing.

.

-------------------------------------------------------------------------*/

-/* Memory sizing constant */ -#define LAN91C111_MEMORY_MULTIPLIER (1024*2)

-#ifndef CONFIG_SMC91111_BASE -#error "SMC91111 Base address must be passed to initialization funciton" -/* #define CONFIG_SMC91111_BASE 0x20000300 */ -#endif

-#define SMC_DEV_NAME "SMC91111" -#define SMC_PHY_ADDR 0x0000 -#define SMC_ALLOC_MAX_TRY 5 -#define SMC_TX_TIMEOUT 30

-#define SMC_PHY_CLOCK_DELAY 1000

-#define ETH_ZLEN 60

-#ifdef CONFIG_SMC_USE_32_BIT -#define USE_32_BIT 1 -#else -#undef USE_32_BIT -#endif

-#ifdef SHARED_RESOURCES -extern void swap_to(int device_id); -#else -# define swap_to(x) -#endif

-#ifndef CONFIG_SMC91111_EXT_PHY -static void smc_phy_configure(struct eth_device *dev); -#endif /* !CONFIG_SMC91111_EXT_PHY */

-/*

.

. Internal routines

.

-*/

-#ifdef CONFIG_SMC_USE_IOFUNCS -/*

input and output functions

Implemented due to inx,outx macros accessing the device improperly

and putting the device into an unkown state.

For instance, on Sharp LPD7A400 SDK, affects were chip memory

could not be free'd (hence the alloc failures), duplicate packets,

packets being corrupt (shifted) on the wire, etc. Switching to the

inx,outx functions fixed this problem.

*/

-static inline word SMC_inw(struct eth_device *dev, dword offset) -{
  word v;
  v = *((volatile word*)(dev->iobase + offset));
  barrier(); *(volatile u32*)(0xc0000000);
  return v;
-}

-static inline void SMC_outw(struct eth_device *dev, word value, dword offset) -{
  *((volatile word*)(dev->iobase + offset)) = value;
  barrier(); *(volatile u32*)(0xc0000000);
-}

-static inline byte SMC_inb(struct eth_device *dev, dword offset) -{
  word  _w;
  _w = SMC_inw(dev, offset & ~((dword)1));
  return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
-}

-static inline void SMC_outb(struct eth_device *dev, byte value, dword offset) -{
  word  _w;
  _w = SMC_inw(dev, offset & ~((dword)1));
  if (offset & 1)
          *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
                  (value<<8) | (_w & 0x00ff);
  else
          *((volatile word*)(dev->iobase + offset)) =
                  value | (_w & 0xff00);
-}

-static inline void SMC_insw(struct eth_device *dev, dword offset,
  volatile uchar* buf, dword len)
-{
  volatile word *p = (volatile word *)buf;
  while (len-- > 0) {
          *p++ = SMC_inw(dev, offset);
          barrier();
          *((volatile u32*)(0xc0000000));
  }
-}

-static inline void SMC_outsw(struct eth_device *dev, dword offset,
  uchar* buf, dword len)
-{
  volatile word *p = (volatile word *)buf;
  while (len-- > 0) {
          SMC_outw(dev, *p++, offset);
          barrier();
          *(volatile u32*)(0xc0000000);
  }
-} -#endif /* CONFIG_SMC_USE_IOFUNCS */

-/*

. A rather simple routine to print out a packet for debugging purposes.

-*/ -#if SMC_DEBUG > 2 -static void print_packet( byte *, int ); -#endif

-#define tx_done(dev) 1

-static int poll4int (struct eth_device *dev, byte mask, int timeout) -{
  int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
  int is_timeout = 0;
  word old_bank = SMC_inw (dev, BSR_REG);
  PRINTK2 ("Polling...\n");
  SMC_SELECT_BANK (dev, 2);
  while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
          if (get_timer (0) >= tmo) {
                  is_timeout = 1;
                  break;
          }
  }
  /* restore old bank selection */
  SMC_SELECT_BANK (dev, old_bank);
  if (is_timeout)
          return 1;
  else
          return 0;
-}

-/* Only one release command at a time, please */ -static inline void smc_wait_mmu_release_complete (struct eth_device *dev) -{
  int count = 0;
  /* assume bank 2 selected */
  while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
          udelay(1);      /* Wait until not busy */
          if (++count > 200)
                  break;
  }
-}

-/*

. Function: smc_reset( void )

. Purpose:

. This sets the SMC91111 chip to its normal state, hopefully from whatever

. mess that any other DOS driver has put it in.

.

. Maybe I should reset more registers to defaults in here? SOFTRST should

. do that for me.

.

. Method:

. 1. send a SOFT RESET

. 2. wait for it to finish

. 3. enable autorelease mode

. 4. reset the memory management unit

. 5. clear all interrupts

.

-*/ -static void smc_reset (struct eth_device *dev) -{
  PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
  /* This resets the registers mostly to defaults, but doesn't
     affect EEPROM.  That seems unnecessary */
  SMC_SELECT_BANK (dev, 0);
  SMC_outw (dev, RCR_SOFTRST, RCR_REG);
  /* Setup the Configuration Register */
  /* This is necessary because the CONFIG_REG is not affected */
  /* by a soft reset */
  SMC_SELECT_BANK (dev, 1);
-#if defined(CONFIG_SMC91111_EXT_PHY)
  SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
-#else
  SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
-#endif
  /* Release from possible power-down state */
  /* Configuration register is not affected by Soft Reset */
  SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
          CONFIG_REG);
  SMC_SELECT_BANK (dev, 0);
  /* this should pause enough for the chip to be happy */
  udelay(10);
  /* Disable transmit and receive functionality */
  SMC_outw (dev, RCR_CLEAR, RCR_REG);
  SMC_outw (dev, TCR_CLEAR, TCR_REG);
  /* set the control register */
  SMC_SELECT_BANK (dev, 1);
  SMC_outw (dev, CTL_DEFAULT, CTL_REG);
  /* Reset the MMU */
  SMC_SELECT_BANK (dev, 2);
  smc_wait_mmu_release_complete (dev);
  SMC_outw (dev, MC_RESET, MMU_CMD_REG);
  while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
          udelay(1);      /* Wait until not busy */
  /* Note:  It doesn't seem that waiting for the MMU busy is needed here,
     but this is a place where future chipsets _COULD_ break.  Be wary
     of issuing another MMU command right after this */
  /* Disable all interrupts */
  SMC_outb (dev, 0, IM_REG);
-}

-/*

. Function: smc_enable

. Purpose: let the chip talk to the outside work

. Method:

. 1. Enable the transmitter

. 2. Enable the receiver

. 3. Enable interrupts

-*/ -static void smc_enable(struct eth_device *dev) -{
  PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
  SMC_SELECT_BANK( dev, 0 );
  /* see the header file for options in TCR/RCR DEFAULT*/
  SMC_outw( dev, TCR_DEFAULT, TCR_REG );
  SMC_outw( dev, RCR_DEFAULT, RCR_REG );
  /* clear MII_DIS */
-/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ -}

-/*

. Function: smc_halt

. Purpose: closes down the SMC91xxx chip.

. Method:

. 1. zero the interrupt mask

. 2. clear the enable receive flag

. 3. clear the enable xmit flags

.

. TODO:

. (1) maybe utilize power down mode.

. Why not yet? Because while the chip will go into power down mode,

. the manual says that it will wake up in response to any I/O requests

. in the register space. Empirical results do not show this working.

-*/ -static void smc_halt(struct eth_device *dev) -{
  PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
  /* no more interrupts for me */
  SMC_SELECT_BANK( dev, 2 );
  SMC_outb( dev, 0, IM_REG );
  /* and tell the card to stay away from that nasty outside world */
  SMC_SELECT_BANK( dev, 0 );
  SMC_outb( dev, RCR_CLEAR, RCR_REG );
  SMC_outb( dev, TCR_CLEAR, TCR_REG );
  swap_to(FLASH);
-}

-/*

. Function: smc_send(struct net_device * )

. Purpose:

. This sends the actual packet to the SMC9xxx chip.

.

. Algorithm:

. First, see if a saved_skb is available.

. ( this should NOT be called if there is no 'saved_skb'

. Now, find the packet number that the chip allocated

. Point the data pointers at it in memory

. Set the length word in the chip's memory

. Dump the packet to chip memory

. Check if a last byte is needed ( odd length packet )

. if so, set the control flag right

. Tell the card to send it

. Enable the transmit interrupt, so I know if it failed

. Free the kernel data if I actually sent it.

-*/ -static int smc_send(struct eth_device *dev, void *packet, int packet_length) -{
  byte packet_no;
  byte *buf;
  int length;
  int numPages;
  int try = 0;
  int time_out;
  byte status;
  byte saved_pnr;
  word saved_ptr;
  /* save PTR and PNR registers before manipulation */
  SMC_SELECT_BANK (dev, 2);
  saved_pnr = SMC_inb( dev, PN_REG );
  saved_ptr = SMC_inw( dev, PTR_REG );
  PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
  length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
  /* allocate memory
   ** The MMU wants the number of pages to be the number of 256 bytes
   ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
   **
   ** The 91C111 ignores the size bits, but the code is left intact
   ** for backwards and future compatibility.
   **
   ** Pkt size for allocating is data length +6 (for additional status
   ** words, length and ctl!)
   **
   ** If odd size then last byte is included in this header.
   */
  numPages = ((length & 0xfffe) + 6);
  numPages >>= 8;         /* Divide by 256 */
  if (numPages > 7) {
          printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
          return 0;
  }
  /* now, try to allocate the memory */
  SMC_SELECT_BANK (dev, 2);
  SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
  /* FIXME: the ALLOC_INT bit never gets set *
   * so the following will always give a     *
   * memory allocation error.                *
   * same code works in armboot though       *
   * -ro
   */
-again:
  try++;
  time_out = MEMORY_WAIT_TIME;
  do {
          status = SMC_inb (dev, SMC91111_INT_REG);
          if (status & IM_ALLOC_INT) {
                  /* acknowledge the interrupt */
                  SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
                  break;
          }
  } while (--time_out);
  if (!time_out) {
          PRINTK2 ("%s: memory allocation, try %d failed ...\n",
                   SMC_DEV_NAME, try);
          if (try < SMC_ALLOC_MAX_TRY)
                  goto again;
          else
                  return 0;
  }
  PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
           SMC_DEV_NAME, try);
  buf = (byte *) packet;
  /* If I get here, I _know_ there is a packet slot waiting for me */
  packet_no = SMC_inb (dev, AR_REG);
  if (packet_no & AR_FAILED) {
          /* or isn't there?  BAD CHIP! */
          printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
          return 0;
  }
  /* we have a packet address, so tell the card to use it */
  SMC_outb (dev, packet_no, PN_REG);
  /* do not write new ptr value if Write data fifo not empty */
  while ( saved_ptr & PTR_NOTEMPTY )
          printf ("Write data fifo not empty!\n");
  /* point to the beginning of the packet */
  SMC_outw (dev, PTR_AUTOINC, PTR_REG);
  PRINTK3 ("%s: Trying to xmit packet of length %x\n",
           SMC_DEV_NAME, length);
-#if SMC_DEBUG > 2
  printf ("Transmitting Packet\n");
  print_packet (buf, length);
-#endif
  /* send the packet length ( +6 for status, length and ctl byte )
     and the status word ( set to zeros ) */
-#ifdef USE_32_BIT
  SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
-#else
  SMC_outw (dev, 0, SMC91111_DATA_REG);
  /* send the packet length ( +6 for status words, length, and ctl */
  SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
-#endif
  /* send the actual data
     . I _think_ it's faster to send the longs first, and then
     . mop up by sending the last word.  It depends heavily
     . on alignment, at least on the 486.  Maybe it would be
     . a good idea to check which is optimal?  But that could take
     . almost as much time as is saved?
   */
-#ifdef USE_32_BIT
  SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
  if (length & 0x2)
          SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
                    SMC91111_DATA_REG);
-#else
  SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
-#endif /* USE_32_BIT */
  /* Send the last byte, if there is one.   */
  if ((length & 1) == 0) {
          SMC_outw (dev, 0, SMC91111_DATA_REG);
  } else {
          SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
  }
  /* and let the chipset deal with it */
  SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
  /* poll for TX INT */
  /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
  /* poll for TX_EMPTY INT - autorelease enabled */
  if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
          /* sending failed */
          PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
          /* release packet */
          /* no need to release, MMU does that now */
          /* wait for MMU getting ready (low) */
          while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
                  udelay(10);
          }
          PRINTK2 ("MMU ready\n");
          return 0;
  } else {
          /* ack. int */
          SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
          /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
          PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
                   length);
          /* release packet */
          /* no need to release, MMU does that now */
          /* wait for MMU getting ready (low) */
          while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
                  udelay(10);
          }
          PRINTK2 ("MMU ready\n");
  }
  /* restore previously saved registers */
  SMC_outb( dev, saved_pnr, PN_REG );
  SMC_outw( dev, saved_ptr, PTR_REG );
  return length;
-}

-static int smc_write_hwaddr(struct eth_device *dev) -{
  int i;
  swap_to(ETHERNET);
  SMC_SELECT_BANK (dev, 1);
-#ifdef USE_32_BIT
  for (i = 0; i < 6; i += 2) {
          word address;
          address = dev->enetaddr[i + 1] << 8;
          address |= dev->enetaddr[i];
          SMC_outw(dev, address, (ADDR0_REG + i));
  }
-#else
  for (i = 0; i < 6; i++)
          SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
-#endif
  swap_to(FLASH);
  return 0;
-}

-/*

Open and Initialize the board

Set up everything, reset the card, etc ..

*/

-static int smc_init(struct eth_device *dev, struct bd_info *bd) -{
  swap_to(ETHERNET);
  PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
  /* reset the hardware */
  smc_reset (dev);
  smc_enable (dev);
  /* Configure the PHY */
-#ifndef CONFIG_SMC91111_EXT_PHY
  smc_phy_configure (dev);
-#endif
  /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
-/* SMC_SELECT_BANK(dev, 0); */ -/* SMC_outw(dev, 0, RPC_REG); */
  printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
  return 0;
-}

-/*-------------------------------------------------------------

.

. smc_rcv - receive a packet from the card

.

. There is ( at least ) a packet waiting to be read from

. chip-memory.

.

. o Read the status

. o If an error, record it

. o otherwise, read in the packet

-*/ -static int smc_rcv(struct eth_device *dev) -{
  int     packet_number;
  word    status;
  word    packet_length;
  int     is_error = 0;
-#ifdef USE_32_BIT
  dword stat_len;
-#endif
  byte saved_pnr;
  word saved_ptr;
  SMC_SELECT_BANK(dev, 2);
  /* save PTR and PTR registers */
  saved_pnr = SMC_inb( dev, PN_REG );
  saved_ptr = SMC_inw( dev, PTR_REG );
  packet_number = SMC_inw( dev, RXFIFO_REG );
  if ( packet_number & RXFIFO_REMPTY ) {
          return 0;
  }
  PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
  /*  start reading from the start of the packet */
  SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
  /* First two words are status and packet_length */
-#ifdef USE_32_BIT
  stat_len = SMC_inl(dev, SMC91111_DATA_REG);
  status = stat_len & 0xffff;
  packet_length = stat_len >> 16;
-#else
  status          = SMC_inw( dev, SMC91111_DATA_REG );
  packet_length   = SMC_inw( dev, SMC91111_DATA_REG );
-#endif
  packet_length &= 0x07ff;  /* mask off top bits */
  PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
  if ( !(status & RS_ERRORS ) ){
          /* Adjust for having already read the first two words */
          packet_length -= 4; /*4; */
          /* set odd length for bug in LAN91C111, */
          /* which never sets RS_ODDFRAME */
          /* TODO ? */
-#ifdef USE_32_BIT
          PRINTK3(" Reading %d dwords (and %d bytes)\n",
                  packet_length >> 2, packet_length & 3 );
          /* QUESTION:  Like in the TX routine, do I want
             to send the DWORDs or the bytes first, or some
             mixture.  A mixture might improve already slow PIO
             performance  */
          SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0],
                   packet_length >> 2);
          /* read the left over bytes */
          if (packet_length & 3) {
                  int i;
                  byte *tail = (byte *)(net_rx_packets[0] +
                          (packet_length & ~3));
                  dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
                  for (i=0; i<(packet_length & 3); i++)
                          *tail++ = (byte) (leftover >> (8*i)) & 0xff;
          }
-#else
          PRINTK3(" Reading %d words and %d byte(s)\n",
                  (packet_length >> 1 ), packet_length & 1 );
          SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0],
                   packet_length >> 1);
-#endif /* USE_32_BIT */

-#if SMC_DEBUG > 2
          printf("Receiving Packet\n");
          print_packet(net_rx_packets[0], packet_length);
-#endif
  } else {
          /* error ... */
          /* TODO ? */
          is_error = 1;
  }
  while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
          udelay(1); /* Wait until not busy */
  /*  error or good, tell the card to get rid of this packet */
  SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
  while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
          udelay(1); /* Wait until not busy */
  /* restore saved registers */
  SMC_outb( dev, saved_pnr, PN_REG );
  SMC_outw( dev, saved_ptr, PTR_REG );
  if (!is_error) {
          /* Pass the packet up to the protocol layers. */
          net_process_received_packet(net_rx_packets[0], packet_length);
          return packet_length;
  } else {
          return 0;
  }
-}

-#if 0 -/*------------------------------------------------------------

. Modify a bit in the LAN91C111 register set

.-------------------------------------------------------------*/

-static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
  unsigned int bit, int val)
-{
  word regval;
  SMC_SELECT_BANK( dev, bank );
  regval = SMC_inw( dev, reg );
  if (val)
          regval |= bit;
  else
          regval &= ~bit;
  SMC_outw( dev, regval, 0 );
  return(regval);
-}

-/*------------------------------------------------------------

. Retrieve a bit in the LAN91C111 register set

.-------------------------------------------------------------*/

-static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit) -{
  SMC_SELECT_BANK( dev, bank );
  if ( SMC_inw( dev, reg ) & bit)
          return(1);
  else
          return(0);
-}

-/*------------------------------------------------------------

. Modify a LAN91C111 register (word access only)

.-------------------------------------------------------------*/

-static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val) -{
  SMC_SELECT_BANK( dev, bank );
  SMC_outw( dev, val, reg );
-}

-/*------------------------------------------------------------

. Retrieve a LAN91C111 register (word access only)

.-------------------------------------------------------------*/

-static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg) -{
  SMC_SELECT_BANK( dev, bank );
  return(SMC_inw( dev, reg ));
-}

-#endif /* 0 */

-/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */

-#if (SMC_DEBUG > 2 )

-/*------------------------------------------------------------

. Debugging function for viewing MII Management serial bitstream

.-------------------------------------------------------------*/

-static void smc_dump_mii_stream (byte * bits, int size) -{
  int i;
  printf ("BIT#:");
  for (i = 0; i < size; ++i) {
          printf ("%d", i % 10);
  }
  printf ("\nMDOE:");
  for (i = 0; i < size; ++i) {
          if (bits[i] & MII_MDOE)
                  printf ("1");
          else
                  printf ("0");
  }
  printf ("\nMDO :");
  for (i = 0; i < size; ++i) {
          if (bits[i] & MII_MDO)
                  printf ("1");
          else
                  printf ("0");
  }
  printf ("\nMDI :");
  for (i = 0; i < size; ++i) {
          if (bits[i] & MII_MDI)
                  printf ("1");
          else
                  printf ("0");
  }
  printf ("\n");
-} -#endif

-/*------------------------------------------------------------

. Reads a register from the MII Management serial interface

.-------------------------------------------------------------*/

-#ifndef CONFIG_SMC91111_EXT_PHY -static word smc_read_phy_register (struct eth_device *dev, byte phyreg) -{
  int oldBank;
  int i;
  byte mask;
  word mii_reg;
  byte bits[64];
  int clk_idx = 0;
  int input_idx;
  word phydata;
  byte phyaddr = SMC_PHY_ADDR;
  /* 32 consecutive ones on MDO to establish sync */
  for (i = 0; i < 32; ++i)
          bits[clk_idx++] = MII_MDOE | MII_MDO;
  /* Start code <01> */
  bits[clk_idx++] = MII_MDOE;
  bits[clk_idx++] = MII_MDOE | MII_MDO;
  /* Read command <10> */
  bits[clk_idx++] = MII_MDOE | MII_MDO;
  bits[clk_idx++] = MII_MDOE;
  /* Output the PHY address, msb first */
  mask = (byte) 0x10;
  for (i = 0; i < 5; ++i) {
          if (phyaddr & mask)
                  bits[clk_idx++] = MII_MDOE | MII_MDO;
          else
                  bits[clk_idx++] = MII_MDOE;
          /* Shift to next lowest bit */
          mask >>= 1;
  }
  /* Output the phy register number, msb first */
  mask = (byte) 0x10;
  for (i = 0; i < 5; ++i) {
          if (phyreg & mask)
                  bits[clk_idx++] = MII_MDOE | MII_MDO;
          else
                  bits[clk_idx++] = MII_MDOE;
          /* Shift to next lowest bit */
          mask >>= 1;
  }
  /* Tristate and turnaround (2 bit times) */
  bits[clk_idx++] = 0;
  /*bits[clk_idx++] = 0; */
  /* Input starts at this bit time */
  input_idx = clk_idx;
  /* Will input 16 bits */
  for (i = 0; i < 16; ++i)
          bits[clk_idx++] = 0;
  /* Final clock bit */
  bits[clk_idx++] = 0;
  /* Save the current bank */
  oldBank = SMC_inw (dev, BANK_SELECT);
  /* Select bank 3 */
  SMC_SELECT_BANK (dev, 3);
  /* Get the current MII register value */
  mii_reg = SMC_inw (dev, MII_REG);
  /* Turn off all MII Interface bits */
  mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
  /* Clock all 64 cycles */
  for (i = 0; i < sizeof bits; ++i) {
          /* Clock Low - output data */
          SMC_outw (dev, mii_reg | bits[i], MII_REG);
          udelay(SMC_PHY_CLOCK_DELAY);
          /* Clock Hi - input data */
          SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
          udelay(SMC_PHY_CLOCK_DELAY);
          bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
  }
  /* Return to idle state */
  /* Set clock to low, data to low, and output tristated */
  SMC_outw (dev, mii_reg, MII_REG);
  udelay(SMC_PHY_CLOCK_DELAY);
  /* Restore original bank select */
  SMC_SELECT_BANK (dev, oldBank);
  /* Recover input data */
  phydata = 0;
  for (i = 0; i < 16; ++i) {
          phydata <<= 1;
          if (bits[input_idx++] & MII_MDI)
                  phydata |= 0x0001;
  }
-#if (SMC_DEBUG > 2 )
  printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
          phyaddr, phyreg, phydata);
  smc_dump_mii_stream (bits, sizeof bits);
-#endif
  return (phydata);
-}

-/*------------------------------------------------------------

. Writes a register to the MII Management serial interface

.-------------------------------------------------------------*/

-static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
  word phydata)
-{
  int oldBank;
  int i;
  word mask;
  word mii_reg;
  byte bits[65];
  int clk_idx = 0;
  byte phyaddr = SMC_PHY_ADDR;
  /* 32 consecutive ones on MDO to establish sync */
  for (i = 0; i < 32; ++i)
          bits[clk_idx++] = MII_MDOE | MII_MDO;
  /* Start code <01> */
  bits[clk_idx++] = MII_MDOE;
  bits[clk_idx++] = MII_MDOE | MII_MDO;
  /* Write command <01> */
  bits[clk_idx++] = MII_MDOE;
  bits[clk_idx++] = MII_MDOE | MII_MDO;
  /* Output the PHY address, msb first */
  mask = (byte) 0x10;
  for (i = 0; i < 5; ++i) {
          if (phyaddr & mask)
                  bits[clk_idx++] = MII_MDOE | MII_MDO;
          else
                  bits[clk_idx++] = MII_MDOE;
          /* Shift to next lowest bit */
          mask >>= 1;
  }
  /* Output the phy register number, msb first */
  mask = (byte) 0x10;
  for (i = 0; i < 5; ++i) {
          if (phyreg & mask)
                  bits[clk_idx++] = MII_MDOE | MII_MDO;
          else
                  bits[clk_idx++] = MII_MDOE;
          /* Shift to next lowest bit */
          mask >>= 1;
  }
  /* Tristate and turnaround (2 bit times) */
  bits[clk_idx++] = 0;
  bits[clk_idx++] = 0;
  /* Write out 16 bits of data, msb first */
  mask = 0x8000;
  for (i = 0; i < 16; ++i) {
          if (phydata & mask)
                  bits[clk_idx++] = MII_MDOE | MII_MDO;
          else
                  bits[clk_idx++] = MII_MDOE;
          /* Shift to next lowest bit */
          mask >>= 1;
  }
  /* Final clock bit (tristate) */
  bits[clk_idx++] = 0;
  /* Save the current bank */
  oldBank = SMC_inw (dev, BANK_SELECT);
  /* Select bank 3 */
  SMC_SELECT_BANK (dev, 3);
  /* Get the current MII register value */
  mii_reg = SMC_inw (dev, MII_REG);
  /* Turn off all MII Interface bits */
  mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
  /* Clock all cycles */
  for (i = 0; i < sizeof bits; ++i) {
          /* Clock Low - output data */
          SMC_outw (dev, mii_reg | bits[i], MII_REG);
          udelay(SMC_PHY_CLOCK_DELAY);
          /* Clock Hi - input data */
          SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
          udelay(SMC_PHY_CLOCK_DELAY);
          bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
  }
  /* Return to idle state */
  /* Set clock to low, data to low, and output tristated */
  SMC_outw (dev, mii_reg, MII_REG);
  udelay(SMC_PHY_CLOCK_DELAY);
  /* Restore original bank select */
  SMC_SELECT_BANK (dev, oldBank);
-#if (SMC_DEBUG > 2 )
  printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
          phyaddr, phyreg, phydata);
  smc_dump_mii_stream (bits, sizeof bits);
-#endif -} -#endif /* !CONFIG_SMC91111_EXT_PHY */

-/*------------------------------------------------------------

. Configures the specified PHY using Autonegotiation. Calls

. smc_phy_fixed() if the user has requested a certain config.

.-------------------------------------------------------------*/

-#ifndef CONFIG_SMC91111_EXT_PHY -static void smc_phy_configure (struct eth_device *dev) -{
  int timeout;
  word my_phy_caps;       /* My PHY capabilities */
  word my_ad_caps;        /* My Advertised capabilities */
  word status = 0;        /*;my status = 0 */
  PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
  /* Reset the PHY, setting all other bits to zero */
  smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
  /* Wait for the reset to complete, or time out */
  timeout = 6;            /* Wait up to 3 seconds */
  while (timeout--) {
          if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
                & PHY_CNTL_RST)) {
                  /* reset complete */
                  break;
          }
          mdelay(500);    /* wait 500 millisecs */
  }
  if (timeout < 1) {
          printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
          goto smc_phy_configure_exit;
  }
  /* Read PHY Register 18, Status Output */
  /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
  /* Enable PHY Interrupts (for register 18) */
  /* Interrupts listed here are disabled */
  smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
  /* Configure the Receive/Phy Control register */
  SMC_SELECT_BANK (dev, 0);
  SMC_outw (dev, RPC_DEFAULT, RPC_REG);
  /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
  my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
  my_ad_caps = PHY_AD_CSMA;       /* I am CSMA capable */
  if (my_phy_caps & PHY_STAT_CAP_T4)
          my_ad_caps |= PHY_AD_T4;
  if (my_phy_caps & PHY_STAT_CAP_TXF)
          my_ad_caps |= PHY_AD_TX_FDX;
  if (my_phy_caps & PHY_STAT_CAP_TXH)
          my_ad_caps |= PHY_AD_TX_HDX;
  if (my_phy_caps & PHY_STAT_CAP_TF)
          my_ad_caps |= PHY_AD_10_FDX;
  if (my_phy_caps & PHY_STAT_CAP_TH)
          my_ad_caps |= PHY_AD_10_HDX;
  /* Update our Auto-Neg Advertisement Register */
  smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
  /* Read the register back.  Without this, it appears that when */
  /* auto-negotiation is restarted, sometimes it isn't ready and */
  /* the link does not come up. */
  smc_read_phy_register(dev, PHY_AD_REG);
  PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
  PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
  /* Restart auto-negotiation process in order to advertise my caps */
  smc_write_phy_register (dev, PHY_CNTL_REG,
                          PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
  /* Wait for the auto-negotiation to complete.  This may take from */
  /* 2 to 3 seconds. */
  /* Wait for the reset to complete, or time out */
  timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
  while (timeout--) {
          status = smc_read_phy_register (dev, PHY_STAT_REG);
          if (status & PHY_STAT_ANEG_ACK) {
                  /* auto-negotiate complete */
                  break;
          }
          mdelay(500);    /* wait 500 millisecs */
          /* Restart auto-negotiation if remote fault */
          if (status & PHY_STAT_REM_FLT) {
                  printf ("%s: PHY remote fault detected\n",
                          SMC_DEV_NAME);
                  /* Restart auto-negotiation */
                  printf ("%s: PHY restarting auto-negotiation\n",
                          SMC_DEV_NAME);
                  smc_write_phy_register (dev, PHY_CNTL_REG,
                                          PHY_CNTL_ANEG_EN |
                                          PHY_CNTL_ANEG_RST |
                                          PHY_CNTL_SPEED |
                                          PHY_CNTL_DPLX);
          }
  }
  if (timeout < 1) {
          printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
  }
  /* Fail if we detected an auto-negotiate remote fault */
  if (status & PHY_STAT_REM_FLT) {
          printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
  }
  /* Re-Configure the Receive/Phy Control register */
  SMC_outw (dev, RPC_DEFAULT, RPC_REG);
-smc_phy_configure_exit: ;

-} -#endif /* !CONFIG_SMC91111_EXT_PHY */

-#if SMC_DEBUG > 2 -static void print_packet( byte * buf, int length ) -{
  int i;
  int remainder;
  int lines;
  printf("Packet of length %d \n", length );
-#if SMC_DEBUG > 3
  lines = length / 16;
  remainder = length % 16;
  for ( i = 0; i < lines ; i ++ ) {
          int cur;
          for ( cur = 0; cur < 8; cur ++ ) {
                  byte a, b;
                  a = *(buf ++ );
                  b = *(buf ++ );
                  printf("%02x%02x ", a, b );
          }
          printf("\n");
  }
  for ( i = 0; i < remainder/2 ; i++ ) {
          byte a, b;
          a = *(buf ++ );
          b = *(buf ++ );
          printf("%02x%02x ", a, b );
  }
  printf("\n");
-#endif -} -#endif

-int smc91111_initialize(u8 dev_num, phys_addr_t base_addr) -{
  struct smc91111_priv *priv;
  struct eth_device *dev;
  int i;
  priv = malloc(sizeof(*priv));
  if (!priv)
          return 0;
  dev = malloc(sizeof(*dev));
  if (!dev) {
          free(priv);
          return 0;
  }
  memset(dev, 0, sizeof(*dev));
  priv->dev_num = dev_num;
  dev->priv = priv;
  dev->iobase = base_addr;
  swap_to(ETHERNET);
  SMC_SELECT_BANK(dev, 1);
  for (i = 0; i < 6; ++i)
          dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
  swap_to(FLASH);
  dev->init = smc_init;
  dev->halt = smc_halt;
  dev->send = smc_send;
  dev->recv = smc_rcv;
  dev->write_hwaddr = smc_write_hwaddr;
  sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
  eth_register(dev);
  return 0;
-} diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h deleted file mode 100644 index f2ba34474598..000000000000 --- a/drivers/net/smc91111.h +++ /dev/null @@ -1,632 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*------------------------------------------------------------------------

. smc91111.h - macros for the LAN91C111 Ethernet Driver

.

. (C) Copyright 2002

. Sysgo Real-Time Solutions, GmbH <www.elinos.com>

. Rolf Offermanns rof@sysgo.de

. Copyright (C) 2001 Standard Microsystems Corporation (SMSC)

. Developed by Simple Network Magic Corporation (SNMC)

. Copyright (C) 1996 by Erik Stahlman (ES)

.

. This file contains register information and access macros for

. the LAN91C111 single chip ethernet controller. It is a modified

. version of the smc9194.h file.

.

. Information contained in this file was obtained from the LAN91C111

. manual from SMC. To get a copy, if you really want one, you can find

. information under www.smsc.com.

.

. Authors

. Erik Stahlman ( erik@vt.edu )

. Daris A Nevil ( dnevil@snmc.com )

.

. History

. 03/16/01 Daris A Nevil Modified for use with LAN91C111 device

.

---------------------------------------------------------------------------*/

-#ifndef _SMC91111_H_ -#define _SMC91111_H_

-#include <asm/types.h> -#include <config.h> -#include <net.h>

-/*

This function may be called by the board specific initialisation code

in order to override the default mac address.

*/

-void smc_set_mac_addr (const unsigned char *addr);

-/* I want some simple types */

-typedef unsigned char byte; -typedef unsigned short word; -typedef unsigned long int dword;

-struct smc91111_priv{
  u8 dev_num;
-};

-/*

. DEBUGGING LEVELS

.

. 0 for normal operation

. 1 for slightly more details

. >2 for various levels of increasingly useless information

. 2 for interrupt tracking, status flags

. 3 for packet info

. 4 for complete packet dumps

-*/ -/*#define SMC_DEBUG 0 */

-/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */

-#define SMC_IO_EXTENT 16

-#if defined(CONFIG_MS7206SE) -#define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); }) -#define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r))) -#define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01)))) -#define SMC_insw(a, r, b, l) \
  do { \
          int __i; \
          word *__b2 = (word *)(b);                 \
          for (__i = 0; __i < (l); __i++) { \
                  *__b2++ = SWAB7206(SMC_inw(a, r));      \
          } \
  } while (0)
-#define SMC_outw(a, d, r) (*((volatile word *)((a)->iobase+(r))) = d) -#define SMC_outb(a, d, r) ({ word __d = (byte)(d); \
                          word __w = SMC_inw((a), ((r)&(~1)));    \
                          if (((r) & 1)) \
                                  __w = (__w & 0x00ff) | (__d << 8); \
                          else \
                                  __w = (__w & 0xff00) | (__d); \
                          SMC_outw((a), __w, ((r)&(~1)));       \
                  })
-#define SMC_outsw(a, r, b, l) \
  do { \
          int __i; \
          word *__b2 = (word *)(b);                 \
          for (__i = 0; __i < (l); __i++) { \
                  SMC_outw(a, SWAB7206(*__b2), r);          \
                  __b2++; \
          } \
  } while (0)
-#else

-#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ -/*

We have only 16 Bit PCMCIA access on Socket 0

*/

-#if CONFIG_ARM64 -#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) -#else -#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) -#endif -#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))

-#if CONFIG_ARM64 -#define SMC_outw(a, d, r) \
                  (*((volatile word*)((a)->iobase+((dword)(r)))) = d)
-#else -#define SMC_outw(a, d, r) \
                  (*((volatile word*)((a)->iobase+(r))) = d)
-#endif -#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \
                          word __w = SMC_inw((a),(r)&~1);  \
                          __w &= ((r)&1) ? 0x00FF : 0xFF00;  \
                          __w |= ((r)&1) ? __d<<8 : __d;  \
                          SMC_outw((a),__w,(r)&~1);  \
                  })
-#if 0 -#define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l)) -#else -#define SMC_outsw(a,r,b,l) ({ int __i; \
                                  word *__b2; \
                                  __b2 = (word *) b; \
                                  for (__i = 0; __i < l; __i++) { \
                                      SMC_outw((a), *(__b2 + __i), r); \
                                  } \
                          })
-#endif

-#if 0 -#define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l)) -#else -#define SMC_insw(a,r,b,l) ({ int __i ; \
                                  word *__b2;  \
                                  __b2 = (word *) b;  \
                                  for (__i = 0; __i < l; __i++) {  \
                                    *(__b2 + __i) = SMC_inw((a),(r));  \
                                    SMC_inw((a),0);  \
                                  };  \
                          })
-#endif

-#endif /* CONFIG_SMC_USE_IOFUNCS */

-#if defined(CONFIG_SMC_USE_32_BIT)

-#ifdef CONFIG_XSENGINE -#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) -#else -#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) -#endif

-#define SMC_insl(a,r,b,l) ({ int __i ; \
                                  dword *__b2;  \
                                  __b2 = (dword *) b;  \
                                  for (__i = 0; __i < l; __i++) {  \
                                    *(__b2 + __i) = SMC_inl((a),(r));  \
                                    SMC_inl((a),0);  \
                                  };  \
                          })
-#ifdef CONFIG_XSENGINE -#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) -#else -#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) -#endif -#define SMC_outsl(a,r,b,l) ({ int __i; \
                                  dword *__b2; \
                                  __b2 = (dword *) b; \
                                  for (__i = 0; __i < l; __i++) { \
                                      SMC_outl((a), *(__b2 + __i), r); \
                                  } \
                          })
-#endif /* CONFIG_SMC_USE_32_BIT */

-#endif

-/*---------------------------------------------------------------

.

. A description of the SMSC registers is probably in order here,

. although for details, the SMC datasheet is invaluable.

.

. Basically, the chip has 4 banks of registers ( 0 to 3 ), which

. are accessed by writing a number into the BANK_SELECT register

. ( I also use a SMC_SELECT_BANK macro for this ).

.

. The banks are configured so that for most purposes, bank 2 is all

. that is needed for simple run time tasks.

-----------------------------------------------------------------------*/

-/*

. Bank Select Register:

.

. yyyy yyyy 0000 00xx

. xx = bank number

. yyyy yyyy = 0x33, for identification purposes.

-*/ -#define BANK_SELECT 14

-/* Transmit Control Register */ -/* BANK 0 */ -#define TCR_REG 0x0000 /* transmit control register */ -#define TCR_ENABLE 0x0001 /* When 1 we can transmit */ -#define TCR_LOOP 0x0002 /* Controls output pin LBK */ -#define TCR_FORCOL 0x0004 /* When 1 will force a collision */ -#define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ -#define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ -#define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ -#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ -#define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ -#define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ -#define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */

-#define TCR_CLEAR 0 /* do NOTHING */ -/* the default settings for the TCR register : */ -/* QUESTION: do I want to enable padding of short packets ? */ -#define TCR_DEFAULT TCR_ENABLE

-/* EPH Status Register */ -/* BANK 0 */ -#define EPH_STATUS_REG 0x0002 -#define ES_TX_SUC 0x0001 /* Last TX was successful */ -#define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ -#define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ -#define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ -#define ES_16COL 0x0010 /* 16 Collisions Reached */ -#define ES_SQET 0x0020 /* Signal Quality Error Test */ -#define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ -#define ES_TXDEFR 0x0080 /* Transmit Deferred */ -#define ES_LATCOL 0x0200 /* Late collision detected on last tx */ -#define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ -#define ES_EXC_DEF 0x0800 /* Excessive Deferral */ -#define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ -#define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ -#define ES_TXUNRN 0x8000 /* Tx Underrun */

-/* Receive Control Register */ -/* BANK 0 */ -#define RCR_REG 0x0004 -#define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ -#define RCR_PRMS 0x0002 /* Enable promiscuous mode */ -#define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ -#define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ -#define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ -#define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ -#define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ -#define RCR_SOFTRST 0x8000 /* resets the chip */

-/* the normal settings for the RCR register : */ -#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) -#define RCR_CLEAR 0x0 /* set it to a base state */

-/* Counter Register */ -/* BANK 0 */ -#define COUNTER_REG 0x0006

-/* Memory Information Register */ -/* BANK 0 */ -#define MIR_REG 0x0008

-/* Receive/Phy Control Register */ -/* BANK 0 */ -#define RPC_REG 0x000A -#define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ -#define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ -#define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ -#define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ -#define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ -#define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ -#define RPC_LED_RES (0x01) /* LED = Reserved */ -#define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ -#define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ -#define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ -#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ -#define RPC_LED_TX (0x06) /* LED = TX packet occurred */ -#define RPC_LED_RX (0x07) /* LED = RX packet occurred */ -#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) -/* buggy schematic: LEDa -> yellow, LEDb --> green */ -#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
                  | (RPC_LED_TX_RX << RPC_LSXA_SHFT)      \
                  | (RPC_LED_100_10 << RPC_LSXB_SHFT)     )
-#else -/* SMSC reference design: LEDa --> green, LEDb --> yellow */ -#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
                  | (RPC_LED_100_10 << RPC_LSXA_SHFT)     \
                  | (RPC_LED_TX_RX << RPC_LSXB_SHFT)      )
-#endif

-/* Bank 0 0x000C is reserved */

-/* Bank Select Register */ -/* All Banks */ -#define BSR_REG 0x000E

-/* Configuration Reg */ -/* BANK 1 */ -#define CONFIG_REG 0x0000 -#define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ -#define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ -#define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ -#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */

-/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ -#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)

-/* Base Address Register */ -/* BANK 1 */ -#define BASE_REG 0x0002

-/* Individual Address Registers */ -/* BANK 1 */ -#define ADDR0_REG 0x0004 -#define ADDR1_REG 0x0006 -#define ADDR2_REG 0x0008

-/* General Purpose Register */ -/* BANK 1 */ -#define GP_REG 0x000A

-/* Control Register */ -/* BANK 1 */ -#define CTL_REG 0x000C -#define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ -#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ -#define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ -#define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ -#define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ -#define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ -#define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ -#define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ -#define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/

-/* MMU Command Register */ -/* BANK 2 */ -#define MMU_CMD_REG 0x0000 -#define MC_BUSY 1 /* When 1 the last release has not completed */ -#define MC_NOP (0<<5) /* No Op */ -#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ -#define MC_RESET (2<<5) /* Reset MMU to initial state */ -#define MC_REMOVE (3<<5) /* Remove the current rx packet */ -#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ -#define MC_FREEPKT (5<<5) /* Release packet in PNR register */ -#define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ -#define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */

-/* Packet Number Register */ -/* BANK 2 */ -#define PN_REG 0x0002

-/* Allocation Result Register */ -/* BANK 2 */ -#define AR_REG 0x0003 -#define AR_FAILED 0x80 /* Alocation Failed */

-/* RX FIFO Ports Register */ -/* BANK 2 */ -#define RXFIFO_REG 0x0004 /* Must be read as a word */ -#define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */

-/* TX FIFO Ports Register */ -/* BANK 2 */ -#define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ -#define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */

-/* Pointer Register */ -/* BANK 2 */ -#define PTR_REG 0x0006 -#define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ -#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ -#define PTR_READ 0x2000 /* When 1 the operation is a read */ -#define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */

-/* Data Register */ -/* BANK 2 */ -#define SMC91111_DATA_REG 0x0008

-/* Interrupt Status/Acknowledge Register */ -/* BANK 2 */ -#define SMC91111_INT_REG 0x000C

-/* Interrupt Mask Register */ -/* BANK 2 */ -#define IM_REG 0x000D -#define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ -#define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ -#define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ -#define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ -#define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ -#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ -#define IM_TX_INT 0x02 /* Transmit Interrrupt */ -#define IM_RCV_INT 0x01 /* Receive Interrupt */

-/* Multicast Table Registers */ -/* BANK 3 */ -#define MCAST_REG1 0x0000 -#define MCAST_REG2 0x0002 -#define MCAST_REG3 0x0004 -#define MCAST_REG4 0x0006

-/* Management Interface Register (MII) */ -/* BANK 3 */ -#define MII_REG 0x0008 -#define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ -#define MII_MDOE 0x0008 /* MII Output Enable */ -#define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ -#define MII_MDI 0x0002 /* MII Input, pin MDI */ -#define MII_MDO 0x0001 /* MII Output, pin MDO */

-/* Revision Register */ -/* BANK 3 */ -#define REV_REG 0x000A /* ( hi: chip id low: rev # ) */

-/* Early RCV Register */ -/* BANK 3 */ -/* this is NOT on SMC9192 */ -#define ERCV_REG 0x000C -#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ -#define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */

-/* External Register */ -/* BANK 7 */ -#define EXT_REG 0x0000

-#define CHIP_9192 3 -#define CHIP_9194 4 -#define CHIP_9195 5 -#define CHIP_9196 6 -#define CHIP_91100 7 -#define CHIP_91100FD 8 -#define CHIP_91111FD 9

-#if 0 -static const char * chip_ids[ 15 ] = {
  NULL, NULL, NULL,
  /* 3 */ "SMC91C90/91C92",
  /* 4 */ "SMC91C94",
  /* 5 */ "SMC91C95",
  /* 6 */ "SMC91C96",
  /* 7 */ "SMC91C100",
  /* 8 */ "SMC91C100FD",
  /* 9 */ "SMC91C111",
  NULL, NULL,
  NULL, NULL, NULL};
-#endif

-/*

. Transmit status bits

-*/ -#define TS_SUCCESS 0x0001 -#define TS_LOSTCAR 0x0400 -#define TS_LATCOL 0x0200 -#define TS_16COL 0x0010

-/*

. Receive status bits

-*/ -#define RS_ALGNERR 0x8000 -#define RS_BRODCAST 0x4000 -#define RS_BADCRC 0x2000 -#define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ -#define RS_TOOLONG 0x0800 -#define RS_TOOSHORT 0x0400 -#define RS_MULTICAST 0x0001 -#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)

-/* PHY Types */ -enum {
  PHY_LAN83C183 = 1,      /* LAN91C111 Internal PHY */
  PHY_LAN83C180
-};

-/* PHY Register Addresses (LAN91C111 Internal PHY) */

-/* PHY Control Register */ -#define PHY_CNTL_REG 0x00 -#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ -#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ -#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ -#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ -#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ -#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ -#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ -#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ -#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */

-/* PHY Status Register */ -#define PHY_STAT_REG 0x01 -#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ -#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ -#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ -#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ -#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ -#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ -#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ -#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ -#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ -#define PHY_STAT_LINK 0x0004 /* 1=valid link */ -#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ -#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */

-/* PHY Identifier Registers */ -#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ -#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */

-/* PHY Auto-Negotiation Advertisement Register */ -#define PHY_AD_REG 0x04 -#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ -#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ -#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ -#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ -#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ -#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ -#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ -#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ -#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */

-/* PHY Auto-negotiation Remote End Capability Register */ -#define PHY_RMT_REG 0x05 -/* Uses same bit definitions as PHY_AD_REG */

-/* PHY Configuration Register 1 */ -#define PHY_CFG1_REG 0x10 -#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ -#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ -#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ -#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ -#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ -#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ -#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ -#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ -#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ -#define PHY_CFG1_TLVL_MASK 0x003C -#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */

-/* PHY Configuration Register 2 */ -#define PHY_CFG2_REG 0x11 -#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ -#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ -#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ -#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */

-/* PHY Status Output (and Interrupt status) Register */ -#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ -#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ -#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ -#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ -#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ -#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ -#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ -#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ -#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ -#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ -#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */

-/* PHY Interrupt/Status Mask Register */ -#define PHY_MASK_REG 0x13 /* Interrupt Mask */ -/* Uses the same bit definitions as PHY_INT_REG */

-/*-------------------------------------------------------------------------

. I define some macros to make it easier to do somewhat common

. or slightly complicated, repeated tasks.

--------------------------------------------------------------------------*/

-/* select a register bank, 0 to 3 */

-#define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); }

-/* this enables an interrupt in the interrupt mask register */ -#define SMC_ENABLE_INT(a,x) {\
          unsigned char mask;\
          SMC_SELECT_BANK((a),2);\
          mask = SMC_inb((a), IM_REG );\
          mask |= (x);\
          SMC_outb( (a), mask, IM_REG ); \
-}

-/* this disables an interrupt from the interrupt mask register */

-#define SMC_DISABLE_INT(a,x) {\
          unsigned char mask;\
          SMC_SELECT_BANK(2);\
          mask = SMC_inb( (a), IM_REG );\
          mask &= ~(x);\
          SMC_outb( (a), mask, IM_REG ); \
-}

-/*----------------------------------------------------------------------

. Define the interrupts that I want to receive from the card

.

. I want:

. IM_EPH_INT, for nasty errors

. IM_RCV_INT, for happy received packets

. IM_RX_OVRN_INT, because I have to kick the receiver

. IM_MDINT, for PHY Register 18 Status Changes

--------------------------------------------------------------------------*/

-#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
  IM_MDINT)
-#endif /* _SMC_91111_H_ */ diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index d4be0c7350dc..5b48a9d43c62 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -4,7 +4,6 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de.

extra-y := hello_world -extra-$(CONFIG_SMC91111) += smc91111_eeprom extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2 extra-$(CONFIG_PPC) += sched

diff --git a/examples/standalone/smc91111_eeprom.c b/examples/standalone/smc91111_eeprom.c deleted file mode 100644 index bf7e93064309..000000000000 --- a/examples/standalone/smc91111_eeprom.c +++ /dev/null @@ -1,372 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
(C) Copyright 2004

Robin Getz rgetz@blacfin.uclinux.org

Heavily borrowed from the following peoples GPL'ed software:

Wolfgang Denk, DENX Software Engineering, wd@denx.de
  Das U-Boot
Ladislav Michl ladis@linux-mips.org
  A rejected patch on the U-Boot mailing list
*/
-#include <common.h> -#include <exports.h> -#include <linux/delay.h> -#include "../drivers/net/smc91111.h"

-#ifndef SMC91111_EEPROM_INIT -# define SMC91111_EEPROM_INIT() -#endif

-#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE -#define EEPROM 0x1 -#define MAC 0x2 -#define UNKNOWN 0x4

-void dump_reg (struct eth_device *dev); -void dump_eeprom (struct eth_device *dev); -int write_eeprom_reg (struct eth_device *dev, int value, int reg); -void copy_from_eeprom (struct eth_device *dev); -void print_MAC (struct eth_device *dev); -int read_eeprom_reg (struct eth_device *dev, int reg); -void print_macaddr (struct eth_device *dev);

-int smc91111_eeprom(int argc, char *const argv[]) -{
  int c, i, j, done, line, reg, value, start, what;
  char input[50];
  struct eth_device dev;
  dev.iobase = CONFIG_SMC91111_BASE;
  /* Print the ABI version */
  app_startup (argv);
  if (XF_VERSION != (int) get_version ()) {
          printf ("Expects ABI version %d\n", XF_VERSION);
          printf ("Actual U-Boot ABI version %d\n",
                  (int) get_version ());
          printf ("Can't run\n\n");
          return (0);
  }
  SMC91111_EEPROM_INIT();
  if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
          printf ("Can't find SMSC91111\n");
          return (0);
  }
  done = 0;
  what = UNKNOWN;
  printf ("\n");
  while (!done) {
          /* print the prompt */
          printf ("SMC91111> ");
          line = 0;
          i = 0;
          start = 1;
          while (!line) {
                  /* Wait for a keystroke */
                  while (!tstc ());
                  c = getc ();
                  /* Make Uppercase */
                  if (c >= 'Z')
                          c -= ('a' - 'A');
                  /* printf(" |%02x| ",c); */
                  switch (c) {
                  case '\r':      /* Enter                */
                  case '\n':
                          input[i] = 0;
                          puts ("\r\n");
                          line = 1;
                          break;
                  case '\0':      /* nul                  */
                          continue;
                  case 0x03:      /* ^C - break           */
                          input[0] = 0;
                          i = 0;
                          line = 1;
                          done = 1;
                          break;
                  case 0x5F:
                  case 0x08:      /* ^H  - backspace      */
                  case 0x7F:      /* DEL - backspace      */
                          if (i > 0) {
                                  puts ("\b \b");
                                  i--;
                          }
                          break;
                  default:
                          if (start) {
                                  if ((c == 'W') || (c == 'D')
                                      || (c == 'M') || (c == 'C')
                                      || (c == 'P')) {
                                          putc (c);
                                          input[i] = c;
                                          if (i <= 45)
                                                  i++;
                                          start = 0;
                                  }
                          } else {
                                  if ((c >= '0' && c <= '9')
                                      || (c >= 'A' && c <= 'F')
                                      || (c == 'E') || (c == 'M')
                                      || (c == ' ')) {
                                          putc (c);
                                          input[i] = c;
                                          if (i <= 45)
                                                  i++;
                                          break;
                                  }
                          }
                          break;
                  }
          }
          for (; i < 49; i++)
                  input[i] = 0;
          switch (input[0]) {
          case ('W'):
                  /* Line should be w reg value */
                  i = 0;
                  reg = 0;
                  value = 0;
                  /* Skip to the next space or end) */
                  while ((input[i] != ' ') && (input[i] != 0))
                          i++;
                  if (input[i] != 0)
                          i++;
                  /* Are we writing to EEPROM or MAC */
                  switch (input[i]) {
                  case ('E'):
                          what = EEPROM;
                          break;
                  case ('M'):
                          what = MAC;
                          break;
                  default:
                          what = UNKNOWN;
                          break;
                  }
                  /* skip to the next space or end */
                  while ((input[i] != ' ') && (input[i] != 0))
                          i++;
                  if (input[i] != 0)
                          i++;
                  /* Find register to write into */
                  j = 0;
                  while ((input[i] != ' ') && (input[i] != 0)) {
                          j = input[i] - 0x30;
                          if (j >= 0xA) {
                                  j -= 0x07;
                          }
                          reg = (reg * 0x10) + j;
                          i++;
                  }
                  while ((input[i] != ' ') && (input[i] != 0))
                          i++;
                  if (input[i] != 0)
                          i++;
                  else
                          what = UNKNOWN;
                  /* Get the value to write */
                  j = 0;
                  while ((input[i] != ' ') && (input[i] != 0)) {
                          j = input[i] - 0x30;
                          if (j >= 0xA) {
                                  j -= 0x07;
                          }
                          value = (value * 0x10) + j;
                          i++;
                  }
                  switch (what) {
                  case 1:
                          printf ("Writing EEPROM register %02x with %04x\n", reg, value);
                          write_eeprom_reg (&dev, value, reg);
                          break;
                  case 2:
                          printf ("Writing MAC register bank %i, reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
                          SMC_SELECT_BANK (&dev, reg >> 4);
                          SMC_outw (&dev, value, reg & 0xE);
                          break;
                  default:
                          printf ("Wrong\n");
                          break;
                  }
                  break;
          case ('D'):
                  dump_eeprom (&dev);
                  break;
          case ('M'):
                  dump_reg (&dev);
                  break;
          case ('C'):
                  copy_from_eeprom (&dev);
                  break;
          case ('P'):
                  print_macaddr (&dev);
                  break;
          default:
                  break;
          }
  }
  return (0);
-}

-void copy_from_eeprom (struct eth_device *dev) -{
  int i;
  SMC_SELECT_BANK (dev, 1);
  SMC_outw (dev, (SMC_inw (dev, CTL_REG) & !CTL_EEPROM_SELECT) |
          CTL_RELOAD, CTL_REG);
  i = 100;
  while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --i)
          udelay(100);
  if (i == 0) {
          printf ("Timeout Refreshing EEPROM registers\n");
  } else {
          printf ("EEPROM contents copied to MAC\n");
  }
-}

-void print_macaddr (struct eth_device *dev) -{
  int i, j, k, mac[6];
  printf ("Current MAC Address in SMSC91111 ");
  SMC_SELECT_BANK (dev, 1);
  for (i = 0; i < 5; i++) {
          printf ("%02x:", SMC_inb (dev, ADDR0_REG + i));
  }
  printf ("%02x\n", SMC_inb (dev, ADDR0_REG + 5));
  i = 0;
  for (j = 0x20; j < 0x23; j++) {
          k = read_eeprom_reg (dev, j);
          mac[i] = k & 0xFF;
          i++;
          mac[i] = k >> 8;
          i++;
  }
  printf ("Current MAC Address in EEPROM    ");
  for (i = 0; i < 5; i++)
          printf ("%02x:", mac[i]);
  printf ("%02x\n", mac[5]);
-} -void dump_eeprom (struct eth_device *dev) -{
  int j, k;
  printf ("IOS2-0    ");
  for (j = 0; j < 8; j++) {
          printf ("%03x     ", j);
  }
  printf ("\n");
  for (k = 0; k < 4; k++) {
          if (k == 0)
                  printf ("CONFIG ");
          if (k == 1)
                  printf ("BASE   ");
          if ((k == 2) || (k == 3))
                  printf ("       ");
          for (j = 0; j < 0x20; j += 4) {
                  printf ("%02x:%04x ", j + k,
                          read_eeprom_reg (dev, j + k));
          }
          printf ("\n");
  }
  for (j = 0x20; j < 0x40; j++) {
          if ((j & 0x07) == 0)
                  printf ("\n");
          printf ("%02x:%04x ", j, read_eeprom_reg (dev, j));
  }
  printf ("\n");
-}

-int read_eeprom_reg (struct eth_device *dev, int reg) -{
  int timeout;
  SMC_SELECT_BANK (dev, 2);
  SMC_outw (dev, reg, PTR_REG);
  SMC_SELECT_BANK (dev, 1);
  SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT |
          CTL_RELOAD, CTL_REG);
  timeout = 100;
  while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
          udelay(100);
  if (timeout == 0) {
          printf ("Timeout Reading EEPROM register %02x\n", reg);
          return 0;
  }
  return SMC_inw (dev, GP_REG);
-}

-int write_eeprom_reg (struct eth_device *dev, int value, int reg) -{
  int timeout;
  SMC_SELECT_BANK (dev, 2);
  SMC_outw (dev, reg, PTR_REG);
  SMC_SELECT_BANK (dev, 1);
  SMC_outw (dev, value, GP_REG);
  SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT |
          CTL_STORE, CTL_REG);
  timeout = 100;
  while ((SMC_inw (dev, CTL_REG) & CTL_STORE) && --timeout)
          udelay(100);
  if (timeout == 0) {
          printf ("Timeout Writing EEPROM register %02x\n", reg);
          return 0;
  }
  return 1;
-}

-void dump_reg (struct eth_device *dev) -{
  int i, j;
  printf ("    ");
  for (j = 0; j < 4; j++) {
          printf ("Bank%i ", j);
  }
  printf ("\n");
  for (i = 0; i < 0xF; i += 2) {
          printf ("%02x  ", i);
          for (j = 0; j < 4; j++) {
                  SMC_SELECT_BANK (dev, j);
                  printf ("%04x  ", SMC_inw (dev, i));
          }
          printf ("\n");
  }
-} diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 2752152f68ee..7b9a5b1c5415 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -19,14 +19,6 @@ /* Integrator CP-specific configuration */ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */

-/*

Hardware drivers

*/

-#define CONFIG_SMC91111 -#define CONFIG_SMC_USE_32_BIT -#define CONFIG_SMC91111_BASE 0xC8000000 -#undef CONFIG_SMC91111_EXT_PHY

#define CONFIG_SERVERIP 192.168.1.100 #define CONFIG_IPADDR 192.168.1.104

diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 077428f50040..0c11b6b3331e 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -84,12 +84,6 @@ #endif #endif /* !CONFIG_GICV3 */

-#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && !defined(CONFIG_DM_ETH) -/* The Vexpress64 BASE_FVP simulator uses SMSC91C111 */ -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000) -#endif

/* PL011 Serial Configuration */ #ifdef CONFIG_TARGET_VEXPRESS64_JUNO

#define CONFIG_PL011_CLOCK 7372800

2.25.1

Acked-by: Ramon Fried rfried.dev@gmail.com

Tom Rini

13 Aug 13 Aug

3:42 a.m.

New subject: [PATCH 09/21] net: Remove smc91111 ethernet driver

On Tue, Aug 02, 2022 at 07:33:35AM -0400, Tom Rini wrote:

...

This driver has not been converted to DM_ETH. The migration deadline passed 2 years ago.

Cc: Linus Walleij linus.walleij@linaro.org Cc: David Feng fenghua@phytium.com.cn Cc: Liviu Dudau liviu.dudau@foss.arm.com Cc: Andre Przywara andre.przywara@arm.com Signed-off-by: Tom Rini trini@konsulko.com Acked-by: Ramon Fried rfried.dev@gmail.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 10/21] net: lpc32xx_eth.c ethernet driver

This driver has not been converted to DM_ETH. The migration deadline passed 2 years ago.

Cc: Trevor Woerner twoerner@gmail.com Signed-off-by: Tom Rini trini@konsulko.com --- Trevor, can you please also update the top-level MAINTAINERS file to list yourself for these chips if you still are interested in them? Thanks. --- arch/arm/include/asm/arch-lpc32xx/config.h | 3 - arch/arm/mach-lpc32xx/cpu.c | 8 - drivers/net/Kconfig | 5 - drivers/net/Makefile | 1 - drivers/net/lpc32xx_eth.c | 651 --------------------- 5 files changed, 668 deletions(-) delete mode 100644 drivers/net/lpc32xx_eth.c

diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 32d68cbeb81a..dc414c7d8452 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -26,9 +26,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }

-/* Ethernet */ -#define LPC32XX_ETH_BASE ETHERNET_BASE - /* NAND */ #if defined(CONFIG_NAND_LPC32XX_SLC) #define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index c2586d092956..a97f9a1958ab 100644 --- a/arch/arm/mach-lpc32xx/cpu.c +++ b/arch/arm/mach-lpc32xx/cpu.c @@ -59,11 +59,3 @@ int print_cpuinfo(void) return 0; } #endif - -#ifdef CONFIG_LPC32XX_ETH -int cpu_eth_init(struct bd_info *bis) -{ - lpc32xx_eth_initialize(bis); - return 0; -} -#endif diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 2fb9aacc208b..76d8057b98fd 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -455,11 +455,6 @@ config KSZ9477 This driver implements a DSA switch driver for the KSZ9477 family of GbE switches using the I2C interface.

-config LPC32XX_ETH - bool "LPC32xx Ethernet MAC interface driver" - depends on ARCH_LPC32XX - default y - config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X diff --git a/drivers/net/Makefile b/drivers/net/Makefile index ac9818107e7e..ecc1dc8bb489 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_KSZ9477) += ksz9477.o -obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c deleted file mode 100644 index 1a5734343935..000000000000 --- a/drivers/net/lpc32xx_eth.c +++ /dev/null @@ -1,651 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * LPC32xx Ethernet MAC interface driver - * - * (C) Copyright 2014 DENX Software Engineering GmbH - * Written-by: Albert ARIBAUD - 3ADEV albert.aribaud@3adev.fr - */ - -#include <common.h> -#include <log.h> -#include <net.h> -#include <malloc.h> -#include <miiphy.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/types.h> -#include <asm/system.h> -#include <asm/byteorder.h> -#include <asm/arch/cpu.h> -#include <asm/arch/config.h> - -/* - * Notes: - * - * 1. Unless specified otherwise, all references to tables or paragraphs - * are to UM10326, "LPC32x0 and LPC32x0/01 User manual". - * - * 2. Only bitfield masks/values which are actually used by the driver - * are defined. - */ - -/* a single RX descriptor. The controller has an array of these */ -struct lpc32xx_eth_rxdesc { - u32 packet; /* Receive packet pointer */ - u32 control; /* Descriptor command status */ -}; - -#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc)) - -/* RX control bitfields/masks (see Table 330) */ -#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF -#define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800 -#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000 - -/* a single RX status. The controller has an array of these */ -struct lpc32xx_eth_rxstat { - u32 statusinfo; /* Transmit Descriptor status */ - u32 statushashcrc; /* Transmit Descriptor CRCs */ -}; - -#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat)) - -/* RX statusinfo bitfields/masks (see Table 333) */ -#define RX_STAT_RXSIZE 0x000007FF -/* Helper: OR of all errors except RANGE */ -#define RX_STAT_ERRORS 0x1B800000 - -/* a single TX descriptor. The controller has an array of these */ -struct lpc32xx_eth_txdesc { - u32 packet; /* Transmit packet pointer */ - u32 control; /* Descriptor control */ -}; - -#define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc)) - -/* TX control bitfields/masks (see Table 335) */ -#define TX_CTRL_TXSIZE 0x000007FF -#define TX_CTRL_LAST 0x40000000 - -/* a single TX status. The controller has an array of these */ -struct lpc32xx_eth_txstat { - u32 statusinfo; /* Transmit Descriptor status */ -}; - -#define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat)) - -/* Ethernet MAC interface registers (see Table 283) */ -struct lpc32xx_eth_registers { - /* MAC registers - 0x3106_0000 to 0x3106_01FC */ - u32 mac1; /* MAC configuration register 1 */ - u32 mac2; /* MAC configuration register 2 */ - u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */ - u32 ipgr; /* Non-back-to-back IPG register */ - u32 clrt; /* Collision Window / Retry register */ - u32 maxf; /* Maximum Frame register */ - u32 supp; /* Phy Support register */ - u32 test; - u32 mcfg; /* MII management configuration reg. */ - u32 mcmd; /* MII management command register */ - u32 madr; /* MII management address register */ - u32 mwtd; /* MII management wite data register */ - u32 mrdd; /* MII management read data register */ - u32 mind; /* MII management indicators register */ - u32 reserved1[2]; - u32 sa0; /* Station address register 0 */ - u32 sa1; /* Station address register 1 */ - u32 sa2; /* Station address register 2 */ - u32 reserved2[45]; - /* Control registers */ - u32 command; - u32 status; - u32 rxdescriptor; - u32 rxstatus; - u32 rxdescriptornumber; /* actually, number MINUS ONE */ - u32 rxproduceindex; /* head of rx desc fifo */ - u32 rxconsumeindex; /* tail of rx desc fifo */ - u32 txdescriptor; - u32 txstatus; - u32 txdescriptornumber; /* actually, number MINUS ONE */ - u32 txproduceindex; /* head of rx desc fifo */ - u32 txconsumeindex; /* tail of rx desc fifo */ - u32 reserved3[10]; - u32 tsv0; /* Transmit status vector register 0 */ - u32 tsv1; /* Transmit status vector register 1 */ - u32 rsv; /* Receive status vector register */ - u32 reserved4[3]; - u32 flowcontrolcounter; - u32 flowcontrolstatus; - u32 reserved5[34]; - /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */ - u32 rxfilterctrl; - u32 rxfilterwolstatus; - u32 rxfilterwolclear; - u32 reserved6; - u32 hashfilterl; - u32 hashfilterh; - u32 reserved7[882]; - /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */ - u32 intstatus; /* Interrupt status register */ - u32 intenable; - u32 intclear; - u32 intset; - u32 reserved8; - u32 powerdown; - u32 reserved9; -}; - -/* MAC1 register bitfields/masks and offsets (see Table 283) */ -#define MAC1_RECV_ENABLE 0x00000001 -#define MAC1_PASS_ALL_RX_FRAMES 0x00000002 -#define MAC1_SOFT_RESET 0x00008000 -/* Helper: general reset */ -#define MAC1_RESETS 0x0000CF00 - -/* MAC2 register bitfields/masks and offsets (see Table 284) */ -#define MAC2_FULL_DUPLEX 0x00000001 -#define MAC2_CRC_ENABLE 0x00000010 -#define MAC2_PAD_CRC_ENABLE 0x00000020 - -/* SUPP register bitfields/masks and offsets (see Table 290) */ -#define SUPP_SPEED 0x00000100 - -/* MCFG register bitfields/masks and offsets (see Table 292) */ -#define MCFG_RESET_MII_MGMT 0x00008000 -/* divide clock by 28 (see Table 293) */ -#define MCFG_CLOCK_SELECT_DIV28 0x0000001C - -/* MADR register bitfields/masks and offsets (see Table 295) */ -#define MADR_REG_MASK 0x0000001F -#define MADR_PHY_MASK 0x00001F00 -#define MADR_REG_OFFSET 0 -#define MADR_PHY_OFFSET 8 - -/* MIND register bitfields/masks (see Table 298) */ -#define MIND_BUSY 0x00000001 - -/* COMMAND register bitfields/masks and offsets (see Table 283) */ -#define COMMAND_RXENABLE 0x00000001 -#define COMMAND_TXENABLE 0x00000002 -#define COMMAND_PASSRUNTFRAME 0x00000040 -#define COMMAND_RMII 0x00000200 -#define COMMAND_FULL_DUPLEX 0x00000400 -/* Helper: general reset */ -#define COMMAND_RESETS 0x00000038 - -/* STATUS register bitfields/masks and offsets (see Table 283) */ -#define STATUS_RXSTATUS 0x00000001 -#define STATUS_TXSTATUS 0x00000002 - -/* RXFILTERCTRL register bitfields/masks (see Table 319) */ -#define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002 -#define RXFILTERCTRL_ACCEPTPERFECT 0x00000020 - -/* Buffers and descriptors */ - -#define ATTRS(n) __aligned(n) - -#define TX_BUF_COUNT 4 -#define RX_BUF_COUNT 4 - -struct lpc32xx_eth_buffers { - ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT]; - ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT]; - ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN]; - ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT]; - ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT]; - ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN]; -}; - -/* port device data struct */ -struct lpc32xx_eth_device { - struct eth_device dev; - struct lpc32xx_eth_registers *regs; - struct lpc32xx_eth_buffers *bufs; - bool phy_rmii; -}; - -#define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device)) - -/* generic macros */ -#define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev) - -/* timeout for MII polling */ -#define MII_TIMEOUT 10000000 - -/* limits for PHY and register addresses */ -#define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET) - -#define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET) - -#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -/* - * mii_reg_read - miiphy_read callback function. - * - * Returns 16bit phy register value, or 0xffff on error - */ -static int mii_reg_read(struct mii_dev *bus, int phy_adr, int devad, - int reg_ofs) -{ - u16 data = 0; - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); - struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; - u32 mind_reg; - u32 timeout; - - /* check parameters */ - if (phy_adr > MII_MAX_PHY) { - printf("%s:%u: Invalid PHY address %d\n", - __func__, __LINE__, phy_adr); - return -EFAULT; - } - if (reg_ofs > MII_MAX_REG) { - printf("%s:%u: Invalid register offset %d\n", - __func__, __LINE__, reg_ofs); - return -EFAULT; - } - - /* write the phy and reg addressse into the MII address reg */ - writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), - &regs->madr); - - /* write 1 to the MII command register to cause a read */ - writel(1, &regs->mcmd); - - /* wait till the MII is not busy */ - timeout = MII_TIMEOUT; - do { - /* read MII indicators register */ - mind_reg = readl(&regs->mind); - if (--timeout == 0) - break; - } while (mind_reg & MIND_BUSY); - - /* write 0 to the MII command register to finish the read */ - writel(0, &regs->mcmd); - - if (timeout == 0) { - printf("%s:%u: MII busy timeout\n", __func__, __LINE__); - return -EFAULT; - } - - data = (u16) readl(&regs->mrdd); - - debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr, - reg_ofs, data); - - return data; -} - -/* - * mii_reg_write - imiiphy_write callback function. - * - * Returns 0 if write succeed, -EINVAL on bad parameters - * -ETIME on timeout - */ -static int mii_reg_write(struct mii_dev *bus, int phy_adr, int devad, - int reg_ofs, u16 data) -{ - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); - struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; - u32 mind_reg; - u32 timeout; - - /* check parameters */ - if (phy_adr > MII_MAX_PHY) { - printf("%s:%u: Invalid PHY address %d\n", - __func__, __LINE__, phy_adr); - return -EFAULT; - } - if (reg_ofs > MII_MAX_REG) { - printf("%s:%u: Invalid register offset %d\n", - __func__, __LINE__, reg_ofs); - return -EFAULT; - } - - /* write the phy and reg addressse into the MII address reg */ - writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), - &regs->madr); - - /* write data to the MII write register */ - writel(data, &regs->mwtd); - - /* wait till the MII is not busy */ - timeout = MII_TIMEOUT; - do { - /* read MII indicators register */ - mind_reg = readl(&regs->mind); - if (--timeout == 0) - break; - } while (mind_reg & MIND_BUSY); - - if (timeout == 0) { - printf("%s:%u: MII busy timeout\n", __func__, - __LINE__); - return -EFAULT; - } - - /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr, - reg_ofs, data);*/ - - return 0; -} -#endif - -/* - * Provide default Ethernet buffers base address if target did not. - * Locate buffers in SRAM at 0x00001000 to avoid cache issues and - * maximize throughput. - */ -#if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE) -#define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000 -#endif - -static struct lpc32xx_eth_device lpc32xx_eth = { - .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE, - .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE, -#if defined(CONFIG_RMII) - .phy_rmii = true, -#endif -}; - -#define TX_TIMEOUT 10000 - -static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; - int timeout, tx_index; - - /* time out if transmit descriptor array remains full too long */ - timeout = TX_TIMEOUT; - while ((readl(&regs->status) & STATUS_TXSTATUS) && - (readl(&regs->txconsumeindex) - == readl(&regs->txproduceindex))) { - if (timeout-- == 0) - return -1; - } - - /* determine next transmit packet index to use */ - tx_index = readl(&regs->txproduceindex); - - /* set up transmit packet */ - memcpy((void *)&bufs->tx_buf[tx_index * PKTSIZE_ALIGN], - (void *)dataptr, datasize); - writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE), - &bufs->tx_desc[tx_index].control); - writel(0, &bufs->tx_stat[tx_index].statusinfo); - - /* pass transmit packet to DMA engine */ - tx_index = (tx_index + 1) % TX_BUF_COUNT; - writel(tx_index, &regs->txproduceindex); - - /* transmission succeeded */ - return 0; -} - -#define RX_TIMEOUT 1000000 - -static int lpc32xx_eth_recv(struct eth_device *dev) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; - int timeout, rx_index; - - /* time out if receive descriptor array remains empty too long */ - timeout = RX_TIMEOUT; - while (readl(&regs->rxproduceindex) == readl(&regs->rxconsumeindex)) { - if (timeout-- == 0) - return -1; - } - - /* determine next receive packet index to use */ - rx_index = readl(&regs->rxconsumeindex); - - /* if data was valid, pass it on */ - if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) { - net_process_received_packet( - &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]), - (bufs->rx_stat[rx_index].statusinfo - & RX_STAT_RXSIZE) + 1); - } - - /* pass receive slot back to DMA engine */ - rx_index = (rx_index + 1) % RX_BUF_COUNT; - writel(rx_index, &regs->rxconsumeindex); - - /* reception successful */ - return 0; -} - -static int lpc32xx_eth_write_hwaddr(struct eth_device *dev) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - - /* Save station address */ - writel((unsigned long) (dev->enetaddr[0] | - (dev->enetaddr[1] << 8)), &regs->sa2); - writel((unsigned long) (dev->enetaddr[2] | - (dev->enetaddr[3] << 8)), &regs->sa1); - writel((unsigned long) (dev->enetaddr[4] | - (dev->enetaddr[5] << 8)), &regs->sa0); - - return 0; -} - -static int lpc32xx_eth_init(struct eth_device *dev) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; - int index; - - /* Initial MAC initialization */ - writel(MAC1_PASS_ALL_RX_FRAMES, &regs->mac1); - writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, &regs->mac2); - writel(PKTSIZE_ALIGN, &regs->maxf); - - /* Retries: 15 (0xF). Collision window: 57 (0x37). */ - writel(0x370F, &regs->clrt); - - /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */ - writel(0x0012, &regs->ipgr); - - /* pass runt (smaller than 64 bytes) frames */ - if (lpc32xx_eth_device->phy_rmii) - writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, &regs->command); - else - writel(COMMAND_PASSRUNTFRAME, &regs->command); - - /* Configure Full/Half Duplex mode */ - if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) { - setbits_le32(&regs->mac2, MAC2_FULL_DUPLEX); - setbits_le32(&regs->command, COMMAND_FULL_DUPLEX); - writel(0x15, &regs->ipgt); - } else { - writel(0x12, &regs->ipgt); - } - - /* Configure 100MBit/10MBit mode */ - if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET) - writel(SUPP_SPEED, &regs->supp); - else - writel(0, &regs->supp); - - /* Save station address */ - writel((unsigned long) (dev->enetaddr[0] | - (dev->enetaddr[1] << 8)), &regs->sa2); - writel((unsigned long) (dev->enetaddr[2] | - (dev->enetaddr[3] << 8)), &regs->sa1); - writel((unsigned long) (dev->enetaddr[4] | - (dev->enetaddr[5] << 8)), &regs->sa0); - - /* set up transmit buffers */ - for (index = 0; index < TX_BUF_COUNT; index++) { - bufs->tx_desc[index].control = 0; - bufs->tx_stat[index].statusinfo = 0; - } - writel((u32)(&bufs->tx_desc), (u32 *)&regs->txdescriptor); - writel((u32)(&bufs->tx_stat), &regs->txstatus); - writel(TX_BUF_COUNT-1, &regs->txdescriptornumber); - - /* set up receive buffers */ - for (index = 0; index < RX_BUF_COUNT; index++) { - bufs->rx_desc[index].packet = - (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN); - bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1; - bufs->rx_stat[index].statusinfo = 0; - bufs->rx_stat[index].statushashcrc = 0; - } - writel((u32)(&bufs->rx_desc), &regs->rxdescriptor); - writel((u32)(&bufs->rx_stat), &regs->rxstatus); - writel(RX_BUF_COUNT-1, &regs->rxdescriptornumber); - - /* set up transmit buffers */ - for (index = 0; index < TX_BUF_COUNT; index++) - bufs->tx_desc[index].packet = - (u32)(bufs->tx_buf + index * PKTSIZE_ALIGN); - - /* Enable broadcast and matching address packets */ - writel(RXFILTERCTRL_ACCEPTBROADCAST | - RXFILTERCTRL_ACCEPTPERFECT, &regs->rxfilterctrl); - - /* Clear and disable interrupts */ - writel(0xFFFF, &regs->intclear); - writel(0, &regs->intenable); - - /* Enable receive and transmit mode of MAC ethernet core */ - setbits_le32(&regs->command, COMMAND_RXENABLE | COMMAND_TXENABLE); - setbits_le32(&regs->mac1, MAC1_RECV_ENABLE); - - /* - * Perform a 'dummy' first send to work around Ethernet.1 - * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011). - * Use zeroed "index" variable as the dummy. - */ - - index = 0; - lpc32xx_eth_send(dev, &index, 4); - - return 0; -} - -static int lpc32xx_eth_halt(struct eth_device *dev) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; - - /* Reset all MAC logic */ - writel(MAC1_RESETS, &regs->mac1); - writel(COMMAND_RESETS, &regs->command); - /* Let reset condition settle */ - udelay(2000); - - return 0; -} - -#if defined(CONFIG_PHYLIB) -int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid) -{ - struct lpc32xx_eth_device *lpc32xx_eth_device = - container_of(dev, struct lpc32xx_eth_device, dev); - struct mii_dev *bus; - struct phy_device *phydev; - int ret; - - bus = mdio_alloc(); - if (!bus) { - printf("mdio_alloc failed\n"); - return -ENOMEM; - } - bus->read = mii_reg_read; - bus->write = mii_reg_write; - strcpy(bus->name, dev->name); - - ret = mdio_register(bus); - if (ret) { - printf("mdio_register failed\n"); - free(bus); - return -ENOMEM; - } - - if (lpc32xx_eth_device->phy_rmii) - phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII); - else - phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII); - - if (!phydev) { - printf("phy_connect failed\n"); - return -ENODEV; - } - - phy_config(phydev); - phy_startup(phydev); - - return 0; -} -#endif - -int lpc32xx_eth_initialize(struct bd_info *bis) -{ - struct eth_device *dev = &lpc32xx_eth.dev; - struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs; - - /* - * Set RMII management clock rate. With HCLK at 104 MHz and - * a divider of 28, this will be 3.72 MHz. - */ - writel(MCFG_RESET_MII_MGMT, &regs->mcfg); - writel(MCFG_CLOCK_SELECT_DIV28, &regs->mcfg); - - /* Reset all MAC logic */ - writel(MAC1_RESETS, &regs->mac1); - writel(COMMAND_RESETS, &regs->command); - - /* wait 10 ms for the whole I/F to reset */ - udelay(10000); - - /* must be less than sizeof(dev->name) */ - strcpy(dev->name, "eth0"); - - dev->init = (void *)lpc32xx_eth_init; - dev->halt = (void *)lpc32xx_eth_halt; - dev->send = (void *)lpc32xx_eth_send; - dev->recv = (void *)lpc32xx_eth_recv; - dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr; - - /* Release SOFT reset to let MII talk to PHY */ - clrbits_le32(&regs->mac1, MAC1_SOFT_RESET); - - /* register driver before talking to phy */ - eth_register(dev); - -#if defined(CONFIG_PHYLIB) - lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR); -#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = mii_reg_read; - mdiodev->write = mii_reg_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - - return 0; -}

-- 2.25.1

Ramon Fried

6 Aug 6 Aug

7:47 p.m.

New subject: [PATCH 10/21] net: lpc32xx_eth.c ethernet driver

On Tue, Aug 2, 2022 at 2:37 PM Tom Rini trini@konsulko.com wrote:

...

This driver has not been converted to DM_ETH. The migration deadline passed 2 years ago.

Cc: Trevor Woerner twoerner@gmail.com Signed-off-by: Tom Rini trini@konsulko.com

Trevor, can you please also update the top-level MAINTAINERS file to list yourself for these chips if you still are interested in them? Thanks.

arch/arm/include/asm/arch-lpc32xx/config.h | 3 - arch/arm/mach-lpc32xx/cpu.c | 8 - drivers/net/Kconfig | 5 - drivers/net/Makefile | 1 - drivers/net/lpc32xx_eth.c | 651 --------------------- 5 files changed, 668 deletions(-) delete mode 100644 drivers/net/lpc32xx_eth.c

diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 32d68cbeb81a..dc414c7d8452 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -26,9 +26,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }

-/* Ethernet */ -#define LPC32XX_ETH_BASE ETHERNET_BASE

/* NAND */ #if defined(CONFIG_NAND_LPC32XX_SLC) #define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index c2586d092956..a97f9a1958ab 100644 --- a/arch/arm/mach-lpc32xx/cpu.c +++ b/arch/arm/mach-lpc32xx/cpu.c @@ -59,11 +59,3 @@ int print_cpuinfo(void) return 0; } #endif

-#ifdef CONFIG_LPC32XX_ETH -int cpu_eth_init(struct bd_info *bis) -{
  lpc32xx_eth_initialize(bis);
  return 0;
-} -#endif diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 2fb9aacc208b..76d8057b98fd 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -455,11 +455,6 @@ config KSZ9477 This driver implements a DSA switch driver for the KSZ9477 family of GbE switches using the I2C interface.

-config LPC32XX_ETH
  bool "LPC32xx Ethernet MAC interface driver"
  depends on ARCH_LPC32XX
  default y
config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X diff --git a/drivers/net/Makefile b/drivers/net/Makefile index ac9818107e7e..ecc1dc8bb489 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_KSZ9477) += ksz9477.o -obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c deleted file mode 100644 index 1a5734343935..000000000000 --- a/drivers/net/lpc32xx_eth.c +++ /dev/null @@ -1,651 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

LPC32xx Ethernet MAC interface driver

(C) Copyright 2014 DENX Software Engineering GmbH

Written-by: Albert ARIBAUD - 3ADEV albert.aribaud@3adev.fr

*/

-#include <common.h> -#include <log.h> -#include <net.h> -#include <malloc.h> -#include <miiphy.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/types.h> -#include <asm/system.h> -#include <asm/byteorder.h> -#include <asm/arch/cpu.h> -#include <asm/arch/config.h>

-/*

Notes:

Unless specified otherwise, all references to tables or paragraphs

are to UM10326, "LPC32x0 and LPC32x0/01 User manual".

Only bitfield masks/values which are actually used by the driver

are defined.

*/

-/* a single RX descriptor. The controller has an array of these */ -struct lpc32xx_eth_rxdesc {
  u32 packet;             /* Receive packet pointer */
  u32 control;            /* Descriptor command status */
-};

-#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))

-/* RX control bitfields/masks (see Table 330) */ -#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF -#define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800 -#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000

-/* a single RX status. The controller has an array of these */ -struct lpc32xx_eth_rxstat {
  u32 statusinfo;         /* Transmit Descriptor status */
  u32 statushashcrc;      /* Transmit Descriptor CRCs */
-};

-#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))

-/* RX statusinfo bitfields/masks (see Table 333) */ -#define RX_STAT_RXSIZE 0x000007FF -/* Helper: OR of all errors except RANGE */ -#define RX_STAT_ERRORS 0x1B800000

-/* a single TX descriptor. The controller has an array of these */ -struct lpc32xx_eth_txdesc {
  u32 packet;             /* Transmit packet pointer */
  u32 control;            /* Descriptor control */
-};

-#define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc))

-/* TX control bitfields/masks (see Table 335) */ -#define TX_CTRL_TXSIZE 0x000007FF -#define TX_CTRL_LAST 0x40000000

-/* a single TX status. The controller has an array of these */ -struct lpc32xx_eth_txstat {
  u32 statusinfo;         /* Transmit Descriptor status */
-};

-#define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat))

-/* Ethernet MAC interface registers (see Table 283) */ -struct lpc32xx_eth_registers {
  /* MAC registers - 0x3106_0000 to 0x3106_01FC */
  u32 mac1;               /* MAC configuration register 1 */
  u32 mac2;               /* MAC configuration register 2 */
  u32 ipgt;               /* Back-to-back Inter-Packet Gap reg. */
  u32 ipgr;               /* Non-back-to-back IPG register */
  u32 clrt;               /* Collision Window / Retry register */
  u32 maxf;               /* Maximum Frame register */
  u32 supp;               /* Phy Support register */
  u32 test;
  u32 mcfg;               /* MII management configuration reg. */
  u32 mcmd;               /* MII management command register */
  u32 madr;               /* MII management address register */
  u32 mwtd;               /* MII management wite data register */
  u32 mrdd;               /* MII management read data register */
  u32 mind;               /* MII management indicators register */
  u32 reserved1[2];
  u32 sa0;                /* Station address register 0 */
  u32 sa1;                /* Station address register 1 */
  u32 sa2;                /* Station address register 2 */
  u32 reserved2[45];
  /* Control registers */
  u32 command;
  u32 status;
  u32 rxdescriptor;
  u32 rxstatus;
  u32 rxdescriptornumber; /* actually, number MINUS ONE */
  u32 rxproduceindex;     /* head of rx desc fifo */
  u32 rxconsumeindex;     /* tail of rx desc fifo */
  u32 txdescriptor;
  u32 txstatus;
  u32 txdescriptornumber; /* actually, number MINUS ONE */
  u32 txproduceindex;     /* head of rx desc fifo */
  u32 txconsumeindex;     /* tail of rx desc fifo */
  u32 reserved3[10];
  u32 tsv0;               /* Transmit status vector register 0 */
  u32 tsv1;               /* Transmit status vector register 1 */
  u32 rsv;                /* Receive status vector register */
  u32 reserved4[3];
  u32 flowcontrolcounter;
  u32 flowcontrolstatus;
  u32 reserved5[34];
  /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */
  u32 rxfilterctrl;
  u32 rxfilterwolstatus;
  u32 rxfilterwolclear;
  u32 reserved6;
  u32 hashfilterl;
  u32 hashfilterh;
  u32 reserved7[882];
  /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */
  u32 intstatus;          /* Interrupt status register */
  u32 intenable;
  u32 intclear;
  u32 intset;
  u32 reserved8;
  u32 powerdown;
  u32 reserved9;
-};

-/* MAC1 register bitfields/masks and offsets (see Table 283) */ -#define MAC1_RECV_ENABLE 0x00000001 -#define MAC1_PASS_ALL_RX_FRAMES 0x00000002 -#define MAC1_SOFT_RESET 0x00008000 -/* Helper: general reset */ -#define MAC1_RESETS 0x0000CF00

-/* MAC2 register bitfields/masks and offsets (see Table 284) */ -#define MAC2_FULL_DUPLEX 0x00000001 -#define MAC2_CRC_ENABLE 0x00000010 -#define MAC2_PAD_CRC_ENABLE 0x00000020

-/* SUPP register bitfields/masks and offsets (see Table 290) */ -#define SUPP_SPEED 0x00000100

-/* MCFG register bitfields/masks and offsets (see Table 292) */ -#define MCFG_RESET_MII_MGMT 0x00008000 -/* divide clock by 28 (see Table 293) */ -#define MCFG_CLOCK_SELECT_DIV28 0x0000001C

-/* MADR register bitfields/masks and offsets (see Table 295) */ -#define MADR_REG_MASK 0x0000001F -#define MADR_PHY_MASK 0x00001F00 -#define MADR_REG_OFFSET 0 -#define MADR_PHY_OFFSET 8

-/* MIND register bitfields/masks (see Table 298) */ -#define MIND_BUSY 0x00000001

-/* COMMAND register bitfields/masks and offsets (see Table 283) */ -#define COMMAND_RXENABLE 0x00000001 -#define COMMAND_TXENABLE 0x00000002 -#define COMMAND_PASSRUNTFRAME 0x00000040 -#define COMMAND_RMII 0x00000200 -#define COMMAND_FULL_DUPLEX 0x00000400 -/* Helper: general reset */ -#define COMMAND_RESETS 0x00000038

-/* STATUS register bitfields/masks and offsets (see Table 283) */ -#define STATUS_RXSTATUS 0x00000001 -#define STATUS_TXSTATUS 0x00000002

-/* RXFILTERCTRL register bitfields/masks (see Table 319) */ -#define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002 -#define RXFILTERCTRL_ACCEPTPERFECT 0x00000020

-/* Buffers and descriptors */

-#define ATTRS(n) __aligned(n)

-#define TX_BUF_COUNT 4 -#define RX_BUF_COUNT 4

-struct lpc32xx_eth_buffers {
  ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT];
  ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT];
  ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN];
  ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT];
  ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT];
  ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN];
-};

-/* port device data struct */ -struct lpc32xx_eth_device {
  struct eth_device dev;
  struct lpc32xx_eth_registers *regs;
  struct lpc32xx_eth_buffers *bufs;
  bool phy_rmii;
-};

-#define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device))

-/* generic macros */ -#define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev)

-/* timeout for MII polling */ -#define MII_TIMEOUT 10000000

-/* limits for PHY and register addresses */ -#define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET)

-#define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET)

-#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -/*

mii_reg_read - miiphy_read callback function.

Returns 16bit phy register value, or 0xffff on error

*/

-static int mii_reg_read(struct mii_dev *bus, int phy_adr, int devad,
                  int reg_ofs)
-{
  u16 data = 0;
  struct eth_device *dev = eth_get_dev_by_name(bus->name);
  struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
  struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
  u32 mind_reg;
  u32 timeout;
  /* check parameters */
  if (phy_adr > MII_MAX_PHY) {
          printf("%s:%u: Invalid PHY address %d\n",
                 __func__, __LINE__, phy_adr);
          return -EFAULT;
  }
  if (reg_ofs > MII_MAX_REG) {
          printf("%s:%u: Invalid register offset %d\n",
                 __func__, __LINE__, reg_ofs);
          return -EFAULT;
  }
  /* write the phy and reg addressse into the MII address reg */
  writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
         &regs->madr);
  /* write 1 to the MII command register to cause a read */
  writel(1, &regs->mcmd);
  /* wait till the MII is not busy */
  timeout = MII_TIMEOUT;
  do {
          /* read MII indicators register */
          mind_reg = readl(&regs->mind);
          if (--timeout == 0)
                  break;
  } while (mind_reg & MIND_BUSY);
  /* write 0 to the MII command register to finish the read */
  writel(0, &regs->mcmd);
  if (timeout == 0) {
          printf("%s:%u: MII busy timeout\n", __func__, __LINE__);
          return -EFAULT;
  }
  data = (u16) readl(&regs->mrdd);
  debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr,
        reg_ofs, data);
  return data;
-}

-/*

mii_reg_write - imiiphy_write callback function.

Returns 0 if write succeed, -EINVAL on bad parameters

-ETIME on timeout

*/

-static int mii_reg_write(struct mii_dev *bus, int phy_adr, int devad,
                   int reg_ofs, u16 data)
-{
  struct eth_device *dev = eth_get_dev_by_name(bus->name);
  struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
  struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
  u32 mind_reg;
  u32 timeout;
  /* check parameters */
  if (phy_adr > MII_MAX_PHY) {
          printf("%s:%u: Invalid PHY address %d\n",
                 __func__, __LINE__, phy_adr);
          return -EFAULT;
  }
  if (reg_ofs > MII_MAX_REG) {
          printf("%s:%u: Invalid register offset %d\n",
                 __func__, __LINE__, reg_ofs);
          return -EFAULT;
  }
  /* write the phy and reg addressse into the MII address reg */
  writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
         &regs->madr);
  /* write data to the MII write register */
  writel(data, &regs->mwtd);
  /* wait till the MII is not busy */
  timeout = MII_TIMEOUT;
  do {
          /* read MII indicators register */
          mind_reg = readl(&regs->mind);
          if (--timeout == 0)
                  break;
  } while (mind_reg & MIND_BUSY);
  if (timeout == 0) {
          printf("%s:%u: MII busy timeout\n", __func__,
                 __LINE__);
          return -EFAULT;
  }
  /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
          reg_ofs, data);*/
  return 0;
-} -#endif

-/*

Provide default Ethernet buffers base address if target did not.

Locate buffers in SRAM at 0x00001000 to avoid cache issues and

maximize throughput.

*/

-#if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE) -#define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000 -#endif

-static struct lpc32xx_eth_device lpc32xx_eth = {
  .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
  .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE,
-#if defined(CONFIG_RMII)
  .phy_rmii = true,
-#endif -};

-#define TX_TIMEOUT 10000

-static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize) -{
  struct lpc32xx_eth_device *lpc32xx_eth_device =
          container_of(dev, struct lpc32xx_eth_device, dev);
  struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
  int timeout, tx_index;
  /* time out if transmit descriptor array remains full too long */
  timeout = TX_TIMEOUT;
  while ((readl(&regs->status) & STATUS_TXSTATUS) &&
         (readl(&regs->txconsumeindex)
         == readl(&regs->txproduceindex))) {
          if (timeout-- == 0)
                  return -1;
  }
  /* determine next transmit packet index to use */
  tx_index = readl(&regs->txproduceindex);
  /* set up transmit packet */
  memcpy((void *)&bufs->tx_buf[tx_index * PKTSIZE_ALIGN],
         (void *)dataptr, datasize);
  writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE),
         &bufs->tx_desc[tx_index].control);
  writel(0, &bufs->tx_stat[tx_index].statusinfo);
  /* pass transmit packet to DMA engine */
  tx_index = (tx_index + 1) % TX_BUF_COUNT;
  writel(tx_index, &regs->txproduceindex);
  /* transmission succeeded */
  return 0;
-}

-#define RX_TIMEOUT 1000000

-static int lpc32xx_eth_recv(struct eth_device *dev) -{
  struct lpc32xx_eth_device *lpc32xx_eth_device =
          container_of(dev, struct lpc32xx_eth_device, dev);
  struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
  int timeout, rx_index;
  /* time out if receive descriptor array remains empty too long */
  timeout = RX_TIMEOUT;
  while (readl(&regs->rxproduceindex) == readl(&regs->rxconsumeindex)) {
          if (timeout-- == 0)
                  return -1;
  }
  /* determine next receive packet index to use */
  rx_index = readl(&regs->rxconsumeindex);
  /* if data was valid, pass it on */
  if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) {
          net_process_received_packet(
                  &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]),
                  (bufs->rx_stat[rx_index].statusinfo
                   & RX_STAT_RXSIZE) + 1);
  }
  /* pass receive slot back to DMA engine */
  rx_index = (rx_index + 1) % RX_BUF_COUNT;
  writel(rx_index, &regs->rxconsumeindex);
  /* reception successful */
  return 0;
-}

-static int lpc32xx_eth_write_hwaddr(struct eth_device *dev) -{
  struct lpc32xx_eth_device *lpc32xx_eth_device =
          container_of(dev, struct lpc32xx_eth_device, dev);
  struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  /* Save station address */
  writel((unsigned long) (dev->enetaddr[0] |
          (dev->enetaddr[1] << 8)), &regs->sa2);
  writel((unsigned long) (dev->enetaddr[2] |
          (dev->enetaddr[3] << 8)), &regs->sa1);
  writel((unsigned long) (dev->enetaddr[4] |
          (dev->enetaddr[5] << 8)), &regs->sa0);
  return 0;
-}

-static int lpc32xx_eth_init(struct eth_device *dev) -{
  struct lpc32xx_eth_device *lpc32xx_eth_device =
          container_of(dev, struct lpc32xx_eth_device, dev);
  struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
  int index;
  /* Initial MAC initialization */
  writel(MAC1_PASS_ALL_RX_FRAMES, &regs->mac1);
  writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, &regs->mac2);
  writel(PKTSIZE_ALIGN, &regs->maxf);
  /* Retries: 15 (0xF). Collision window: 57 (0x37). */
  writel(0x370F, &regs->clrt);
  /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
  writel(0x0012, &regs->ipgr);
  /* pass runt (smaller than 64 bytes) frames */
  if (lpc32xx_eth_device->phy_rmii)
          writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, &regs->command);
  else
          writel(COMMAND_PASSRUNTFRAME, &regs->command);
  /* Configure Full/Half Duplex mode */
  if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {
          setbits_le32(&regs->mac2, MAC2_FULL_DUPLEX);
          setbits_le32(&regs->command, COMMAND_FULL_DUPLEX);
          writel(0x15, &regs->ipgt);
  } else {
          writel(0x12, &regs->ipgt);
  }
  /* Configure 100MBit/10MBit mode */
  if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET)
          writel(SUPP_SPEED, &regs->supp);
  else
          writel(0, &regs->supp);
  /* Save station address */
  writel((unsigned long) (dev->enetaddr[0] |
          (dev->enetaddr[1] << 8)), &regs->sa2);
  writel((unsigned long) (dev->enetaddr[2] |
          (dev->enetaddr[3] << 8)), &regs->sa1);
  writel((unsigned long) (dev->enetaddr[4] |
          (dev->enetaddr[5] << 8)), &regs->sa0);
  /* set up transmit buffers */
  for (index = 0; index < TX_BUF_COUNT; index++) {
          bufs->tx_desc[index].control = 0;
          bufs->tx_stat[index].statusinfo = 0;
  }
  writel((u32)(&bufs->tx_desc), (u32 *)&regs->txdescriptor);
  writel((u32)(&bufs->tx_stat), &regs->txstatus);
  writel(TX_BUF_COUNT-1, &regs->txdescriptornumber);
  /* set up receive buffers */
  for (index = 0; index < RX_BUF_COUNT; index++) {
          bufs->rx_desc[index].packet =
                  (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN);
          bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1;
          bufs->rx_stat[index].statusinfo = 0;
          bufs->rx_stat[index].statushashcrc = 0;
  }
  writel((u32)(&bufs->rx_desc), &regs->rxdescriptor);
  writel((u32)(&bufs->rx_stat), &regs->rxstatus);
  writel(RX_BUF_COUNT-1, &regs->rxdescriptornumber);
  /* set up transmit buffers */
  for (index = 0; index < TX_BUF_COUNT; index++)
          bufs->tx_desc[index].packet =
                  (u32)(bufs->tx_buf + index * PKTSIZE_ALIGN);
  /* Enable broadcast and matching address packets */
  writel(RXFILTERCTRL_ACCEPTBROADCAST |
          RXFILTERCTRL_ACCEPTPERFECT, &regs->rxfilterctrl);
  /* Clear and disable interrupts */
  writel(0xFFFF, &regs->intclear);
  writel(0, &regs->intenable);
  /* Enable receive and transmit mode of MAC ethernet core */
  setbits_le32(&regs->command, COMMAND_RXENABLE | COMMAND_TXENABLE);
  setbits_le32(&regs->mac1, MAC1_RECV_ENABLE);
  /*
   * Perform a 'dummy' first send to work around Ethernet.1
   * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011).
   * Use zeroed "index" variable as the dummy.
   */
  index = 0;
  lpc32xx_eth_send(dev, &index, 4);
  return 0;
-}

-static int lpc32xx_eth_halt(struct eth_device *dev) -{
  struct lpc32xx_eth_device *lpc32xx_eth_device =
          container_of(dev, struct lpc32xx_eth_device, dev);
  struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  /* Reset all MAC logic */
  writel(MAC1_RESETS, &regs->mac1);
  writel(COMMAND_RESETS, &regs->command);
  /* Let reset condition settle */
  udelay(2000);
  return 0;
-}

-#if defined(CONFIG_PHYLIB) -int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid) -{
  struct lpc32xx_eth_device *lpc32xx_eth_device =
          container_of(dev, struct lpc32xx_eth_device, dev);
  struct mii_dev *bus;
  struct phy_device *phydev;
  int ret;
  bus = mdio_alloc();
  if (!bus) {
          printf("mdio_alloc failed\n");
          return -ENOMEM;
  }
  bus->read = mii_reg_read;
  bus->write = mii_reg_write;
  strcpy(bus->name, dev->name);
  ret = mdio_register(bus);
  if (ret) {
          printf("mdio_register failed\n");
          free(bus);
          return -ENOMEM;
  }
  if (lpc32xx_eth_device->phy_rmii)
          phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII);
  else
          phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
  if (!phydev) {
          printf("phy_connect failed\n");
          return -ENODEV;
  }
  phy_config(phydev);
  phy_startup(phydev);
  return 0;
-} -#endif

-int lpc32xx_eth_initialize(struct bd_info *bis) -{
  struct eth_device *dev = &lpc32xx_eth.dev;
  struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs;
  /*
   * Set RMII management clock rate. With HCLK at 104 MHz and
   * a divider of 28, this will be 3.72 MHz.
   */
  writel(MCFG_RESET_MII_MGMT, &regs->mcfg);
  writel(MCFG_CLOCK_SELECT_DIV28, &regs->mcfg);
  /* Reset all MAC logic */
  writel(MAC1_RESETS, &regs->mac1);
  writel(COMMAND_RESETS, &regs->command);
  /* wait 10 ms for the whole I/F to reset */
  udelay(10000);
  /* must be less than sizeof(dev->name) */
  strcpy(dev->name, "eth0");
  dev->init = (void *)lpc32xx_eth_init;
  dev->halt = (void *)lpc32xx_eth_halt;
  dev->send = (void *)lpc32xx_eth_send;
  dev->recv = (void *)lpc32xx_eth_recv;
  dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr;
  /* Release SOFT reset to let MII talk to PHY */
  clrbits_le32(&regs->mac1, MAC1_SOFT_RESET);
  /* register driver before talking to phy */
  eth_register(dev);
-#if defined(CONFIG_PHYLIB)
  lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR);
-#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  int retval;
  struct mii_dev *mdiodev = mdio_alloc();
  if (!mdiodev)
          return -ENOMEM;
  strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  mdiodev->read = mii_reg_read;
  mdiodev->write = mii_reg_write;
  retval = mdio_register(mdiodev);
  if (retval < 0)
          return retval;
-#endif
  return 0;
-}

2.25.1

Acked-by: Ramon Fried rfried.dev@gmail.com

Tom Rini

21 Aug 21 Aug

4:42 a.m.

New subject: [PATCH 10/21] net: lpc32xx_eth.c ethernet driver

On Tue, Aug 02, 2022 at 07:33:36AM -0400, Tom Rini wrote:

...

This driver has not been converted to DM_ETH. The migration deadline passed 2 years ago.

Cc: Trevor Woerner twoerner@gmail.com Signed-off-by: Tom Rini trini@konsulko.com Acked-by: Ramon Fried rfried.dev@gmail.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 11/21] fsl-mc: Update dependencies for DM_ETH

When using DM_ETH, which should be the default now, we need to always have DM_MDIO and FSL_LS_MDIO enabled, so select them.

Cc: Priyanka Jain priyanka.jain@nxp.com Cc: Rajesh Bhagat rajesh.bhagat@nxp.com Cc: Wasim Khan wasim.khan@nxp.com Cc: Udit Agarwal udit.agarwal@nxp.com Cc: Ashish Kumar Ashish.Kumar@nxp.com Cc: Meenakshi Aggarwal meenakshi.aggarwal@nxp.com Cc: Patrick Delaunay patrick.delaunay@foss.st.com Cc: Patrice Chotard patrice.chotard@foss.st.com Cc: Manish Tomar Manish.Tomar@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- drivers/net/fsl-mc/Kconfig | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/net/fsl-mc/Kconfig b/drivers/net/fsl-mc/Kconfig index ae4c35799bf7..8fc34dc26f15 100644 --- a/drivers/net/fsl-mc/Kconfig +++ b/drivers/net/fsl-mc/Kconfig @@ -6,6 +6,8 @@ menuconfig FSL_MC_ENET bool "NXP Management Complex" depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A default y + select DM_MDIO + select FSL_LS_MDIO select RESV_RAM help Enable Management Complex (MC) network

-- 2.25.1

Tom Rini

21 Aug 21 Aug

4:42 a.m.

New subject: [PATCH 11/21] fsl-mc: Update dependencies for DM_ETH

On Tue, Aug 02, 2022 at 07:33:37AM -0400, Tom Rini wrote:

...

When using DM_ETH, which should be the default now, we need to always have DM_MDIO and FSL_LS_MDIO enabled, so select them.

Cc: Priyanka Jain priyanka.jain@nxp.com Cc: Rajesh Bhagat rajesh.bhagat@nxp.com Cc: Wasim Khan wasim.khan@nxp.com Cc: Udit Agarwal udit.agarwal@nxp.com Cc: Ashish Kumar Ashish.Kumar@nxp.com Cc: Meenakshi Aggarwal meenakshi.aggarwal@nxp.com Cc: Patrick Delaunay patrick.delaunay@foss.st.com Cc: Patrice Chotard patrice.chotard@foss.st.com Cc: Manish Tomar Manish.Tomar@nxp.com Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 12/21] layerscape: Disable CONFIG_FMAN_ENET on some platforms

On platforms that have not migrated to enabling CONFIG_DM_ETH already, disable CONFIG_FMAN_ENET.

Cc: Mingkai Hu mingkai.hu@nxp.com Cc: Rajesh Bhagat rajesh.bhagat@nxp.com Cc: Pramod Kumar pramod.kumar_1@nxp.com Cc: Peng Fan peng.fan@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- Note that board/freescale/corenet_ds/MAINTAINERS shows them all orphaned and should likely be removed. --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- arch/powerpc/cpu/mpc85xx/fdt.c | 2 +- board/freescale/corenet_ds/corenet_ds.c | 5 +---- board/freescale/corenet_ds/eth_hydra.c | 7 +------ board/freescale/ls1043aqds/eth.c | 10 ++++++---- board/freescale/ls1043aqds/ls1043aqds.c | 5 +---- board/freescale/ls1046aqds/eth.c | 10 ++++++---- board/freescale/ls1046aqds/ls1046aqds.c | 5 +---- configs/P3041DS_NAND_defconfig | 1 - configs/P3041DS_SDCARD_defconfig | 1 - configs/P3041DS_SPIFLASH_defconfig | 1 - configs/P3041DS_defconfig | 1 - configs/P5040DS_NAND_defconfig | 1 - configs/P5040DS_SDCARD_defconfig | 1 - configs/P5040DS_SPIFLASH_defconfig | 1 - configs/P5040DS_defconfig | 1 - configs/ls1043aqds_defconfig | 1 - configs/ls1043aqds_lpuart_defconfig | 1 - configs/ls1043aqds_nand_defconfig | 1 - configs/ls1043aqds_nor_ddr3_defconfig | 1 - configs/ls1043aqds_qspi_defconfig | 1 - configs/ls1043aqds_sdcard_ifc_defconfig | 1 - configs/ls1043aqds_sdcard_qspi_defconfig | 1 - configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1043aqds_tfa_defconfig | 1 - configs/ls1043ardb_SECURE_BOOT_defconfig | 1 - configs/ls1043ardb_defconfig | 1 - configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 - configs/ls1043ardb_nand_defconfig | 1 - configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 - configs/ls1043ardb_sdcard_defconfig | 1 - configs/ls1043ardb_tfa_defconfig | 1 - configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1046afrwy_tfa_defconfig | 1 - configs/ls1046aqds_SECURE_BOOT_defconfig | 1 - configs/ls1046aqds_defconfig | 1 - configs/ls1046aqds_lpuart_defconfig | 1 - configs/ls1046aqds_nand_defconfig | 1 - configs/ls1046aqds_qspi_defconfig | 1 - configs/ls1046aqds_sdcard_ifc_defconfig | 1 - configs/ls1046aqds_sdcard_qspi_defconfig | 1 - configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1046aqds_tfa_defconfig | 1 - configs/ls1046ardb_emmc_defconfig | 1 - configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 1 - configs/ls1046ardb_qspi_defconfig | 1 - configs/ls1046ardb_qspi_spl_defconfig | 1 - configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 - configs/ls1046ardb_sdcard_defconfig | 1 - configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1046ardb_tfa_defconfig | 1 - 51 files changed, 18 insertions(+), 71 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 2fa7ebf16391..427de1cb339d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -671,7 +671,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) "clock-frequency", get_qman_freq(), 1); #endif

-#ifdef CONFIG_SYS_DPAA_FMAN +#ifdef CONFIG_FMAN_ENET fdt_fixup_fman_firmware(blob); #endif #ifdef CONFIG_FSL_PFE diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index c8ad6a1b01ce..3186b182d31b 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -643,7 +643,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) ft_fixup_qe_snum(blob); #endif

-#ifdef CONFIG_SYS_DPAA_FMAN +#ifdef CONFIG_FMAN_ENET fdt_fixup_fman_firmware(blob); #endif

diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 3a83e65f2fe5..2a980404880e 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -207,10 +207,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_liodn(blob); fsl_fdt_fixup_dr_usb(blob, bd);

-#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif +#ifdef CONFIG_FMAN_ENET fdt_fixup_board_enet(blob); #endif

diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index a27e905ace9d..6f0ea1fe7e02 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -315,8 +315,6 @@ static void initialize_lane_to_slot(void) lane_to_slot[17] = lane_to_slot[16]; }

-#endif /* #ifdef CONFIG_FMAN_ENET */ - /* * Configure the status for the virtual MDIO nodes * @@ -332,7 +330,6 @@ static void initialize_lane_to_slot(void) */ void fdt_fixup_board_enet(void *fdt) { -#ifdef CONFIG_FMAN_ENET unsigned int i; int lane;

@@ -363,12 +360,10 @@ void fdt_fixup_board_enet(void *fdt) lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) fdt_status_okay_by_alias(fdt, "emi2_xgmii"); -#endif }

int board_eth_init(struct bd_info *bis) { -#ifdef CONFIG_FMAN_ENET struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; @@ -520,7 +515,7 @@ int board_eth_init(struct bd_info *bis) miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));

cpu_eth_init(bis); -#endif

return pci_eth_init(bis); } +#endif diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index e156ba010451..7bfbacde4fbd 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -30,8 +30,6 @@ #define EMI1_SLOT4 5 #define EMI2 6

-static int mdio_mux[NUM_FM_PORTS]; - static const char * const mdio_names[] = { "LS1043AQDS_MDIO_RGMII1", "LS1043AQDS_MDIO_RGMII2", @@ -43,7 +41,11 @@ static const char * const mdio_names[] = { };

/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ +#ifdef CONFIG_FMAN_ENET +static int mdio_mux[NUM_FM_PORTS]; + static u8 lane_to_slot[] = {1, 2, 3, 4}; +#endif

static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) { @@ -75,6 +77,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; }

+#ifdef CONFIG_FMAN_ENET struct ls1043aqds_mdio { u8 muxval; struct mii_dev *realbus; @@ -296,7 +299,6 @@ void fdt_fixup_board_enet(void *fdt)

int board_eth_init(struct bd_info *bis) { -#ifdef CONFIG_FMAN_ENET int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; @@ -493,7 +495,7 @@ int board_eth_init(struct bd_info *bis) }

cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */

return pci_eth_init(bis); } +#endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 13359f947bb5..7ac2c1ae901d 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -556,10 +556,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd);

-#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif +#ifdef CONFIG_FMAN_ENET fdt_fixup_board_enet(blob); #endif

diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 8233f5461ee3..13207a1a37d5 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -27,8 +27,6 @@ #define EMI1_SLOT2 3 #define EMI1_SLOT4 4

-static int mdio_mux[NUM_FM_PORTS]; - static const char * const mdio_names[] = { "LS1046AQDS_MDIO_RGMII1", "LS1046AQDS_MDIO_RGMII2", @@ -39,7 +37,11 @@ static const char * const mdio_names[] = { };

/* Map SerDes 1 & 2 lanes to default slot. */ +#ifdef CONFIG_FMAN_ENET +static int mdio_mux[NUM_FM_PORTS]; + static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0}; +#endif

static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval) { @@ -71,6 +73,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; }

+#ifdef CONFIG_FMAN_ENET struct ls1046aqds_mdio { u8 muxval; struct mii_dev *realbus; @@ -263,7 +266,6 @@ void fdt_fixup_board_enet(void *fdt)

int board_eth_init(struct bd_info *bis) { -#ifdef CONFIG_FMAN_ENET int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -423,7 +425,7 @@ int board_eth_init(struct bd_info *bis) }

cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */

return pci_eth_init(bis); } +#endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index e5b5441e2c3f..aa6e30e6b2a6 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -439,10 +439,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd);

-#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif +#ifdef CONFIG_FMAN_ENET fdt_fixup_board_enet(blob); #endif

diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index 7afb7a45ec85..d3abe684befc 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -95,7 +95,6 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x100000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 35e2e4f161d9..1365a7e5e16e 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -90,7 +90,6 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0xD2000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 2e50dc44f788..e6922bb97c2c 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -92,7 +92,6 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index b494dfa82234..3ba00ffc9cef 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -87,7 +87,6 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index b36f525cc19c..9fdfb77b6404 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -95,7 +95,6 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x100000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index 4111901fc401..61897d65410f 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -89,7 +89,6 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0xD2000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 5d493ee89c5e..2e3a67f23944 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -91,7 +91,6 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index dbcb02765d6c..617a9e86f420 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -86,7 +86,6 @@ CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index d7ff7e2970fb..ea95a68be259 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -95,7 +95,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 462fad1cd48f..84f65780077d 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -95,7 +95,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 63287ca533b3..1b49f53abed9 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -125,7 +125,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index fc72f4cdaf64..6a04b063aa83 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -96,7 +96,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 30cc15a12f3d..0ef4fe3db379 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -85,7 +85,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 172ab723c61b..cf9fd13777c6 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -122,7 +122,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 447a51513fe3..cacd85e4cf5c 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -110,7 +110,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index b414d400e6a1..e05746454495 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -94,7 +94,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 9bac24a27b30..c67876b9520d 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -103,7 +103,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 0a40bf0f9f99..231e7f07c5bc 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -80,7 +80,6 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index f27eadf39211..764e88fdd531 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -83,7 +83,6 @@ CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index da23382940f8..1a45a0030130 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -104,7 +104,6 @@ CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 2be08bbb7b35..999b2101ce93 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -111,7 +111,6 @@ CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index d9b841df1a4e..0e55f5b40b9f 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -104,7 +104,6 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 79feb55dfb15..dea50b3389a4 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -108,7 +108,6 @@ CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index f9cb304ba1cc..08222eadd8e0 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -85,7 +85,6 @@ CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index 1be7002a1859..a7592886db0f 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -63,7 +63,6 @@ CONFIG_PHYLIB=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index f41434c7419b..e57d9a7907fd 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -69,7 +69,6 @@ CONFIG_PHYLIB=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 3a71185b865a..7a0b786be75d 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -93,7 +93,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 35abfb323f65..d582f61d4eee 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -96,7 +96,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 5316c80c83d2..9731b85b0c4d 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -96,7 +96,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 8550190d2295..bd58d3a90f74 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -124,7 +124,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 049cf1e56f98..0dca44a8b0bd 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -86,7 +86,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 6cdc78da3f0f..d023f534210c 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -124,7 +124,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 68aae882a807..aed01d44f1c4 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -112,7 +112,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 7efa5cbebd07..e8676e2ca1ea 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -94,7 +94,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 3846b95e71d5..8faeeb4773ea 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -104,7 +104,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 331419844669..462f700be8aa 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -102,7 +102,6 @@ CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 2ea72cc2a8ad..db7ecc4f452f 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -78,7 +78,6 @@ CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index c6b537f3b8dd..844a4db464b7 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -82,7 +82,6 @@ CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 57cebf5f8b43..00adb099fff0 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -110,7 +110,6 @@ CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 6960aa9d3ffd..9528aa387299 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -101,7 +101,6 @@ CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 9ca4315c83c7..49643b005020 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -102,7 +102,6 @@ CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index e192ef48b131..186eee983427 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -72,7 +72,6 @@ CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 6e5f29a708dd..038c2d4288f4 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -78,7 +78,6 @@ CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y

-- 2.25.1

Tom Rini

9 Aug 9 Aug

4:16 p.m.

New subject: [PATCHv2 12a/21] ppc: Remove corenet_ds boards

These boards have been orphaned for some time and are behind on various DM migrations. Remove them.

Cc: Priyanka Jain priyanka.jain@nxp.com Cc: Peng Fan peng.fan@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- Changes in v2: - New patch

.azure-pipelines.yml | 4 +- arch/powerpc/cpu/mpc85xx/Kconfig | 1 - board/freescale/corenet_ds/Kconfig | 38 - board/freescale/corenet_ds/MAINTAINERS | 21 - board/freescale/corenet_ds/Makefile | 14 - board/freescale/corenet_ds/corenet_ds.c | 218 ----- board/freescale/corenet_ds/corenet_ds.h | 12 - board/freescale/corenet_ds/ddr.c | 287 ------- board/freescale/corenet_ds/eth_hydra.c | 526 ------------ board/freescale/corenet_ds/eth_p4080.c | 489 ----------- board/freescale/corenet_ds/eth_superhydra.c | 783 ------------------ board/freescale/corenet_ds/p3041ds_ddr.c | 11 - board/freescale/corenet_ds/p4080ds_ddr.c | 346 -------- board/freescale/corenet_ds/p5040ds_ddr.c | 15 - board/freescale/corenet_ds/rcw_p3041ds.cfg | 11 - board/freescale/corenet_ds/rcw_p4080ds.cfg | 11 - board/freescale/corenet_ds/rcw_p5040ds.cfg | 11 - .../{corenet_ds => p2041rdb}/pbi.cfg | 0 .../{corenet_ds => p2041rdb}/rcw_p2041rdb.cfg | 0 configs/P2041RDB_NAND_defconfig | 4 +- configs/P2041RDB_SDCARD_defconfig | 4 +- configs/P2041RDB_SPIFLASH_defconfig | 4 +- configs/P3041DS_NAND_defconfig | 113 --- configs/P3041DS_SDCARD_defconfig | 108 --- configs/P3041DS_SPIFLASH_defconfig | 110 --- configs/P3041DS_defconfig | 105 --- configs/P4080DS_SDCARD_defconfig | 105 --- configs/P4080DS_SPIFLASH_defconfig | 107 --- configs/P4080DS_defconfig | 102 --- configs/P5040DS_NAND_defconfig | 113 --- configs/P5040DS_SDCARD_defconfig | 107 --- configs/P5040DS_SPIFLASH_defconfig | 109 --- configs/P5040DS_defconfig | 104 --- doc/README.pblimage | 2 +- include/configs/P3041DS.h | 18 - include/configs/P4080DS.h | 17 - include/configs/P5040DS.h | 13 - 37 files changed, 8 insertions(+), 4035 deletions(-) delete mode 100644 board/freescale/corenet_ds/Kconfig delete mode 100644 board/freescale/corenet_ds/MAINTAINERS delete mode 100644 board/freescale/corenet_ds/Makefile delete mode 100644 board/freescale/corenet_ds/corenet_ds.c delete mode 100644 board/freescale/corenet_ds/corenet_ds.h delete mode 100644 board/freescale/corenet_ds/ddr.c delete mode 100644 board/freescale/corenet_ds/eth_hydra.c delete mode 100644 board/freescale/corenet_ds/eth_p4080.c delete mode 100644 board/freescale/corenet_ds/eth_superhydra.c delete mode 100644 board/freescale/corenet_ds/p3041ds_ddr.c delete mode 100644 board/freescale/corenet_ds/p4080ds_ddr.c delete mode 100644 board/freescale/corenet_ds/p5040ds_ddr.c delete mode 100644 board/freescale/corenet_ds/rcw_p3041ds.cfg delete mode 100644 board/freescale/corenet_ds/rcw_p4080ds.cfg delete mode 100644 board/freescale/corenet_ds/rcw_p5040ds.cfg rename board/freescale/{corenet_ds => p2041rdb}/pbi.cfg (100%) rename board/freescale/{corenet_ds => p2041rdb}/rcw_p2041rdb.cfg (100%) delete mode 100644 configs/P3041DS_NAND_defconfig delete mode 100644 configs/P3041DS_SDCARD_defconfig delete mode 100644 configs/P3041DS_SPIFLASH_defconfig delete mode 100644 configs/P3041DS_defconfig delete mode 100644 configs/P4080DS_SDCARD_defconfig delete mode 100644 configs/P4080DS_SPIFLASH_defconfig delete mode 100644 configs/P4080DS_defconfig delete mode 100644 configs/P5040DS_NAND_defconfig delete mode 100644 configs/P5040DS_SDCARD_defconfig delete mode 100644 configs/P5040DS_SPIFLASH_defconfig delete mode 100644 configs/P5040DS_defconfig delete mode 100644 include/configs/P3041DS.h delete mode 100644 include/configs/P4080DS.h delete mode 100644 include/configs/P5040DS.h

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 36ca3cb46264..3ec6b4b709fb 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -517,9 +517,7 @@ stages: non_fsl_ppc: BUILDMAN: "powerpc -x freescale" mpc85xx_freescale: - BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x bsc91*" - t208xrdb_corenet_ds: - BUILDMAN: "t208xrdb corenet_ds" + BUILDMAN: "mpc85xx&freescale -x t102* -x p1_p2_rdb_pc -x p1010rdb -x bsc91*" fsl_ppc: BUILDMAN: "mpc83xx&freescale" t102x: diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 8f35d3cf5ed8..277d30ac4515 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1444,7 +1444,6 @@ config FSL_VIA bool

source "board/emulation/qemu-ppce500/Kconfig" -source "board/freescale/corenet_ds/Kconfig" source "board/freescale/mpc8548cds/Kconfig" source "board/freescale/p1010rdb/Kconfig" source "board/freescale/p1_p2_rdb_pc/Kconfig" diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig deleted file mode 100644 index dbcd1afcbad1..000000000000 --- a/board/freescale/corenet_ds/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -if TARGET_P3041DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P3041DS" - -endif - -if TARGET_P4080DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P4080DS" - -endif - -if TARGET_P5040DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P5040DS" - -endif diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS deleted file mode 100644 index f0da86a34ca3..000000000000 --- a/board/freescale/corenet_ds/MAINTAINERS +++ /dev/null @@ -1,21 +0,0 @@ -CORENET_DS BOARD -#M: - -S: Maintained -F: board/freescale/corenet_ds/ -F: include/configs/P3041DS.h -F: configs/P3041DS_defconfig -F: configs/P3041DS_NAND_defconfig -F: configs/P3041DS_SDCARD_defconfig -F: configs/P3041DS_SPIFLASH_defconfig -F: configs/P3041DS_SRIO_PCIE_BOOT_defconfig -F: include/configs/P4080DS.h -F: configs/P4080DS_defconfig -F: configs/P4080DS_SDCARD_defconfig -F: configs/P4080DS_SPIFLASH_defconfig -F: configs/P4080DS_SRIO_PCIE_BOOT_defconfig -F: include/configs/P5040DS.h -F: configs/P5040DS_defconfig -F: configs/P5040DS_NAND_defconfig -F: configs/P5040DS_SDCARD_defconfig -F: configs/P5040DS_SPIFLASH_defconfig -F: configs/P5040DS_SECURE_BOOT_defconfig diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile deleted file mode 100644 index 4d62fc9ce190..000000000000 --- a/board/freescale/corenet_ds/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2007-2009 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += corenet_ds.o -obj-y += ddr.o -obj-$(CONFIG_TARGET_P3041DS) += eth_hydra.o -obj-$(CONFIG_TARGET_P4080DS) += eth_p4080.o -obj-$(CONFIG_TARGET_P5040DS) += eth_superhydra.o -obj-$(CONFIG_TARGET_P3041DS) += p3041ds_ddr.o -obj-$(CONFIG_TARGET_P4080DS) += p4080ds_ddr.o -obj-$(CONFIG_TARGET_P5040DS) += p5040ds_ddr.o diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c deleted file mode 100644 index 3a83e65f2fe5..000000000000 --- a/board/freescale/corenet_ds/corenet_ds.c +++ /dev/null @@ -1,218 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <fdt_support.h> -#include <image.h> -#include <init.h> -#include <netdev.h> -#include <asm/global_data.h> -#include <linux/compiler.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_liodn.h> -#include <fm_eth.h> - -#include "../common/ngpixis.h" -#include "corenet_ds.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard (void) -{ - u8 sw; - struct cpu_type *cpu = gd->arch.cpu; -#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ - defined(CONFIG_TARGET_P5040DS) - unsigned int i; -#endif - static const char * const freq[] = {"100", "125", "156.25", "212.5" }; - - printf("Board: %sDS, ", cpu->name); - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); - - sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); - sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("Promjet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else - printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); - - /* Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ - puts("SERDES Reference Clocks: "); -#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ - defined(CONFIG_TARGET_P5040DS) - sw = in_8(&PIXIS_SW(5)); - for (i = 0; i < 3; i++) { - unsigned int clock = (sw >> (6 - (2 * i))) & 3; - - printf("Bank%u=%sMhz ", i+1, freq[clock]); - } -#ifdef CONFIG_TARGET_P5040DS - /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ - sw = in_8(&PIXIS_SW(9)); - printf("Bank4=%sMhz ", freq[sw & 3]); -#endif - puts("\n"); -#else - sw = in_8(&PIXIS_SW(3)); - /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ - /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ - /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ - printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); - printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); - printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); -#endif - - return 0; -} - -int board_early_init_f(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - /* - * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 - * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce - * the noise introduced by these unterminated and unused clock pairs. - */ - setbits_be32(&gur->ddrclkdr, 0x001B001B); - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ - 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ - - return 0; -} - -#define NUM_SRDS_BANKS 3 - -int misc_init_r(void) -{ - serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - u32 actual[NUM_SRDS_BANKS]; - unsigned int i; - u8 sw; - -#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ - defined(CONFIG_TARGET_P5040DS) - sw = in_8(&PIXIS_SW(5)); - for (i = 0; i < 3; i++) { - unsigned int clock = (sw >> (6 - (2 * i))) & 3; - switch (clock) { - case 0: - actual[i] = SRDS_PLLCR0_RFCK_SEL_100; - break; - case 1: - actual[i] = SRDS_PLLCR0_RFCK_SEL_125; - break; - case 2: - actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; - break; - default: - printf("Warning: SDREFCLK%u switch setting of '11' is " - "unsupported\n", i + 1); - break; - } - } -#else - /* Warn if the expected SERDES reference clocks don't match the - * actual reference clocks. This needs to be done after calling - * p4080_erratum_serdes8(), since that function may modify the clocks. - */ - sw = in_8(&PIXIS_SW(3)); - actual[0] = (sw & 0x40) ? - SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; - actual[1] = (sw & 0x20) ? - SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; - actual[2] = (sw & 0x10) ? - SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; -#endif - - for (i = 0; i < NUM_SRDS_BANKS; i++) { - u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; - if (expected != actual[i]) { - printf("Warning: SERDES bank %u expects reference clock" - " %sMHz, but actual is %sMHz\n", i + 1, - serdes_clock_to_string(expected), - serdes_clock_to_string(actual[i])); - } - } - - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fsl_fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif - fdt_fixup_board_enet(blob); -#endif - - return 0; -} diff --git a/board/freescale/corenet_ds/corenet_ds.h b/board/freescale/corenet_ds/corenet_ds.h deleted file mode 100644 index 84e5c4a2de21..000000000000 --- a/board/freescale/corenet_ds/corenet_ds.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#ifndef __CORENET_DS_H__ -#define __CORENET_DS_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, struct bd_info *bd); - -#endif diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c deleted file mode 100644 index 2c440673e7c3..000000000000 --- a/board/freescale/corenet_ds/ddr.c +++ /dev/null @@ -1,287 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <i2c.h> -#include <hwconfig.h> -#include <init.h> -#include <log.h> -#include <vsprintf.h> -#include <asm/global_data.h> -#include <asm/mmu.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <asm/fsl_law.h> - -DECLARE_GLOBAL_DATA_PTR; - - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -extern fixed_ddr_parm_t fixed_ddr_parm_0[]; -#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) -extern fixed_ddr_parm_t fixed_ddr_parm_1[]; -#endif - -phys_size_t fixed_sdram(void) -{ - int i; - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - phys_size_t ddr_size; - unsigned int lawbar1_target_id; - ulong ddr_freq, ddr_freq_mhz; - - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && - (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { - memcpy(&ddr_cfg_regs, - fixed_ddr_parm_0[i].ddr_settings, - sizeof(ddr_cfg_regs)); - break; - } - } - - if (fixed_ddr_parm_0[i].max_freq == 0) - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - -#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) - memcpy(&ddr_cfg_regs, - fixed_ddr_parm_1[i].ddr_settings, - sizeof(ddr_cfg_regs)); - ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0); -#endif - - /* - * setup laws for DDR. If not interleaving, presuming half memory on - * DDR1 and the other half on DDR2 - */ - if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, - LAW_TRGT_IF_DDR_INTRLV) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - } else { -#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) - /* We require both controllers have identical DIMMs */ - lawbar1_target_id = LAW_TRGT_IF_DDR_1; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size / 2, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - lawbar1_target_id = LAW_TRGT_IF_DDR_2; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2, - ddr_size / 2, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } -#else - lawbar1_target_id = LAW_TRGT_IF_DDR_1; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } -#endif - } - return ddr_size; -} - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 wrlvl_start; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | |delay | - */ - {4, 850, 4, 6, 0xff, 2, 0}, - {4, 950, 5, 7, 0xff, 2, 0}, - {4, 1050, 5, 8, 0xff, 2, 0}, - {4, 1250, 5, 10, 0xff, 2, 0}, - {4, 1350, 5, 11, 0xff, 2, 0}, - {4, 1666, 5, 12, 0xff, 2, 0}, - {2, 850, 5, 6, 0xff, 2, 0}, - {2, 1050, 5, 7, 0xff, 2, 0}, - {2, 1250, 4, 6, 0xff, 2, 0}, - {2, 1350, 5, 7, 0xff, 2, 0}, - {2, 1666, 5, 8, 0xff, 2, 0}, - {1, 1250, 4, 6, 0xff, 2, 0}, - {1, 1335, 4, 7, 0xff, 2, 0}, - {1, 1666, 4, 8, 0xff, 2, 0}, - {} -}; - -/* - * The two slots have slightly different timing. The center values are good - * for both slots. We use identical speed tables for them. In future use, if - * DIMMs have fewer center values that require two separated tables, copy the - * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. - */ -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | |delay | - */ - {4, 850, 4, 6, 0xff, 2, 0}, - {4, 950, 5, 7, 0xff, 2, 0}, - {4, 1050, 5, 8, 0xff, 2, 0}, - {4, 1250, 5, 10, 0xff, 2, 0}, - {4, 1350, 5, 11, 0xff, 2, 0}, - {4, 1666, 5, 12, 0xff, 2, 0}, - {2, 850, 4, 6, 0xff, 2, 0}, - {2, 1050, 4, 7, 0xff, 2, 0}, - {2, 1666, 4, 8, 0xff, 2, 0}, - {1, 850, 4, 5, 0xff, 2, 0}, - {1, 950, 4, 7, 0xff, 2, 0}, - {1, 1666, 4, 8, 0xff, 2, 0}, - {} -}; - -/* - * The two slots have slightly different timing. See comments above. - */ -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twot_en = pbsp_highest->force_2t; - } else { - panic("DIMM is not supported by this board"); - } -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 60 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN; -} - -int dram_init(void) -{ - phys_size_t dram_size; - - puts("Initializing...."); - - if (fsl_use_spd()) { - puts("using SPD\n"); - dram_size = fsl_ddr_sdram(); - } else { - puts("using fixed parameters\n"); - dram_size = fixed_sdram(); - } - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - debug(" DDR: "); - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c deleted file mode 100644 index a27e905ace9d..000000000000 --- a/board/freescale/corenet_ds/eth_hydra.c +++ /dev/null @@ -1,526 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * Author: Timur Tabi timur@freescale.com - */ - -/* - * This file handles the board muxing between the Fman Ethernet MACs and - * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference - * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are - * provided by the standard Freescale four-port SGMII riser card. The 10Gb - * XGMII PHY is provided via the XAUI riser card. Since there is only one - * Fman device on a P3041 and P5020, we only support one SGMII card and one - * RGMII card. - * - * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control - * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is - * always the same (0). The value for SGMII depends on which slot the riser is - * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, - * the value is based on which slot the XAUI is inserted in. - * - * The SERDES configuration is used to determine where the SGMII and XAUI cards - * exist, and also which Fman MACs are routed to which PHYs. So for a given - * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed - * to PHYs dynamically. - * - * - * This file also updates the device tree in three ways: - * - * 1) The status of each virtual MDIO node that is referenced by an Ethernet - * node is set to "okay". - * - * 2) The phy-handle property of each active Ethernet MAC node is set to the - * appropriate PHY node. - * - * 3) The "mux value" for each virtual MDIO node is set to the correct value, - * if necessary. Some virtual MDIO nodes do not have configurable mux - * values, so those values are hard-coded in the DTS. On the HYDRA board, - * the virtual MDIO node for the SGMII card needs to be updated. - * - * For all this to work, the device tree needs to have the following: - * - * 1) An alias for each PHY node that an Ethernet node could be routed to. - * - * 2) An alias for each real and virtual MDIO node that is disabled by default - * and might need to be enabled, and also might need to have its mux-value - * updated. - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fdt_support.h> -#include <fsl_dtsec.h> - -#include "../common/ngpixis.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET - -#define BRDCFG1_EMI1_SEL_MASK 0x78 -#define BRDCFG1_EMI1_SEL_SLOT1 0x10 -#define BRDCFG1_EMI1_SEL_SLOT2 0x20 -#define BRDCFG1_EMI1_SEL_SLOT5 0x30 -#define BRDCFG1_EMI1_SEL_SLOT6 0x40 -#define BRDCFG1_EMI1_SEL_SLOT7 0x50 -#define BRDCFG1_EMI1_SEL_RGMII 0x00 -#define BRDCFG1_EMI1_EN 0x08 -#define BRDCFG1_EMI2_SEL_MASK 0x06 -#define BRDCFG1_EMI2_SEL_SLOT1 0x00 -#define BRDCFG1_EMI2_SEL_SLOT2 0x02 - -#define BRDCFG2_REG_GPIO_SEL 0x20 - -#define PHY_BASE_ADDR 0x00 - -/* - * BRDCFG1 mask and value for each MAC - * - * This array contains the BRDCFG1 values (in mask/val format) that route the - * MDIO bus to a particular RGMII or SGMII PHY. - */ -struct { - u8 mask; - u8 val; -} mdio_mux[NUM_FM_PORTS]; - -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0 -}; - -/* - * Set the board muxing for a given MAC - * - * The MDIO layer calls this function every time it wants to talk to a PHY. - */ -void hydra_mux_mdio(u8 mask, u8 val) -{ - clrsetbits_8(&pixis->brdcfg1, mask, val); -} - -struct hydra_mdio { - u8 mask; - u8 val; - struct mii_dev *realbus; -}; - -static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct hydra_mdio *priv = bus->priv; - - hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct hydra_mdio *priv = bus->priv; - - hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int hydra_mdio_reset(struct mii_dev *bus) -{ - struct hydra_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static void hydra_mdio_set_mux(char *name, u8 mask, u8 val) -{ - struct mii_dev *bus = miiphy_get_dev_by_name(name); - struct hydra_mdio *priv = bus->priv; - - priv->mask = mask; - priv->val = val; -} - -static int hydra_mdio_init(char *realbusname, char *fakebusname) -{ - struct hydra_mdio *hmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate Hydra MDIO bus\n"); - return -1; - } - - hmdio = malloc(sizeof(*hmdio)); - if (!hmdio) { - printf("Failed to allocate Hydra private data\n"); - free(bus); - return -1; - } - - bus->read = hydra_mdio_read; - bus->write = hydra_mdio_write; - bus->reset = hydra_mdio_reset; - strcpy(bus->name, fakebusname); - - hmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!hmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(hmdio); - return -1; - } - - bus->priv = hmdio; - - return mdio_register(bus); -} - -/* - * Given an alias or a path for a node, set the mux value of that node. - * - * If 'alias' is not a valid alias, then it is treated as a full path to the - * node. No error checking is performed. - * - * This function is normally called to set the fsl,hydra-mdio-muxval property - * of a virtual MDIO node. - */ -static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux) -{ - const char *path = fdt_get_alias(fdt, alias); - - if (!path) - path = alias; - - do_fixup_by_path(fdt, path, "reg", - &mux, sizeof(mux), 1); - do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval", - &mux, sizeof(mux), 1); -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. That - * information is stored in mdio_mux[]. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used, and we recalculate the offset anyway. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - * - * Note that this code would be cleaner if had a function called - * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[] - * array. That's because all we're doing is figuring out the PHY address for - * a given Fman MAC and writing it to the device tree. Well, we already did - * the hard work to figure that out in board_eth_init(), so it's silly to - * repeat that here. - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask; - char phy[16]; - - if (port == FM1_10GEC1) { - /* XAUI */ - int lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - /* The XAUI PHY is identified by the slot */ - sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - return; - } - - if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) { - /* RGMII */ - /* The RGMII PHY is identified by the MAC connected to it */ - sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1); - fdt_set_phy_handle(fdt, compat, addr, phy); - return; - } - - /* If it's not RGMII or XGMII, it must be SGMII */ - if (mux) { - /* The SGMII PHY is identified by the MAC connected to it */ - sprintf(phy, "phy_sgmii_%x", - CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } -} - -#define PIXIS_SW2_LANE_23_SEL 0x80 -#define PIXIS_SW2_LANE_45_SEL 0x40 -#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 -#define PIXIS_SW2_LANE_67_SEL_5 0x00 -#define PIXIS_SW2_LANE_67_SEL_6 0x20 -#define PIXIS_SW2_LANE_67_SEL_7 0x10 -#define PIXIS_SW2_LANE_8_SEL 0x08 -#define PIXIS_SW2_LANE_1617_SEL 0x04 - -/* - * Initialize the lane_to_slot[] array. - * - * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board - * slots is hard-coded. On the Hydra board, however, the mapping is controlled - * by board switch SW2, so the lane_to_slot[] array needs to be dynamically - * initialized. - */ -static void initialize_lane_to_slot(void) -{ - u8 sw2 = in_8(&PIXIS_SW(2)); - - lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; - lane_to_slot[3] = lane_to_slot[2]; - - lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; - lane_to_slot[5] = lane_to_slot[4]; - - switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { - case PIXIS_SW2_LANE_67_SEL_5: - lane_to_slot[6] = 5; - break; - case PIXIS_SW2_LANE_67_SEL_6: - lane_to_slot[6] = 6; - break; - case PIXIS_SW2_LANE_67_SEL_7: - lane_to_slot[6] = 7; - break; - } - lane_to_slot[7] = lane_to_slot[6]; - - lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; - - lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; - lane_to_slot[17] = lane_to_slot[16]; -} - -#endif /* #ifdef CONFIG_FMAN_ENET */ - -/* - * Configure the status for the virtual MDIO nodes - * - * Rather than create the virtual MDIO nodes from scratch for each active - * virtual MDIO, we expect the DTS to have the nodes defined already, and we - * only enable the ones that are actually active. - * - * We assume that the DTS already hard-codes the status for all the - * virtual MDIO nodes to "disabled", so all we need to do is enable the - * active ones. - * - * For SGMII, we also need to set the mux value in the node. - */ -void fdt_fixup_board_enet(void *fdt) -{ -#ifdef CONFIG_FMAN_ENET - unsigned int i; - int lane; - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane >= 0) { - fdt_status_okay_by_alias(fdt, "emi1_sgmii"); - /* Also set the MUX value */ - fdt_set_mdio_mux(fdt, "emi1_sgmii", - mdio_mux[i].val); - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fdt_status_okay_by_alias(fdt, "emi1_rgmii"); - break; - default: - break; - } - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) - fdt_status_okay_by_alias(fdt, "emi2_xgmii"); -#endif -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - struct mii_dev *bus; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ - setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); - - memset(mdio_mux, 0, sizeof(mdio_mux)); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* Register the three virtual MDIO front-ends */ - hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO"); - hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO"); - - /* - * Program the DTSEC PHY addresses assuming that they are all SGMII. - * For any DTSEC that's RGMII, we'll override its PHY address later. - * We assume that DTSEC5 is only used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - switch (slot) { - case 1: - /* Always DTSEC5 on Bank 3 */ - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | - BRDCFG1_EMI1_EN; - break; - case 2: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | - BRDCFG1_EMI1_EN; - break; - case 5: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | - BRDCFG1_EMI1_EN; - break; - case 6: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | - BRDCFG1_EMI1_EN; - break; - case 7: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | - BRDCFG1_EMI1_EN; - break; - }; - - hydra_mdio_set_mux("HYDRA_SGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* - * If DTSEC4 is RGMII, then it's routed via via EC1 to - * the first on-board RGMII port. If DTSEC5 is RGMII, - * then it's routed via via EC2 to the second on-board - * RGMII port. The other DTSECs cannot be routed to - * RGMII. - */ - fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1); - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | - BRDCFG1_EMI1_EN; - hydra_mdio_set_mux("HYDRA_RGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("HYDRA_RGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"); - set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR); - - /* - * For 10G, we only support one XAUI card per Fman. If present, then we - * force its routing and never touch those bits again, which removes the - * need for Linux to do any muxing. This works because of the way - * BRDCFG1 is defined, but it's a bit hackish. - * - * The PHY address for the XAUI card depends on which slot it's in. The - * macros we use imply that the PHY address is based on which FM, but - * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, - * and FM2 could only use a XAUI in slot 4. On the Hydra board, we - * check the actual slot and just use the macros as-is, even though - * the P3041 and P5020 only have one Fman. - */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - slot = lane_to_slot[lane]; - if (slot == 1) { - /* XAUI card is in slot 1 */ - clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, - BRDCFG1_EMI2_SEL_SLOT1); - fm_info_set_phy_address(FM1_10GEC1, - CONFIG_SYS_FM1_10GEC1_PHY_ADDR); - } else { - /* XAUI card is in slot 2 */ - clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, - BRDCFG1_EMI2_SEL_SLOT2); - fm_info_set_phy_address(FM1_10GEC1, - CONFIG_SYS_FM2_10GEC1_PHY_ADDR); - } - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c deleted file mode 100644 index df5a69bcba31..000000000000 --- a/board/freescale/corenet_ds/eth_p4080.c +++ /dev/null @@ -1,489 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <fdt_support.h> -#include <net.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <linux/delay.h> - -#include "../common/ngpixis.h" -#include "../common/fman.h" -#include <fsl_dtsec.h> - -#define EMI_NONE 0xffffffff -#define EMI_MASK 0xf0000000 -#define EMI1_RGMII 0x0 -#define EMI1_SLOT3 0x80000000 /* bank1 EFGH */ -#define EMI1_SLOT4 0x40000000 /* bank2 ABCD */ -#define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */ -#define EMI2_SLOT4 0x10000000 /* bank2 ABCD */ -#define EMI2_SLOT5 0x30000000 /* bank3 ABCD */ -#define EMI1_MASK 0xc0000000 -#define EMI2_MASK 0x30000000 - -#define PHY_BASE_ADDR 0x00 -#define PHY_BASE_ADDR_SLOT5 0x10 - -static int mdio_mux[NUM_FM_PORTS]; - -static char *mdio_names[16] = { - "P4080DS_MDIO0", - "P4080DS_MDIO1", - NULL, - "P4080DS_MDIO3", - "P4080DS_MDIO4", - NULL, NULL, NULL, - "P4080DS_MDIO8", - NULL, NULL, NULL, - "P4080DS_MDIO12", - NULL, NULL, NULL, -}; - -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot. - */ -static u8 lane_to_slot[] = { - 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5 -}; - -static char *p4080ds_mdio_name_for_muxval(u32 muxval) -{ - return mdio_names[(muxval & EMI_MASK) >> 28]; -} - -struct mii_dev *mii_dev_for_muxval(u32 muxval) -{ - struct mii_dev *bus; - char *name = p4080ds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS) -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - if (phydev->drv->uid == PHY_UID_TN2020) { - unsigned long timeout = 1 * 1000; /* 1 seconds */ - enum srds_prtcl device; - - /* - * Wait for the XAUI to come out of reset. This is when it - * starts transmitting alignment signals. - */ - while (--timeout) { - int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1); - if (reg < 0) { - printf("TN2020: Error reading from PHY at " - "address %u\n", phydev->addr); - break; - } - /* - * Note that we've never actually seen - * MDIO_CTRL1_RESET set to 1. - */ - if ((reg & MDIO_CTRL1_RESET) == 0) - break; - udelay(1000); - } - - if (!timeout) { - printf("TN2020: Timeout waiting for PHY at address %u " - " to reset.\n", phydev->addr); - } - - switch (phydev->addr) { - case CONFIG_SYS_FM1_10GEC1_PHY_ADDR: - device = XAUI_FM1; - break; - case CONFIG_SYS_FM2_10GEC1_PHY_ADDR: - device = XAUI_FM2; - break; - default: - device = NONE; - } - - serdes_reset_rx(device); - } - - return 0; -} -#endif - -struct p4080ds_mdio { - u32 muxval; - struct mii_dev *realbus; -}; - -static void p4080ds_mux_mdio(u32 muxval) -{ - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK); - gpioval |= muxval; - - out_be32(&pgpio->gpdat, gpioval); -} - -static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct p4080ds_mdio *priv = bus->priv; - - p4080ds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct p4080ds_mdio *priv = bus->priv; - - p4080ds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int p4080ds_mdio_reset(struct mii_dev *bus) -{ - struct p4080ds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int p4080ds_mdio_init(char *realbusname, u32 muxval) -{ - struct p4080ds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate P4080DS MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate P4080DS private data\n"); - free(bus); - return -1; - } - - bus->read = p4080ds_mdio_read; - bus->write = p4080ds_mdio_write; - bus->reset = p4080ds_mdio_reset; - sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, - enum fm_port port, int offset) -{ - if (mdio_mux[port] == EMI1_RGMII) - fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); - - if (mdio_mux[port] == EMI1_SLOT3) { - int idx = port - FM2_DTSEC1 + 5; - char phy[16]; - - sprintf(phy, "phy%d_slot3", idx); - - fdt_set_phy_handle(blob, prop, pa, phy); - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - - /* - * P4080DS can be configured in many different ways, supporting a number - * of combinations of ethernet devices and phy types. In order to - * have just one device tree for all of those configurations, we fix up - * the tree here. By default, the device tree configures FM1 and FM2 - * for SGMII, and configures XAUI on both 10G interfaces. So we have - * a number of different variables to track: - * - * 1) Whether the device is configured at all. Whichever devices are - * not enabled should be disabled by setting the "status" property - * to "disabled". - * 2) What the PHY interface is. If this is an RGMII connection, - * we should change the "phy-connection-type" property to - * "rgmii" - * 3) Which PHY is being used. Because the MDIO buses are muxed, - * we need to redirect the "phy-handle" property to point at the - * PHY on the right slot/bus. - */ - - /* We've got six MDIO nodes that may or may not need to exist */ - fdt_status_disabled_by_alias(fdt, "emi1_slot3"); - fdt_status_disabled_by_alias(fdt, "emi1_slot4"); - fdt_status_disabled_by_alias(fdt, "emi1_slot5"); - fdt_status_disabled_by_alias(fdt, "emi2_slot4"); - fdt_status_disabled_by_alias(fdt, "emi2_slot5"); - - for (i = 0; i < NUM_FM_PORTS; i++) { - switch (mdio_mux[i]) { - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); - break; - case EMI1_SLOT5: - fdt_status_okay_by_alias(fdt, "emi1_slot5"); - break; - case EMI2_SLOT4: - fdt_status_okay_by_alias(fdt, "emi2_slot4"); - break; - case EMI2_SLOT5: - fdt_status_okay_by_alias(fdt, "emi2_slot5"); - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - int i; - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - struct mii_dev *bus; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - /* The first 4 GPIOs are outputs to control MDIO bus muxing */ - out_be32(&pgpio->gpdir, EMI_MASK); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* Register the 6 muxing front-ends to the MDIO buses */ - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4); - p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5); - - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); - -#if (CONFIG_SYS_NUM_FMAN == 2) - fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); -#endif - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI1_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fm_info_set_phy_address(i, 0); - mdio_mux[i] = EMI1_RGMII; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - bus = mii_dev_for_muxval(EMI1_SLOT5); - set_sgmii_phy(bus, FM1_DTSEC1, - CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5); - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { - int idx = i - FM1_10GEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(XAUI_FM1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 4: - mdio_mux[i] = EMI2_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI2_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - default: - break; - } - } - -#if (CONFIG_SYS_NUM_FMAN == 2) - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI1_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fm_info_set_phy_address(i, 0); - mdio_mux[i] = EMI1_RGMII; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - bus = mii_dev_for_muxval(EMI1_SLOT3); - set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR); - bus = mii_dev_for_muxval(EMI1_SLOT4); - set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR); - - for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { - int idx = i - FM2_10GEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(XAUI_FM2 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 4: - mdio_mux[i] = EMI2_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI2_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - default: - break; - } - } -#endif - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c deleted file mode 100644 index 55bac0f7615d..000000000000 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ /dev/null @@ -1,783 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * Author: Srikanth Srinivasan srikanth.srinivasan@freescale.com - */ - -/* - * This file handles the board muxing between the Fman Ethernet MACs and - * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference - * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are - * provided by the standard Freescale four-port SGMII riser card. The 10Gb - * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans - * and 5 1G interfaces and 10G interface per FMan. Based on the options in - * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time. - * - * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control - * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is - * always the same (0). The value for SGMII depends on which slot the riser is - * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, - * the value is based on which slot the XAUI is inserted in. - * - * The SERDES configuration is used to determine where the SGMII and XAUI cards - * exist, and also which Fman's MACs are routed to which PHYs. So for a given - * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed - * to PHYs dynamically. - * - * - * This file also updates the device tree in three ways: - * - * 1) The status of each virtual MDIO node that is referenced by an Ethernet - * node is set to "okay". - * - * 2) The phy-handle property of each active Ethernet MAC node is set to the - * appropriate PHY node. - * - * 3) The "mux value" for each virtual MDIO node is set to the correct value, - * if necessary. Some virtual MDIO nodes do not have configurable mux - * values, so those values are hard-coded in the DTS. On the HYDRA board, - * the virtual MDIO node for the SGMII card needs to be updated. - * - * For all this to work, the device tree needs to have the following: - * - * 1) An alias for each PHY node that an Ethernet node could be routed to. - * - * 2) An alias for each real and virtual MDIO node that is disabled by default - * and might need to be enabled, and also might need to have its mux-value - * updated. - */ - -#include <common.h> -#include <log.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fdt_support.h> -#include <fsl_dtsec.h> - -#include "../common/ngpixis.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET - -#define BRDCFG1_EMI1_SEL_MASK 0x70 -#define BRDCFG1_EMI1_SEL_SLOT1 0x10 -#define BRDCFG1_EMI1_SEL_SLOT2 0x20 -#define BRDCFG1_EMI1_SEL_SLOT5 0x30 -#define BRDCFG1_EMI1_SEL_SLOT6 0x40 -#define BRDCFG1_EMI1_SEL_SLOT7 0x50 -#define BRDCFG1_EMI1_SEL_SLOT3 0x60 -#define BRDCFG1_EMI1_SEL_RGMII 0x00 -#define BRDCFG1_EMI1_EN 0x08 -#define BRDCFG1_EMI2_SEL_MASK 0x06 -#define BRDCFG1_EMI2_SEL_SLOT1 0x00 -#define BRDCFG1_EMI2_SEL_SLOT2 0x02 - -#define BRDCFG2_REG_GPIO_SEL 0x20 - -/* SGMII */ -#define PHY_BASE_ADDR 0x00 -#define REGNUM 0x00 -#define PORT_NUM_FM1 0x04 -#define PORT_NUM_FM2 0x02 - -/* - * BRDCFG1 mask and value for each MAC - * - * This array contains the BRDCFG1 values (in mask/val format) that route the - * MDIO bus to a particular RGMII or SGMII PHY. - */ -static struct { - u8 mask; - u8 val; -} mdio_mux[NUM_FM_PORTS]; - -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0 -}; - -/* - * Set the board muxing for a given MAC - * - * The MDIO layer calls this function every time it wants to talk to a PHY. - */ -void super_hydra_mux_mdio(u8 mask, u8 val) -{ - clrsetbits_8(&pixis->brdcfg1, mask, val); -} - -struct super_hydra_mdio { - u8 mask; - u8 val; - struct mii_dev *realbus; -}; - -static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct super_hydra_mdio *priv = bus->priv; - - super_hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct super_hydra_mdio *priv = bus->priv; - - super_hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int super_hydra_mdio_reset(struct mii_dev *bus) -{ - struct super_hydra_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val) -{ - struct mii_dev *bus = miiphy_get_dev_by_name(name); - struct super_hydra_mdio *priv = bus->priv; - - priv->mask = mask; - priv->val = val; -} - -static int super_hydra_mdio_init(char *realbusname, char *fakebusname) -{ - struct super_hydra_mdio *hmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate Hydra MDIO bus\n"); - return -1; - } - - hmdio = malloc(sizeof(*hmdio)); - if (!hmdio) { - printf("Failed to allocate Hydra private data\n"); - free(bus); - return -1; - } - - bus->read = super_hydra_mdio_read; - bus->write = super_hydra_mdio_write; - bus->reset = super_hydra_mdio_reset; - strcpy(bus->name, fakebusname); - - hmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!hmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(hmdio); - return -1; - } - - bus->priv = hmdio; - - return mdio_register(bus); -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. That - * information is stored in mdio_mux[]. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - enum srds_prtcl device; - int lane, slot, phy; - char alias[32]; - - /* RGMII and XGMII are already mapped correctly in the DTS */ - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - device = serdes_device_from_fm_port(port); - lane = serdes_get_first_lane(device); - slot = lane_to_slot[lane]; - phy = fm_info_get_phy_address(port); - - sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - } -} - -#define PIXIS_SW2_LANE_23_SEL 0x80 -#define PIXIS_SW2_LANE_45_SEL 0x40 -#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 -#define PIXIS_SW2_LANE_67_SEL_5 0x00 -#define PIXIS_SW2_LANE_67_SEL_6 0x20 -#define PIXIS_SW2_LANE_67_SEL_7 0x10 -#define PIXIS_SW2_LANE_8_SEL 0x08 -#define PIXIS_SW2_LANE_1617_SEL 0x04 -#define PIXIS_SW11_LANE_9_SEL 0x04 -/* - * Initialize the lane_to_slot[] array. - * - * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board - * slots is hard-coded. On the Hydra board, however, the mapping is controlled - * by board switch SW2, so the lane_to_slot[] array needs to be dynamically - * initialized. - */ -static void initialize_lane_to_slot(void) -{ - u8 sw2 = in_8(&PIXIS_SW(2)); - /* SW11 appears in the programming model as SW9 */ - u8 sw11 = in_8(&PIXIS_SW(9)); - - lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; - lane_to_slot[3] = lane_to_slot[2]; - - lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; - lane_to_slot[5] = lane_to_slot[4]; - - switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { - case PIXIS_SW2_LANE_67_SEL_5: - lane_to_slot[6] = 5; - break; - case PIXIS_SW2_LANE_67_SEL_6: - lane_to_slot[6] = 6; - break; - case PIXIS_SW2_LANE_67_SEL_7: - lane_to_slot[6] = 7; - break; - } - lane_to_slot[7] = lane_to_slot[6]; - - lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; - lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3; - - lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; - lane_to_slot[17] = lane_to_slot[16]; -} - -#endif /* #ifdef CONFIG_FMAN_ENET */ - -/* - * Configure the status for the virtual MDIO nodes - * - * Rather than create the virtual MDIO nodes from scratch for each active - * virtual MDIO, we expect the DTS to have the nodes defined already, and we - * only enable the ones that are actually active. - * - * We assume that the DTS already hard-codes the status for all the - * virtual MDIO nodes to "disabled", so all we need to do is enable the - * active ones. - */ -void fdt_fixup_board_enet(void *fdt) -{ -#ifdef CONFIG_FMAN_ENET - enum fm_port i; - int lane, slot; - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_sg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", - alias, slot); - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fdt_status_okay_by_alias(fdt, "hydra_rg"); - debug("Enabled MDIO node hydra_rg\n"); - break; - default: - break; - } - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_xg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", alias, slot); - } - -#if CONFIG_SYS_NUM_FMAN == 2 - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_sg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", - alias, slot); - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - fdt_status_okay_by_alias(fdt, "hydra_rg"); - debug("Enabled MDIO node hydra_rg\n"); - break; - default: - break; - } - } - - lane = serdes_get_first_lane(XAUI_FM2); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_xg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", alias, slot); - } -#endif /* CONFIG_SYS_NUM_FMAN == 2 */ -#endif /* CONFIG_FMAN_ENET */ -} - -/* - * Mapping of SerDes Protocol to MDIO MUX value and PHY address. - * - * Fman 1: - * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 - * Mux Phy | Mux Phy | Mux Phy | Mux Phy - * Value Addr | Value Addr | Value Addr | Value Addr - * 0x00 2 1c | 2 1d | 2 1e | 2 1f - * 0x01 | | 6 1c | - * 0x02 | | 3 1c | 3 1d - * 0x03 2 1c | 2 1d | 2 1e | 2 1f - * 0x04 2 1c | 2 1d | 2 1e | 2 1f - * 0x05 | | 3 1c | 3 1d - * 0x06 2 1c | 2 1d | 2 1e | 2 1f - * 0x07 | | 6 1c | - * 0x11 2 1c | 2 1d | 2 1e | 2 1f - * 0x2a 2 | | 2 1e | 2 1f - * 0x34 6 1c | 6 1d | 4 1e | 4 1f - * 0x35 | | 3 1c | 3 1d - * 0x36 6 1c | 6 1d | 4 1e | 4 1f - * | | | - * Fman 2: | | | - * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 - * EMI1 | EMI1 | EMI1 | EMI1 - * Mux Phy | Mux Phy | Mux Phy | Mux Phy - * Value Addr | Value Addr | Value Addr | Value Addr - * 0x00 | | 6 1c | 6 1d - * 0x01 | | | - * 0x02 | | 6 1c | 6 1d - * 0x03 3 1c | 3 1d | 6 1c | 6 1d - * 0x04 3 1c | 3 1d | 6 1c | 6 1d - * 0x05 | | 6 1c | 6 1d - * 0x06 | | 6 1c | 6 1d - * 0x07 | | | - * 0x11 | | | - * 0x2a | | | - * 0x34 | | | - * 0x35 | | | - * 0x36 | | | - */ - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - struct mii_dev *bus; - int qsgmii; - int phy_real_addr; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int srds_prtcl = (in_be32(&gur->rcwsr[4]) & - FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ - setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); - - memset(mdio_mux, 0, sizeof(mdio_mux)); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* Register the three virtual MDIO front-ends */ - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_RGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_FM1_SGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_FM2_SGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_FM3_SGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, - "SUPER_HYDRA_FM1_TGEC_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, - "SUPER_HYDRA_FM2_TGEC_MDIO"); - - /* - * Program the DTSEC PHY addresses assuming that they are all SGMII. - * For any DTSEC that's RGMII, we'll override its PHY address later. - * We assume that DTSEC5 is only used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); - -#if (CONFIG_SYS_NUM_FMAN == 2) - fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); -#endif - - switch (srds_prtcl) { - case 0: - case 3: - case 4: - case 6: - case 0x11: - case 0x2a: - case 0x34: - case 0x36: - fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - break; - case 1: - case 2: - case 5: - case 7: - case 0x35: - fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - break; - default: - printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - switch (slot) { - case 1: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | - BRDCFG1_EMI1_EN; - break; - case 2: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | - BRDCFG1_EMI1_EN; - break; - case 3: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | - BRDCFG1_EMI1_EN; - break; - case 5: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | - BRDCFG1_EMI1_EN; - break; - case 6: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | - BRDCFG1_EMI1_EN; - break; - case 7: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | - BRDCFG1_EMI1_EN; - break; - }; - - super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* - * FM1 DTSEC5 is routed via EC1 to the first on-board - * RGMII port. FM2 DTSEC5 is routed via EC2 to the - * second on-board RGMII port. The other DTSECs cannot - * be routed to RGMII. - */ - debug("FM1@DTSEC%u is RGMII at address %u\n", - idx + 1, 0); - fm_info_set_phy_address(i, 0); - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | - BRDCFG1_EMI1_EN; - super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"); - qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM); - - if (qsgmii) { - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) { - if (fm_info_get_enet_if(i) == - PHY_INTERFACE_MODE_SGMII) { - phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1; - fm_info_set_phy_address(i, phy_real_addr); - } - } - switch (srds_prtcl) { - case 0x00: - case 0x03: - case 0x04: - case 0x06: - case 0x11: - case 0x2a: - case 0x34: - case 0x36: - fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2); - fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3); - break; - case 0x01: - case 0x02: - case 0x05: - case 0x07: - case 0x35: - fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0); - fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); - break; - default: - break; - } - } - - /* - * For 10G, we only support one XAUI card per Fman. If present, then we - * force its routing and never touch those bits again, which removes the - * need for Linux to do any muxing. This works because of the way - * BRDCFG1 is defined, but it's a bit hackish. - * - * The PHY address for the XAUI card depends on which slot it's in. The - * macros we use imply that the PHY address is based on which FM, but - * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, - * and FM2 could only use a XAUI in slot 4. On the Hydra board, we - * check the actual slot and just use the macros as-is, even though - * the P3041 and P5020 only have one Fman. - */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); - mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2; - super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); - -#if (CONFIG_SYS_NUM_FMAN == 2) - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - debug("FM2@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - switch (slot) { - case 1: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | - BRDCFG1_EMI1_EN; - break; - case 2: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | - BRDCFG1_EMI1_EN; - break; - case 3: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | - BRDCFG1_EMI1_EN; - break; - case 5: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | - BRDCFG1_EMI1_EN; - break; - case 6: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | - BRDCFG1_EMI1_EN; - break; - case 7: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | - BRDCFG1_EMI1_EN; - break; - }; - - if (i == FM2_DTSEC1 || i == FM2_DTSEC2) { - super_hydra_mdio_set_mux( - "SUPER_HYDRA_FM3_SGMII_MDIO", - mdio_mux[i].mask, - mdio_mux[i].val); - fm_info_set_mdio(i, miiphy_get_dev_by_name( - "SUPER_HYDRA_FM3_SGMII_MDIO")); - } else { - super_hydra_mdio_set_mux( - "SUPER_HYDRA_FM2_SGMII_MDIO", - mdio_mux[i].mask, - mdio_mux[i].val); - fm_info_set_mdio(i, miiphy_get_dev_by_name( - "SUPER_HYDRA_FM2_SGMII_MDIO")); - } - - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* - * FM1 DTSEC5 is routed via EC1 to the first on-board - * RGMII port. FM2 DTSEC5 is routed via EC2 to the - * second on-board RGMII port. The other DTSECs cannot - * be routed to RGMII. - */ - debug("FM2@DTSEC%u is RGMII at address %u\n", - idx + 1, 1); - fm_info_set_phy_address(i, 1); - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | - BRDCFG1_EMI1_EN; - super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman2: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO"); - set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR); - bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO"); - set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR); - - /* - * For 10G, we only support one XAUI card per Fman. If present, then we - * force its routing and never touch those bits again, which removes the - * need for Linux to do any muxing. This works because of the way - * BRDCFG1 is defined, but it's a bit hackish. - * - * The PHY address for the XAUI card depends on which slot it's in. The - * macros we use imply that the PHY address is based on which FM, but - * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, - * and FM2 could only use a XAUI in slot 4. On the Hydra board, we - * check the actual slot and just use the macros as-is, even though - * the P3041 and P5020 only have one Fman. - */ - lane = serdes_get_first_lane(XAUI_FM2); - if (lane >= 0) { - debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); - mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1; - super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - } - - fm_info_set_mdio(FM2_10GEC1, - miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); - -#endif - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c deleted file mode 100644 index c62d85ccc0e1..000000000000 --- a/board/freescale/corenet_ds/p3041ds_ddr.c +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c deleted file mode 100644 index 9839eaceaf95..000000000000 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> - -#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 -#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 -#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 -#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912 -#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40 -#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000 -#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100 -#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104 -#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944 -#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF -#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830 -#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000 -#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100 -#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104 -#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844 -#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce -#define CONFIG_SYS_DDR_MODE_1_900 0x00441620 -#define CONFIG_SYS_DDR_MODE_2_900 0x00080000 -#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100 -#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc -#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 -#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 -#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202 -#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 -#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 -#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {750, 850, &ddr_cfg_regs_800}, - {850, 950, &ddr_cfg_regs_900}, - {950, 1050, &ddr_cfg_regs_1000}, - {1050, 1250, &ddr_cfg_regs_1200}, - {0, 0, NULL} -}; - -fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {750, 850, &ddr_cfg_regs_800_2nd}, - {850, 950, &ddr_cfg_regs_900_2nd}, - {950, 1050, &ddr_cfg_regs_1000_2nd}, - {1050, 1250, &ddr_cfg_regs_1200_2nd}, - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c deleted file mode 100644 index 112733be781e..000000000000 --- a/board/freescale/corenet_ds/p5040ds_ddr.c +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {0, 0, NULL} -}; - -fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/rcw_p3041ds.cfg b/board/freescale/corenet_ds/rcw_p3041ds.cfg deleted file mode 100644 index 8813156219fc..000000000000 --- a/board/freescale/corenet_ds/rcw_p3041ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P3041DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -12600000 00000000 241C0000 00000000 -D8984A01 03002000 58000000 41000000 -00000000 00000000 00000000 10070000 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/rcw_p4080ds.cfg b/board/freescale/corenet_ds/rcw_p4080ds.cfg deleted file mode 100644 index 6a2633959984..000000000000 --- a/board/freescale/corenet_ds/rcw_p4080ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P4080DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -105a0000 00000000 1e1e181e 0000cccc -58400000 3c3c2000 58000000 e1000000 -00000000 00000000 00000000 008b6000 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/rcw_p5040ds.cfg b/board/freescale/corenet_ds/rcw_p5040ds.cfg deleted file mode 100644 index 82fa7417d9be..000000000000 --- a/board/freescale/corenet_ds/rcw_p5040ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P5040DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -0c580000 00000000 22121200 00000000 -089c4400 00283000 58000000 61000000 -00000000 00000000 00000000 10070000 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/p2041rdb/pbi.cfg similarity index 100% rename from board/freescale/corenet_ds/pbi.cfg rename to board/freescale/p2041rdb/pbi.cfg diff --git a/board/freescale/corenet_ds/rcw_p2041rdb.cfg b/board/freescale/p2041rdb/rcw_p2041rdb.cfg similarity index 100% rename from board/freescale/corenet_ds/rcw_p2041rdb.cfg rename to board/freescale/p2041rdb/rcw_p2041rdb.cfg diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 0e8c2aa00bc2..cc62719a89a0 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -21,8 +21,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg" CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 5b9f5a44690d..b0e4bb89639e 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -21,8 +21,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg" CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 0a061610c09a..517c7d25ed93 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -23,8 +23,8 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_RAMBOOT_PBL=y CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg" CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig deleted file mode 100644 index 7afb7a45ec85..000000000000 --- a/configs/P3041DS_NAND_defconfig +++ /dev/null @@ -1,113 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_DEFAULT_DEVICE_TREE="p3041ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_PCIE4=y -CONFIG_SYS_FSL_NUM_CC_PLLS=2 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xFFA00C21 -CONFIG_SYS_OR0_PRELIM=0xFFFC0796 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR2_PRELIM_BOOL=y -CONFIG_SYS_BR2_PRELIM=0xE8001001 -CONFIG_SYS_OR2_PRELIM=0xF8000F85 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_ELBC=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x100000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig deleted file mode 100644 index 35e2e4f161d9..000000000000 --- a/configs/P3041DS_SDCARD_defconfig +++ /dev/null @@ -1,108 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_DEFAULT_DEVICE_TREE="p3041ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_PCIE4=y -CONFIG_SYS_FSL_NUM_CC_PLLS=2 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0xD2000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig deleted file mode 100644 index 2e50dc44f788..000000000000 --- a/configs/P3041DS_SPIFLASH_defconfig +++ /dev/null @@ -1,110 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="p3041ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_PCIE4=y -CONFIG_SYS_FSL_NUM_CC_PLLS=2 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x110000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig deleted file mode 100644 index b494dfa82234..000000000000 --- a/configs/P3041DS_defconfig +++ /dev/null @@ -1,105 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="p3041ds" -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_PCIE4=y -CONFIG_SYS_FSL_NUM_CC_PLLS=2 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig deleted file mode 100644 index b8728788886b..000000000000 --- a/configs/P4080DS_SDCARD_defconfig +++ /dev/null @@ -1,105 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_DEFAULT_DEVICE_TREE="p4080ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P4080DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=4 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_LBA48=y -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0xD2000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig deleted file mode 100644 index cdd956b9f98d..000000000000 --- a/configs/P4080DS_SPIFLASH_defconfig +++ /dev/null @@ -1,107 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="p4080ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P4080DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=4 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_LBA48=y -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x110000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig deleted file mode 100644 index 6b22602e67c3..000000000000 --- a/configs/P4080DS_defconfig +++ /dev/null @@ -1,102 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="p4080ds" -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P4080DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=4 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_LBA48=y -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig deleted file mode 100644 index b36f525cc19c..000000000000 --- a/configs/P5040DS_NAND_defconfig +++ /dev/null @@ -1,113 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_DEFAULT_DEVICE_TREE="p5040ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=3 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xFFA00C21 -CONFIG_SYS_OR0_PRELIM=0xFFFC0796 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR2_PRELIM_BOOL=y -CONFIG_SYS_BR2_PRELIM=0xE8001001 -CONFIG_SYS_OR2_PRELIM=0xF8000F85 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_ELBC=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x100000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig deleted file mode 100644 index 4111901fc401..000000000000 --- a/configs/P5040DS_SDCARD_defconfig +++ /dev/null @@ -1,107 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_DEFAULT_DEVICE_TREE="p5040ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=3 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0xD2000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig deleted file mode 100644 index 5d493ee89c5e..000000000000 --- a/configs/P5040DS_SPIFLASH_defconfig +++ /dev/null @@ -1,109 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="p5040ds" -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=3 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x110000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig deleted file mode 100644 index dbcb02765d6c..000000000000 --- a/configs/P5040DS_defconfig +++ /dev/null @@ -1,104 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="p5040ds" -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=3 -CONFIG_MP=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_DM=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_SPD_BUS_NUM=1 -CONFIG_DDR_ECC=y -CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xE8001001 -CONFIG_SYS_OR0_PRELIM=0xF8000F85 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE0001001 -CONFIG_SYS_OR1_PRELIM=0xF8000FF7 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x57 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_SYS_MAX_FLASH_BANKS=2 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 -CONFIG_MII=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 diff --git a/doc/README.pblimage b/doc/README.pblimage index 7fdd26b71b2b..58202c14a285 100644 --- a/doc/README.pblimage +++ b/doc/README.pblimage @@ -61,7 +61,7 @@ Following steps describe it in detail. Board specific configuration file specifications: ------------------------------------------------ 1. Configuration files rcw.cfg and pbi.cfg must present in the -board/freescale/corenet_ds/, rcw.cfg is for RCW, pbi.cfg is for +board/freescale/<BOARD>/ directory, rcw.cfg is for RCW, pbi.cfg is for PBI instructions. File name must not be changed since they are used in Makefile. 2. These files can have empty lines and lines starting with "#" as first diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h deleted file mode 100644 index 42e507bac0bb..000000000000 --- a/include/configs/P3041DS.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -/* - * P3041 DS board configuration file - * - */ -#define CONFIG_SYS_DPAA_RMAN - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h deleted file mode 100644 index fd558398e4a1..000000000000 --- a/include/configs/P4080DS.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * P4080 DS board configuration file - * Also supports P4040 DS - */ - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h deleted file mode 100644 index c8fc879d2f88..000000000000 --- a/include/configs/P5040DS.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * P5040 DS board configuration file - * - */ - -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h"

-- 2.25.1

Tom Rini

4:16 p.m.

New subject: [PATCHv2 12b/21] layerscape: Disable CONFIG_FMAN_ENET on *aqds* platforms

The *aqds* platforms have not been migrated to be able to enable CONFIG_DM_ETH with CONFIG_FMAN_ENET. Disable CONFIG_FMAN_ENET on these platforms.

Cc: Mingkai Hu mingkai.hu@nxp.com Cc: Rajesh Bhagat rajesh.bhagat@nxp.com Cc: Pramod Kumar pramod.kumar_1@nxp.com Cc: Peng Fan peng.fan@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- Changes in v2: - Depend on patch to delete corenet_ds platforms - Only disable on *aqds* after it was noted that the other layerscape platforms had been migrated. --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- board/freescale/ls1043aqds/eth.c | 10 ++++++---- board/freescale/ls1043aqds/ls1043aqds.c | 5 +---- board/freescale/ls1046aqds/eth.c | 10 ++++++---- board/freescale/ls1046aqds/ls1046aqds.c | 5 +---- configs/ls1043aqds_defconfig | 1 - configs/ls1043aqds_lpuart_defconfig | 1 - configs/ls1043aqds_nand_defconfig | 1 - configs/ls1043aqds_nor_ddr3_defconfig | 1 - configs/ls1043aqds_qspi_defconfig | 1 - configs/ls1043aqds_sdcard_ifc_defconfig | 1 - configs/ls1043aqds_sdcard_qspi_defconfig | 1 - configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1043aqds_tfa_defconfig | 1 - configs/ls1046aqds_SECURE_BOOT_defconfig | 1 - configs/ls1046aqds_defconfig | 1 - configs/ls1046aqds_lpuart_defconfig | 1 - configs/ls1046aqds_nand_defconfig | 1 - configs/ls1046aqds_qspi_defconfig | 1 - configs/ls1046aqds_sdcard_ifc_defconfig | 1 - configs/ls1046aqds_sdcard_qspi_defconfig | 1 - configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1046aqds_tfa_defconfig | 1 - 23 files changed, 15 insertions(+), 35 deletions(-)

-#ifdef CONFIG_SYS_DPAA_FMAN +#ifdef CONFIG_FMAN_ENET fdt_fixup_fman_firmware(blob); #endif #ifdef CONFIG_FSL_PFE diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index e156ba010451..7bfbacde4fbd 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -30,8 +30,6 @@ #define EMI1_SLOT4 5 #define EMI2 6

-static int mdio_mux[NUM_FM_PORTS]; - static const char * const mdio_names[] = { "LS1043AQDS_MDIO_RGMII1", "LS1043AQDS_MDIO_RGMII2", @@ -43,7 +41,11 @@ static const char * const mdio_names[] = { };

/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ +#ifdef CONFIG_FMAN_ENET +static int mdio_mux[NUM_FM_PORTS]; + static u8 lane_to_slot[] = {1, 2, 3, 4}; +#endif

static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) { @@ -75,6 +77,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; }

+#ifdef CONFIG_FMAN_ENET struct ls1043aqds_mdio { u8 muxval; struct mii_dev *realbus; @@ -296,7 +299,6 @@ void fdt_fixup_board_enet(void *fdt)

cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */

-#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif +#ifdef CONFIG_FMAN_ENET fdt_fixup_board_enet(blob); #endif

-static int mdio_mux[NUM_FM_PORTS]; - static const char * const mdio_names[] = { "LS1046AQDS_MDIO_RGMII1", "LS1046AQDS_MDIO_RGMII2", @@ -39,7 +37,11 @@ static const char * const mdio_names[] = { };

/* Map SerDes 1 & 2 lanes to default slot. */ +#ifdef CONFIG_FMAN_ENET +static int mdio_mux[NUM_FM_PORTS]; + static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0}; +#endif

static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval) { @@ -71,6 +73,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; }

+#ifdef CONFIG_FMAN_ENET struct ls1046aqds_mdio { u8 muxval; struct mii_dev *realbus; @@ -263,7 +266,6 @@ void fdt_fixup_board_enet(void *fdt)

cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */

-#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif +#ifdef CONFIG_FMAN_ENET fdt_fixup_board_enet(blob); #endif

diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index d7ff7e2970fb..ea95a68be259 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -95,7 +95,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 462fad1cd48f..84f65780077d 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -95,7 +95,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 63287ca533b3..1b49f53abed9 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -125,7 +125,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index fc72f4cdaf64..6a04b063aa83 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -96,7 +96,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 30cc15a12f3d..0ef4fe3db379 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -85,7 +85,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 172ab723c61b..cf9fd13777c6 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -122,7 +122,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 447a51513fe3..cacd85e4cf5c 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -110,7 +110,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index b414d400e6a1..e05746454495 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -94,7 +94,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 9bac24a27b30..c67876b9520d 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -103,7 +103,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 3a71185b865a..7a0b786be75d 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -93,7 +93,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 35abfb323f65..d582f61d4eee 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -96,7 +96,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 5316c80c83d2..9731b85b0c4d 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -96,7 +96,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x60900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 8550190d2295..bd58d3a90f74 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -124,7 +124,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 049cf1e56f98..0dca44a8b0bd 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -86,7 +86,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x40900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 6cdc78da3f0f..d023f534210c 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -124,7 +124,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 68aae882a807..aed01d44f1c4 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -112,7 +112,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 7efa5cbebd07..e8676e2ca1ea 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -94,7 +94,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 3846b95e71d5..8faeeb4773ea 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -104,7 +104,6 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_E1000=y -CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y

-- 2.25.1

Tom Rini

21 Aug 21 Aug

4:43 a.m.

New subject: [PATCHv2 12b/21] layerscape: Disable CONFIG_FMAN_ENET on *aqds* platforms

On Tue, Aug 09, 2022 at 10:16:22AM -0400, Tom Rini wrote:

...

The *aqds* platforms have not been migrated to be able to enable CONFIG_DM_ETH with CONFIG_FMAN_ENET. Disable CONFIG_FMAN_ENET on these platforms.

Cc: Mingkai Hu mingkai.hu@nxp.com Cc: Rajesh Bhagat rajesh.bhagat@nxp.com Cc: Pramod Kumar pramod.kumar_1@nxp.com Cc: Peng Fan peng.fan@nxp.com Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

4:43 a.m.

New subject: [PATCHv2 12a/21] ppc: Remove corenet_ds boards

On Tue, Aug 09, 2022 at 10:16:21AM -0400, Tom Rini wrote:

...

These boards have been orphaned for some time and are behind on various DM migrations. Remove them.

Cc: Priyanka Jain priyanka.jain@nxp.com Cc: Peng Fan peng.fan@nxp.com Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 13/21] mpc8548cds: Guard old ethernet code with !DM_ETH

There is some code here for the legacy non-DM_ETH case, add a guard around it.

Cc: Priyanka Jain priyanka.jain@nxp.com Cc: Peng Fan peng.fan@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- board/freescale/mpc8548cds/mpc8548cds.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index cfb5b0b38bbe..5cb16b5082b5 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -168,7 +168,8 @@ void lbc_sdram_init(void) #endif /* enable SDRAM init */ }

-void configure_rgmii(void) +#ifndef CONFIG_DM_ETH +static void configure_rgmii(void) { unsigned short temp;

@@ -247,3 +248,4 @@ int board_eth_init(struct bd_info *bis)

return pci_eth_init(bis); } +#endif

-- 2.25.1

Tom Rini

21 Aug 21 Aug

4:42 a.m.

New subject: [PATCH 13/21] mpc8548cds: Guard old ethernet code with !DM_ETH

On Tue, Aug 02, 2022 at 07:33:39AM -0400, Tom Rini wrote:

...

There is some code here for the legacy non-DM_ETH case, add a guard around it.

Cc: Priyanka Jain priyanka.jain@nxp.com Cc: Peng Fan peng.fan@nxp.com Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 14/21] net: ks8851_mll: Remove legacy non-DM_ETH code and callers

As this driver has been converted to DM_ETH and the migration deadline is 2 years passed, remove the legacy code and callers.

Cc: Eugen Hristev eugen.hristev@microchip.com Signed-off-by: Tom Rini trini@konsulko.com --- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 35 ----------- drivers/net/ks8851_mll.c | 75 ----------------------- 2 files changed, 110 deletions(-)

diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 018fed9cc2ae..a337db4efc68 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -135,30 +135,6 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_LCD */

-#ifdef CONFIG_KS8851_MLL -void at91sam9n12ek_ks8851_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - - writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[2].setup); - writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | - AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7), - &smc->cs[2].pulse); - writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9), - &smc->cs[2].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | - AT91_SMC_MODE_TDF_CYCLE(1), - &smc->cs[2].mode); - - /* Configure NCS2 PIN */ - at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0); -} -#endif - #ifdef CONFIG_USB_ATMEL void at91sam9n12ek_usb_hw_init(void) { @@ -193,10 +169,6 @@ int board_init(void) at91_lcd_hw_init(); #endif

-#ifdef CONFIG_KS8851_MLL - at91sam9n12ek_ks8851_hw_init(); -#endif - #ifdef CONFIG_USB_ATMEL at91sam9n12ek_usb_hw_init(); #endif @@ -204,13 +176,6 @@ int board_init(void) return 0; }

-#ifdef CONFIG_KS8851_MLL -int board_eth_init(struct bd_info *bis) -{ - return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR); -} -#endif - int dram_init(void) { gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c index 9dd9b33955ae..518548e3bbcd 100644 --- a/drivers/net/ks8851_mll.c +++ b/drivers/net/ks8851_mll.c @@ -28,9 +28,6 @@ * @extra_byte : number of extra byte prepended rx pkt. */ struct ks_net { -#ifndef CONFIG_DM_ETH - struct eth_device dev; -#endif phys_addr_t iobase; int bus_width; u16 sharedbus; @@ -505,77 +502,6 @@ static void ks8851_mll_write_hwaddr_common(struct ks_net *ks, u8 enetaddr[6]) ks_wrreg16(ks, KS_MARL, addrl); }

-#ifndef CONFIG_DM_ETH -static int ks8851_mll_init(struct eth_device *dev, struct bd_info *bd) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - - return ks8851_mll_init_common(ks); -} - -static void ks8851_mll_halt(struct eth_device *dev) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - - ks8851_mll_halt_common(ks); -} - -static int ks8851_mll_send(struct eth_device *dev, void *packet, int length) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - - return ks8851_mll_send_common(ks, packet, length); -} - -static int ks8851_mll_recv(struct eth_device *dev) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - int ret; - - ret = ks8851_mll_recv_common(ks, net_rx_packets[0]); - if (ret) - net_process_received_packet(net_rx_packets[0], ret); - - return ret; -} - -static int ks8851_mll_write_hwaddr(struct eth_device *dev) -{ - struct ks_net *ks = container_of(dev, struct ks_net, dev); - - ks8851_mll_write_hwaddr_common(ks, ks->dev.enetaddr); - - return 0; -} - -int ks8851_mll_initialize(u8 dev_num, int base_addr) -{ - struct ks_net *ks; - - ks = calloc(1, sizeof(*ks)); - if (!ks) - return -ENOMEM; - - ks->iobase = base_addr; - - /* Try to detect chip. Will fail if not present. */ - if (ks8851_mll_detect_chip(ks)) { - free(ks); - return -1; - } - - ks->dev.init = ks8851_mll_init; - ks->dev.halt = ks8851_mll_halt; - ks->dev.send = ks8851_mll_send; - ks->dev.recv = ks8851_mll_recv; - ks->dev.write_hwaddr = ks8851_mll_write_hwaddr; - sprintf(ks->dev.name, "%s-%hu", DRIVERNAME, dev_num); - - eth_register(&ks->dev); - - return 0; -} -#else /* ifdef CONFIG_DM_ETH */ static int ks8851_start(struct udevice *dev) { struct ks_net *ks = dev_get_priv(dev); @@ -703,4 +629,3 @@ U_BOOT_DRIVER(ks8851) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif

-- 2.25.1

Ramon Fried

6 Aug 6 Aug

7:47 p.m.

New subject: [PATCH 14/21] net: ks8851_mll: Remove legacy non-DM_ETH code and callers

On Tue, Aug 2, 2022 at 2:37 PM Tom Rini trini@konsulko.com wrote:

...

As this driver has been converted to DM_ETH and the migration deadline is 2 years passed, remove the legacy code and callers.

Cc: Eugen Hristev eugen.hristev@microchip.com Signed-off-by: Tom Rini trini@konsulko.com

board/atmel/at91sam9n12ek/at91sam9n12ek.c | 35 ----------- drivers/net/ks8851_mll.c | 75 ----------------------- 2 files changed, 110 deletions(-)

diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 018fed9cc2ae..a337db4efc68 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -135,30 +135,6 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_LCD */

-#ifdef CONFIG_KS8851_MLL -void at91sam9n12ek_ks8851_hw_init(void) -{
  struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
         AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
         &smc->cs[2].setup);
  writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
         AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
         &smc->cs[2].pulse);
  writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
         &smc->cs[2].cycle);
  writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
         AT91_SMC_MODE_EXNW_DISABLE |
         AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
         AT91_SMC_MODE_TDF_CYCLE(1),
         &smc->cs[2].mode);
  /* Configure NCS2 PIN */
  at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0);
-} -#endif

#ifdef CONFIG_USB_ATMEL void at91sam9n12ek_usb_hw_init(void) { @@ -193,10 +169,6 @@ int board_init(void) at91_lcd_hw_init(); #endif

-#ifdef CONFIG_KS8851_MLL
  at91sam9n12ek_ks8851_hw_init();
-#endif

#ifdef CONFIG_USB_ATMEL at91sam9n12ek_usb_hw_init(); #endif @@ -204,13 +176,6 @@ int board_init(void) return 0; }

-#ifdef CONFIG_KS8851_MLL -int board_eth_init(struct bd_info *bis) -{
  return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
-} -#endif

int dram_init(void) { gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c index 9dd9b33955ae..518548e3bbcd 100644 --- a/drivers/net/ks8851_mll.c +++ b/drivers/net/ks8851_mll.c @@ -28,9 +28,6 @@

@extra_byte : number of extra byte prepended rx pkt.

*/ struct ks_net { -#ifndef CONFIG_DM_ETH
  struct eth_device       dev;
-#endif phys_addr_t iobase; int bus_width; u16 sharedbus; @@ -505,77 +502,6 @@ static void ks8851_mll_write_hwaddr_common(struct ks_net *ks, u8 enetaddr[6]) ks_wrreg16(ks, KS_MARL, addrl); }

-#ifndef CONFIG_DM_ETH -static int ks8851_mll_init(struct eth_device *dev, struct bd_info *bd) -{
  struct ks_net *ks = container_of(dev, struct ks_net, dev);
  return ks8851_mll_init_common(ks);
-}

-static void ks8851_mll_halt(struct eth_device *dev) -{
  struct ks_net *ks = container_of(dev, struct ks_net, dev);
  ks8851_mll_halt_common(ks);
-}

-static int ks8851_mll_send(struct eth_device *dev, void *packet, int length) -{
  struct ks_net *ks = container_of(dev, struct ks_net, dev);
  return ks8851_mll_send_common(ks, packet, length);
-}

-static int ks8851_mll_recv(struct eth_device *dev) -{
  struct ks_net *ks = container_of(dev, struct ks_net, dev);
  int ret;
  ret = ks8851_mll_recv_common(ks, net_rx_packets[0]);
  if (ret)
          net_process_received_packet(net_rx_packets[0], ret);
  return ret;
-}

-static int ks8851_mll_write_hwaddr(struct eth_device *dev) -{
  struct ks_net *ks = container_of(dev, struct ks_net, dev);
  ks8851_mll_write_hwaddr_common(ks, ks->dev.enetaddr);
  return 0;
-}

-int ks8851_mll_initialize(u8 dev_num, int base_addr) -{
  struct ks_net *ks;
  ks = calloc(1, sizeof(*ks));
  if (!ks)
          return -ENOMEM;
  ks->iobase = base_addr;
  /* Try to detect chip. Will fail if not present. */
  if (ks8851_mll_detect_chip(ks)) {
          free(ks);
          return -1;
  }
  ks->dev.init = ks8851_mll_init;
  ks->dev.halt = ks8851_mll_halt;
  ks->dev.send = ks8851_mll_send;
  ks->dev.recv = ks8851_mll_recv;
  ks->dev.write_hwaddr = ks8851_mll_write_hwaddr;
  sprintf(ks->dev.name, "%s-%hu", DRIVERNAME, dev_num);
  eth_register(&ks->dev);
  return 0;
-} -#else /* ifdef CONFIG_DM_ETH */ static int ks8851_start(struct udevice *dev) { struct ks_net *ks = dev_get_priv(dev); @@ -703,4 +629,3 @@ U_BOOT_DRIVER(ks8851) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, };

-#endif

2.25.1

Acked-by: Ramon Fried rfried.dev@gmail.com

Tom Rini

21 Aug 21 Aug

4:42 a.m.

New subject: [PATCH 14/21] net: ks8851_mll: Remove legacy non-DM_ETH code and callers

On Tue, Aug 02, 2022 at 07:33:40AM -0400, Tom Rini wrote:

...

As this driver has been converted to DM_ETH and the migration deadline is 2 years passed, remove the legacy code and callers.

Cc: Eugen Hristev eugen.hristev@microchip.com Signed-off-by: Tom Rini trini@konsulko.com Acked-by: Ramon Fried rfried.dev@gmail.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 15/21] igep00x0: Disable networking

This platform needs to be converted to use DM_ETH as the deadline is 2 years passed due. Disable networking support for now.

Cc: Enric Balletbo i Serra eballetbo@gmail.com Signed-off-by: Tom Rini trini@konsulko.com --- board/isee/igep00x0/igep00x0.c | 58 ---------------------------------- configs/igep00x0_defconfig | 5 +-- 2 files changed, 1 insertion(+), 62 deletions(-)

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 0932f62b9beb..6c5e6fbbcb0d 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -88,62 +88,6 @@ int onenand_board_init(struct mtd_info *mtd) return 1; }

-#if defined(CONFIG_CMD_NET) -static void reset_net_chip(int gpio) -{ - if (!gpio_request(gpio, "eth nrst")) { - gpio_direction_output(gpio, 1); - udelay(1); - gpio_set_value(gpio, 0); - udelay(40); - gpio_set_value(gpio, 1); - mdelay(10); - } -} - -/* - * Routine: setup_net_chip - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void setup_net_chip(void) -{ - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - static const u32 gpmc_lan_config[] = { - NET_LAN9221_GPMC_CONFIG1, - NET_LAN9221_GPMC_CONFIG2, - NET_LAN9221_GPMC_CONFIG3, - NET_LAN9221_GPMC_CONFIG4, - NET_LAN9221_GPMC_CONFIG5, - NET_LAN9221_GPMC_CONFIG6, - }; - - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], - CONFIG_SMC911X_BASE, GPMC_SIZE_16M); - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); - - reset_net_chip(64); -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_SMC911X - return smc911x_initialize(0, CONFIG_SMC911X_BASE); -#else - return 0; -#endif -} -#else -static inline void setup_net_chip(void) {} -#endif - #ifdef CONFIG_OF_BOARD_SETUP static int ft_enable_by_compatible(void *blob, char *compat, int enable) { @@ -234,8 +178,6 @@ int misc_init_r(void) OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, OMAP34XX_CTRL_WKUP_CTRL);

- setup_net_chip(); - omap_die_id_display();

set_led(); diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index 17c97ac27f79..25eda11dd45e 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -67,7 +67,7 @@ CONFIG_ENV_UBI_VOLUME="config" CONFIG_ENV_UBI_VOLUME_REDUND="config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y -CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_NET is not set CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y @@ -81,9 +81,6 @@ CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_MTD_UBI_FASTMAP=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x2C000000 -CONFIG_SMC911X_32_BIT=y CONFIG_CONS_INDEX=3 CONFIG_SPI=y CONFIG_DM_SPI=y

-- 2.25.1

Tom Rini

21 Aug 21 Aug

4:43 a.m.

New subject: [PATCH 15/21] igep00x0: Disable networking

On Tue, Aug 02, 2022 at 07:33:41AM -0400, Tom Rini wrote:

...

This platform needs to be converted to use DM_ETH as the deadline is 2 years passed due. Disable networking support for now.

Cc: Enric Balletbo i Serra eballetbo@gmail.com Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Ladislav Michl

28 Sep 28 Sep

7:53 p.m.

New subject: [PATCH 15/21] igep00x0: Disable networking

On Tue, Aug 02, 2022 at 07:33:41AM -0400, Tom Rini wrote:

...

This platform needs to be converted to use DM_ETH as the deadline is 2 years passed due. Disable networking support for now.

Oh well, my bad. There are too many patches accumulated. Please see bellow for original version for reference (applied after this one is reverted) Alternatively I can rebase on current master, just let me know whichever way you prefer.

ladis

...

Cc: Enric Balletbo i Serra <eballetbo at gmail.com> Signed-off-by: Tom Rini <trini at konsulko.com>

board/isee/igep00x0/igep00x0.c | 58 ---------------------------------- configs/igep00x0_defconfig | 5 +-- 2 files changed, 1 insertion(+), 62 deletions(-)

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 0932f62b9beb..6c5e6fbbcb0d 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -88,62 +88,6 @@ int onenand_board_init(struct mtd_info *mtd) return 1; }

-#if defined(CONFIG_CMD_NET) -static void reset_net_chip(int gpio) -{
if (!gpio_request(gpio, "eth nrst")) {
gpio_direction_output(gpio, 1);
udelay(1);
gpio_set_value(gpio, 0);
udelay(40);
gpio_set_value(gpio, 1);
mdelay(10);
}
-}

-/*
Routine: setup_net_chip

Description: Setting up the configuration GPMC registers specific to the
Ethernet hardware.
*/
-static void setup_net_chip(void) -{
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;

static const u32 gpmc_lan_config[] = {
NET_LAN9221_GPMC_CONFIG1,
NET_LAN9221_GPMC_CONFIG2,
NET_LAN9221_GPMC_CONFIG3,
NET_LAN9221_GPMC_CONFIG4,
NET_LAN9221_GPMC_CONFIG5,
NET_LAN9221_GPMC_CONFIG6,
};

enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
	CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */

writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);

/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */

writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);

/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */

writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
&ctrl_base->gpmc_nadv_ale);
reset_net_chip(64);
-}

-int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_SMC911X

return smc911x_initialize(0, CONFIG_SMC911X_BASE);

-#else

return 0;

-#endif -} -#else -static inline void setup_net_chip(void) {} -#endif

#ifdef CONFIG_OF_BOARD_SETUP static int ft_enable_by_compatible(void *blob, char *compat, int enable) { @@ -234,8 +178,6 @@ int misc_init_r(void) OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, OMAP34XX_CTRL_WKUP_CTRL);

setup_net_chip();

omap_die_id_display();

set_led();

diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index 17c97ac27f79..25eda11dd45e 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -67,7 +67,7 @@ CONFIG_ENV_UBI_VOLUME="config" CONFIG_ENV_UBI_VOLUME_REDUND="config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y -CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_NET is not set CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y @@ -81,9 +81,6 @@ CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_MTD_UBI_FASTMAP=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x2C000000 -CONFIG_SMC911X_32_BIT=y CONFIG_CONS_INDEX=3 CONFIG_SPI=y CONFIG_DM_SPI=y -- 2.25.1

From: Ladislav Michl ladis@linux-mips.org Date: Tue, 5 Apr 2022 15:47:45 +0200 Subject: [PATCH] ARM: igep00x0: convert to DM_ETH

The GPMC bus hasn't been converted, so omap3-igep0020-u-boot.dtsi needs to provide the address of the ethernet controller.

Signed-off-by: Ladislav Michl ladis@linux-mips.org --- arch/arm/dts/omap3-igep0020-u-boot.dtsi | 12 ++++++++++++ board/isee/igep00x0/igep00x0.c | 12 +----------- configs/igep00x0_defconfig | 2 +- 3 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/arch/arm/dts/omap3-igep0020-u-boot.dtsi b/arch/arm/dts/omap3-igep0020-u-boot.dtsi index 41beaf0900..d418b6a79f 100644 --- a/arch/arm/dts/omap3-igep0020-u-boot.dtsi +++ b/arch/arm/dts/omap3-igep0020-u-boot.dtsi @@ -9,6 +9,18 @@ chosen { stdout-path = &uart3; }; + + ethernet@2c000000 { + compatible = "smsc,lan9221","smsc,lan9115"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2c000000 0xff>; + bank-width = <2>; + vddvario-supply = <&vddvario>; + vdd33a-supply = <&vdd33a>; + reg-io-width = <4>; + smsc,save-mac-address; + }; };

&uart1 { diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 0932f62b9b..b48acf9d9b 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -12,7 +12,6 @@ #include <dm.h> #include <ns16550.h> #include <twl4030.h> -#include <netdev.h> #include <spl.h> #include <asm/gpio.h> #include <asm/io.h> @@ -119,7 +118,7 @@ static void setup_net_chip(void) };

enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], - CONFIG_SMC911X_BASE, GPMC_SIZE_16M); + 0x2C000000, GPMC_SIZE_16M);

/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); @@ -131,15 +130,6 @@ static void setup_net_chip(void)

reset_net_chip(64); } - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_SMC911X - return smc911x_initialize(0, CONFIG_SMC911X_BASE); -#else - return 0; -#endif -} #else static inline void setup_net_chip(void) {} #endif diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index f0d6ac56b6..9f895113d9 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -70,8 +70,8 @@ CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_MTD_UBI_FASTMAP=y +CONFIG_DM_ETH=y CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x2C000000 CONFIG_SMC911X_32_BIT=y CONFIG_CONS_INDEX=3 CONFIG_SPI=y

-- 2.32.0

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 16/21] am335x_sl50: Disable SPL_NET

Now that we are about to enable DM_ETH by default, disable SPL_NET as SPL_DM is not enabled currently.

Cc: Enric Balletbo i Serra eballetbo@gmail.com Signed-off-by: Tom Rini trini@konsulko.com --- configs/am335x_sl50_defconfig | 2 -- 1 file changed, 2 deletions(-)

diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 22f5b632d6d2..65b20550c0c6 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -32,8 +32,6 @@ CONFIG_SPL_MTD_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NET=y -CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" CONFIG_SPL_OS_BOOT=y CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700

-- 2.25.1

Tom Rini

21 Aug 21 Aug

4:43 a.m.

New subject: [PATCH 16/21] am335x_sl50: Disable SPL_NET

On Tue, Aug 02, 2022 at 07:33:42AM -0400, Tom Rini wrote:

...

Now that we are about to enable DM_ETH by default, disable SPL_NET as SPL_DM is not enabled currently.

Cc: Enric Balletbo i Serra eballetbo@gmail.com Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

4:43 a.m.

New subject: [PATCH 16/21] am335x_sl50: Disable SPL_NET

On Tue, Aug 02, 2022 at 07:33:42AM -0400, Tom Rini wrote:

...

Now that we are about to enable DM_ETH by default, disable SPL_NET as SPL_DM is not enabled currently.

Cc: Enric Balletbo i Serra eballetbo@gmail.com Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 17/21] ls1021aqds/ls1021aiot: Remove legacy non-DM_ETH code

Now that we are about to enable DM_ETH by default, remove legacy code.

Cc: Alison Wang alison.wang@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- board/freescale/common/Makefile | 1 - board/freescale/common/sgmii_riser.c | 130 ----------------- board/freescale/ls1021aiot/ls1021aiot.c | 38 ----- board/freescale/ls1021aqds/Makefile | 1 - board/freescale/ls1021aqds/eth.c | 186 ------------------------ include/configs/ls1021aqds.h | 8 - 6 files changed, 364 deletions(-) delete mode 100644 board/freescale/common/sgmii_riser.c delete mode 100644 board/freescale/ls1021aqds/eth.c

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 7c93d30e1d2a..377c6aa077dc 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -41,7 +41,6 @@ obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o endif -obj-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o ifndef CONFIG_RAMBOOT_PBL obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o endif diff --git a/board/freescale/common/sgmii_riser.c b/board/freescale/common/sgmii_riser.c deleted file mode 100644 index 23157930101f..000000000000 --- a/board/freescale/common/sgmii_riser.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Freescale SGMII Riser Card - * - * This driver supports the SGMII Riser card found on the - * "DS" style of development board from Freescale. - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * Copyright 2008 Freescale Semiconductor, Inc. - * - */ - -#include <config.h> -#include <common.h> -#include <log.h> -#include <net.h> -#include <linux/libfdt.h> -#include <tsec.h> -#include <fdt_support.h> - -void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num) -{ - int i; - - for (i = 0; i < num; i++) - if (tsec_info[i].flags & TSEC_SGMII) - tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET; -} - -void fsl_sgmii_riser_fdt_fixup(void *fdt) -{ - struct eth_device *dev; - int node; - int mdio_node; - int i = -1; - int etsec_num = 0; - - node = fdt_path_offset(fdt, "/aliases"); - if (node < 0) - return; - - while ((dev = eth_get_dev_by_index(++i)) != NULL) { - struct tsec_private *priv; - int phy_node; - int enet_node; - uint32_t ph; - char sgmii_phy[16]; - char enet[16]; - const u32 *phyh; - const char *model; - const char *path; - - if (!strstr(dev->name, "eTSEC")) - continue; - - priv = dev->priv; - if (!(priv->flags & TSEC_SGMII)) { - etsec_num++; - continue; - } - - mdio_node = fdt_node_offset_by_compatible(fdt, -1, - "fsl,gianfar-mdio"); - if (mdio_node < 0) - return; - - sprintf(sgmii_phy, "sgmii-phy@%d", etsec_num); - phy_node = fdt_subnode_offset(fdt, mdio_node, sgmii_phy); - if (phy_node > 0) { - fdt_increase_size(fdt, 32); - ph = fdt_create_phandle(fdt, phy_node); - if (!ph) - continue; - } - - sprintf(enet, "ethernet%d", etsec_num++); - path = fdt_getprop(fdt, node, enet, NULL); - if (!path) { - debug("No alias for %s\n", enet); - continue; - } - - enet_node = fdt_path_offset(fdt, path); - if (enet_node < 0) - continue; - - model = fdt_getprop(fdt, enet_node, "model", NULL); - - /* - * We only want to do this to eTSECs. On some platforms - * there are more than one type of gianfar-style ethernet - * controller, and as we are creating an implicit connection - * between ethernet nodes and eTSEC devices, it is best to - * make the connection use as much explicit information - * as exists. - */ - if (!strstr(model, "TSEC")) - continue; - - if (phy_node < 0) { - /* - * This part is only for old device tree without - * sgmii_phy nodes. It's kept just for compatible - * reason. Soon to be deprecated if all device tree - * get updated. - */ - phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL); - if (!phyh) - continue; - - phy_node = fdt_node_offset_by_phandle(fdt, - fdt32_to_cpu(*phyh)); - - priv = dev->priv; - - if (priv->flags & TSEC_SGMII) - fdt_setprop_cell(fdt, phy_node, "reg", - priv->phyaddr); - } else { - fdt_setprop(fdt, enet_node, "phy-handle", &ph, - sizeof(ph)); - fdt_setprop_string(fdt, enet_node, - "phy-connection-type", - phy_string_for_interface( - PHY_INTERFACE_MODE_SGMII)); - } - } -} diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index 5ab03b334041..3ed6100b7cf0 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -109,44 +109,6 @@ int dram_init(void) return 0; }

-#ifdef CONFIG_TSEC_ENET -int board_eth_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - puts("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} -#endif - int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index 65030342be3c..8cbf33fa0cef 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -6,5 +6,4 @@

obj-y += ls1021aqds.o obj-y += ddr.o -obj-y += eth.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/eth.c b/board/freescale/ls1021aqds/eth.c deleted file mode 100644 index a9f162b974d4..000000000000 --- a/board/freescale/ls1021aqds/eth.c +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * This file handles the board muxing between the RGMII/SGMII PHYs on - * Freescale LS1021AQDS board. The RGMII PHYs are the three on-board 1Gb - * ports. The SGMII PHYs are provided by the standard Freescale four-port - * SGMII riser card. - * - * Muxing is handled via the PIXIS BRDCFG4 register. The EMI1 bits control - * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII depends - * on which port is used. The value for SGMII depends on which slot the riser - * is inserted in. - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/arch/fsl_serdes.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <malloc.h> - -#include "../common/sgmii_riser.h" -#include "../common/qixis.h" - -#define EMI1_MASK 0x1f -#define EMI1_RGMII0 1 -#define EMI1_RGMII1 2 -#define EMI1_RGMII2 3 -#define EMI1_SGMII1 0x1c -#define EMI1_SGMII2 0x1d - -struct ls1021a_mdio { - struct mii_dev *realbus; -}; - -static void ls1021a_mux_mdio(int addr) -{ - u8 brdcfg4; - - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= EMI1_MASK; - - switch (addr) { - case EMI1_RGMII0: - brdcfg4 |= 0; - break; - case EMI1_RGMII1: - brdcfg4 |= 0x20; - break; - case EMI1_RGMII2: - brdcfg4 |= 0x40; - break; - case EMI1_SGMII1: - brdcfg4 |= 0x60; - break; - case EMI1_SGMII2: - brdcfg4 |= 0x80; - break; - default: - brdcfg4 |= 0xa0; - break; - } - - QIXIS_WRITE(brdcfg[4], brdcfg4); -} - -static int ls1021a_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1021a_mdio *priv = bus->priv; - - ls1021a_mux_mdio(addr); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1021a_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1021a_mdio *priv = bus->priv; - - ls1021a_mux_mdio(addr); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int ls1021a_mdio_reset(struct mii_dev *bus) -{ - struct ls1021a_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1021a_mdio_init(char *realbusname, char *fakebusname) -{ - struct ls1021a_mdio *lsmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate LS102xA MDIO bus\n"); - return -1; - } - - lsmdio = malloc(sizeof(*lsmdio)); - if (!lsmdio) { - printf("Failed to allocate LS102xA private data\n"); - free(bus); - return -1; - } - - bus->read = ls1021a_mdio_read; - bus->write = ls1021a_mdio_write; - bus->reset = ls1021a_mdio_reset; - strcpy(bus->name, fakebusname); - - lsmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!lsmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(lsmdio); - return -1; - } - - bus->priv = lsmdio; - - return mdio_register(bus); -} - -int board_eth_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[3]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode\n"); - tsec_info[num].flags |= TSEC_SGMII; - tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; - } else { - tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - puts("eTSEC2 is in sgmii mode\n"); - tsec_info[num].flags |= TSEC_SGMII; - tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; - } else { - tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; - num++; -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_init(tsec_info, num); -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - /* Register the virtual MDIO front-ends */ - ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_RGMII_MDIO"); - ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_SGMII_MDIO"); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d9a973c13fba..aaf28a346d05 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -285,14 +285,6 @@ #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 - -#define CONFIG_FSL_SGMII_RISER 1 -#define SGMII_RISER_PHY_OFFSET 0x1b - -#ifdef CONFIG_FSL_SGMII_RISER -#define CONFIG_SYS_TBIPA_VALUE 8 -#endif - #endif

#define CONFIG_PEN_ADDR_BIG_ENDIAN

-- 2.25.1

Tom Rini

21 Aug 21 Aug

4:43 a.m.

New subject: [PATCH 17/21] ls1021aqds/ls1021aiot: Remove legacy non-DM_ETH code

On Tue, Aug 02, 2022 at 07:33:43AM -0400, Tom Rini wrote:

...

Now that we are about to enable DM_ETH by default, remove legacy code.

Cc: Alison Wang alison.wang@nxp.com Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 18/21] vinco: Remove legacy non-DM_ETH code

Now that we are about to enable DM_ETH by default, remove legacy code.

Cc: Gregory CLEMENT gregory.clement@bootlin.com Signed-off-by: Tom Rini trini@konsulko.com --- The MAINTAINERS file needs to be updated as well, thanks. --- board/l+g/vinco/vinco.c | 3 --- 1 file changed, 3 deletions(-)

diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c index 9c4c5fdc4a53..db1075a594ac 100644 --- a/board/l+g/vinco/vinco.c +++ b/board/l+g/vinco/vinco.c @@ -204,9 +204,6 @@ int board_eth_init(struct bd_info *bis)

#ifdef CONFIG_USB_GADGET_ATMEL_USBA usba_udc_probe(&pdata); -#ifdef CONFIG_USB_ETH_RNDIS - usb_eth_initialize(bis); -#endif #endif

return rc;

-- 2.25.1

Tom Rini

21 Aug 21 Aug

4:43 a.m.

New subject: [PATCH 18/21] vinco: Remove legacy non-DM_ETH code

On Tue, Aug 02, 2022 at 07:33:44AM -0400, Tom Rini wrote:

...

Now that we are about to enable DM_ETH by default, remove legacy code.

Cc: Gregory CLEMENT gregory.clement@bootlin.com Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 19/21] warp7: Remove legacy non-DM_ETH code

Now that we are about to enable DM_ETH by default, remove legacy code.

Cc: Fabio Estevam festevam@gmail.com Signed-off-by: Tom Rini trini@konsulko.com --- board/warp7/warp7.c | 13 ------------- 1 file changed, 13 deletions(-)

diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 95b8e82dd1cc..ead52d5a490c 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -66,19 +66,6 @@ int power_init_board(void) } #endif

-int board_eth_init(struct bd_info *bis) -{ - int ret = 0; - -#ifdef CONFIG_USB_ETHER - ret = usb_eth_initialize(bis); - if (ret < 0) - printf("Error %d registering USB ether.\n", ret); -#endif - - return ret; -} - int board_init(void) { /* address of boot parameters */

-- 2.25.1

Tom Rini

21 Aug 21 Aug

4:43 a.m.

New subject: [PATCH 19/21] warp7: Remove legacy non-DM_ETH code

On Tue, Aug 02, 2022 at 07:33:45AM -0400, Tom Rini wrote:

...

Now that we are about to enable DM_ETH by default, remove legacy code.

Cc: Fabio Estevam festevam@gmail.com Signed-off-by: Tom Rini trini@konsulko.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 20/21] smdkc100: Remove legacy non-DM_ETH code

Now that we are about to enable DM_ETH by default, remove legacy code.

Cc: Minkyu Kang mk7.kang@samsung.com Signed-off-by: Tom Rini trini@konsulko.com --- board/samsung/smdkc100/smdkc100.c | 9 --------- 1 file changed, 9 deletions(-)

diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 69ed715403fb..b944e44c1ac4 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -69,12 +69,3 @@ int checkboard(void) return 0; } #endif - -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -}

-- 2.25.1

Minkyu Kang

3 Aug 3 Aug

4:23 p.m.

New subject: [PATCH 20/21] smdkc100: Remove legacy non-DM_ETH code

Hi,

On Tue, 2 Aug 2022 at 20:39, Tom Rini trini@konsulko.com wrote:

...

Now that we are about to enable DM_ETH by default, remove legacy code.

Cc: Minkyu Kang mk7.kang@samsung.com Signed-off-by: Tom Rini trini@konsulko.com

board/samsung/smdkc100/smdkc100.c | 9 --------- 1 file changed, 9 deletions(-)

diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 69ed715403fb..b944e44c1ac4 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -69,12 +69,3 @@ int checkboard(void) return 0; } #endif

-int board_eth_init(struct bd_info *bis) -{
  int rc = 0;
-#ifdef CONFIG_SMC911X
  rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
  return rc;
-}

2.25.1

Reviewed-by: Minkyu Kang mk7.kang@samsung.com

-- Thanks, Minkyu Kang.

Tom Rini

21 Aug 21 Aug

4:43 a.m.

New subject: [PATCH 20/21] smdkc100: Remove legacy non-DM_ETH code

On Tue, Aug 02, 2022 at 07:33:46AM -0400, Tom Rini wrote:

...

Now that we are about to enable DM_ETH by default, remove legacy code.

Cc: Minkyu Kang mk7.kang@samsung.com Signed-off-by: Tom Rini trini@konsulko.com Reviewed-by: Minkyu Kang mk7.kang@samsung.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:33 p.m.

New subject: [PATCH 21/21] net: Make DM_ETH be selected by NETDEVICE

The deadline for DM_ETH migration passed 2 years ago. Now that platforms which cannot be migrated have been either removed or had drivers disabled, and platforms that needed minor help to migrate have been forcefully migrated, we can complete the migration.

This entails select'ing DM_ETH under NETDEVICES, and then removing now extraneous depends on lines. In a few places, we can now either remove options or just simplify later dependencies.

Cc: Ramon Fried rfried.dev@gmail.com Cc: Simon Glass sjg@chromium.org Signed-off-by: Tom Rini trini@konsulko.com --- Makefile | 1 - drivers/net/Kconfig | 78 ++++++++++++--------------------------------- 2 files changed, 21 insertions(+), 58 deletions(-)

diff --git a/Makefile b/Makefile index ff25f9297486..315b2a6ced08 100644 --- a/Makefile +++ b/Makefile @@ -1145,7 +1145,6 @@ ifneq ($(CONFIG_DM),y) endif $(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\ $(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG)) - $(call deprecated,CONFIG_DM_ETH,Ethernet drivers,v2020.07,$(CONFIG_NET)) $(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY)) $(call deprecated,CONFIG_DM_KEYBOARD,Keyboard drivers,v2022.10,$(CONFIG_KEYBOARD)) @# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 76d8057b98fd..dfdc5ad72f75 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -7,7 +7,7 @@ config ETH def_bool y

config DM_ETH - bool "Enable Driver Model for Ethernet drivers" + bool depends on DM help Enable driver model for Ethernet. @@ -18,7 +18,7 @@ config DM_ETH

config DM_MDIO bool "Enable Driver Model for MDIO devices" - depends on DM_ETH && PHYLIB + depends on PHYLIB help Enable driver model for MDIO devices

@@ -43,7 +43,7 @@ config DM_MDIO_MUX

config DM_DSA bool "Enable Driver Model for DSA switches" - depends on DM_ETH && DM_MDIO + depends on DM_MDIO depends on PHY_FIXED help Enable driver model for DSA switches @@ -94,7 +94,7 @@ config DSA_SANDBOX menuconfig NETDEVICES bool "Network device support" depends on NET - default y if DM_ETH + select DM_ETH help You must select Y to enable any network device support Generally if you have any networking support this is a given @@ -112,7 +112,7 @@ config PHY_GIGE

config AG7XXX bool "Atheros AG7xxx Ethernet MAC support" - depends on DM_ETH && ARCH_ATH79 + depends on ARCH_ATH79 select PHYLIB help This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is @@ -121,7 +121,6 @@ config AG7XXX

config ALTERA_TSE bool "Altera Triple-Speed Ethernet MAC support" - depends on DM_ETH select PHYLIB help This driver supports the Altera Triple-Speed (TSE) Ethernet MAC. @@ -154,7 +153,7 @@ config BCM_SF2_ETH_GMAC

config BCM6348_ETH bool "BCM6348 EMAC support" - depends on DM_ETH && ARCH_BMIPS + depends on ARCH_BMIPS select DMA select DMA_CHANNELS select MII @@ -164,7 +163,7 @@ config BCM6348_ETH

config BCM6368_ETH bool "BCM6368 EMAC support" - depends on DM_ETH && ARCH_BMIPS + depends on ARCH_BMIPS select DMA select MII help @@ -172,21 +171,19 @@ config BCM6368_ETH

config BCMGENET bool "BCMGENET V5 support" - depends on DM_ETH select PHYLIB help This driver supports the BCMGENET Ethernet MAC.

config CORTINA_NI_ENET bool "Cortina-Access Ethernet driver" - depends on DM_ETH && CORTINA_PLATFORM + depends on CORTINA_PLATFORM help This driver supports the Cortina-Access Ethernet MAC for all supported CAxxxx SoCs.

config CALXEDA_XGMAC bool "Calxeda XGMAC support" - depends on DM_ETH help This driver supports the XGMAC in Calxeda Highbank and Midway machines. @@ -198,7 +195,6 @@ config DRIVER_DM9000

config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support" - depends on DM_ETH select PHYLIB help This driver supports the Synopsys Designware Ethernet QOS (Quality @@ -273,7 +269,7 @@ config EEPRO100 ethernet family of adapters.

config ETH_SANDBOX - depends on DM_ETH && SANDBOX + depends on SANDBOX default y bool "Sandbox: Mocked Ethernet driver" help @@ -283,7 +279,7 @@ config ETH_SANDBOX This driver is particularly useful in the test/dm/eth.c tests

config ETH_SANDBOX_RAW - depends on DM_ETH && SANDBOX + depends on SANDBOX default y bool "Sandbox: Bridge to Linux Raw Sockets" help @@ -303,7 +299,6 @@ config ETH_DESIGNWARE

config ETH_DESIGNWARE_MESON8B bool "Amlogic Meson8b and later glue driver for Synopsys Designware Ethernet MAC" - depends on DM_ETH select ETH_DESIGNWARE help This provides glue layer to use Synopsys Designware Ethernet MAC @@ -314,7 +309,7 @@ config ETH_DESIGNWARE_SOCFPGA select SYSCON select DW_ALTDESCRIPTOR bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC" - depends on DM_ETH && ETH_DESIGNWARE + depends on ETH_DESIGNWARE help The Altera SoCFPGA requires additional configuration of the Altera system manager to correctly interface with the PHY. @@ -322,7 +317,7 @@ config ETH_DESIGNWARE_SOCFPGA

config ETH_DESIGNWARE_S700 bool "Actins S700 glue driver for Synopsys Designware Ethernet MAC" - depends on DM_ETH && ETH_DESIGNWARE + depends on ETH_DESIGNWARE help This provides glue layer to use Synopsys Designware Ethernet MAC present on Actions S700 SoC. @@ -386,7 +381,6 @@ config FTMAC100

config FTGMAC100 bool "Ftgmac100 Ethernet Support" - depends on DM_ETH select PHYLIB help This driver supports the Faraday's FTGMAC100 Gigabit SoC @@ -414,7 +408,6 @@ config SYS_DISCOVER_PHY

config MCFFEC bool "ColdFire Ethernet Support" - depends on DM_ETH select PHYLIB select SYS_DISCOVER_PHY help @@ -427,7 +420,6 @@ config SYS_UNIFY_CACHE

config FSLDMAFEC bool "ColdFire DMA Ethernet Support" - depends on DM_ETH select PHYLIB select SYS_DISCOVER_PHY help @@ -439,15 +431,6 @@ config KS8851_MLL help The Microchip KS8851 parallel bus external ethernet interface chip.

-if KS8851_MLL -if !DM_ETH -config KS8851_MLL_BASEADDR - hex "Microchip KS8851-MLL Base Address" - help - Define this to hold the physical address of the device (I/O space) -endif #DM_ETH -endif #KS8851_MLL - config KSZ9477 bool "Microchip KSZ9477 I2C controller driver" depends on DM_DSA && DM_I2C @@ -458,7 +441,7 @@ config KSZ9477 config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X - select PHYLIB if DM_ETH + select PHYLIB help This driver supports the network interface units in the Marvell Orion5x and Kirkwood SoCs @@ -558,7 +541,6 @@ config OCTEONTX2_CGX_INTF

config PCH_GBE bool "Intel Platform Controller Hub EG20T GMAC driver" - depends on DM_ETH select PHYLIB help This MAC is present in Intel Platform Controller Hub EG20T. It @@ -619,25 +601,14 @@ config SJA1105 config SMC911X bool "SMSC LAN911x and LAN921x controller driver"

-if SMC911X - -if !DM_ETH -config SMC911X_BASE - hex "SMC911X Base Address" - help - Define this to hold the physical address - of the device (I/O space) -endif #DM_ETH - config SMC911X_32_BIT bool "Enable SMC911X 32-bit interface" + depends on SMC911X help Define this if data bus is 32 bits. If your processor use a narrower 16 bit bus or cannot convert one 32 bit word to two 16 bit words, leave this to "n".

-endif #SMC911X - config SUN7I_GMAC bool "Enable Allwinner GMAC Ethernet support" help @@ -653,14 +624,12 @@ config SUN7I_GMAC_FORCE_TXERR

config SUN4I_EMAC bool "Allwinner Sun4i Ethernet MAC support" - depends on DM_ETH select PHYLIB help This driver supports the Allwinner based SUN4I Ethernet MAC.

config SUN8I_EMAC bool "Allwinner Sun8i Ethernet MAC support" - depends on DM_ETH select PHYLIB select PHY_GIGE help @@ -682,7 +651,6 @@ config TULIP This driver supports DEC DC2114x Fast ethernet chips.

config XILINX_AXIEMAC - depends on DM_ETH select PHYLIB select MII bool "Xilinx AXI Ethernet" @@ -690,7 +658,7 @@ config XILINX_AXIEMAC This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.

config XILINX_AXIMRMAC - depends on DM_ETH && ARCH_VERSAL + depends on ARCH_VERSAL bool "Xilinx AXI MRMAC" help MRMAC is a high performance, low latency, adaptable Ethernet @@ -699,7 +667,6 @@ config XILINX_AXIMRMAC Versal designs.

config XILINX_EMACLITE - depends on DM_ETH select PHYLIB select MII bool "Xilinx Ethernetlite" @@ -707,7 +674,6 @@ config XILINX_EMACLITE This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.

config ZYNQ_GEM - depends on DM_ETH select PHYLIB bool "Xilinx Ethernet GEM" help @@ -715,7 +681,7 @@ config ZYNQ_GEM

config PIC32_ETH bool "Microchip PIC32 Ethernet Support" - depends on DM_ETH && MACH_PIC32 + depends on MACH_PIC32 select PHYLIB help This driver implements 10/100 Mbps Ethernet and MAC layer for @@ -723,14 +689,14 @@ config PIC32_ETH

config GMAC_ROCKCHIP bool "Rockchip Synopsys Designware Ethernet MAC" - depends on DM_ETH && ETH_DESIGNWARE + depends on ETH_DESIGNWARE help This driver provides Rockchip SoCs network support based on the Synopsys Designware driver.

config RENESAS_RAVB bool "Renesas Ethernet AVB MAC" - depends on DM_ETH && RCAR_GEN3 + depends on RCAR_GEN3 select PHYLIB help This driver implements support for the Ethernet AVB block in @@ -748,7 +714,7 @@ config MPC8XX_FEC

config SNI_AVE bool "Socionext AVE Ethernet support" - depends on DM_ETH && ARCH_UNIPHIER + depends on ARCH_UNIPHIER select PHYLIB select SYSCON select REGMAP @@ -758,7 +724,7 @@ config SNI_AVE

config SNI_NETSEC bool "Socionext NETSEC Ethernet support" - depends on DM_ETH && SYNQUACER_SPI + depends on SYNQUACER_SPI select PHYLIB help This driver implements support for the Socionext SynQuacer NETSEC @@ -847,7 +813,6 @@ config TSEC_ENET

config MEDIATEK_ETH bool "MediaTek Ethernet GMAC Driver" - depends on DM_ETH select PHYLIB select DM_GPIO select DM_RESET @@ -857,7 +822,6 @@ config MEDIATEK_ETH

config HIGMACV300_ETH bool "HiSilicon Gigabit Ethernet Controller" - depends on DM_ETH select DM_RESET select PHYLIB help @@ -866,7 +830,7 @@ config HIGMACV300_ETH

config FSL_ENETC bool "NXP ENETC Ethernet controller" - depends on DM_ETH && DM_MDIO + depends on DM_MDIO help This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs.

-- 2.25.1

Ramon Fried

6 Aug 6 Aug

7:46 p.m.

New subject: [PATCH 21/21] net: Make DM_ETH be selected by NETDEVICE

On Tue, Aug 2, 2022 at 2:35 PM Tom Rini trini@konsulko.com wrote:

...

The deadline for DM_ETH migration passed 2 years ago. Now that platforms which cannot be migrated have been either removed or had drivers disabled, and platforms that needed minor help to migrate have been forcefully migrated, we can complete the migration.

This entails select'ing DM_ETH under NETDEVICES, and then removing now extraneous depends on lines. In a few places, we can now either remove options or just simplify later dependencies.

Cc: Ramon Fried rfried.dev@gmail.com Cc: Simon Glass sjg@chromium.org Signed-off-by: Tom Rini trini@konsulko.com

Makefile | 1 - drivers/net/Kconfig | 78 ++++++++++++--------------------------------- 2 files changed, 21 insertions(+), 58 deletions(-)

diff --git a/Makefile b/Makefile index ff25f9297486..315b2a6ced08 100644 --- a/Makefile +++ b/Makefile @@ -1145,7 +1145,6 @@ ifneq ($(CONFIG_DM),y) endif $(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\ $(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
  $(call deprecated,CONFIG_DM_ETH,Ethernet drivers,v2020.07,$(CONFIG_NET))
  $(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
  $(call deprecated,CONFIG_DM_KEYBOARD,Keyboard drivers,v2022.10,$(CONFIG_KEYBOARD))
  @# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 76d8057b98fd..dfdc5ad72f75 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -7,7 +7,7 @@ config ETH def_bool y

config DM_ETH
  bool "Enable Driver Model for Ethernet drivers"
  bool
  depends on DM
  help
    Enable driver model for Ethernet.
@@ -18,7 +18,7 @@ config DM_ETH

config DM_MDIO bool "Enable Driver Model for MDIO devices"
  depends on DM_ETH && PHYLIB
  depends on PHYLIB
  help
    Enable driver model for MDIO devices
@@ -43,7 +43,7 @@ config DM_MDIO_MUX

config DM_DSA bool "Enable Driver Model for DSA switches"
  depends on DM_ETH && DM_MDIO
  depends on DM_MDIO
  depends on PHY_FIXED
  help
    Enable driver model for DSA switches
@@ -94,7 +94,7 @@ config DSA_SANDBOX menuconfig NETDEVICES bool "Network device support" depends on NET
  default y if DM_ETH
  select DM_ETH
  help
    You must select Y to enable any network device support
    Generally if you have any networking support this is a given
@@ -112,7 +112,7 @@ config PHY_GIGE

config AG7XXX bool "Atheros AG7xxx Ethernet MAC support"
  depends on DM_ETH && ARCH_ATH79
  depends on ARCH_ATH79
  select PHYLIB
  help
    This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is
@@ -121,7 +121,6 @@ config AG7XXX

config ALTERA_TSE bool "Altera Triple-Speed Ethernet MAC support"
  depends on DM_ETH
  select PHYLIB
  help
    This driver supports the Altera Triple-Speed (TSE) Ethernet MAC.
@@ -154,7 +153,7 @@ config BCM_SF2_ETH_GMAC

config BCM6348_ETH bool "BCM6348 EMAC support"
  depends on DM_ETH && ARCH_BMIPS
  depends on ARCH_BMIPS
  select DMA
  select DMA_CHANNELS
  select MII
@@ -164,7 +163,7 @@ config BCM6348_ETH

config BCM6368_ETH bool "BCM6368 EMAC support"
  depends on DM_ETH && ARCH_BMIPS
  depends on ARCH_BMIPS
  select DMA
  select MII
  help
@@ -172,21 +171,19 @@ config BCM6368_ETH

config BCMGENET bool "BCMGENET V5 support"
  depends on DM_ETH
  select PHYLIB
  help
    This driver supports the BCMGENET Ethernet MAC.
config CORTINA_NI_ENET bool "Cortina-Access Ethernet driver"
  depends on DM_ETH && CORTINA_PLATFORM
  depends on CORTINA_PLATFORM
  help
    This driver supports the Cortina-Access Ethernet MAC for
    all supported CAxxxx SoCs.
config CALXEDA_XGMAC bool "Calxeda XGMAC support"
  depends on DM_ETH
  help
    This driver supports the XGMAC in Calxeda Highbank and Midway
    machines.
@@ -198,7 +195,6 @@ config DRIVER_DM9000

config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support"
  depends on DM_ETH
  select PHYLIB
  help
    This driver supports the Synopsys Designware Ethernet QOS (Quality
@@ -273,7 +269,7 @@ config EEPRO100 ethernet family of adapters.

config ETH_SANDBOX
  depends on DM_ETH && SANDBOX
  depends on SANDBOX
  default y
  bool "Sandbox: Mocked Ethernet driver"
  help
@@ -283,7 +279,7 @@ config ETH_SANDBOX This driver is particularly useful in the test/dm/eth.c tests

config ETH_SANDBOX_RAW
  depends on DM_ETH && SANDBOX
  depends on SANDBOX
  default y
  bool "Sandbox: Bridge to Linux Raw Sockets"
  help
@@ -303,7 +299,6 @@ config ETH_DESIGNWARE

config ETH_DESIGNWARE_MESON8B bool "Amlogic Meson8b and later glue driver for Synopsys Designware Ethernet MAC"
  depends on DM_ETH
  select ETH_DESIGNWARE
  help
    This provides glue layer to use Synopsys Designware Ethernet MAC
@@ -314,7 +309,7 @@ config ETH_DESIGNWARE_SOCFPGA select SYSCON select DW_ALTDESCRIPTOR bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC"
  depends on DM_ETH && ETH_DESIGNWARE
  depends on ETH_DESIGNWARE
  help
    The Altera SoCFPGA requires additional configuration of the
    Altera system manager to correctly interface with the PHY.
@@ -322,7 +317,7 @@ config ETH_DESIGNWARE_SOCFPGA

config ETH_DESIGNWARE_S700 bool "Actins S700 glue driver for Synopsys Designware Ethernet MAC"
  depends on DM_ETH && ETH_DESIGNWARE
  depends on ETH_DESIGNWARE
  help
    This provides glue layer to use Synopsys Designware Ethernet MAC
    present on Actions S700 SoC.
@@ -386,7 +381,6 @@ config FTMAC100

config FTGMAC100 bool "Ftgmac100 Ethernet Support"
  depends on DM_ETH
  select PHYLIB
  help
    This driver supports the Faraday's FTGMAC100 Gigabit SoC
@@ -414,7 +408,6 @@ config SYS_DISCOVER_PHY

config MCFFEC bool "ColdFire Ethernet Support"
  depends on DM_ETH
  select PHYLIB
  select SYS_DISCOVER_PHY
  help
@@ -427,7 +420,6 @@ config SYS_UNIFY_CACHE

config FSLDMAFEC bool "ColdFire DMA Ethernet Support"
  depends on DM_ETH
  select PHYLIB
  select SYS_DISCOVER_PHY
  help
@@ -439,15 +431,6 @@ config KS8851_MLL help The Microchip KS8851 parallel bus external ethernet interface chip.

-if KS8851_MLL -if !DM_ETH -config KS8851_MLL_BASEADDR
  hex "Microchip KS8851-MLL Base Address"
  help
    Define this to hold the physical address of the device (I/O space)
-endif #DM_ETH -endif #KS8851_MLL

config KSZ9477 bool "Microchip KSZ9477 I2C controller driver" depends on DM_DSA && DM_I2C @@ -458,7 +441,7 @@ config KSZ9477 config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X
  select PHYLIB if DM_ETH
  select PHYLIB
  help
    This driver supports the network interface units in the
    Marvell Orion5x and Kirkwood SoCs
@@ -558,7 +541,6 @@ config OCTEONTX2_CGX_INTF

config PCH_GBE bool "Intel Platform Controller Hub EG20T GMAC driver"
  depends on DM_ETH
  select PHYLIB
  help
    This MAC is present in Intel Platform Controller Hub EG20T. It
@@ -619,25 +601,14 @@ config SJA1105 config SMC911X bool "SMSC LAN911x and LAN921x controller driver"

-if SMC911X

-if !DM_ETH -config SMC911X_BASE
  hex "SMC911X Base Address"
  help
    Define this to hold the physical address
    of the device (I/O space)
-endif #DM_ETH

config SMC911X_32_BIT bool "Enable SMC911X 32-bit interface"
  depends on SMC911X
  help
    Define this if data bus is 32 bits. If your processor use a
    narrower 16 bit bus or cannot convert one 32 bit word to two 16 bit
    words, leave this to "n".
-endif #SMC911X

config SUN7I_GMAC bool "Enable Allwinner GMAC Ethernet support" help @@ -653,14 +624,12 @@ config SUN7I_GMAC_FORCE_TXERR

config SUN4I_EMAC bool "Allwinner Sun4i Ethernet MAC support"
  depends on DM_ETH
  select PHYLIB
  help
    This driver supports the Allwinner based SUN4I Ethernet MAC.
config SUN8I_EMAC bool "Allwinner Sun8i Ethernet MAC support"
   depends on DM_ETH
   select PHYLIB
  select PHY_GIGE
   help
@@ -682,7 +651,6 @@ config TULIP This driver supports DEC DC2114x Fast ethernet chips.

config XILINX_AXIEMAC
  depends on DM_ETH
  select PHYLIB
  select MII
  bool "Xilinx AXI Ethernet"
@@ -690,7 +658,7 @@ config XILINX_AXIEMAC This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.

config XILINX_AXIMRMAC
  depends on DM_ETH && ARCH_VERSAL
  depends on ARCH_VERSAL
  bool "Xilinx AXI MRMAC"
  help
    MRMAC is a high performance, low latency, adaptable Ethernet
@@ -699,7 +667,6 @@ config XILINX_AXIMRMAC Versal designs.

config XILINX_EMACLITE
  depends on DM_ETH
  select PHYLIB
  select MII
  bool "Xilinx Ethernetlite"
@@ -707,7 +674,6 @@ config XILINX_EMACLITE This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.

config ZYNQ_GEM
  depends on DM_ETH
  select PHYLIB
  bool "Xilinx Ethernet GEM"
  help
@@ -715,7 +681,7 @@ config ZYNQ_GEM

config PIC32_ETH bool "Microchip PIC32 Ethernet Support"
  depends on DM_ETH && MACH_PIC32
  depends on MACH_PIC32
  select PHYLIB
  help
    This driver implements 10/100 Mbps Ethernet and MAC layer for
@@ -723,14 +689,14 @@ config PIC32_ETH

config GMAC_ROCKCHIP bool "Rockchip Synopsys Designware Ethernet MAC"
  depends on DM_ETH && ETH_DESIGNWARE
  depends on ETH_DESIGNWARE
  help
    This driver provides Rockchip SoCs network support based on the
    Synopsys Designware driver.
config RENESAS_RAVB bool "Renesas Ethernet AVB MAC"
  depends on DM_ETH && RCAR_GEN3
  depends on RCAR_GEN3
  select PHYLIB
  help
    This driver implements support for the Ethernet AVB block in
@@ -748,7 +714,7 @@ config MPC8XX_FEC

config SNI_AVE bool "Socionext AVE Ethernet support"
  depends on DM_ETH && ARCH_UNIPHIER
  depends on ARCH_UNIPHIER
  select PHYLIB
  select SYSCON
  select REGMAP
@@ -758,7 +724,7 @@ config SNI_AVE

config SNI_NETSEC bool "Socionext NETSEC Ethernet support"
  depends on DM_ETH && SYNQUACER_SPI
  depends on SYNQUACER_SPI
  select PHYLIB
  help
    This driver implements support for the Socionext SynQuacer NETSEC
@@ -847,7 +813,6 @@ config TSEC_ENET

config MEDIATEK_ETH bool "MediaTek Ethernet GMAC Driver"
  depends on DM_ETH
  select PHYLIB
  select DM_GPIO
  select DM_RESET
@@ -857,7 +822,6 @@ config MEDIATEK_ETH

config HIGMACV300_ETH bool "HiSilicon Gigabit Ethernet Controller"
  depends on DM_ETH
  select DM_RESET
  select PHYLIB
  help
@@ -866,7 +830,7 @@ config HIGMACV300_ETH

config FSL_ENETC bool "NXP ENETC Ethernet controller"
  depends on DM_ETH && DM_MDIO
  depends on DM_MDIO
  help
    This driver supports the NXP ENETC Ethernet controller found on some
    of the NXP SoCs.
-- 2.25.1

Acked-by: Ramon Fried rfried.dev@gmail.com

Simon Glass

8:21 p.m.

New subject: [PATCH 21/21] net: Make DM_ETH be selected by NETDEVICE

Hi Tom,

On Tue, 2 Aug 2022 at 05:35, Tom Rini trini@konsulko.com wrote:

...

The deadline for DM_ETH migration passed 2 years ago. Now that platforms which cannot be migrated have been either removed or had drivers disabled, and platforms that needed minor help to migrate have been forcefully migrated, we can complete the migration.

This entails select'ing DM_ETH under NETDEVICES, and then removing now extraneous depends on lines. In a few places, we can now either remove options or just simplify later dependencies.

Cc: Ramon Fried rfried.dev@gmail.com Cc: Simon Glass sjg@chromium.org Signed-off-by: Tom Rini trini@konsulko.com

Makefile | 1 - drivers/net/Kconfig | 78 ++++++++++++--------------------------------- 2 files changed, 21 insertions(+), 58 deletions(-)

With this I saw a build error on MCR3000, but perhaps you have send a removal patch for it, which I missed?

Regards, Simon

Tom Rini

10:01 p.m.

New subject: [PATCH 21/21] net: Make DM_ETH be selected by NETDEVICE

On Sat, Aug 06, 2022 at 12:21:21PM -0600, Simon Glass wrote:

...

Hi Tom,

On Tue, 2 Aug 2022 at 05:35, Tom Rini trini@konsulko.com wrote:

...
The deadline for DM_ETH migration passed 2 years ago. Now that platforms which cannot be migrated have been either removed or had drivers disabled, and platforms that needed minor help to migrate have been forcefully migrated, we can complete the migration.

This entails select'ing DM_ETH under NETDEVICES, and then removing now extraneous depends on lines. In a few places, we can now either remove options or just simplify later dependencies.

Cc: Ramon Fried rfried.dev@gmail.com Cc: Simon Glass sjg@chromium.org Signed-off-by: Tom Rini trini@konsulko.com

Makefile | 1 - drivers/net/Kconfig | 78 ++++++++++++--------------------------------- 2 files changed, 21 insertions(+), 58 deletions(-)

With this I saw a build error on MCR3000, but perhaps you have send a removal patch for it, which I missed?

I thought I mentioned in the cover letter that this depends on the existing migration patch for the driver in question.

-- Tom

Simon Glass

7 Aug 7 Aug

5:47 p.m.

New subject: [PATCH 21/21] net: Make DM_ETH be selected by NETDEVICE

Hi Tom,

On Sat, 6 Aug 2022 at 14:02, Tom Rini trini@konsulko.com wrote:

...

On Sat, Aug 06, 2022 at 12:21:21PM -0600, Simon Glass wrote:

...
Hi Tom,

On Tue, 2 Aug 2022 at 05:35, Tom Rini trini@konsulko.com wrote:

...
The deadline for DM_ETH migration passed 2 years ago. Now that platforms which cannot be migrated have been either removed or had drivers disabled, and platforms that needed minor help to migrate have been forcefully migrated, we can complete the migration.

This entails select'ing DM_ETH under NETDEVICES, and then removing now extraneous depends on lines. In a few places, we can now either remove options or just simplify later dependencies.

Cc: Ramon Fried rfried.dev@gmail.com Cc: Simon Glass sjg@chromium.org Signed-off-by: Tom Rini trini@konsulko.com

Makefile | 1 - drivers/net/Kconfig | 78 ++++++++++++--------------------------------- 2 files changed, 21 insertions(+), 58 deletions(-)

With this I saw a build error on MCR3000, but perhaps you have send a removal patch for it, which I missed?

I thought I mentioned in the cover letter that this depends on the existing migration patch for the driver in question.

Oh, sorry. I wish patchwork would show the cover letter.

Regards, Simon

Tom Rini

6:39 p.m.

New subject: [PATCH 21/21] net: Make DM_ETH be selected by NETDEVICE

On Sun, Aug 07, 2022 at 09:47:54AM -0600, Simon Glass wrote:

...

Hi Tom,

On Sat, 6 Aug 2022 at 14:02, Tom Rini trini@konsulko.com wrote:

...
On Sat, Aug 06, 2022 at 12:21:21PM -0600, Simon Glass wrote:

...
Hi Tom,

On Tue, 2 Aug 2022 at 05:35, Tom Rini trini@konsulko.com wrote:

...
The deadline for DM_ETH migration passed 2 years ago. Now that platforms which cannot be migrated have been either removed or had drivers disabled, and platforms that needed minor help to migrate have been forcefully migrated, we can complete the migration.

This entails select'ing DM_ETH under NETDEVICES, and then removing now extraneous depends on lines. In a few places, we can now either remove options or just simplify later dependencies.

Cc: Ramon Fried rfried.dev@gmail.com Cc: Simon Glass sjg@chromium.org Signed-off-by: Tom Rini trini@konsulko.com

Makefile | 1 - drivers/net/Kconfig | 78 ++++++++++++--------------------------------- 2 files changed, 21 insertions(+), 58 deletions(-)

With this I saw a build error on MCR3000, but perhaps you have send a removal patch for it, which I missed?

I thought I mentioned in the cover letter that this depends on the existing migration patch for the driver in question.

Oh, sorry. I wish patchwork would show the cover letter.

It does, but not from the series link, but just "expand" from an individual patch in a series. It's how I've been copy/pasting cover letters are the merge commit message for big series, fwiw.

-- Tom

Simon Glass

8:49 p.m.

New subject: [PATCH 21/21] net: Make DM_ETH be selected by NETDEVICE

Hi Tom,

On Sun, 7 Aug 2022 at 10:39, Tom Rini trini@konsulko.com wrote:

...

On Sun, Aug 07, 2022 at 09:47:54AM -0600, Simon Glass wrote:

...
Hi Tom,

On Sat, 6 Aug 2022 at 14:02, Tom Rini trini@konsulko.com wrote:

...
On Sat, Aug 06, 2022 at 12:21:21PM -0600, Simon Glass wrote:

...
Hi Tom,

On Tue, 2 Aug 2022 at 05:35, Tom Rini trini@konsulko.com wrote:

...
The deadline for DM_ETH migration passed 2 years ago. Now that platforms which cannot be migrated have been either removed or had drivers disabled, and platforms that needed minor help to migrate have been forcefully migrated, we can complete the migration.

This entails select'ing DM_ETH under NETDEVICES, and then removing now extraneous depends on lines. In a few places, we can now either remove options or just simplify later dependencies.

Cc: Ramon Fried rfried.dev@gmail.com Cc: Simon Glass sjg@chromium.org Signed-off-by: Tom Rini trini@konsulko.com

Makefile | 1 - drivers/net/Kconfig | 78 ++++++++++++--------------------------------- 2 files changed, 21 insertions(+), 58 deletions(-)

With this I saw a build error on MCR3000, but perhaps you have send a removal patch for it, which I missed?

I thought I mentioned in the cover letter that this depends on the existing migration patch for the driver in question.

Oh, sorry. I wish patchwork would show the cover letter.

It does, but not from the series link, but just "expand" from an individual patch in a series. It's how I've been copy/pasting cover letters are the merge commit message for big series, fwiw.

Oh dear, I had no idea about that. What a strange UI. Thank you for letting me know!

Regards, Simon

Tom Rini

21 Aug 21 Aug

4:43 a.m.

New subject: [PATCH 21/21] net: Make DM_ETH be selected by NETDEVICE

On Tue, Aug 02, 2022 at 07:33:47AM -0400, Tom Rini wrote:

...

The deadline for DM_ETH migration passed 2 years ago. Now that platforms which cannot be migrated have been either removed or had drivers disabled, and platforms that needed minor help to migrate have been forcefully migrated, we can complete the migration.

This entails select'ing DM_ETH under NETDEVICES, and then removing now extraneous depends on lines. In a few places, we can now either remove options or just simplify later dependencies.

Cc: Ramon Fried rfried.dev@gmail.com Cc: Simon Glass sjg@chromium.org Signed-off-by: Tom Rini trini@konsulko.com Acked-by: Ramon Fried rfried.dev@gmail.com

Applied to u-boot/master, thanks!

-- Tom

Tom Rini

2 Aug 2 Aug

1:51 p.m.

On Tue, Aug 02, 2022 at 07:33:26AM -0400, Tom Rini wrote:

...

As I've noted before, with v2022.07 being released, we have gone 2 years past the DM_ETH migration deadline. What this series does is a few things:

Remove some boards that either lack DM migration at all, or lack OF_CONTROL. DM migration has had an explicit deadline, and OF_CONTROL an implict one.

Remove some un-migrated ethernet drivers. I had reached out in private to some people about this and they had hoped to have done the conversion by now. Unfortunately, here we now are.

Perform some minor forceful migrations on boards. These boards use OF_CONTROL and drivers which use DM_ETH, so I am hopeful that just removing or guarding the code here is fine and works.

Disable networkgin on some other boards. Unlike boards in the above case, it looks like the board code itself needs some updates, as was done on the platforms that have already been migrated.

Finally, select DM_ETH for all NETDEVICES and update dependencies.

This series depends on https://patchwork.ozlabs.org/project/uboot/patch/8ae444f17dc5db69a1da809875a... being applied and in practical terms depennds on my current outstanding Kconfig migrations as well.

Adding back the CC list git send-email dropped...

-- Tom

Tom Rini

8 Aug 8 Aug

9:09 p.m.

On Tue, Aug 02, 2022 at 07:51:18AM -0400, Tom Rini wrote:

...

On Tue, Aug 02, 2022 at 07:33:26AM -0400, Tom Rini wrote:

...
As I've noted before, with v2022.07 being released, we have gone 2 years past the DM_ETH migration deadline. What this series does is a few things:

Remove some boards that either lack DM migration at all, or lack OF_CONTROL. DM migration has had an explicit deadline, and OF_CONTROL an implict one.

Remove some un-migrated ethernet drivers. I had reached out in private to some people about this and they had hoped to have done the conversion by now. Unfortunately, here we now are.

Perform some minor forceful migrations on boards. These boards use OF_CONTROL and drivers which use DM_ETH, so I am hopeful that just removing or guarding the code here is fine and works.

Disable networkgin on some other boards. Unlike boards in the above case, it looks like the board code itself needs some updates, as was done on the platforms that have already been migrated.

Finally, select DM_ETH for all NETDEVICES and update dependencies.

This series depends on https://patchwork.ozlabs.org/project/uboot/patch/8ae444f17dc5db69a1da809875a... being applied and in practical terms depennds on my current outstanding Kconfig migrations as well.

Adding back the CC list git send-email dropped...

Just following up here as I got some acks/feedback on the platforms that will be loosing functionality, but not as much as I hoped. I will be applying this series soon.

-- Tom

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Fabio Estevam
Heiko Schocher
Ladislav Michl
Minkyu Kang
Ramon Fried
Simon Glass
Tom Rini