Signed-off-by: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr ---

include/configs/pcm052.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 302c7dd..1858662 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -125,7 +125,7 @@ "blimg_addr=0x81000400\0" \ "kernel_file=zImage\0" \ "kernel_addr=0x82000000\0" \ - "fdt_file=vf610-pcm052.dtb\0" \ + "fdt_file=zImage.dtb\0" \ "fdt_addr=0x81000000\0" \ "ram_file=uRamdisk\0" \ "ram_addr=0x83000000\0" \

This format can be flashed directly at address 0 of the NAND FLASH, as it contains all necessary headers.

Signed-off-by: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr ---

Makefile | 6 ++ arch/arm/config.mk | 3 + arch/arm/cpu/armv7/vf610/Makefile | 5 ++ common/image.c | 1 + include/configs/pcm052.h | 14 ++-- include/image.h | 1 + tools/Makefile | 1 + tools/vybridimage.c | 164 ++++++++++++++++++++++++++++++++++++++ 8 files changed, 187 insertions(+), 8 deletions(-) create mode 100644 tools/vybridimage.c

diff --git a/Makefile b/Makefile index c30f90a..75c74d5 100644 --- a/Makefile +++ b/Makefile @@ -844,6 +844,12 @@ endif %.imx: %.bin $(Q)$(MAKE) $(build)=arch/arm/imx-common $@

+%.vyb: %.imx + $(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@ + +quiet_cmd_copy = COPY $@ + cmd_copy = cp $< $@ + u-boot.dtb: dts/dt.dtb $(call cmd,copy)

diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 8f85862..542b897 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -144,4 +144,7 @@ else ALL-y += u-boot.imx endif endif +ifneq ($(CONFIG_VF610),) +ALL-y += u-boot.vyb +endif endif diff --git a/arch/arm/cpu/armv7/vf610/Makefile b/arch/arm/cpu/armv7/vf610/Makefile index 68cb756..2945377 100644 --- a/arch/arm/cpu/armv7/vf610/Makefile +++ b/arch/arm/cpu/armv7/vf610/Makefile @@ -6,3 +6,8 @@

obj-y += generic.o obj-y += timer.o + +MKIMAGEFLAGS_u-boot.vyb = -T vybridimage + +u-boot.vyb: u-boot.imx + $(call if_changed,mkimage) diff --git a/common/image.c b/common/image.c index a5d19ab..c0ad36a 100644 --- a/common/image.c +++ b/common/image.c @@ -161,6 +161,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_RKIMAGE, "rkimage", "Rockchip Boot Image" }, { IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" }, { IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" }, + { IH_TYPE_VYBRIDIMAGE, "vybridimage", "Vybrid Boot Image", }, { IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" }, { IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" }, { IH_TYPE_FPGA, "fpga", "FPGA Image" }, diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 1858662..cd235cc 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -120,9 +120,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "blimg_file=u-boot.imx\0" \ - "blsec_addr=0x81000000\0" \ - "blimg_addr=0x81000400\0" \ + "blimg_file=u-boot.vyb\0" \ + "blimg_addr=0x81000000\0" \ "kernel_file=zImage\0" \ "kernel_addr=0x82000000\0" \ "fdt_file=zImage.dtb\0" \ @@ -164,12 +163,11 @@ "nand read ${kernel_addr} kernel; " \ "nand read ${ram_addr} root; " \ "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ - "update_bootloader_from_tftp=mtdparts default; " \ - "nand read ${blsec_addr} bootloader; " \ - "mw.b ${blimg_addr} 0xff 0x5FC00; " \ - "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \ + "update_bootloader_from_tftp=if tftp ${blimg_addr} "\ + "${tftpdir}${blimg_file}; then " \ + "mtdparts default; " \ "nand erase.part bootloader; " \ - "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \ + "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \ "${kernel_file}; " \ "then mtdparts default; " \ diff --git a/include/image.h b/include/image.h index 64da722..2b1296c 100644 --- a/include/image.h +++ b/include/image.h @@ -278,6 +278,7 @@ enum { IH_TYPE_ZYNQIMAGE, /* Xilinx Zynq Boot Image */ IH_TYPE_ZYNQMPIMAGE, /* Xilinx ZynqMP Boot Image */ IH_TYPE_FPGA, /* FPGA Image */ + IH_TYPE_VYBRIDIMAGE, /* VYBRID .vyb Image */

IH_TYPE_COUNT, /* Number of image types */ }; diff --git a/tools/Makefile b/tools/Makefile index 421414b..e6f7993 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -89,6 +89,7 @@ dumpimage-mkimage-objs := aisimage.o \ os_support.o \ pblimage.o \ pbl_crc32.o \ + vybridimage.o \ $(ROCKCHIP_OBS) \ socfpgaimage.o \ lib/sha1.o \ diff --git a/tools/vybridimage.c b/tools/vybridimage.c new file mode 100644 index 0000000..a31fc10 --- /dev/null +++ b/tools/vybridimage.c @@ -0,0 +1,164 @@ +/* + * Image manipulator for Vybrid SoCs + * + * Derived from vybridimage.c + * + * (C) Copyright 2016 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD albert.aribaud@3adev.fr + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include <compiler.h> +#include <image.h> + +/* + * NAND page 0 boot header + */ + +struct nand_page_0_boot_header { + union { + uint32_t fcb[128]; + uint8_t fcb_bytes[512]; + }; /* 0x00000000 - 0x000001ff */ + uint8_t sw_ecc[512]; /* 0x00000200 - 0x000003ff */ + uint32_t padding[65280]; /* 0x00000400 - 0x0003ffff */ + uint8_t ivt_prefix[1024]; /* 0x00040000 - 0x000403ff */ +}; + +/* signature byte for a readable block */ + +static struct nand_page_0_boot_header vybridimage_header; + +static int vybridimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_VYBRIDIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +static uint8_t vybridimage_sw_ecc(uint8_t byte) +{ + uint8_t bit0 = (byte & (1 << 0)) ? 1 : 0; + uint8_t bit1 = (byte & (1 << 1)) ? 1 : 0; + uint8_t bit2 = (byte & (1 << 2)) ? 1 : 0; + uint8_t bit3 = (byte & (1 << 3)) ? 1 : 0; + uint8_t bit4 = (byte & (1 << 4)) ? 1 : 0; + uint8_t bit5 = (byte & (1 << 5)) ? 1 : 0; + uint8_t bit6 = (byte & (1 << 6)) ? 1 : 0; + uint8_t bit7 = (byte & (1 << 7)) ? 1 : 0; + uint8_t res = 0; + + res |= ((bit6 ^ bit5 ^ bit3 ^ bit2) << 0); + res |= ((bit7 ^ bit5 ^ bit4 ^ bit2 ^ bit1) << 1); + res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); + res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3); + res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4); + + return res; +} + +static int vybridimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + int idx; + + if (hdr->fcb[1] != 0x46434220) + return -1; + if (hdr->fcb[2] != 1) + return -1; + if (hdr->fcb[7] != 64) + return -1; + if (hdr->fcb[14] != 6) + return -1; + if (hdr->fcb[30] != 0x0001ff00) + return -1; + if (hdr->fcb[43] != 1) + return -1; + if (hdr->fcb[54] != 0) + return -1; + if (hdr->fcb[55] != 8) + return -1; + + /* check software ECC */ + for (idx = 0; idx < sizeof(hdr->fcb_bytes); idx++) { + uint8_t sw_ecc = vybridimage_sw_ecc(hdr->fcb_bytes[idx]); + if (sw_ecc != hdr->sw_ecc[idx]) + return -1; + } + + return 0; +} + +static void vybridimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + int idx; + + /* fill header with 0x00 for first 56 entries then 0xff */ + memset(&hdr->fcb[0], 0x0, 56*sizeof(uint32_t)); + memset(&hdr->fcb[56], 0xff, 72*sizeof(uint32_t)); + /* fill SW ecc and padding with 0xff */ + memset(&hdr->sw_ecc[0], 0xff, sizeof(hdr->sw_ecc)); + memset(&hdr->padding[0], 0xff, sizeof(hdr->padding)); + /* fill IVT prefix with 0x00 */ + memset(&hdr->ivt_prefix[0], 0x00, sizeof(hdr->ivt_prefix)); + + /* populate fcb */ + hdr->fcb[1] = 0x46434220; /* signature */ + hdr->fcb[2] = 0x00000001; /* version */ + hdr->fcb[5] = 2048; /* page size */ + hdr->fcb[6] = (2048+64); /* page + OOB size */ + hdr->fcb[7] = 64; /* pages per block */ + hdr->fcb[14] = 6; /* ECC mode 6 */ + hdr->fcb[26] = 128; /* fw address (0x40000) in 2K pages */ + hdr->fcb[27] = 128; /* fw address (0x40000) in 2K pages */ + hdr->fcb[30] = 0x0001ff00; /* DBBT search area start address */ + hdr->fcb[33] = 2048; /* BB marker physical offset */ + hdr->fcb[43] = 1; /* DISBBM */ + hdr->fcb[54] = 0; /* DISBB_Search */ + hdr->fcb[55] = 8; /* Bad block search limit */ + + /* compute software ECC */ + for (idx = 0; idx < sizeof(hdr->fcb_bytes); idx++) + hdr->sw_ecc[idx] = vybridimage_sw_ecc(hdr->fcb_bytes[idx]); +} + +static void vybridimage_print_hdr_field(struct nand_page_0_boot_header *hdr, + int idx) +{ + printf("header.fcb[%d] = %08x\n", idx, hdr->fcb[idx]); +} + +static void vybridimage_print_header(const void *ptr) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + int idx; + + for (idx = 0; idx < 56; idx++) + vybridimage_print_hdr_field(hdr, idx); +} + +/* + * vybridimage parameters + */ +U_BOOT_IMAGE_TYPE( + vybridimage, + "Vybrid Boot Image", + sizeof(vybridimage_header), + (void *)&vybridimage_header, + NULL, + vybridimage_verify_header, + vybridimage_print_header, + vybridimage_set_header, + NULL, + vybridimage_check_image_types, + NULL, + NULL +);

Signed-off-by: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr ---

arch/arm/Kconfig | 4 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/bk4r1.dts | 48 +++++++++++++ arch/arm/dts/vf.dtsi | 4 +- board/phytec/pcm052/Kconfig | 20 ++++++ board/phytec/pcm052/pcm052.c | 168 +++++++++++++++++++++++++++++-------------- configs/bk4r1_defconfig | 32 +++++++++ include/configs/bk4r1.h | 33 +++++++++ include/configs/pcm052.h | 45 ++++++++++-- 9 files changed, 297 insertions(+), 60 deletions(-) create mode 100644 arch/arm/dts/bk4r1.dts create mode 100644 configs/bk4r1_defconfig create mode 100644 include/configs/bk4r1.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0083bf9..3c2d33a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -678,6 +678,10 @@ config TARGET_PCM052 bool "Support pcm-052" select CPU_V7

+config TARGET_BK4R1 + bool "Support BK4r1" + select CPU_V7 + config ARCH_ZYNQ bool "Xilinx Zynq Platform" select CPU_V7 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index df57288..3e3b5c3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -274,7 +274,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ vf610-colibri.dtb \ vf610-twr.dtb \ - pcm052.dtb + pcm052.dtb \ + bk4r1.dtb

dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2l-evm.dtb \ diff --git a/arch/arm/dts/bk4r1.dts b/arch/arm/dts/bk4r1.dts new file mode 100644 index 0000000..197e5ab --- /dev/null +++ b/arch/arm/dts/bk4r1.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +/dts-v1/; +#include "vf.dtsi" + +/ { + model = "Phytec phyCORE-Vybrid"; + compatible = "phytec,pcm052", "fsl,vf610"; + + chosen { + stdout-path = &uart1; + }; + + aliases { + spi0 = &qspi0; + }; + +}; + +&uart1 { + status = "okay"; +}; + +&qspi0 { + bus-num = <0>; + num-cs = <2>; + status = "okay"; + + qflash0: spi_flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <108000000>; + reg = <0>; + }; + + qflash1: spi_flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <66000000>; + reg = <1>; + }; +}; diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi index 1530d2f..404dfe9 100644 --- a/arch/arm/dts/vf.dtsi +++ b/arch/arm/dts/vf.dtsi @@ -80,7 +80,9 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,vf610-qspi"; - reg = <0x40044000 0x1000>; + reg = <0x40044000 0x1000>, + <0x20000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; status = "disabled"; };

diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig index 88524a3..212f994 100644 --- a/board/phytec/pcm052/Kconfig +++ b/board/phytec/pcm052/Kconfig @@ -17,3 +17,23 @@ config PCM052_DDR_SIZE default 256

endif + +if TARGET_BK4R1 + +config SYS_BOARD + default "pcm052" + +config SYS_VENDOR + default "phytec" + +config SYS_SOC + default "vf610" + +config SYS_CONFIG_NAME + default "bk4r1" + +config PCM052_DDR_SIZE + int + default 512 + +endif diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 7341899..e75ff4f 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -152,57 +152,6 @@ static struct ddrmc_phy_setting pcm052_phy_settings[] = {

int dram_init(void) { - static const struct ddr3_jedec_timings pcm052_ddr_timings = { - .tinit = 5, - .trst_pwron = 80000, - .cke_inactive = 200000, - .wrlat = 5, - .caslat_lin = 12, - .trc = 6, - .trrd = 4, - .tccd = 4, - .tbst_int_interval = 4, - .tfaw = 18, - .trp = 6, - .twtr = 4, - .tras_min = 15, - .tmrd = 4, - .trtp = 4, - .tras_max = 14040, - .tmod = 12, - .tckesr = 4, - .tcke = 3, - .trcd_int = 6, - .tras_lockout = 1, - .tdal = 10, - .bstlen = 3, - .tdll = 512, - .trp_ab = 6, - .tref = 1542, - .trfc = 64, - .tref_int = 5, - .tpdex = 3, - .txpdll = 10, - .txsnr = 68, - .txsr = 506, - .cksrx = 5, - .cksre = 5, - .freq_chg_en = 1, - .zqcl = 256, - .zqinit = 512, - .zqcs = 64, - .ref_per_zq = 64, - .zqcs_rotate = 1, - .aprebit = 10, - .cmd_age_cnt = 255, - .age_cnt = 255, - .q_fullness = 0, - .odt_rd_mapcs0 = 1, - .odt_wr_mapcs0 = 1, - .wlmrd = 40, - .wldqsen = 25, - }; - static const iomux_v3_cfg_t pcm052_pads[] = { PCM052_VF610_PAD_DDR_A15__DDR_A_15, PCM052_VF610_PAD_DDR_A14__DDR_A_14, @@ -256,11 +205,126 @@ int dram_init(void) PCM052_VF610_PAD_DDR_RESETB, };

- imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); +#if defined(CONFIG_TARGET_PCM052) + + static const struct ddr3_jedec_timings pcm052_ddr_timings = { + .tinit = 5, + .trst_pwron = 80000, + .cke_inactive = 200000, + .wrlat = 5, + .caslat_lin = 12, + .trc = 6, + .trrd = 4, + .tccd = 4, + .tbst_int_interval = 4, + .tfaw = 18, + .trp = 6, + .twtr = 4, + .tras_min = 15, + .tmrd = 4, + .trtp = 4, + .tras_max = 14040, + .tmod = 12, + .tckesr = 4, + .tcke = 3, + .trcd_int = 6, + .tras_lockout = 1, + .tdal = 10, + .bstlen = 3, + .tdll = 512, + .trp_ab = 6, + .tref = 1542, + .trfc = 64, + .tref_int = 5, + .tpdex = 3, + .txpdll = 10, + .txsnr = 68, + .txsr = 506, + .cksrx = 5, + .cksre = 5, + .freq_chg_en = 1, + .zqcl = 256, + .zqinit = 512, + .zqcs = 64, + .ref_per_zq = 64, + .zqcs_rotate = 1, + .aprebit = 10, + .cmd_age_cnt = 255, + .age_cnt = 255, + .q_fullness = 0, + .odt_rd_mapcs0 = 1, + .odt_wr_mapcs0 = 1, + .wlmrd = 40, + .wldqsen = 25, + };

ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, pcm052_phy_settings, 1, 2);

+#elif defined(CONFIG_TARGET_BK4R1) + + static const struct ddr3_jedec_timings pcm052_ddr_timings = { + .tinit = 5, + .trst_pwron = 80000, + .cke_inactive = 200000, + .wrlat = 5, + .caslat_lin = 12, + .trc = 6, + .trrd = 4, + .tccd = 4, + .tbst_int_interval = 0, + .tfaw = 16, + .trp = 6, + .twtr = 4, + .tras_min = 15, + .tmrd = 4, + .trtp = 4, + .tras_max = 28080, + .tmod = 12, + .tckesr = 4, + .tcke = 3, + .trcd_int = 6, + .tras_lockout = 1, + .tdal = 12, + .bstlen = 3, + .tdll = 512, + .trp_ab = 6, + .tref = 3120, + .trfc = 104, + .tref_int = 0, + .tpdex = 3, + .txpdll = 10, + .txsnr = 108, + .txsr = 512, + .cksrx = 5, + .cksre = 5, + .freq_chg_en = 1, + .zqcl = 256, + .zqinit = 512, + .zqcs = 64, + .ref_per_zq = 64, + .zqcs_rotate = 1, + .aprebit = 10, + .cmd_age_cnt = 255, + .age_cnt = 255, + .q_fullness = 0, + .odt_rd_mapcs0 = 1, + .odt_wr_mapcs0 = 1, + .wlmrd = 40, + .wldqsen = 25, + }; + + ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, + pcm052_phy_settings, 1, 1); + +#else /* Unknown PCM052 variant */ + +#error DDR characteristics undefined for this target. Please define them. + +#endif + + imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

return 0; diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig new file mode 100644 index 0000000..3994459 --- /dev/null +++ b/configs/bk4r1_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_TARGET_BK4R1=y +CONFIG_DEFAULT_DEVICE_TREE="bk4r1" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_VYBRID_GPIO=y +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_BUSWIDTH_16BIT=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_CMD_DM=y diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h new file mode 100644 index 0000000..5861eeb --- /dev/null +++ b/include/configs/bk4r1.h @@ -0,0 +1,33 @@ +/* + * Copyright 2016 3ADEV http://3adev.com + * Written-by: Albert ARIBAUD albert.aribaud@3adev.fr + * + * Configuration settings for the phytec PCM-052 SoM-based BK4R1. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Define the BK4r1-specific env commands */ +#define PCM052_EXTRA_ENV_SETTINGS \ + "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \ + "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0" + +/* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/ +#define PCM052_BOOTCOMMAND "run set_gpio103; sf probe; " + +/* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */ +#define PCM052_NET_INIT "run set_gpio122; " + +/* add NOR to MTD env */ +#define MTDIDS_DEFAULT "nand0=NAND,nor0=NOR" +#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\ + ",128k(env1)"\ + ",128k(env2)"\ + ",128k(dtb)"\ + ",6144k(kernel)"\ + ",-(root);"\ + "NOR:-(nor)" + +/* now include standard PCM052 config */ + +#include "configs/pcm052.h" diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index b3e5054..75848d3 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -53,7 +53,12 @@ #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_PARTITIONS #define CONFIG_MTD_DEVICE + +#ifndef MTDIDS_DEFAULT #define MTDIDS_DEFAULT "nand0=NAND" +#endif + +#ifndef MTDPARTS_DEFAULT #define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\ ",128k(env1)"\ ",128k(env2)"\ @@ -62,6 +67,8 @@ ",-(root)" #endif

+#endif + #define CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -86,7 +93,6 @@ /* QSPI Configs*/

#ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SYS_FSL_QSPI_LE @@ -116,8 +122,31 @@ #define CONFIG_SYS_TEXT_BASE 0x3f408000 #define CONFIG_BOARD_SIZE_LIMIT 524288

-#define CONFIG_BOOTCOMMAND "run bootcmd_sd" +/* if no target-specific extra environment settings were defined by the + target, define an empty one */ +#ifndef PCM052_EXTRA_ENV_SETTINGS +#define PCM052_EXTRA_ENV_SETTINGS +#endif + +/* if no target-specific boot command was defined by the target, + define an empty one */ +#ifndef PCM052_BOOTCOMMAND +#define PCM052_BOOTCOMMAND +#endif + +/* if no target-specific extra environment settings were defined by the + target, define an empty one */ +#ifndef PCM052_NET_INIT +#define PCM052_NET_INIT +#endif + +/* boot command, including the target-defined one if any */ +#define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand" + +/* Extra env settings (including the target-defined ones if any) */ #define CONFIG_EXTRA_ENV_SETTINGS \ + PCM052_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "blimg_file=u-boot.vyb\0" \ @@ -164,7 +193,8 @@ "nand read ${kernel_addr} kernel; " \ "nand read ${ram_addr} root; " \ "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ - "update_bootloader_from_tftp=if tftp ${blimg_addr} "\ + "update_bootloader_from_tftp=" PCM052_NET_INIT \ + "if tftp ${blimg_addr} "\ "${tftpdir}${blimg_file}; then " \ "mtdparts default; " \ "nand erase.part bootloader; " \ @@ -177,7 +207,8 @@ "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \ "nand erase.part dtb; " \ "nand write ${fdt_addr} dtb ${filesize}; fi\0" \ - "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ + "update_kernel_from_tftp=" PCM052_NET_INIT \ + "if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ "then setenv fdtsize ${filesize}; " \ "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \ "mtdparts default; " \ @@ -185,13 +216,15 @@ "nand write ${fdt_addr} dtb ${fdtsize}; " \ "nand erase.part kernel; " \ "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \ - "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \ + "update_rootfs_from_tftp=" PCM052_NET_INIT \ + "if tftp ${sys_addr} ${tftpdir}${filesys}; " \ "then mtdparts default; " \ "nand erase.part root; " \ "ubi part root; " \ "ubi create rootfs; " \ "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \ - "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ + "update_ramdisk_from_tftp=" PCM052_NET_INIT \ + "if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ "then mtdparts default; " \ "nand erase.part root; " \ "nand write ${ram_addr} root ${filesize}; fi\0"

Hi Stefano,

Le Thu, 6 Oct 2016 09:21:13 +0200, Stefano Babic sbabic@denx.de a écrit :

Hi Albert,

On 26/09/2016 09:08, Albert ARIBAUD (3ADEV) wrote:

...

BK4R1 is basically PCM052 with the following differences or quirks:

1. it has 512MB of DDR using MT41K256M16HA_125IT, while the PCM052 has 256MB using MT41J128M16HA_15EIT;

2. it has 1GB of NAND. The size increase is supported by the env directly;

3. its Ethernet ports are physicaly tied together until GPIO 122 is raised. As this is a safety feature U-Boot does not untie the ports except if it needs networking, for instance when doing NAND updates via TFTP;

4. it has a USB hub which may remain in reset if GPIO 130 is not raised. This is done unconditionally at boot;

5. It has two NOR SPI flash chips on QSPI.

This series has been run through checkpatch and has no errors or warning except the following one:

    warning: arch/arm/Kconfig,681: please write a
    paragraph that describes the config symbol fully

Which I believe does not apply, as target configs in this file never have descriptions.

Albert ARIBAUD (3ADEV) (6): pcm052: fix MTD partitioning pcm052: remove target-specific dtb name from env pcm052: add 'm4go' command tools: mkimage: add support for Vybrid image format pcm052: allow specifying onboard DDR size in configs pcm052: add new BK4r1 target based on PCM052 SoM

Makefile | 6 ++ arch/arm/Kconfig | 4 + arch/arm/config.mk | 3 + arch/arm/cpu/armv7/vf610/Makefile | 5 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/bk4r1.dts | 48 +++++++++ arch/arm/dts/vf.dtsi | 4 +- board/phytec/pcm052/Kconfig | 24 +++++ board/phytec/pcm052/pcm052.c | 206 ++++++++++++++++++++++++++++---------- common/image.c | 1 + configs/bk4r1_defconfig | 32 ++++++ include/configs/bk4r1.h | 33 ++++++ include/configs/pcm052.h | 78 ++++++++++----- include/image.h | 1 + tools/Makefile | 1 + tools/vybridimage.c | 164 ++++++++++++++++++++++++++++++ 16 files changed, 535 insertions(+), 78 deletions(-) create mode 100644 arch/arm/dts/bk4r1.dts create mode 100644 configs/bk4r1_defconfig create mode 100644 include/configs/bk4r1.h create mode 100644 tools/vybridimage.c

It looks like that CONFIG_CMD_UBI for bk4r1 is not set and I get build errors.

Hmm... What U-Boot commit do you apply above?

Is it ok for you if I add directly this by applying ?

I'll check this and let you know later today.

diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 3994459..26d9e81 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -30,3 +30,4 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MTD=y CONFIG_CMD_DM=y +CONFIG_CMD_UBI=y

Regards, Stefano

Cordialement, Albert ARIBAUD 3ADEV