Not all ARM V7 based cpus has VBAR for remapping vector base address. So, update VBAR only if it available.

Reviewed-by: Tom Rini trini@konsulko.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/start.S | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7e2695761e..937f7051fe 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -73,9 +73,11 @@ switch_to_hypervisor_ret: bic r0, #CR_V @ V = 0 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register

+#ifdef CONFIG_HAS_VBAR /* Set vector address in CP15 VBAR register */ ldr r0, =_start mcr p15, 0, r0, c12, c0, 0 @Set VBAR +#endif #endif

/* the mask ROM code should have PLL and others stable */

Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols.

As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder.

Reviewed-by: Tom Rini trini@konsulko.com Tested-by: Michal Simek michal.simek@xilinx.com Suggested-by: Alexander Graf agraf@suse.de Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/Kconfig | 54 ++++++++++++++++----------------- arch/arm/Makefile | 6 ++-- arch/arm/cpu/armv7/Kconfig | 4 +-- arch/arm/include/asm/system.h | 4 +-- arch/arm/lib/cache-cp15.c | 2 +- arch/arm/mach-at91/Kconfig | 12 ++++---- arch/arm/mach-at91/Makefile | 2 +- arch/arm/mach-at91/config.mk | 2 +- arch/arm/mach-bcm283x/Kconfig | 4 +-- arch/arm/mach-exynos/Kconfig | 4 +-- arch/arm/mach-exynos/Makefile | 2 +- arch/arm/mach-exynos/soc.c | 2 +- arch/arm/mach-mvebu/Kconfig | 2 +- arch/arm/mach-qemu/Kconfig | 2 +- arch/arm/mach-rmobile/Kconfig | 2 +- arch/arm/mach-rockchip/Kconfig | 12 ++++---- arch/arm/mach-stm32mp/Kconfig | 2 +- arch/arm/mach-sunxi/Kconfig | 22 +++++++------- arch/arm/mach-tegra/Kconfig | 2 +- arch/arm/mach-uniphier/Kconfig | 2 +- arch/arm/mach-uniphier/Makefile | 2 +- cmd/Kconfig | 2 +- drivers/serial/arm_dcc.c | 2 +- 23 files changed, 75 insertions(+), 75 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7212fc5afa..df475626e7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -180,7 +180,7 @@ config CPU_ARM1176 select HAS_VBAR select SYS_CACHE_SHIFT_5

-config CPU_V7 +config CPU_V7A bool select HAS_VBAR select HAS_THUMB2 @@ -207,7 +207,7 @@ config SYS_CPU default "arm946es" if CPU_ARM946ES default "arm1136" if CPU_ARM1136 default "arm1176" if CPU_ARM1176 - default "armv7" if CPU_V7 + default "armv7" if CPU_V7A default "armv7m" if CPU_V7M default "pxa" if CPU_PXA default "sa1100" if CPU_SA1100 @@ -221,7 +221,7 @@ config SYS_ARM_ARCH default 5 if CPU_ARM946ES default 6 if CPU_ARM1136 default 6 if CPU_ARM1176 - default 7 if CPU_V7 + default 7 if CPU_V7A default 7 if CPU_V7M default 5 if CPU_PXA default 4 if CPU_SA1100 @@ -244,7 +244,7 @@ config SYS_CACHELINE_SIZE

config ARM_SMCCC bool "Support for ARM SMC Calling Convention (SMCCC)" - depends on CPU_V7 || ARM64 + depends on CPU_V7A || ARM64 select ARM_PSCI_FW help Say Y here if you want to enable ARM SMC Calling Convention. @@ -429,7 +429,7 @@ config TARGET_SPEAR600

config TARGET_STV0991 bool "Support stv0991" - select CPU_V7 + select CPU_V7A select DM select DM_SERIAL select DM_SPI @@ -481,36 +481,36 @@ config ARCH_BCM283X

config TARGET_VEXPRESS_CA15_TC2 bool "Support vexpress_ca15_tc2" - select CPU_V7 + select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select PL011_SERIAL

config TARGET_VEXPRESS_CA5X2 bool "Support vexpress_ca5x2" - select CPU_V7 + select CPU_V7A select PL011_SERIAL

config TARGET_VEXPRESS_CA9X4 bool "Support vexpress_ca9x4" - select CPU_V7 + select CPU_V7A select PL011_SERIAL

config TARGET_BCM23550_W1D bool "Support bcm23550_w1d" - select CPU_V7 + select CPU_V7A imply CRC32_VERIFY imply FAT_WRITE

config TARGET_BCM28155_AP bool "Support bcm28155_ap" - select CPU_V7 + select CPU_V7A imply CRC32_VERIFY imply FAT_WRITE

config TARGET_BCMCYGNUS bool "Support bcmcygnus" - select CPU_V7 + select CPU_V7A imply CRC32_VERIFY imply CMD_HASH imply FAT_WRITE @@ -521,7 +521,7 @@ config TARGET_BCMCYGNUS

config TARGET_BCMNSP bool "Support bcmnsp" - select CPU_V7 + select CPU_V7A

config TARGET_BCMNS2 bool "Support Broadcom Northstar2" @@ -544,7 +544,7 @@ config ARCH_EXYNOS

config ARCH_S5PC1XX bool "Samsung S5PC1XX" - select CPU_V7 + select CPU_V7A select DM select DM_SERIAL select DM_GPIO @@ -552,7 +552,7 @@ config ARCH_S5PC1XX

config ARCH_HIGHBANK bool "Calxeda Highbank" - select CPU_V7 + select CPU_V7A select PL011_SERIAL

config ARCH_INTEGRATOR @@ -563,7 +563,7 @@ config ARCH_INTEGRATOR

config ARCH_KEYSTONE bool "TI Keystone" - select CPU_V7 + select CPU_V7A select SUPPORT_SPL select SYS_THUMB_BUILD select CMD_POWEROFF @@ -573,7 +573,7 @@ config ARCH_KEYSTONE

config ARCH_OMAP2PLUS bool "TI OMAP2+" - select CPU_V7 + select CPU_V7A select SPL_BOARD_INIT if SPL select SPL_STACK_R if SPL select SUPPORT_SPL @@ -611,13 +611,13 @@ config ARCH_MX28

config ARCH_MX7ULP bool "NXP MX7ULP" - select CPU_V7 + select CPU_V7A select ROM_UNIFIED_SECTIONS imply MXC_GPIO

config ARCH_MX7 bool "Freescale MX7" - select CPU_V7 + select CPU_V7A select SYS_FSL_HAS_SEC if SECURE_BOOT select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -627,7 +627,7 @@ config ARCH_MX7

config ARCH_MX6 bool "Freescale MX6" - select CPU_V7 + select CPU_V7A select SYS_FSL_HAS_SEC if SECURE_BOOT select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -641,7 +641,7 @@ endif

config ARCH_MX5 bool "Freescale MX5" - select CPU_V7 + select CPU_V7A select BOARD_EARLY_INIT_F imply MXC_GPIO

@@ -677,7 +677,7 @@ config ARCH_SNAPDRAGON

config ARCH_SOCFPGA bool "Altera SOCFPGA family" - select CPU_V7 + select CPU_V7A select SUPPORT_SPL select OF_CONTROL select SPL_OF_CONTROL @@ -734,7 +734,7 @@ config ARCH_SUNXI

config ARCH_VF610 bool "Freescale Vybrid" - select CPU_V7 + select CPU_V7A select SYS_FSL_ERRATUM_ESDHC111 imply CMD_MTDPARTS imply NAND @@ -742,7 +742,7 @@ config ARCH_VF610 config ARCH_ZYNQ bool "Xilinx Zynq based platform" select BOARD_LATE_INIT - select CPU_V7 + select CPU_V7A select SUPPORT_SPL select OF_CONTROL select SPL_BOARD_INIT if SPL @@ -982,7 +982,7 @@ config TARGET_LS1088ARDB config TARGET_LS1021AQDS bool "Support ls1021aqds" select BOARD_LATE_INIT - select CPU_V7 + select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select SUPPORT_SPL @@ -996,7 +996,7 @@ config TARGET_LS1021AQDS config TARGET_LS1021ATWR bool "Support ls1021atwr" select BOARD_LATE_INIT - select CPU_V7 + select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select SUPPORT_SPL @@ -1009,7 +1009,7 @@ config TARGET_LS1021ATWR config TARGET_LS1021AIOT bool "Support ls1021aiot" select BOARD_LATE_INIT - select CPU_V7 + select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select SUPPORT_SPL @@ -1125,7 +1125,7 @@ config STM32

config ARCH_STI bool "Support STMicrolectronics SoCs" - select CPU_V7 + select CPU_V7A select DM select DM_SERIAL select BLK diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4fa8b38397..2979ad86fd 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -3,7 +3,7 @@ #

ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy) -CONFIG_CPU_V7= +CONFIG_CPU_V7A= CONFIG_CPU_ARM720T=y endif

@@ -16,7 +16,7 @@ arch-$(CONFIG_CPU_SA1100) =-march=armv4 arch-$(CONFIG_CPU_PXA) = arch-$(CONFIG_CPU_ARM1136) =-march=armv5 arch-$(CONFIG_CPU_ARM1176) =-march=armv5t -arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, \ +arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \ $(call cc-option, -march=armv7, -march=armv5)) arch-$(CONFIG_ARM64) =-march=armv8-a

@@ -40,7 +40,7 @@ tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100 tune-$(CONFIG_CPU_PXA) =-mcpu=xscale tune-$(CONFIG_CPU_ARM1136) = tune-$(CONFIG_CPU_ARM1176) = -tune-$(CONFIG_CPU_V7) = +tune-$(CONFIG_CPU_V7A) = tune-$(CONFIG_ARM64) =

# Evaluate tune cc-option calls now diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index b9c4f4e79b..37a0be932e 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -1,4 +1,4 @@ -if CPU_V7 +if CPU_V7A

config CPU_V7_HAS_NONSEC bool @@ -52,7 +52,7 @@ config ARMV7_PSCI_NR_CPUS

config ARMV7_LPAE bool "Use LPAE page table format" if EXPERT - depends on CPU_V7 + depends on CPU_V7A default n ---help--- Say Y here to use the long descriptor page table format. This is diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 4f043cad0b..c1f87f9caf 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -451,7 +451,7 @@ enum dcache_option { DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2), DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3), }; -#elif defined(CONFIG_CPU_V7) +#elif defined(CONFIG_CPU_V7A) /* Short-Descriptor Translation Table Level 1 Bits */ #define TTB_SECT_NS_MASK (1 << 19) #define TTB_SECT_NG_MASK (1 << 17) @@ -493,7 +493,7 @@ enum { MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, };

-#ifdef CONFIG_CPU_V7 +#ifdef CONFIG_CPU_V7A /* TTBR0 bits */ #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 #define TTBR0_RGN_NC (0 << 3) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f0c1b03728..b09c631636 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -161,7 +161,7 @@ static inline void mmu_setup(void) asm volatile("mcr p15, 0, %0, c10, c2, 0" : : "r" (MEMORY_ATTRIBUTES) : "memory"); } -#elif defined(CONFIG_CPU_V7) +#elif defined(CONFIG_CPU_V7A) if (is_hyp()) { /* Set HTCR to disable LPAE */ asm volatile("mcr p15, 4, %0, c2, c0, 2" diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 3621dfa760..6f046875ab 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -45,15 +45,15 @@ config AT91SAM9X5

config SAMA5D2 bool - select CPU_V7 + select CPU_V7A

config SAMA5D3 bool - select CPU_V7 + select CPU_V7A

config SAMA5D4 bool - select CPU_V7 + select CPU_V7A

choice prompt "Atmel AT91 board select" @@ -158,7 +158,7 @@ config TARGET_SAMA5D2_XPLAINED

config TARGET_SAMA5D27_SOM1_EK bool "SAMA5D27 SOM1 EK board" - select CPU_V7 + select CPU_V7A select SUPPORT_SPL select BOARD_EARLY_INIT_F select BOARD_LATE_INIT @@ -250,7 +250,7 @@ config TARGET_WB45N config TARGET_WB50N bool "Support Laird WB50N" select BOARD_LATE_INIT - select CPU_V7 + select CPU_V7A select SUPPORT_SPL select BOARD_EARLY_INIT_F

@@ -293,6 +293,6 @@ source "board/laird/wb50n/Kconfig"

config SPL_LDSCRIPT default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS - default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if CPU_V7 + default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if CPU_V7A

endif diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index a908004b0a..2733a0bc7f 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -18,4 +18,4 @@ endif obj-y += clock.o obj-$(CONFIG_CPU_ARM920T) += arm920t/ obj-$(CONFIG_CPU_ARM926EJS) += arm926ejs/ -obj-$(CONFIG_CPU_V7) += armv7/ +obj-$(CONFIG_CPU_V7A) += armv7/ diff --git a/arch/arm/mach-at91/config.mk b/arch/arm/mach-at91/config.mk index 7168abbd58..9a023efb19 100644 --- a/arch/arm/mach-at91/config.mk +++ b/arch/arm/mach-at91/config.mk @@ -2,7 +2,7 @@ ifeq ($(CONFIG_CPU_ARM926EJS),y) PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) endif

-ifeq ($(CONFIG_CPU_V7),y) +ifeq ($(CONFIG_CPU_V7A),y) ifndef CONFIG_SPL_BUILD ALL-y += u-boot.img endif diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index a78239d63e..821caedbf7 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -7,7 +7,7 @@ config BCM2836 bool "Broadcom BCM2836 SoC support" depends on ARCH_BCM283X select ARMV7_LPAE - select CPU_V7 + select CPU_V7A

config BCM2837 bool "Broadcom BCM2837 SoC support" @@ -18,7 +18,7 @@ config BCM2837_32B depends on ARCH_BCM283X select BCM2837 select ARMV7_LPAE - select CPU_V7 + select CPU_V7A

config BCM2837_64B bool "Broadcom BCM2837 SoC 64-bit support" diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 5ac047d892..65d9168ae2 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -6,7 +6,7 @@ choice

config ARCH_EXYNOS4 bool "Exynos4 SoC family" - select CPU_V7 + select CPU_V7A select BOARD_EARLY_INIT_F help Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There @@ -15,7 +15,7 @@ config ARCH_EXYNOS4

config ARCH_EXYNOS5 bool "Exynos5 SoC family" - select CPU_V7 + select CPU_V7A select BOARD_EARLY_INIT_F select SHA_HW_ACCEL imply CRC32_VERIFY diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 0cc6c3253a..49a3e22927 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -6,7 +6,7 @@ #

obj-y += soc.o -obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o system.o +obj-$(CONFIG_CPU_V7A) += clock.o pinmux.o power.o system.o obj-$(CONFIG_ARM64) += mmu-arm64.o

obj-$(CONFIG_EXYNOS5420) += sec_boot.o diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index cf149ad1a8..181656e7b0 100644 --- a/arch/arm/mach-exynos/soc.c +++ b/arch/arm/mach-exynos/soc.c @@ -21,7 +21,7 @@ void *secondary_boot_addr = (void *)_main;

void reset_cpu(ulong addr) { -#ifdef CONFIG_CPU_V7 +#ifdef CONFIG_CPU_V7A writel(0x1, samsung_get_base_swreset()); #endif } diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 01d700bf2e..ec42cf9044 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -6,7 +6,7 @@ config HAVE_MVEBU_EFUSE

config ARMADA_32BIT bool - select CPU_V7 + select CPU_V7A select SUPPORT_SPL select SPL_DM select SPL_DM_SEQ_ALIAS diff --git a/arch/arm/mach-qemu/Kconfig b/arch/arm/mach-qemu/Kconfig index 133163aecf..dfc43999a2 100644 --- a/arch/arm/mach-qemu/Kconfig +++ b/arch/arm/mach-qemu/Kconfig @@ -14,7 +14,7 @@ endif config TARGET_QEMU_ARM_32BIT bool "Support qemu_arm" depends on ARCH_QEMU - select CPU_V7 + select CPU_V7A select ARCH_SUPPORT_PSCI

config TARGET_QEMU_ARM_64BIT diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 4b05d78839..fc4b3c3219 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -6,7 +6,7 @@ choice

config RCAR_32 bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)" - select CPU_V7 + select CPU_V7A

config RCAR_GEN3 bool "Renesas ARM SoCs R-Car Gen3 (64bit)" diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 0adaed4367..34bc895967 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -2,7 +2,7 @@ if ARCH_ROCKCHIP

config ROCKCHIP_RK3036 bool "Support Rockchip RK3036" - select CPU_V7 + select CPU_V7A select SUPPORT_SPL select SPL imply USB_FUNCTION_ROCKUSB @@ -15,7 +15,7 @@ config ROCKCHIP_RK3036

config ROCKCHIP_RK3128 bool "Support Rockchip RK3128" - select CPU_V7 + select CPU_V7A help The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options @@ -24,7 +24,7 @@ config ROCKCHIP_RK3128

config ROCKCHIP_RK3188 bool "Support Rockchip RK3188" - select CPU_V7 + select CPU_V7A select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SPL @@ -46,7 +46,7 @@ config ROCKCHIP_RK3188

config ROCKCHIP_RK322X bool "Support Rockchip RK3228/RK3229" - select CPU_V7 + select CPU_V7A select SUPPORT_SPL select SPL select ROCKCHIP_BROM_HELPER @@ -59,7 +59,7 @@ config ROCKCHIP_RK322X

config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" - select CPU_V7 + select CPU_V7A select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SPL @@ -152,7 +152,7 @@ config ROCKCHIP_RK3399

config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" - select CPU_V7 + select CPU_V7A help The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 8ca97bf0c9..bb3e287a55 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -24,7 +24,7 @@ config SYS_SOC

config TARGET_STM32MP1 bool "Support stm32mp1xx" - select CPU_V7 + select CPU_V7A select PINCTRL_STM32 select STM32_RESET select SYSRESET_SYSCON diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index b868f0e350..f0c9d1b058 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -136,7 +136,7 @@ choice

config MACH_SUN4I bool "sun4i (Allwinner A10)" - select CPU_V7 + select CPU_V7A select ARM_CORTEX_CPU_IS_UP select DRAM_SUN4I select SUNXI_GEN_SUN4I @@ -144,7 +144,7 @@ config MACH_SUN4I

config MACH_SUN5I bool "sun5i (Allwinner A13)" - select CPU_V7 + select CPU_V7A select ARM_CORTEX_CPU_IS_UP select DRAM_SUN4I select SUNXI_GEN_SUN4I @@ -153,7 +153,7 @@ config MACH_SUN5I

config MACH_SUN6I bool "sun6i (Allwinner A31)" - select CPU_V7 + select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI @@ -166,7 +166,7 @@ config MACH_SUN6I

config MACH_SUN7I bool "sun7i (Allwinner A20)" - select CPU_V7 + select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI @@ -177,7 +177,7 @@ config MACH_SUN7I

config MACH_SUN8I_A23 bool "sun8i (Allwinner A23)" - select CPU_V7 + select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI @@ -189,7 +189,7 @@ config MACH_SUN8I_A23

config MACH_SUN8I_A33 bool "sun8i (Allwinner A33)" - select CPU_V7 + select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI @@ -201,7 +201,7 @@ config MACH_SUN8I_A33

config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" - select CPU_V7 + select CPU_V7A select DRAM_SUN8I_A83T select SUNXI_GEN_SUN6I select MMC_SUNXI_HAS_NEW_MODE @@ -209,7 +209,7 @@ config MACH_SUN8I_A83T

config MACH_SUN8I_H3 bool "sun8i (Allwinner H3)" - select CPU_V7 + select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI @@ -218,7 +218,7 @@ config MACH_SUN8I_H3

config MACH_SUN8I_R40 bool "sun8i (Allwinner R40)" - select CPU_V7 + select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI @@ -229,7 +229,7 @@ config MACH_SUN8I_R40

config MACH_SUN8I_V3S bool "sun8i (Allwinner V3s)" - select CPU_V7 + select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI @@ -241,7 +241,7 @@ config MACH_SUN8I_V3S

config MACH_SUN9I bool "sun9i (Allwinner A80)" - select CPU_V7 + select CPU_V7A select DRAM_SUN9I select SUN6I_PRCM select SUNXI_HIGH_SRAM diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index fd0082d22a..d565f5d331 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -49,7 +49,7 @@ config TEGRA_NO_BPMP

config TEGRA_ARMV7_COMMON bool "Tegra 32-bit common options" - select CPU_V7 + select CPU_V7A select SPL select SPL_BOARD_INIT if SPL select SUPPORT_SPL diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index cc759b3e01..91bea776e6 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -5,7 +5,7 @@ config SYS_CONFIG_NAME

config ARCH_UNIPHIER_32BIT bool - select CPU_V7 + select CPU_V7A select CPU_V7_HAS_NONSEC select ARMV7_NONSEC select ARCH_SUPPORT_PSCI diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 7a0b25ad51..16890da22c 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -33,5 +33,5 @@ obj-y += dram/

obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/

-obj-$(CONFIG_CPU_V7) += arm32/ +obj-$(CONFIG_CPU_V7A) += arm32/ obj-$(CONFIG_ARM64) += arm64/ diff --git a/cmd/Kconfig b/cmd/Kconfig index bc1d2f31c0..511d9117a0 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1103,7 +1103,7 @@ config BOOTP_PXE_CLIENTARCH config BOOTP_VCI_STRING string depends on CMD_BOOTP - default "U-Boot.armv7" if CPU_V7 || CPU_V7M + default "U-Boot.armv7" if CPU_V7A || CPU_V7M default "U-Boot.armv8" if ARM64 default "U-Boot.arm" if ARM default "U-Boot" diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index 07981e18ee..b6769a94cf 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -20,7 +20,7 @@ #include <dm.h> #include <serial.h>

-#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7) +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7A) /* * ARMV6 & ARMV7 */

Add a Kconfig entry for MMU and imply for all platforms using cache-cp15.c containing MMU setup. Using imply instead of select so that MMU can be disabled by defconfigs when not needed.

Tested-by: Michal Simek michal.simek@xilinx.com Reviewed-by: Tom Rini trini@konsulko.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/Kconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index df475626e7..8854227d9a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -74,6 +74,12 @@ config ARM_ASM_UNIFIED config THUMB2_KERNEL bool

+config SYS_ARM_MMU + bool "MMU-based Paged Memory Management Support" + help + Select if you want MMU-based virtualised addressing space + support by paged memory management. + # If set, the workarounds for these ARM errata are applied early during U-Boot # startup. Note that in general these options force the workarounds to be # applied; no CPU-type/version detection exists, unlike the similar options in @@ -158,33 +164,40 @@ config ARM_ERRATA_855873 config CPU_ARM720T bool select SYS_CACHE_SHIFT_5 + imply SYS_ARM_MMU

config CPU_ARM920T bool select SYS_CACHE_SHIFT_5 + imply SYS_ARM_MMU

config CPU_ARM926EJS bool select SYS_CACHE_SHIFT_5 + imply SYS_ARM_MMU

config CPU_ARM946ES bool select SYS_CACHE_SHIFT_5 + imply SYS_ARM_MMU

config CPU_ARM1136 bool select SYS_CACHE_SHIFT_5 + imply SYS_ARM_MMU

config CPU_ARM1176 bool select HAS_VBAR select SYS_CACHE_SHIFT_5 + imply SYS_ARM_MMU

config CPU_V7A bool select HAS_VBAR select HAS_THUMB2 select SYS_CACHE_SHIFT_6 + imply SYS_ARM_MMU

config CPU_V7M bool @@ -195,10 +208,12 @@ config CPU_V7M config CPU_PXA bool select SYS_CACHE_SHIFT_5 + imply SYS_ARM_MMU

config CPU_SA1100 bool select SYS_CACHE_SHIFT_5 + imply SYS_ARM_MMU

config SYS_CPU default "arm720t" if CPU_ARM720T

Certain ARM architectures like ARMv7-A, ARMv7-R has support for enabling caches using CP15 registers. To have a common support for all these architectures, introduce a Kconfig symbol SYS_ARM_CACHE_CP15 that selects cache-cp15.c

Tested-by: Michal Simek michal.simek@xilinx.com Reviewed-by: Tom Rini trini@konsulko.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/Kconfig | 7 +++++++ arch/arm/lib/Makefile | 6 +----- 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8854227d9a..8efaccbcb8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -74,8 +74,15 @@ config ARM_ASM_UNIFIED config THUMB2_KERNEL bool

+config SYS_ARM_CACHE_CP15 + bool "CP15 based cache enabling support" + help + Select this if your processor suports enabling caches by using + CP15 registers. + config SYS_ARM_MMU bool "MMU-based Paged Memory Management Support" + select SYS_ARM_CACHE_CP15 help Select if you want MMU-based virtualised addressing space support by paged memory management. diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 3d3085e917..39c0c693dc 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -63,11 +63,7 @@ obj-y += reset.o endif

obj-y += cache.o -ifndef CONFIG_ARM64 -ifndef CONFIG_CPU_V7M -obj-y += cache-cp15.o -endif -endif +obj-$(CONFIG_SYS_ARM_CACHE_CP15) += cache-cp15.o

obj-y += psci-dt.o

From: Michal Simek michal.simek@xilinx.com

The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput.

Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. So,reuse the same armv7 folder and introduce a new config CPU_V7R in order to differentiate from v7 based platforms.

Tested-by: Michal Simek michal.simek@xilinx.com Reviewed-by: Tom Rini trini@konsulko.com Signed-off-by: Michal Simek michal.simek@xilinx.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/Kconfig | 7 +++++++ arch/arm/Makefile | 2 ++ arch/arm/cpu/armv7/start.S | 2 ++ cmd/Kconfig | 2 +- 4 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8efaccbcb8..fcdbded22a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -212,6 +212,11 @@ config CPU_V7M select THUMB2_KERNEL select SYS_CACHE_SHIFT_5

+config CPU_V7R + bool + select HAS_THUMB2 + select SYS_CACHE_SHIFT_6 + config CPU_PXA bool select SYS_CACHE_SHIFT_5 @@ -230,6 +235,7 @@ config SYS_CPU default "arm1136" if CPU_ARM1136 default "arm1176" if CPU_ARM1176 default "armv7" if CPU_V7A + default "armv7" if CPU_V7R default "armv7m" if CPU_V7M default "pxa" if CPU_PXA default "sa1100" if CPU_SA1100 @@ -245,6 +251,7 @@ config SYS_ARM_ARCH default 6 if CPU_ARM1176 default 7 if CPU_V7A default 7 if CPU_V7M + default 7 if CPU_V7R default 5 if CPU_PXA default 4 if CPU_SA1100 default 8 if ARM64 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 2979ad86fd..3f5343bc01 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -18,6 +18,7 @@ arch-$(CONFIG_CPU_ARM1136) =-march=armv5 arch-$(CONFIG_CPU_ARM1176) =-march=armv5t arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \ $(call cc-option, -march=armv7, -march=armv5)) +arch-$(CONFIG_CPU_V7R) =-march=armv7-r arch-$(CONFIG_ARM64) =-march=armv8-a

# On Tegra systems we must build SPL for the armv4 core on the device @@ -41,6 +42,7 @@ tune-$(CONFIG_CPU_PXA) =-mcpu=xscale tune-$(CONFIG_CPU_ARM1136) = tune-$(CONFIG_CPU_ARM1176) = tune-$(CONFIG_CPU_V7A) = +tune-$(CONFIG_CPU_V7R) = tune-$(CONFIG_ARM64) =

# Evaluate tune cc-option calls now diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 937f7051fe..29b51f2a0f 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -82,7 +82,9 @@ switch_to_hypervisor_ret:

/* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_CPU_V7A bl cpu_init_cp15 +#endif #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY bl cpu_init_crit #endif diff --git a/cmd/Kconfig b/cmd/Kconfig index 511d9117a0..9c1115db59 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1103,7 +1103,7 @@ config BOOTP_PXE_CLIENTARCH config BOOTP_VCI_STRING string depends on CMD_BOOTP - default "U-Boot.armv7" if CPU_V7A || CPU_V7M + default "U-Boot.armv7" if CPU_V7A || CPU_V7M || CPU_V7R default "U-Boot.armv8" if ARM64 default "U-Boot.arm" if ARM default "U-Boot"

The Memory Protection Unit(MPU) allows to partition memory into regions and set individual protection attributes for each region. In absence of MPU a default map[1] will take effect. Add support for configuring MPU on Cortex-R, by reusing the existing support for Cortex-M processor.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I100240...

Tested-by: Michal Simek michal.simek@xilinx.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/Kconfig | 12 +++ arch/arm/cpu/armv7/Makefile | 2 + arch/arm/cpu/armv7/mpu_v7r.c | 109 +++++++++++++++++++++++++ arch/arm/cpu/armv7m/Makefile | 3 +- arch/arm/cpu/armv7m/mpu.c | 43 +--------- arch/arm/include/asm/armv7_mpu.h | 131 ++++++++++++++++++++++++++++++ arch/arm/include/asm/armv7m_mpu.h | 67 --------------- arch/arm/mach-stm32/soc.c | 2 +- 8 files changed, 259 insertions(+), 110 deletions(-) create mode 100644 arch/arm/cpu/armv7/mpu_v7r.c create mode 100644 arch/arm/include/asm/armv7_mpu.h delete mode 100644 arch/arm/include/asm/armv7m_mpu.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fcdbded22a..99fb11435b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -87,6 +87,15 @@ config SYS_ARM_MMU Select if you want MMU-based virtualised addressing space support by paged memory management.

+config SYS_ARM_MPU + bool 'Use the ARM v7 PMSA Compliant MPU' + help + Some ARM systems without an MMU have instead a Memory Protection + Unit (MPU) that defines the type and permissions for regions of + memory. + If your CPU has an MPU then you should choose 'y' here unless you + know that you do not want to use the MPU. + # If set, the workarounds for these ARM errata are applied early during U-Boot # startup. Note that in general these options force the workarounds to be # applied; no CPU-type/version detection exists, unlike the similar options in @@ -211,11 +220,14 @@ config CPU_V7M select HAS_THUMB2 select THUMB2_KERNEL select SYS_CACHE_SHIFT_5 + select SYS_ARM_MPU

config CPU_V7R bool select HAS_THUMB2 select SYS_CACHE_SHIFT_6 + select SYS_ARM_MPU + select SYS_ARM_CACHE_CP15

config CPU_PXA bool diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index b14ee54519..d085b3be93 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,6 +12,8 @@ obj-y += cache_v7.o cache_v7_asm.o obj-y += cpu.o cp15.o obj-y += syslib.o

+obj-$(CONFIG_SYS_ARM_MPU) += mpu_v7r.o + ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c new file mode 100644 index 0000000000..1576511ec5 --- /dev/null +++ b/arch/arm/cpu/armv7/mpu_v7r.c @@ -0,0 +1,109 @@ +/* + * Cortex-R Memory Protection Unit specific code + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla lokeshvutla@ti.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <asm/armv7.h> +#include <asm/system.h> +#include <asm/barriers.h> +#include <linux/compiler.h> + +#include <asm/armv7_mpu.h> + +/* MPU Type register definitions */ +#define MPUIR_S_SHIFT 0 +#define MPUIR_S_MASK BIT(MPUIR_S_SHIFT) +#define MPUIR_DREGION_SHIFT 8 +#define MPUIR_DREGION_MASK (0xff << 8) + +/** + * Note: + * The Memory Protection Unit(MPU) allows to partition memory into regions + * and set individual protection attributes for each region. In absence + * of MPU a default map[1] will take effect. make sure to run this code + * from a region which has execution permissions by default. + * [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I100240... + */ + +void disable_mpu(void) +{ + u32 reg; + + reg = get_cr(); + reg &= ~CR_M; + dsb(); + set_cr(reg); + isb(); +} + +void enable_mpu(void) +{ + u32 reg; + + reg = get_cr(); + reg |= CR_M; + dsb(); + set_cr(reg); + isb(); +} + +int mpu_enabled(void) +{ + return get_cr() & CR_M; +} + +void mpu_config(struct mpu_region_config *rgn) +{ + u32 attr, val; + + attr = get_attr_encoding(rgn->mr_attr); + + /* MPU Region Number Register */ + asm volatile ("mcr p15, 0, %0, c6, c2, 0" : : "r" (rgn->region_no)); + + /* MPU Region Base Address Register */ + asm volatile ("mcr p15, 0, %0, c6, c1, 0" : : "r" (rgn->start_addr)); + + /* MPU Region Size and Enable Register */ + if (rgn->reg_size) + val = (rgn->reg_size << REGION_SIZE_SHIFT) | ENABLE_REGION; + else + val = DISABLE_REGION; + asm volatile ("mcr p15, 0, %0, c6, c1, 2" : : "r" (val)); + + /* MPU Region Access Control Register */ + val = rgn->xn << XN_SHIFT | rgn->ap << AP_SHIFT | attr; + asm volatile ("mcr p15, 0, %0, c6, c1, 4" : : "r" (val)); +} + +void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns) +{ + u32 num, i; + + asm volatile ("mrc p15, 0, %0, c0, c0, 4" : "=r" (num)); + num = (num & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT; + /* Regions to be configured cannot be greater than available regions */ + if (num < num_rgns) + num_rgns = num; + /** + * Assuming dcache might not be enabled at this point, disabling + * and invalidating only icache. + */ + icache_disable(); + invalidate_icache_all(); + + disable_mpu(); + + for (i = 0; i < num_rgns; i++) + mpu_config(&rgns[i]); + + enable_mpu(); + + icache_enable(); +} diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile index 257fc7faf3..c1742cb967 100644 --- a/arch/arm/cpu/armv7m/Makefile +++ b/arch/arm/cpu/armv7m/Makefile @@ -6,5 +6,6 @@ #

extra-y := start.o -obj-y += cpu.o cache.o mpu.o +obj-y += cpu.o cache.o +obj-$(CONFIG_SYS_ARM_MPU) += mpu.o obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o diff --git a/arch/arm/cpu/armv7m/mpu.c b/arch/arm/cpu/armv7m/mpu.c index e4d090e5de..6c419e07f5 100644 --- a/arch/arm/cpu/armv7m/mpu.c +++ b/arch/arm/cpu/armv7m/mpu.c @@ -7,7 +7,7 @@

#include <linux/bitops.h> #include <asm/armv7m.h> -#include <asm/armv7m_mpu.h> +#include <asm/armv7_mpu.h> #include <asm/io.h>

#define V7M_MPU_CTRL_ENABLE BIT(0) @@ -16,20 +16,6 @@ #define V7M_MPU_CTRL_PRIVDEFENA BIT(2) #define VALID_REGION BIT(4)

-#define ENABLE_REGION BIT(0) - -#define AP_SHIFT 24 -#define XN_SHIFT 28 -#define TEX_SHIFT 19 -#define S_SHIFT 18 -#define C_SHIFT 17 -#define B_SHIFT 16 -#define REGION_SIZE_SHIFT 1 - -#define CACHEABLE (1 << C_SHIFT) -#define BUFFERABLE (1 << B_SHIFT) -#define SHAREABLE (1 << S_SHIFT) - void disable_mpu(void) { writel(0, &V7M_MPU->ctrl); @@ -48,32 +34,7 @@ void mpu_config(struct mpu_region_config *reg_config) { uint32_t attr;

- switch (reg_config->mr_attr) { - case STRONG_ORDER: - attr = SHAREABLE; - break; - case SHARED_WRITE_BUFFERED: - attr = BUFFERABLE; - break; - case O_I_WT_NO_WR_ALLOC: - attr = CACHEABLE; - break; - case O_I_WB_NO_WR_ALLOC: - attr = CACHEABLE | BUFFERABLE; - break; - case O_I_NON_CACHEABLE: - attr = 1 << TEX_SHIFT; - break; - case O_I_WB_RD_WR_ALLOC: - attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE; - break; - case DEVICE_NON_SHARED: - attr = (2 << TEX_SHIFT) | BUFFERABLE; - break; - default: - attr = 0; /* strongly ordered */ - break; - }; + attr = get_attr_encoding(reg_config->mr_attr);

writel(reg_config->start_addr | VALID_REGION | reg_config->region_no, &V7M_MPU->rbar); diff --git a/arch/arm/include/asm/armv7_mpu.h b/arch/arm/include/asm/armv7_mpu.h new file mode 100644 index 0000000000..72d576d823 --- /dev/null +++ b/arch/arm/include/asm/armv7_mpu.h @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Vikas Manocha, vikas.manocha@st.com for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV7_MPU_H +#define _ASM_ARMV7_MPU_H + +#ifdef CONFIG_CPU_V7M +#define AP_SHIFT 24 +#define XN_SHIFT 28 +#define TEX_SHIFT 19 +#define S_SHIFT 18 +#define C_SHIFT 17 +#define B_SHIFT 16 +#else /* CONFIG_CPU_V7R */ +#define XN_SHIFT 12 +#define AP_SHIFT 8 +#define TEX_SHIFT 3 +#define S_SHIFT 2 +#define C_SHIFT 1 +#define B_SHIFT 0 +#endif /* CONFIG_CPU_V7R */ + +#define CACHEABLE BIT(C_SHIFT) +#define BUFFERABLE BIT(B_SHIFT) +#define SHAREABLE BIT(S_SHIFT) +#define REGION_SIZE_SHIFT 1 +#define ENABLE_REGION BIT(0) +#define DISABLE_REGION 0 + +enum region_number { + REGION_0 = 0, + REGION_1, + REGION_2, + REGION_3, + REGION_4, + REGION_5, + REGION_6, + REGION_7, +}; + +enum ap { + NO_ACCESS = 0, + PRIV_RW_USR_NO, + PRIV_RW_USR_RO, + PRIV_RW_USR_RW, + UNPREDICTABLE, + PRIV_RO_USR_NO, + PRIV_RO_USR_RO, +}; + +enum mr_attr { + STRONG_ORDER = 0, + SHARED_WRITE_BUFFERED, + O_I_WT_NO_WR_ALLOC, + O_I_WB_NO_WR_ALLOC, + O_I_NON_CACHEABLE, + O_I_WB_RD_WR_ALLOC, + DEVICE_NON_SHARED, +}; +enum size { + REGION_8MB = 22, + REGION_16MB, + REGION_32MB, + REGION_64MB, + REGION_128MB, + REGION_256MB, + REGION_512MB, + REGION_1GB, + REGION_2GB, + REGION_4GB, +}; + +enum xn { + XN_DIS = 0, + XN_EN, +}; + +struct mpu_region_config { + uint32_t start_addr; + enum region_number region_no; + enum xn xn; + enum ap ap; + enum mr_attr mr_attr; + enum size reg_size; +}; + +void disable_mpu(void); +void enable_mpu(void); +int mpu_enabled(void); +void mpu_config(struct mpu_region_config *reg_config); +void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns); + +static inline u32 get_attr_encoding(u32 mr_attr) +{ + u32 attr; + + switch (mr_attr) { + case STRONG_ORDER: + attr = SHAREABLE; + break; + case SHARED_WRITE_BUFFERED: + attr = BUFFERABLE; + break; + case O_I_WT_NO_WR_ALLOC: + attr = CACHEABLE; + break; + case O_I_WB_NO_WR_ALLOC: + attr = CACHEABLE | BUFFERABLE; + break; + case O_I_NON_CACHEABLE: + attr = 1 << TEX_SHIFT; + break; + case O_I_WB_RD_WR_ALLOC: + attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE; + break; + case DEVICE_NON_SHARED: + attr = (2 << TEX_SHIFT) | BUFFERABLE; + break; + default: + attr = 0; /* strongly ordered */ + break; + }; + + return attr; +} + +#endif /* _ASM_ARMV7_MPU_H */ diff --git a/arch/arm/include/asm/armv7m_mpu.h b/arch/arm/include/asm/armv7m_mpu.h deleted file mode 100644 index 0f73cf1dc0..0000000000 --- a/arch/arm/include/asm/armv7m_mpu.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, vikas.manocha@st.com for STMicroelectronics. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -enum region_number { - REGION_0 = 0, - REGION_1, - REGION_2, - REGION_3, - REGION_4, - REGION_5, - REGION_6, - REGION_7, -}; - -enum ap { - NO_ACCESS = 0, - PRIV_RW_USR_NO, - PRIV_RW_USR_RO, - PRIV_RW_USR_RW, - UNPREDICTABLE, - PRIV_RO_USR_NO, - PRIV_RO_USR_RO, -}; - -enum mr_attr { - STRONG_ORDER = 0, - SHARED_WRITE_BUFFERED, - O_I_WT_NO_WR_ALLOC, - O_I_WB_NO_WR_ALLOC, - O_I_NON_CACHEABLE, - O_I_WB_RD_WR_ALLOC, - DEVICE_NON_SHARED, -}; -enum size { - REGION_8MB = 22, - REGION_16MB, - REGION_32MB, - REGION_64MB, - REGION_128MB, - REGION_256MB, - REGION_512MB, - REGION_1GB, - REGION_2GB, - REGION_4GB, -}; - -enum xn { - XN_DIS = 0, - XN_EN, -}; - -struct mpu_region_config { - uint32_t start_addr; - enum region_number region_no; - enum xn xn; - enum ap ap; - enum mr_attr mr_attr; - enum size reg_size; -}; - -void disable_mpu(void); -void enable_mpu(void); -void mpu_config(struct mpu_region_config *reg_config); diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index f6fd0b2e23..f4c5bb16ff 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -7,7 +7,7 @@

#include <common.h> #include <asm/io.h> -#include <asm/armv7m_mpu.h> +#include <asm/armv7_mpu.h>

int arch_cpu_init(void) {