[U-Boot] [PATCH 1/8 v3] powerpc/srio: Rewrite the struct ccsr_rio
Rewrite this struct for the support of two ports and two message units registers.
Signed-off-by: Liu Gang Gang.Liu@freescale.com --- Changes in v2: - Change the subject and commit message. - Remove the offsets in the comments. - Rewrite the struct for the support of two ports and two message units registers.
Changes in v3: - Move some SRIO macros to the appropriate board configure header files.
arch/powerpc/include/asm/immap_85xx.h | 384 +++++++++++++++++++-------------- include/configs/MPC8548CDS.h | 5 + include/configs/MPC8568MDS.h | 5 + include/configs/MPC8569MDS.h | 5 + include/configs/P2020DS.h | 5 + include/configs/P2041RDB.h | 3 + include/configs/corenet_ds.h | 7 + 7 files changed, 254 insertions(+), 160 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9b08cb8..42db6c9 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1353,171 +1353,235 @@ typedef struct ccsr_cpm { } ccsr_cpm_t; #endif
-/* RapidIO Registers */ -typedef struct ccsr_rio { - u32 didcar; /* Device Identity Capability */ - u32 dicar; /* Device Information Capability */ - u32 aidcar; /* Assembly Identity Capability */ - u32 aicar; /* Assembly Information Capability */ - u32 pefcar; /* Processing Element Features Capability */ - u32 spicar; /* Switch Port Information Capability */ - u32 socar; /* Source Operations Capability */ - u32 docar; /* Destination Operations Capability */ +#ifdef CONFIG_SYS_SRIO +/* Architectural regsiters */ +struct rio_arch { + u32 didcar; /* Device Identity CAR */ + u32 dicar; /* Device Information CAR */ + u32 aidcar; /* Assembly Identity CAR */ + u32 aicar; /* Assembly Information CAR */ + u32 pefcar; /* Processing Element Features CAR */ + u8 res0[4]; + u32 socar; /* Source Operations CAR */ + u32 docar; /* Destination Operations CAR */ u8 res1[32]; - u32 msr; /* Mailbox Cmd And Status */ - u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */ + u32 mcsr; /* Mailbox CSR */ + u32 pwdcsr; /* Port-Write and Doorbell CSR */ u8 res2[4]; u32 pellccsr; /* Processing Element Logic Layer CCSR */ u8 res3[12]; - u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */ - u32 bdidcsr; /* Base Device ID Cmd & Status */ + u32 lcsbacsr; /* Local Configuration Space BACSR */ + u32 bdidcsr; /* Base Device ID CSR */ u8 res4[4]; - u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */ - u32 ctcsr; /* Component Tag Cmd & Status */ - u8 res5[144]; - u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */ - u8 res6[28]; - u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */ - u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */ - u8 res7[20]; - u32 pgccsr; /* Port General Cmd & Status */ - u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */ - u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */ - u32 plascsr; /* Port Local Ackid Status Cmd & Status */ - u8 res8[12]; - u32 pescsr; /* Port Error & Status Cmd & Status */ - u32 pccsr; /* Port Control Cmd & Status */ - u8 res9[65184]; - u32 cr; /* Port Control Cmd & Status */ - u8 res10[12]; - u32 pcr; /* Port Configuration */ - u32 peir; /* Port Error Injection */ - u8 res11[3048]; - u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */ - u8 res12[12]; - u32 rowar0; /* RIO Outbound Attrs 0 */ - u8 res13[12]; - u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */ - u8 res14[4]; - u32 rowbar1; /* RIO Outbound Window Base Addr 1 */ - u8 res15[4]; - u32 rowar1; /* RIO Outbound Attrs 1 */ - u8 res16[12]; - u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */ - u8 res17[4]; - u32 rowbar2; /* RIO Outbound Window Base Addr 2 */ - u8 res18[4]; - u32 rowar2; /* RIO Outbound Attrs 2 */ - u8 res19[12]; - u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */ - u8 res20[4]; - u32 rowbar3; /* RIO Outbound Window Base Addr 3 */ - u8 res21[4]; - u32 rowar3; /* RIO Outbound Attrs 3 */ - u8 res22[12]; - u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */ - u8 res23[4]; - u32 rowbar4; /* RIO Outbound Window Base Addr 4 */ - u8 res24[4]; - u32 rowar4; /* RIO Outbound Attrs 4 */ - u8 res25[12]; - u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */ - u8 res26[4]; - u32 rowbar5; /* RIO Outbound Window Base Addr 5 */ - u8 res27[4]; - u32 rowar5; /* RIO Outbound Attrs 5 */ - u8 res28[12]; - u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */ - u8 res29[4]; - u32 rowbar6; /* RIO Outbound Window Base Addr 6 */ - u8 res30[4]; - u32 rowar6; /* RIO Outbound Attrs 6 */ - u8 res31[12]; - u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */ - u8 res32[4]; - u32 rowbar7; /* RIO Outbound Window Base Addr 7 */ - u8 res33[4]; - u32 rowar7; /* RIO Outbound Attrs 7 */ - u8 res34[12]; - u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */ - u8 res35[4]; - u32 rowbar8; /* RIO Outbound Window Base Addr 8 */ - u8 res36[4]; - u32 rowar8; /* RIO Outbound Attrs 8 */ - u8 res37[76]; - u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */ - u8 res38[4]; - u32 riwbar4; /* RIO Inbound Window Base Addr 4 */ - u8 res39[4]; - u32 riwar4; /* RIO Inbound Attrs 4 */ - u8 res40[12]; - u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */ - u8 res41[4]; - u32 riwbar3; /* RIO Inbound Window Base Addr 3 */ - u8 res42[4]; - u32 riwar3; /* RIO Inbound Attrs 3 */ - u8 res43[12]; - u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */ - u8 res44[4]; - u32 riwbar2; /* RIO Inbound Window Base Addr 2 */ - u8 res45[4]; - u32 riwar2; /* RIO Inbound Attrs 2 */ - u8 res46[12]; - u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */ - u8 res47[4]; - u32 riwbar1; /* RIO Inbound Window Base Addr 1 */ - u8 res48[4]; - u32 riwar1; /* RIO Inbound Attrs 1 */ - u8 res49[12]; - u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */ - u8 res50[12]; - u32 riwar0; /* RIO Inbound Attrs 0 */ - u8 res51[12]; - u32 pnfedr; /* Port Notification/Fatal Error Detect */ - u32 pnfedir; /* Port Notification/Fatal Error Detect */ - u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */ - u32 pecr; /* Port Error Control */ - u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */ - u32 pepr1; /* Port Error Packet 1 */ - u32 pepr2; /* Port Error Packet 2 */ - u8 res52[4]; - u32 predr; /* Port Recoverable Error Detect */ - u8 res53[4]; - u32 pertr; /* Port Error Recovery Threshold */ - u32 prtr; /* Port Retry Threshold */ - u8 res54[464]; - u32 omr; /* Outbound Mode */ - u32 osr; /* Outbound Status */ - u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */ - u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */ - u32 eosar; /* Extended Outbound Unit Source Addr */ - u32 osar; /* Outbound Unit Source Addr */ - u32 odpr; /* Outbound Destination Port */ - u32 odatr; /* Outbound Destination Attrs */ - u32 odcr; /* Outbound Doubleword Count */ - u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */ - u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */ - u8 res55[52]; - u32 imr; /* Outbound Mode */ - u32 isr; /* Inbound Status */ - u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */ - u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */ - u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */ - u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */ - u8 res56[1000]; - u32 dmr; /* Doorbell Mode */ - u32 dsr; /* Doorbell Status */ - u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */ - u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */ - u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */ - u32 dqhpar; /* Doorbell Queue Head Ptr Addr */ - u8 res57[104]; - u32 pwmr; /* Port-Write Mode */ - u32 pwsr; /* Port-Write Status */ - u32 epwqbar; /* Extended Port-Write Queue Base Addr */ - u32 pwqbar; /* Port-Write Queue Base Addr */ - u8 res58[60176]; -} ccsr_rio_t; + u32 hbdidlcsr; /* Host Base Device ID Lock CSR */ + u32 ctcsr; /* Component Tag CSR */ +}; + +/* Extended Features Space: 1x/4x LP-Serial Port registers */ +struct rio_lp_serial_port { + u32 plmreqcsr; /* Port Link Maintenance Request CSR */ + u32 plmrespcsr; /* Port Link Maintenance Response CS */ + u32 plascsr; /* Port Local Ackid Status CSR */ + u8 res0[12]; + u32 pescsr; /* Port Error and Status CSR */ + u32 pccsr; /* Port Control CSR */ +}; + +/* Extended Features Space: 1x/4x LP-Serial registers */ +struct rio_lp_serial { + u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */ + u8 res0[28]; + u32 pltoccsr; /* Port Link Time-out CCSR */ + u32 prtoccsr; /* Port Response Time-out CCSR */ + u8 res1[20]; + u32 pgccsr; /* Port General CSR */ + struct rio_lp_serial_port port[CONFIG_SRIO_PORT_MAX_NUM]; +}; + +/* Logical error reporting registers */ +struct rio_logical_err { + u32 erbh; /* Error Reporting Block Header Register */ + u8 res0[4]; + u32 ltledcsr; /* Logical/Transport layer error DCSR */ + u32 ltleecsr; /* Logical/Transport layer error ECSR */ + u8 res1[4]; + u32 ltlaccsr; /* Logical/Transport layer ACCSR */ + u32 ltldidccsr; /* Logical/Transport layer DID CCSR */ + u32 ltlcccsr; /* Logical/Transport layer control CCSR */ +}; + +/* Physical error reporting port registers */ +struct rio_phys_err_port { + u32 edcsr; /* Port error detect CSR */ + u32 erecsr; /* Port error rate enable CSR */ + u32 ecacsr; /* Port error capture attributes CSR */ + u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */ + u32 peccsr[3]; /* Port error capture CSR */ + u8 res0[12]; + u32 ercsr; /* Port error rate CSR */ + u32 ertcsr; /* Port error rate threshold CSR */ + u8 res1[16]; +}; + +/* Physical error reporting registers */ +struct rio_phys_err { + struct rio_phys_err_port port[CONFIG_SRIO_PORT_MAX_NUM]; +}; + +/* Implementation Space: General Port-Common */ +struct rio_impl_common { + u8 res0[4]; + u32 llcr; /* Logical Layer Configuration Register */ + u8 res1[8]; + u32 epwisr; /* Error / Port-Write Interrupt SR */ + u8 res2[12]; + u32 lretcr; /* Logical Retry Error Threshold CR */ + u8 res3[92]; + u32 pretcr; /* Physical Retry Erorr Threshold CR */ + u8 res4[124]; +}; + +/* Implementation Space: Port Specific */ +struct rio_impl_port_spec { + u32 adidcsr; /* Port Alt. Device ID CSR */ + u8 res0[28]; + u32 ptaacr; /* Port Pass-Through/Accept-All CR */ + u32 lopttlcr; + u8 res1[8]; + u32 iecsr; /* Port Implementation Error CSR */ + u8 res2[12]; + u32 pcr; /* Port Phsyical Configuration Register */ + u8 res3[20]; + u32 slcsr; /* Port Serial Link CSR */ + u8 res4[4]; + u32 sleicr; /* Port Serial Link Error Injection */ + u32 a0txcr; /* Port Arbitration 0 Tx CR */ + u32 a1txcr; /* Port Arbitration 1 Tx CR */ + u32 a2txcr; /* Port Arbitration 2 Tx CR */ + u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */ + u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */ +}; + +/* Implementation Space: register */ +struct rio_implement { + struct rio_impl_common com; + struct rio_impl_port_spec port[CONFIG_SRIO_PORT_MAX_NUM]; +}; + +/* Revision Control Register */ +struct rio_rev_ctrl { + u32 ipbrr[2]; /* IP Block Revision Register */ +}; + +struct rio_atmu_row { + u32 rowtar; /* RapidIO Outbound Window TAR */ + u32 rowtear; /* RapidIO Outbound Window TEAR */ + u32 rowbar; + u8 res0[4]; + u32 rowar; /* RapidIO Outbound Attributes Register */ + u32 rowsr[3]; /* Port RapidIO outbound window segment register */ +}; + +struct rio_atmu_riw { + u32 riwtar; /* RapidIO Inbound Window Translation AR */ + u8 res0[4]; + u32 riwbar; /* RapidIO Inbound Window Base AR */ + u8 res1[4]; + u32 riwar; /* RapidIO Inbound Attributes Register */ + u8 res2[12]; +}; + +/* ATMU window registers */ +struct rio_atmu_win { + struct rio_atmu_row outbw[CONFIG_SRIO_OB_WIN_NUM]; + u8 res0[64]; + struct rio_atmu_riw inbw[CONFIG_SRIO_IB_WIN_NUM]; +}; + +struct rio_atmu { + struct rio_atmu_win port[CONFIG_SRIO_PORT_MAX_NUM]; +}; + +#ifdef CONFIG_SYS_RMU +struct rio_msg { + u32 omr; /* Outbound Mode Register */ + u32 osr; /* Outbound Status Register */ + u32 eodqdpar; /* Extended Outbound DQ DPAR */ + u32 odqdpar; /* Outbound Descriptor Queue DPAR */ + u32 eosar; /* Extended Outbound Unit Source AR */ + u32 osar; /* Outbound Unit Source AR */ + u32 odpr; /* Outbound Destination Port Register */ + u32 odatr; /* Outbound Destination Attributes Register */ + u32 odcr; /* Outbound Doubleword Count Register */ + u32 eodqepar; /* Extended Outbound DQ EPAR */ + u32 odqepar; /* Outbound Descriptor Queue EPAR */ + u32 oretr; /* Outbound Retry Error Threshold Register */ + u32 omgr; /* Outbound Multicast Group Register */ + u32 omlr; /* Outbound Multicast List Register */ + u8 res0[40]; + u32 imr; /* Outbound Mode Register */ + u32 isr; /* Inbound Status Register */ + u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */ + u32 idqdpar; /* Inbound Descriptor Queue DPAR */ + u32 eifqepar; /* Extended Inbound Frame Queue EPAR */ + u32 ifqepar; /* Inbound Frame Queue EPAR */ + u32 imirir; /* Inbound Maximum Interrutp RIR */ + u8 res1[4]; + u32 eihqepar; /* Extended inbound message header queue EPAR */ + u32 ihqepar; /* Inbound message header queue EPAR */ + u8 res2[120]; +}; + +struct rio_dbell { + u32 odmr; /* Outbound Doorbell Mode Register */ + u32 odsr; /* Outbound Doorbell Status Register */ + u8 res0[16]; + u32 oddpr; /* Outbound Doorbell Destination Port */ + u32 oddatr; /* Outbound Doorbell Destination AR */ + u8 res1[12]; + u32 oddretr; /* Outbound Doorbell Retry Threshold CR */ + u8 res2[48]; + u32 idmr; /* Inbound Doorbell Mode Register */ + u32 idsr; /* Inbound Doorbell Status Register */ + u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */ + u32 iqdpar; /* Inbound Doorbell Queue DPAR */ + u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */ + u32 idqepar; /* Inbound Doorbell Queue EPAR */ + u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */ +}; + +struct rio_pw { + u32 pwmr; /* Port-Write Mode Register */ + u32 pwsr; /* Port-Write Status Register */ + u32 epwqbar; /* Extended Port-Write Queue BAR */ + u32 pwqbar; /* Port-Write Queue Base Address Register */ +}; +#endif + +/* RapidIO Registers */ +struct ccsr_rio { + struct rio_arch arch; + u8 res0[144]; + struct rio_lp_serial lp_serial; + u8 res1[1152]; + struct rio_logical_err logical_err; + u8 res2[32]; + struct rio_phys_err phys_err; + u8 res3[63808]; + struct rio_implement impl; + u8 res4[2552]; + struct rio_rev_ctrl rev; + struct rio_atmu atmu; +#ifdef CONFIG_SYS_RMU + u8 res5[8192]; + struct rio_msg msg[CONFIG_SRIO_MSG_UNIT_NUM]; + u8 res6[512]; + struct rio_dbell dbell; + u8 res7[100]; + struct rio_pw pw; +#endif +}; +#endif
/* Quick Engine Block Pin Muxing Registers */ typedef struct par_io { diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 1a6ba69..339749b 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -46,6 +46,11 @@
#define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO_PORT_MAX_NUM 1 /* SRIO port max number */ +#define CONFIG_SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define CONFIG_SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ +#define CONFIG_SYS_RMU +#define CONFIG_SRIO_MSG_UNIT_NUM 2 /* SRIO message unit number */
#define CONFIG_PCI /* enable any pci type devices */ #define CONFIG_PCI1 /* PCI controller 1 */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index f9c8dfb..d2c1500 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -37,6 +37,11 @@
#define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO_PORT_MAX_NUM 1 /* SRIO port max number */ +#define CONFIG_SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define CONFIG_SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ +#define CONFIG_SYS_RMU +#define CONFIG_SRIO_MSG_UNIT_NUM 2 /* SRIO message unit number */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* PCI controller */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 7a5d86d..c5a2115 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -37,6 +37,11 @@
#define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO_PORT_MAX_NUM 1 /* SRIO port max number */ +#define CONFIG_SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define CONFIG_SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ +#define CONFIG_SYS_RMU +#define CONFIG_SRIO_MSG_UNIT_NUM 2 /* SRIO message unit number */
#define CONFIG_PCI 1 /* Disable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controller */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index f0eb029..d98a93e 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -66,6 +66,11 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PORT_MAX_NUM 2 /* SRIO port max number */ +#define CONFIG_SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define CONFIG_SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ +#define CONFIG_SYS_RMU +#define CONFIG_SRIO_MSG_UNIT_NUM 2 /* SRIO message unit number */
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index da98f8f..6cf4eb4 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -67,6 +67,9 @@ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ #define CONFIG_SYS_DPAA_RMAN /* RMan */ +#define CONFIG_SRIO_PORT_MAX_NUM 2 /* SRIO port max number */ +#define CONFIG_SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define CONFIG_SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */
#define CONFIG_FSL_LAW /* Use common FSL init code */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 77dd0a2..5067bb7 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -62,6 +62,13 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PORT_MAX_NUM 2 /* SRIO port max number */ +#define CONFIG_SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define CONFIG_SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ +#ifndef CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_RMU +#define CONFIG_SRIO_MSG_UNIT_NUM 2 /* SRIO message unit number */ +#endif
#define CONFIG_FSL_LAW /* Use common FSL init code */
When defined CONFIG_ENV_IS_NOWHERE, there will be some compilation errors:
./common/env_nowhere.o: In function `env_relocate_spec': ./common/env_nowhere.c:38: multiple definition of `env_relocate_spec' ./common/env_flash.o: ./common/env_flash.c:326: first defined here ./common/env_nowhere.o: In function `env_get_char_spec': ./common/env_nowhere.c:42: multiple definition of `env_get_char_spec' ./common/env_flash.o:./common/env_flash.c:78: first defined here ./common/env_nowhere.o: In function `env_init': ./common/env_nowhere.c:51: multiple definition of `env_init' ./common/env_flash.o:./common/env_flash.c:237: first defined here make[1]: *** [./common/libcommon.o] Error 1 make[1]: Leaving directory `./common' make: *** [./common/libcommon.o] Error 2
Remove the CONFIG_ENV_IS_IN_FLASH if defined CONFIG_ENV_IS_NOWHERE.
Signed-off-by: Liu Gang Gang.Liu@freescale.com --- Changes in v2: - Subject changed to "powerpc/corenet_ds". - Change the commit message more clearly.
Changes in v3: - No
include/configs/corenet_ds.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 5067bb7..89e6b6e 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -104,6 +104,8 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
This document describes the implementation of the boot from SRIO, includes the introduction of envionment, an example based on P4080DS platform, an example of the slave's RCW, and the description about how to use this feature.
Signed-off-by: Liu Gang Gang.Liu@freescale.com --- Changes in v2: - Subject changed to "powerpc/corenet_ds". - Change the name of the document for "corenet" platform.
Changes in v3: - No
doc/README.srio-boot-corenet | 103 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 103 insertions(+), 0 deletions(-) create mode 100644 doc/README.srio-boot-corenet
diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet new file mode 100644 index 0000000..56b094c --- /dev/null +++ b/doc/README.srio-boot-corenet @@ -0,0 +1,103 @@ +------------------------------ +SRIO Boot on Corenet Platforms +------------------------------ + +For some PowerPC processors with SRIO interface, boot location can be configured +to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot +image, ucode and ENV. All the images can be fetched from another processor's +memory space by SRIO link connected between them. + +This document describes the processes based on an example implemented on P4080DS +platforms and a RCW example with boot from SRIO configuration. + +Environment of the SRIO boot: + a) Master and slave can be SOCs in one board or SOCs in separate boards. + b) They are connected with SRIO links, whether 1x or 4x, and directly or + through switch system. + c) Only Master has NorFlash for booting, and all the Master's and Slave's + U-Boot images, UCodes will be stored in this flash. + d) Slave has its own EEPROM for RCW and PBI. + e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot + location to SRIO, and holdoff all the cores if needed. + + ---------- ----------- ----------- + | | | | | | + | | | | | | + | NorFlash|<----->| Master | SRIO | Slave |<---->[EEPROM] + | | | |<===========>| | + | | | | | | + ---------- ----------- ----------- + +The example based on P4080DS platform: + Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO + ports 0 will be connected directly and will be used for the boot from SRIO. + + 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. + 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000 + 00000010: 1818 1818 0000 8888 7440 4000 0000 2000 + 00000020: f400 0000 0100 0000 0000 0000 0000 0000 + 00000030: 0000 0000 0083 0000 0000 0000 0000 0000 + 00000040: 0000 0000 0000 0000 0813 8040 698b 93fe + + 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. + 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000 + 00000010: 1818 1818 0000 8888 7440 4000 0000 2000 + 00000020: f440 0000 0100 0000 0000 0000 0000 0000 + 00000030: 0000 0000 0083 0000 0000 0000 0000 0000 + 00000040: 0000 0000 0000 0000 0813 8040 063c 778f + + 3. Sequence in Step by Step. + a) Update RCW for slave with boot from SRIO port 0 configuration. + b) Program slave's U-Boot image, UCode, and ENV parameters into master's + NorFlash. + c) Start up master and it will boot up normally from its NorFlash. + Then, it will finish necessary configurations for slave's boot from + SRIO port 0. + d) Master will set inbound SRIO windows covered slave's U-Boot image stored + in master's NorFlash. + e) Master will set an inbound SRIO window covered slave's UCode stored in + master's NorFlash. + f) Master will set an inbound SRIO window covered slave's ENV stored in + master's NorFlash. + g) If need to release slave's core, master will set outbound SRIO windows + in order to configure slave's registers for the core's releasing. + h) If all cores of slave in holdoff, slave should be powered on before all + the above master's steps, and wait to be released by master. If not all + cores in holdoff, that means core 0 will start up normally, slave should + be powered on after all the above master's steps. In the startup phase + of the slave from SRIO, it will finish some necessary configurations. + i) Slave will set a specific TLB entry for the boot process. + j) Slave will set a LAW entry with the TargetID SRIO port 0 for the boot. + k) Slave will set a specific TLB entry in order to fetch UCode and ENV + from master. + l) Slave will set a LAW entry with the TargetID SRIO port 0 for UCode and ENV. + +How to use this feature: + To use this feature, you need to focus three points. + + 1. Slave's RCW with SRIO boot configurations, and all cores in holdoff + configurations if needed. + Please refer to the examples given above. + + 2. U-Boot image's compilation. + For master, U-Boot image should be generated specifically by + + make xxxx_SRIOBOOT_MASTER_config. + + For example, master U-Boot image used on P4080DS should be compiled with + + make P4080DS_SRIOBOOT_MASTER_config. + + For slave, U-Boot image should be generated specifically by + + make xxxx_SRIOBOOT_SLAVE_config. + + For example, slave U-Boot image used on P4080DS should be compiled with + + make P4080DS_SRIOBOOT_SLAVE_config. + + 3. Necessary modifications based on a specific environment. + For a specific environment, the SRIO port for boot, the addresses of the + slave's U-Boot image, UCode, ENV stored in master's NorFlash, and any other + configurations can be modified in the file: + include/configs/corenet_ds.h.
For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements:
master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot.
For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on.
Signed-off-by: Liu Gang Gang.Liu@freescale.com Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- Changes in v2: - Subject changed to "powerpc/corenet_ds". - Use "(void *)" instead of "(u32)" when calling "out_be32()". - Use "NOR flash" instead of "Nor flash". - Get rid of the base address + offset notation. Use C structs instead. - Get rid of hard coded magic numbers. Use macro instead. - Use "debug()" instead of "printf()".
Changes in v3: - No
arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 ++- arch/powerpc/cpu/mpc8xxx/srio.c | 51 +++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_srio.h | 61 +++++++++++++++++++++++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 3 ++ boards.cfg | 3 ++ include/configs/corenet_ds.h | 18 ++++++++++ 6 files changed, 140 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/include/asm/fsl_srio.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2e4a06c..97a7fe1 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,6 +37,7 @@ #include <asm/mmu.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> +#include <asm/fsl_srio.h> #include <linux/compiler.h> #include "mp.h" #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -48,8 +49,6 @@
DECLARE_GLOBAL_DATA_PTR;
-extern void srio_init(void); - #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -443,6 +442,9 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO srio_init(); +#ifdef CONFIG_SRIOBOOT_MASTER + srio_boot_master(); +#endif #endif
#if defined(CONFIG_MP) diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index e46d328..77fa32f 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -21,6 +21,10 @@ #include <config.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> +#include <asm/fsl_srio.h> + +#define SRIO_PORT_ACCEPT_ALL 0x10000001 +#define SRIO_IB_ATMU_AR 0x80f55000
#if defined(CONFIG_FSL_CORENET) #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 @@ -84,3 +88,50 @@ void srio_init(void) setbits_be32(&gur->devdisr, _DEVDISR_RMU); } } + +#ifdef CONFIG_SRIOBOOT_MASTER +void srio_boot_master(void) +{ + struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + + /* set port accept-all */ + out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr, + SRIO_PORT_ACCEPT_ALL); + + debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", + CONFIG_SRIOBOOT_MASTER_PORT); + /* configure inbound window5 for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window 5 for slave's image; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + + /* configure inbound window4 for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window 4 for slave's image; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); +} +#endif diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h new file mode 100644 index 0000000..e4cd9b6 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -0,0 +1,61 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FSL_SRIO_H_ +#define _FSL_SRIO_H_ + +enum atmu_size { + ATMU_SIZE_4K = 0xb, + ATMU_SIZE_8K, + ATMU_SIZE_16K, + ATMU_SIZE_32K, + ATMU_SIZE_64K, + ATMU_SIZE_128K, + ATMU_SIZE_256K, + ATMU_SIZE_512K, + ATMU_SIZE_1M, + ATMU_SIZE_2M, + ATMU_SIZE_4M, + ATMU_SIZE_8M, + ATMU_SIZE_16M, + ATMU_SIZE_32M, + ATMU_SIZE_64M, + ATMU_SIZE_128M, + ATMU_SIZE_256M, + ATMU_SIZE_512M, + ATMU_SIZE_1G, + ATMU_SIZE_2G, + ATMU_SIZE_4G, + ATMU_SIZE_8G, + ATMU_SIZE_16G, + ATMU_SIZE_32G, + ATMU_SIZE_64G, +}; + +#define atmu_size_mask(sz) (__ilog2_u64(sz) - 1) +#define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1)) + +extern void srio_init(void); +#ifdef CONFIG_SRIOBOOT_MASTER +extern void srio_boot_master(void); +#endif +#endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 42db6c9..7d432e6 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2507,6 +2507,7 @@ struct ccsr_rman {
#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 +#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
#define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) @@ -2580,6 +2581,8 @@ struct ccsr_rman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) #define CONFIG_SYS_FSL_FM2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) +#define CONFIG_SYS_FSL_SRIO_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) diff --git a/boards.cfg b/boards.cfg index 05ce1ae..30b9b51 100644 --- a/boards.cfg +++ b/boards.cfg @@ -756,6 +756,7 @@ P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER P3060QDS powerpc mpc85xx p3060qds freescale P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT @@ -763,11 +764,13 @@ P4080DS powerpc mpc85xx corenet_ds freesca P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER P5020DS powerpc mpc85xx corenet_ds freescale P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 89e6b6e..e7a4c5a 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -382,6 +382,24 @@ #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/* + * SRIOBOOT - MASTER + */ +#ifdef CONFIG_SRIOBOOT_MASTER +/* master port for srioboot*/ +#define CONFIG_SRIOBOOT_MASTER_PORT 0 +/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */ +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull +#endif + +/* * eSPI - Enhanced SPI */ #define CONFIG_FSL_ESPI
For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements:
master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. 5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode locally.
For the slave module, need to finish these processes: 1. Set the boot location to SRIO1 or SRIO2 by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot. 4. Slave's u-boot image should be generated specifically by make xxxx_SRIOBOOT_SLAVE_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
Signed-off-by: Liu Gang Gang.Liu@freescale.com Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- Changes in v2: - Subject changed to "powerpc/corenet_ds". - Use "(void *)" instead of "(u32)" when calling "out_be32()". - Use "NOR flash" instead of "Nor flash". - Get rid of the base address + offset notation. Use C structs instead. - Get rid of hard coded magic numbers. Use macro instead. - Use "debug()" instead of "printf()". - Add the description for CONFIG_SYS_QE_FMAN_FW_IN_REMOTE and also update the README for this.
Changes in v3: - No
README | 6 ++++++ board/freescale/common/p_corenet/law.c | 9 +++++++++ board/freescale/common/p_corenet/tlb.c | 9 +++++++++ boards.cfg | 3 +++ drivers/net/fm/fm.c | 2 ++ include/configs/corenet_ds.h | 28 ++++++++++++++++++++++++++++ 6 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/README b/README index eba6378..719cc20 100644 --- a/README +++ b/README @@ -3384,6 +3384,12 @@ within that device. Specifies that QE/FMAN firmware is located on the primary SPI device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE + Specifies that QE/FMAN firmware is located in the remote (master) + memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which + can be mapped from slave TLB->slave LAW->slave SRIO outbound window + ->master inbound window->master LAW->the ucode address in master's + NOR flash.
Building the Software: ====================== diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 09ef561..1fbab4d 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -48,6 +48,15 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif +#ifdef CONFIG_SRIOBOOT_SLAVE +#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0) + SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), +#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1) + SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), +#endif +#endif };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 6a0026a..a8c8b3c 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIOBOOT_SLAVE) + /* + * SRIOBOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR, + CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), #else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/boards.cfg b/boards.cfg index 30b9b51..11f9ef2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -757,6 +757,7 @@ P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER +P3041DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P3060QDS powerpc mpc85xx p3060qds freescale P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT @@ -765,12 +766,14 @@ P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER +P4080DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P5020DS powerpc mpc85xx corenet_ds freescale P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER +P5020DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 0b8c33f..49c74c2 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -408,6 +408,8 @@ int fm_init_common(int index, struct ccsr_fman *reg) /* flush cache after read */ flush_cache((ulong)addr, cnt * 512); } +#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) + void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; #endif
/* Upload the Fman microcode if it's present */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e7a4c5a..d5295fe 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -33,6 +33,15 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif
+#ifdef CONFIG_SRIOBOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -400,6 +409,15 @@ #endif
/* + * SRIOBOOT - SLAVE + */ +#ifdef CONFIG_SRIOBOOT_SLAVE +/* slave port for srioboot */ +#define CONFIG_SRIOBOOT_SLAVE_PORT0 +/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */ +#endif + +/* * eSPI - Enhanced SPI */ #define CONFIG_FSL_ESPI @@ -519,6 +537,16 @@ #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIOBOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO outbound window->master inbound window->master LAW-> + * the ucode address in master's NOR flash. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_QE_FMAN_FW_ADDR NULL #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface. For the corenet platform, ucode is for Fman.
Master needs to: 1. Put the slave's ucode image into it's own memory space. 2. Set an inbound SRIO window covered slave's ucode stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.
Signed-off-by: Liu Gang Gang.Liu@freescale.com Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- Changes in v2: - Subject changed to "powerpc/corenet_ds". - Use "(void *)" instead of "(u32)" when calling "out_be32()". - Use "NOR flash" instead of "Nor flash". - Get rid of the base address + offset notation. Use C structs instead. - Get rid of hard coded magic numbers. Use macro instead. - Use "debug()" instead of "printf()". - Correct some comment style errors.
Changes in v3: - No
arch/powerpc/cpu/mpc8xxx/srio.c | 25 +++++++++++++++++++++---- board/freescale/common/p_corenet/law.c | 4 ++++ board/freescale/common/p_corenet/tlb.c | 10 ++++++++++ include/configs/corenet_ds.h | 12 +++++++++++- 4 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 77fa32f..e593f22 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -100,8 +100,8 @@ void srio_boot_master(void)
debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", CONFIG_SRIOBOOT_MASTER_PORT); - /* configure inbound window5 for slave's u-boot image */ - debug("SRIOBOOT - MASTER: Inbound window 5 for slave's image; " + /* configure inbound window for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1, (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1, @@ -117,8 +117,8 @@ void srio_boot_master(void) SRIO_IB_ATMU_AR | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
- /* configure inbound window4 for slave's u-boot image */ - debug("SRIOBOOT - MASTER: Inbound window 4 for slave's image; " + /* configure inbound window for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2, (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2, @@ -133,5 +133,22 @@ void srio_boot_master(void) .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar, SRIO_IB_ATMU_AR | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + + /* configure inbound window for slave's ucode */ + debug("SRIOBOOT - MASTER: Inbound window for slave's ucode; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS, + (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS, + CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar, + CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar, + CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE)); } #endif diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 1fbab4d..c4566dd 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -52,9 +52,13 @@ struct law_entry law_table[] = { #if defined(CONFIG_SRIOBOOT_SLAVE_PORT0) SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), + SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), #elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1) SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), + SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), #endif #endif }; diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index a8c8b3c..da21627 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -147,6 +147,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_1M, 1), #endif +#ifdef CONFIG_SRIOBOOT_SLAVE + /* + * SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode + * and ENV from master + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 17, BOOKE_PAGESZ_1M, 1), +#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index d5295fe..54762c7 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -406,6 +406,13 @@ #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */ #define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull +/* + * for slave UCODE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull +#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull +#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */ #endif
/* @@ -415,6 +422,9 @@ /* slave port for srioboot */ #define CONFIG_SRIOBOOT_SLAVE_PORT0 /* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */ +#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR) #endif
/* @@ -546,7 +556,7 @@ * the ucode address in master's NOR flash. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR NULL +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
When boot from SRIO, slave's ENV can be stored in master's memory space, then slave can fetch the ENV through SRIO interface.
NOTE: Because the slave can not erase, write master's NOR flash by SRIO interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands.
Master needs to: 1. Put the slave's ENV into it's own memory space. 2. Set an inbound SRIO window covered slave's ENV stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode and ENV from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.
Signed-off-by: Liu Gang Gang.Liu@freescale.com Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- Changes in v2: - Subject changed to "powerpc/corenet_ds". - Update the README for "CONFIG_ENV_IS_IN_REMOTE". - Use "(void *)" instead of "(u32)" when calling "out_be32()". - Use "NOR flash" instead of "Nor flash". - Get rid of the base address + offset notation. Use C structs instead. - Get rid of hard coded magic numbers. Use macro instead. - Use "debug()" instead of "printf()". - Some code styles changed.
Changes in v3: - No
README | 18 +++++++++ arch/powerpc/cpu/mpc8xxx/srio.c | 17 ++++++++ common/Makefile | 1 + common/cmd_nvedit.c | 3 +- common/env_remote.c | 79 +++++++++++++++++++++++++++++++++++++++ include/configs/corenet_ds.h | 13 ++++++ 6 files changed, 130 insertions(+), 1 deletions(-) create mode 100644 common/env_remote.c
diff --git a/README b/README index 719cc20..ab61ed2 100644 --- a/README +++ b/README @@ -2943,6 +2943,24 @@ to save the current settings. environment area within the total memory of your DataFlash placed at the specified address.
+- CONFIG_ENV_IS_IN_REMOTE: + + Define this if you have a remote memory space which you + want to use for the local device's environment. + + - CONFIG_ENV_ADDR: + - CONFIG_ENV_SIZE: + + These two #defines specify the address and size of the + environment area within the remote memory space. The + local device can get the environment from remote memory + space by SRIO or other links. + +BE CAREFUL! For some special cases, the local device can not use +"saveenv" command. For example, the local device will get the +environment stored in a remote NOR flash by SRIO link, but it can +not erase, write this NOR flash by SRIO interface. + - CONFIG_ENV_IS_IN_NAND:
Define this if you have a NAND device which you want to use diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index e593f22..5694561 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -150,5 +150,22 @@ void srio_boot_master(void) .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar, SRIO_IB_ATMU_AR | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE)); + + /* configure inbound window for slave's ENV */ + debug("SRIOBOOT - MASTER: Inbound window for slave's ENV; " + "Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n", + CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS, + CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS, + CONFIG_SRIOBOOT_SLAVE_ENV_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar, + CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar, + CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE)); } #endif diff --git a/common/Makefile b/common/Makefile index 2d9ae8c..bd9e8a3 100644 --- a/common/Makefile +++ b/common/Makefile @@ -58,6 +58,7 @@ COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o +COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
# command diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 20080dc..359d1bf 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -65,9 +65,10 @@ DECLARE_GLOBAL_DATA_PTR; !defined(CONFIG_ENV_IS_IN_NVRAM) && \ !defined(CONFIG_ENV_IS_IN_ONENAND) && \ !defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \ + !defined(CONFIG_ENV_IS_IN_REMOTE) && \ !defined(CONFIG_ENV_IS_NOWHERE) # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\ -SPI_FLASH|MG_DISK|NVRAM|MMC} or CONFIG_ENV_IS_NOWHERE +SPI_FLASH|MG_DISK|NVRAM|MMC|REMOTE} or CONFIG_ENV_IS_NOWHERE #endif
#define XMK_STR(x) #x diff --git a/common/env_remote.c b/common/env_remote.c new file mode 100644 index 0000000..3bf0f95 --- /dev/null +++ b/common/env_remote.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <linux/stddef.h> + +char *env_name_spec = "Remote"; + +#ifdef ENV_IS_EMBEDDED +env_t *env_ptr = &environment; +#else /* ! ENV_IS_EMBEDDED */ +env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; +#endif /* ENV_IS_EMBEDDED */ + +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET 0 +#endif + +uchar env_get_char_spec(int index) +{ + return *((uchar *)(gd->env_addr + index)); +} + +int env_init(void) +{ + if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { + gd->env_addr = (ulong)&(env_ptr->data); + gd->env_valid = 1; + return 0; + } + + gd->env_addr = (ulong)default_environment; + gd->env_valid = 0; + return 0; +} + +#ifdef CONFIG_CMD_SAVEENV +int saveenv(void) +{ +#ifdef CONFIG_SRIOBOOT_SLAVE + printf("Can not support the 'saveenv' when boot from SRIO!\n"); + return 1; +#else + return 0; +#endif +} +#endif /* CONFIG_CMD_SAVEENV */ + +void env_relocate_spec(void) +{ +#ifndef ENV_IS_EMBEDDED + env_import((char *)env_ptr, 1); +#endif +} diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 54762c7..cce5948 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -84,7 +84,9 @@ #define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH +#ifndef CONFIG_SRIOBOOT_SLAVE #define CONFIG_ENV_IS_NOWHERE +#endif #else #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -113,6 +115,10 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIOBOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_ENV_IS_NOWHERE) #define CONFIG_ENV_SIZE 0x2000 #else @@ -413,6 +419,13 @@ #define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull #define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull #define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */ +/* + * for slave ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull +#define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull +#define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */ #endif
/*
When boot from SRIO, slave's core can be in holdoff after powered on for some specific requirements. Master can release the slave's core at the right time by SRIO interface.
Master needs to: 1. Set outbound SRIO windows in order to configure slave's registers for the core's releasing. 2. Check the SRIO port status when release slave core, if no errors, will implement the process of the slave core's releasing. Slave needs to: 1. Set all the cores in holdoff by RCW. 2. Be powered on before master's boot.
Signed-off-by: Liu Gang Gang.Liu@freescale.com Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- Changes in v2: - Subject changed to "powerpc/corenet_ds". - Use "(void *)" instead of "(u32)" when calling "out_be32()". - Use "NOR flash" instead of "Nor flash". - Get rid of the base address + offset notation. Use C structs instead. - Get rid of hard coded magic numbers. Use macro instead. - Use "debug()" instead of "printf()".
Changes in v3: - No
arch/powerpc/cpu/mpc85xx/cpu_init.c | 3 + arch/powerpc/cpu/mpc8xxx/srio.c | 125 +++++++++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_srio.h | 3 + include/configs/corenet_ds.h | 4 + 4 files changed, 135 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 97a7fe1..2cd5db7 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -444,6 +444,9 @@ skip_l2: srio_init(); #ifdef CONFIG_SRIOBOOT_MASTER srio_boot_master(); +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF + srio_boot_master_release_slave(); +#endif #endif #endif
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 5694561..c7f3949 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -25,6 +25,12 @@
#define SRIO_PORT_ACCEPT_ALL 0x10000001 #define SRIO_IB_ATMU_AR 0x80f55000 +#define SRIO_OB_ATMU_AR_MAINT 0x80077000 +#define SRIO_OB_ATMU_AR_RW 0x80045000 +#define SRIO_LCSBA1CSR_OFFSET 0x5c +#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */ +#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */ +#define SRIO_LCSBA1CSR 0x60000000
#if defined(CONFIG_FSL_CORENET) #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 @@ -168,4 +174,123 @@ void srio_boot_master(void) SRIO_IB_ATMU_AR | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE)); } + +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF +void srio_boot_master_release_slave(void) +{ + struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + u32 escsr; + debug("SRIOBOOT - MASTER: " + "Check the port status and release slave core ...\n"); + + escsr = in_be32((void *)&srio->lp_serial + .port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr); + if (escsr & 0x2) { + if (escsr & 0x10100) { + debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n", + CONFIG_SRIOBOOT_MASTER_PORT); + } else { + debug("SRIOBOOT - MASTER: " + "Port [ %d ] is ready, now release slave's core ...\n", + CONFIG_SRIOBOOT_MASTER_PORT); + /* + * configure outbound window + * with maintenance attribute to set slave's LCSBA1CSR + */ + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowtar, 0); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowtear, 0); + if (CONFIG_SRIOBOOT_MASTER_PORT) + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowbar, + CONFIG_SYS_SRIO2_MEM_PHYS >> 12); + else + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowbar, + CONFIG_SYS_SRIO1_MEM_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowar, + SRIO_OB_ATMU_AR_MAINT + | atmu_size_mask(SRIO_MAINT_WIN_SIZE)); + + /* + * configure outbound window + * with R/W attribute to set slave's BRR + */ + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowtar, + SRIO_LCSBA1CSR >> 9); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowtear, 0); + if (CONFIG_SRIOBOOT_MASTER_PORT) + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowbar, + (CONFIG_SYS_SRIO2_MEM_PHYS + + SRIO_MAINT_WIN_SIZE) >> 12); + else + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowbar, + (CONFIG_SYS_SRIO1_MEM_PHYS + + SRIO_MAINT_WIN_SIZE) >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowar, + SRIO_OB_ATMU_AR_RW + | atmu_size_mask(SRIO_RW_WIN_SIZE)); + + /* + * Set the LCSBA1CSR register in slave + * by the maint-outbound window + */ + if (CONFIG_SRIOBOOT_MASTER_PORT) { + out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET, + SRIO_LCSBA1CSR); + while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET) + != SRIO_LCSBA1CSR) + ; + /* + * And then set the BRR register + * to release slave core + */ + out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + + SRIO_MAINT_WIN_SIZE + + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, + CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + } else { + out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET, + SRIO_LCSBA1CSR); + while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET) + != SRIO_LCSBA1CSR) + ; + /* + * And then set the BRR register + * to release slave core + */ + out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + + SRIO_MAINT_WIN_SIZE + + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, + CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + } + debug("SRIOBOOT - MASTER: " + "Release slave successfully! Now the slave should start up!\n"); + } + } else + debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", + CONFIG_SRIOBOOT_MASTER_PORT); +} +#endif #endif diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h index e4cd9b6..a905a26 100644 --- a/arch/powerpc/include/asm/fsl_srio.h +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -57,5 +57,8 @@ enum atmu_size { extern void srio_init(void); #ifdef CONFIG_SRIOBOOT_MASTER extern void srio_boot_master(void); +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF +extern void srio_boot_master_release_slave(void); +#endif #endif #endif diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index cce5948..a4fa722 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -426,6 +426,10 @@ #define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull #define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull #define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */ +/* slave core release by master*/ +#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF +#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */ #endif
/*
On Tue, Mar 6, 2012 at 3:45 AM, Liu Gang Gang.Liu@freescale.com wrote:
Rewrite this struct for the support of two ports and two message units registers.
Signed-off-by: Liu Gang Gang.Liu@freescale.com
Changes in v2: - Change the subject and commit message. - Remove the offsets in the comments. - Rewrite the struct for the support of two ports and two message units registers.
Changes in v3: - Move some SRIO macros to the appropriate board configure header files.
arch/powerpc/include/asm/immap_85xx.h | 384 +++++++++++++++++++-------------- include/configs/MPC8548CDS.h | 5 + include/configs/MPC8568MDS.h | 5 + include/configs/MPC8569MDS.h | 5 + include/configs/P2020DS.h | 5 + include/configs/P2041RDB.h | 3 + include/configs/corenet_ds.h | 7 +
It occurs to me that these defines are really better suited for arch/powerpc/include/asm/config_mpc85xx.h. Notice that's where the other SOC-specific configs (like number of devices) are kept. Changing things there will make it easier to support different boards.
Andy
Hi, Andy,
On Tue, 2012-03-06 at 16:30 -0600, Andy Fleming wrote:
arch/powerpc/include/asm/immap_85xx.h | 384 +++++++++++++++++++-------------- include/configs/MPC8548CDS.h | 5 + include/configs/MPC8568MDS.h | 5 + include/configs/MPC8569MDS.h | 5 + include/configs/P2020DS.h | 5 + include/configs/P2041RDB.h | 3 + include/configs/corenet_ds.h | 7 +
It occurs to me that these defines are really better suited for arch/powerpc/include/asm/config_mpc85xx.h. Notice that's where the other SOC-specific configs (like number of devices) are kept. Changing things there will make it easier to support different boards.
Yeah,I think your comment should be better, and that may be clearer and easier for these defines to support different boards with the file .../config_mpc85xx.h. I'll do some tests and update the patches based on your comment.
Thanks a lot!
Liu Gang
participants (2)
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Andy Fleming -
Liu Gang