From: Peng Fan peng.fan@nxp.com

The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE set to 0x7E1000.

Signed-off-by: Peng Fan peng.fan@nxp.com --- common/spl/Kconfig | 1 + configs/imx8mm-cl-iot-gate-optee_defconfig | 1 - configs/imx8mm-cl-iot-gate_defconfig | 1 - configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 - configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 - configs/imx8mm-mx8menlo_defconfig | 1 - configs/imx8mm_beacon_defconfig | 1 - configs/imx8mm_data_modul_edm_sbc_defconfig | 1 - configs/imx8mm_evk_defconfig | 1 - configs/imx8mm_venice_defconfig | 1 - configs/phycore-imx8mm_defconfig | 1 - configs/verdin-imx8mm_defconfig | 1 - 12 files changed, 1 insertion(+), 11 deletions(-)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2ad2351c6eb..848237c1e85 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -82,6 +82,7 @@ config SPL_MAX_SIZE default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616 default 0x7000 if RCAR_GEN3 default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0 + default 0x27000 if IMX8MM && SPL_TEXT_BASE = 0x7E1000 default 0x0 help Maximum size of the SPL image (text, data, rodata, and linker lists diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index 80055912096..a02010621ea 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index dae7ddc20e0..f05ac98326c 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -25,7 +25,6 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index 69ebc6fa325..7d08b244f2c 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb" -CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index a3c142feb28..acc5d34659b 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb" -CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index ec672f8764e..2a6f3b7c412 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -34,7 +34,6 @@ CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index bf2b6486347..fd21f9f6db8 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -25,7 +25,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi;" CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" -CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 399b388460f..1fae936bda5 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -41,7 +41,6 @@ CONFIG_CONSOLE_MUX=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 00af724bbaa..24bb136c7ad 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 190209d6325..2f7857bdfb6 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -31,7 +31,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 0316d45caeb..3a169692735 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -26,7 +26,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 34afdc57911..8c5274d33f1 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -32,7 +32,6 @@ CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000

From: Ye Li ye.li@nxp.com

The SPL SDP is configured as BOOT_DEVICE_BOARD, so when booting from USB, change its type to BOOT_DEVICE_BOARD, so we can use SDP.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 64ca2967721..e89e2277ef7 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -177,7 +177,7 @@ u32 spl_boot_device(void) case QSPI_BOOT: return BOOT_DEVICE_NOR; case USB_BOOT: - return BOOT_DEVICE_USB; + return BOOT_DEVICE_BOARD; default: return BOOT_DEVICE_NONE; }

From: Peng Fan peng.fan@nxp.com

For SoCs support ROM API, CONFIG_SPL_BOOTROM_SUPPORT is needed, so use this macro to guard the code to avoid extend the list.

And drop the guard with structure definition, there is no need.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/mach-imx/sys_proto.h | 2 -- arch/arm/mach-imx/Kconfig | 3 ++- 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index fdbbfb169cb..fc5e5c66aad 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -146,7 +146,6 @@ struct rproc_att { u32 size; /* size of reg range */ };

-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP) struct rom_api { u16 ver; u16 tag; @@ -178,7 +177,6 @@ enum boot_dev_type_e { #define ROM_API_OKAY 0xF0

extern struct rom_api *g_rom_api; -#endif

/* For i.MX ULP */ #define BT0CFG_LPBOOT_MASK 0x1 diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index ad0fb365023..5e9c4d9b355 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -166,7 +166,8 @@ config DDRMC_VF610_CALIBRATION

config SPL_IMX_ROMAPI_LOADADDR hex "Default load address to load image through ROM API" - depends on IMX8MN || IMX8MP || IMX8ULP + depends on SPL_BOOTROM_SUPPORT + default 0

config IMX_DCD_ADDR hex "DCD Blocks location on the image"

From: Peng Fan peng.fan@nxp.com

i.MX8MN/P/ULP supports ROM API, they have almost same get_boot_device implementation, so move to a common file. And when support i.MX9, no need to include the other function copy.

Since sys_proto.h is included in imx_romapi.c, there will be build warning for i.MX8M because wdog_regs not defined, so include imx-regs.h in i.MX8M sys_proro.h

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8m/sys_proto.h | 1 + arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/imx8m/soc.c | 47 ---------------- arch/arm/mach-imx/imx8ulp/soc.c | 44 --------------- arch/arm/mach-imx/imx_romapi.c | 60 +++++++++++++++++++++ 5 files changed, 62 insertions(+), 91 deletions(-) create mode 100644 arch/arm/mach-imx/imx_romapi.c

diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h index f8854e77128..55b46afaf78 100644 --- a/arch/arm/include/asm/arch-imx8m/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h @@ -7,6 +7,7 @@ #define __ARCH_NMX8M_SYS_PROTO_H

#include <asm/mach-imx/sys_proto.h> +#include <asm/arch/imx-regs.h>

void set_wdog_reset(struct wdog_regs *wdog); void enable_tzc380(void); diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index aa0b6447f14..c5be63dfe4f 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -242,4 +242,5 @@ obj-$(CONFIG_IMX8M) += imx8m/ obj-$(CONFIG_ARCH_IMX8) += imx8/ obj-$(CONFIG_ARCH_IMXRT) += imxrt/

+obj-$(CONFIG_IMX8MN)$(CONFIG_IMX8MP)$(CONFIG_IMX8ULP) += imx_romapi.o obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 59335356b57..d2a856f5410 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -599,53 +599,6 @@ int arch_cpu_init(void)

#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) struct rom_api *g_rom_api = (struct rom_api *)0x980; - -enum boot_device get_boot_device(void) -{ - volatile gd_t *pgd = gd; - int ret; - u32 boot; - u16 boot_type; - u8 boot_instance; - enum boot_device boot_dev = SD1_BOOT; - - ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, - ((uintptr_t)&boot) ^ QUERY_BT_DEV); - set_gd(pgd); - - if (ret != ROM_API_OKAY) { - puts("ROMAPI: failure at query_boot_info\n"); - return -1; - } - - boot_type = boot >> 16; - boot_instance = (boot >> 8) & 0xff; - - switch (boot_type) { - case BT_DEV_TYPE_SD: - boot_dev = boot_instance + SD1_BOOT; - break; - case BT_DEV_TYPE_MMC: - boot_dev = boot_instance + MMC1_BOOT; - break; - case BT_DEV_TYPE_NAND: - boot_dev = NAND_BOOT; - break; - case BT_DEV_TYPE_FLEXSPINOR: - boot_dev = QSPI_BOOT; - break; - case BT_DEV_TYPE_SPI_NOR: - boot_dev = SPI_NOR_BOOT; - break; - case BT_DEV_TYPE_USB: - boot_dev = USB_BOOT; - break; - default: - break; - } - - return boot_dev; -} #endif

#if defined(CONFIG_IMX8M) diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 35020c9714d..529fda4594e 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -34,50 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;

struct rom_api *g_rom_api = (struct rom_api *)0x1980;

-enum boot_device get_boot_device(void) -{ - volatile gd_t *pgd = gd; - int ret; - u32 boot; - u16 boot_type; - u8 boot_instance; - enum boot_device boot_dev = SD1_BOOT; - - ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, - ((uintptr_t)&boot) ^ QUERY_BT_DEV); - set_gd(pgd); - - if (ret != ROM_API_OKAY) { - puts("ROMAPI: failure at query_boot_info\n"); - return -1; - } - - boot_type = boot >> 16; - boot_instance = (boot >> 8) & 0xff; - - switch (boot_type) { - case BT_DEV_TYPE_SD: - boot_dev = boot_instance + SD1_BOOT; - break; - case BT_DEV_TYPE_MMC: - boot_dev = boot_instance + MMC1_BOOT; - break; - case BT_DEV_TYPE_NAND: - boot_dev = NAND_BOOT; - break; - case BT_DEV_TYPE_FLEXSPINOR: - boot_dev = QSPI_BOOT; - break; - case BT_DEV_TYPE_USB: - boot_dev = USB_BOOT; - break; - default: - break; - } - - return boot_dev; -} - bool is_usb_boot(void) { return get_boot_device() == USB_BOOT; diff --git a/arch/arm/mach-imx/imx_romapi.c b/arch/arm/mach-imx/imx_romapi.c new file mode 100644 index 00000000000..3b2cc6935dc --- /dev/null +++ b/arch/arm/mach-imx/imx_romapi.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/global_data.h> +#include <env.h> +#include <env_internal.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern struct rom_api *g_rom_api; + +enum boot_device get_boot_device(void) +{ + volatile gd_t *pgd = gd; + int ret; + u32 boot; + u16 boot_type; + u8 boot_instance; + enum boot_device boot_dev = SD1_BOOT; + + ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, + ((uintptr_t)&boot) ^ QUERY_BT_DEV); + set_gd(pgd); + + if (ret != ROM_API_OKAY) { + puts("ROMAPI: failure at query_boot_info\n"); + return -1; + } + + boot_type = boot >> 16; + boot_instance = (boot >> 8) & 0xff; + + switch (boot_type) { + case BT_DEV_TYPE_SD: + boot_dev = boot_instance + SD1_BOOT; + break; + case BT_DEV_TYPE_MMC: + boot_dev = boot_instance + MMC1_BOOT; + break; + case BT_DEV_TYPE_NAND: + boot_dev = NAND_BOOT; + break; + case BT_DEV_TYPE_FLEXSPINOR: + boot_dev = QSPI_BOOT; + break; + case BT_DEV_TYPE_USB: + boot_dev = USB_BOOT; + break; + default: + break; + } + + return boot_dev; +}

From: Peng Fan peng.fan@nxp.com

Add i.MX9 Kconfig and basic files for the new SoC

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/Kconfig | 11 + arch/arm/include/asm/arch-imx/cpu.h | 2 + arch/arm/include/asm/arch-imx9/clock.h | 0 arch/arm/include/asm/arch-imx9/gpio.h | 0 arch/arm/include/asm/arch-imx9/imx-regs.h | 13 + arch/arm/include/asm/arch-imx9/imx93_pins.h | 729 ++++++++++++++++++++ arch/arm/include/asm/arch-imx9/sys_proto.h | 11 + arch/arm/include/asm/mach-imx/iomux-v3.h | 11 +- arch/arm/include/asm/mach-imx/sys_proto.h | 3 + arch/arm/mach-imx/Makefile | 11 +- arch/arm/mach-imx/imx9/Kconfig | 17 + arch/arm/mach-imx/imx9/Makefile | 6 + arch/arm/mach-imx/imx9/clock.c | 27 + arch/arm/mach-imx/imx9/lowlevel_init.S | 26 + arch/arm/mach-imx/imx9/soc.c | 127 ++++ arch/arm/mach-imx/spl.c | 2 +- 16 files changed, 991 insertions(+), 5 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx9/clock.h create mode 100644 arch/arm/include/asm/arch-imx9/gpio.h create mode 100644 arch/arm/include/asm/arch-imx9/imx-regs.h create mode 100644 arch/arm/include/asm/arch-imx9/imx93_pins.h create mode 100644 arch/arm/include/asm/arch-imx9/sys_proto.h create mode 100644 arch/arm/mach-imx/imx9/Kconfig create mode 100644 arch/arm/mach-imx/imx9/Makefile create mode 100644 arch/arm/mach-imx/imx9/clock.c create mode 100644 arch/arm/mach-imx/imx9/lowlevel_init.S create mode 100644 arch/arm/mach-imx/imx9/soc.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index dab785efad5..12ec661ac3b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -925,6 +925,15 @@ config ARCH_IMX8ULP imply CMD_DM imply DM_EVENT

+config ARCH_IMX9 + bool "NXP i.MX9 platform" + select ARM64 + select DM + select MACH_IMX + select SUPPORT_SPL + imply CMD_DM + imply DM_EVENT + config ARCH_IMXRT bool "NXP i.MXRT platform" select CPU_V7M @@ -2251,6 +2260,8 @@ source "arch/arm/mach-imx/imx8m/Kconfig"

source "arch/arm/mach-imx/imx8ulp/Kconfig"

+source "arch/arm/mach-imx/imx9/Kconfig" + source "arch/arm/mach-imx/imxrt/Kconfig"

source "arch/arm/mach-imx/mxs/Kconfig" diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 4f63803765e..d54e6e63352 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -59,6 +59,7 @@

#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ +#define MXC_CPU_IMX93 0xC1 /* dummy ID */

#define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 @@ -66,6 +67,7 @@ #define MXC_SOC_IMX8 0x90 /* dummy */ #define MXC_SOC_IMXRT 0xB0 /* dummy */ #define MXC_SOC_MX7ULP 0xE0 /* dummy */ +#define MXC_SOC_IMX9 0xC0 /* dummy */

#define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/include/asm/arch-imx9/gpio.h b/arch/arm/include/asm/arch-imx9/gpio.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h new file mode 100644 index 00000000000..2adbdadf03c --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_REGS_H__ +#define __ASM_ARCH_IMX9_REGS_H__ + +#define ARCH_MXC + +#define IOMUXC_BASE_ADDR 0x443C0000UL + +#endif diff --git a/arch/arm/include/asm/arch-imx9/imx93_pins.h b/arch/arm/include/asm/arch-imx9/imx93_pins.h new file mode 100644 index 00000000000..f13aef5619c --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/imx93_pins.h @@ -0,0 +1,729 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX93_PINS_H__ +#define __ASM_ARCH_IMX93_PINS_H__ + +#include <asm/mach-imx/iomux-v3.h> + +enum { + MX93_PAD_DAP_TDI__JTAG_MUX_TDI = IOMUX_PAD(0x1B0, 0x0000, 0, 0x3D8, 0, 0), + MX93_PAD_DAP_TDI__MQS2_LEFT = IOMUX_PAD(0x1B0, 0x0000, 1, 0x0000, 0, 0), + MX93_PAD_DAP_TDI__CAN2_TX = IOMUX_PAD(0x1B0, 0x0000, 3, 0x0000, 0, 0), + MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 = IOMUX_PAD(0x1B0, 0x0000, 4, 0x0000, 0, 0), + MX93_PAD_DAP_TDI__GPIO3_IO28 = IOMUX_PAD(0x1B0, 0x0000, 5, 0x0000, 0, 0), + MX93_PAD_DAP_TDI__LPUART5_RX = IOMUX_PAD(0x1B0, 0x0000, 6, 0x430, 0, 0), + + MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS = IOMUX_PAD(0x1B4, 0x0004, 0, 0x3DC, 0, 0), + MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 = IOMUX_PAD(0x1B4, 0x0004, 4, 0x0000, 0, 0), + MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 = IOMUX_PAD(0x1B4, 0x0004, 5, 0x0000, 0, 0), + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B = IOMUX_PAD(0x1B4, 0x0004, 6, 0x0000, 0, 0), + + MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK = IOMUX_PAD(0x1B8, 0x0008, 0, 0x3D4, 0, 0), + MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 = IOMUX_PAD(0x1B8, 0x0008, 4, 0x0000, 0, 0), + MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 = IOMUX_PAD(0x1B8, 0x0008, 5, 0x0000, 0, 0), + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B = IOMUX_PAD(0x1B8, 0x0008, 6, 0x42C, 0, 0), + + MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO = IOMUX_PAD(0x1BC, 0x000C, 0, 0x0000, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT = IOMUX_PAD(0x1BC, 0x000C, 1, 0x0000, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX = IOMUX_PAD(0x1BC, 0x000C, 3, 0x364, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 = IOMUX_PAD(0x1BC, 0x000C, 4, 0x0000, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 = IOMUX_PAD(0x1BC, 0x000C, 5, 0x0000, 0, 0), + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX = IOMUX_PAD(0x1BC, 0x000C, 6, 0x434, 0, 0), + + MX93_PAD_GPIO_IO00__GPIO2_IO00 = IOMUX_PAD(0x1C0, 0x0010, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO00__LPI2C3_SDA = IOMUX_PAD(0x1C0, 0x0010, 1, 0x3E4, 0, 0), + MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK = IOMUX_PAD(0x1C0, 0x0010, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK = IOMUX_PAD(0x1C0, 0x0010, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO00__LPSPI6_PCS0 = IOMUX_PAD(0x1C0, 0x0010, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO00__LPUART5_TX = IOMUX_PAD(0x1C0, 0x0010, 5, 0x434, 1, 0), + MX93_PAD_GPIO_IO00__LPI2C5_SDA = IOMUX_PAD(0x1C0, 0x0010, 6, 0x3EC, 0, 0), + MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 = IOMUX_PAD(0x1C0, 0x0010, 7, 0x36C, 0, 0), + + MX93_PAD_GPIO_IO01__GPIO2_IO01 = IOMUX_PAD(0x1C4, 0x0014, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO01__LPI2C3_SCL = IOMUX_PAD(0x1C4, 0x0014, 1, 0x3E0, 0, 0), + MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 = IOMUX_PAD(0x1C4, 0x0014, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE = IOMUX_PAD(0x1C4, 0x0014, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO01__LPSPI6_SIN = IOMUX_PAD(0x1C4, 0x0014, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO01__LPUART5_RX = IOMUX_PAD(0x1C4, 0x0014, 5, 0x430, 1, 0), + MX93_PAD_GPIO_IO01__LPI2C5_SCL = IOMUX_PAD(0x1C4, 0x0014, 6, 0x3E8, 0, 0), + MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 = IOMUX_PAD(0x1C4, 0x0014, 7, 0x370, 0, 0), + + MX93_PAD_GPIO_IO02__GPIO2_IO02 = IOMUX_PAD(0x1C8, 0x0018, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__LPI2C4_SDA = IOMUX_PAD(0x1C8, 0x0018, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC = IOMUX_PAD(0x1C8, 0x0018, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC = IOMUX_PAD(0x1C8, 0x0018, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__LPSPI6_SOUT = IOMUX_PAD(0x1C8, 0x0018, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO02__LPUART5_CTS_B = IOMUX_PAD(0x1C8, 0x0018, 5, 0x42C, 1, 0), + MX93_PAD_GPIO_IO02__LPI2C6_SDA = IOMUX_PAD(0x1C8, 0x0018, 6, 0x3F4, 0, 0), + MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 = IOMUX_PAD(0x1C8, 0x0018, 7, 0x374, 0, 0), + + MX93_PAD_GPIO_IO03__GPIO2_IO03 = IOMUX_PAD(0x1CC, 0x001C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPI2C4_SCL = IOMUX_PAD(0x1CC, 0x001C, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC = IOMUX_PAD(0x1CC, 0x001C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC = IOMUX_PAD(0x1CC, 0x001C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPSPI6_SCK = IOMUX_PAD(0x1CC, 0x001C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPUART5_RTS_B = IOMUX_PAD(0x1CC, 0x001C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO03__LPI2C6_SCL = IOMUX_PAD(0x1CC, 0x001C, 6, 0x3F0, 0, 0), + MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 = IOMUX_PAD(0x1CC, 0x001C, 7, 0x378, 0, 0), + + MX93_PAD_GPIO_IO04__GPIO2_IO04 = IOMUX_PAD(0x1D0, 0x0020, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__TPM3_CH0 = IOMUX_PAD(0x1D0, 0x0020, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__PDM_CLK = IOMUX_PAD(0x1D0, 0x0020, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 = IOMUX_PAD(0x1D0, 0x0020, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__LPSPI7_PCS0 = IOMUX_PAD(0x1D0, 0x0020, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__LPUART6_TX = IOMUX_PAD(0x1D0, 0x0020, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO04__LPI2C6_SDA = IOMUX_PAD(0x1D0, 0x0020, 6, 0x3F4, 1, 0), + MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 = IOMUX_PAD(0x1D0, 0x0020, 7, 0x37C, 0, 0), + + MX93_PAD_GPIO_IO05__GPIO2_IO05 = IOMUX_PAD(0x1D4, 0x0024, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__TPM4_CH0 = IOMUX_PAD(0x1D4, 0x0024, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 = IOMUX_PAD(0x1D4, 0x0024, 2, 0x438, 0, 0), + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 = IOMUX_PAD(0x1D4, 0x0024, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__LPSPI7_SIN = IOMUX_PAD(0x1D4, 0x0024, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__LPUART6_RX = IOMUX_PAD(0x1D4, 0x0024, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO05__LPI2C6_SCL = IOMUX_PAD(0x1D4, 0x0024, 6, 0x3F0, 1, 0), + MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 = IOMUX_PAD(0x1D4, 0x0024, 7, 0x380, 0, 0), + + MX93_PAD_GPIO_IO06__GPIO2_IO06 = IOMUX_PAD(0x1D8, 0x0028, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__TPM5_CH0 = IOMUX_PAD(0x1D8, 0x0028, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 = IOMUX_PAD(0x1D8, 0x0028, 2, 0x43C, 0, 0), + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 = IOMUX_PAD(0x1D8, 0x0028, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__LPSPI7_SOUT = IOMUX_PAD(0x1D8, 0x0028, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__LPUART6_CTS_B = IOMUX_PAD(0x1D8, 0x0028, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO06__LPI2C7_SDA = IOMUX_PAD(0x1D8, 0x0028, 6, 0x3FC, 0, 0), + MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 = IOMUX_PAD(0x1D8, 0x0028, 7, 0x384, 0, 0), + + MX93_PAD_GPIO_IO07__GPIO2_IO07 = IOMUX_PAD(0x1DC, 0x002C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__LPSPI3_PCS1 = IOMUX_PAD(0x1DC, 0x002C, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 = IOMUX_PAD(0x1DC, 0x002C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 = IOMUX_PAD(0x1DC, 0x002C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__LPSPI7_SCK = IOMUX_PAD(0x1DC, 0x002C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__LPUART6_RTS_B = IOMUX_PAD(0x1DC, 0x002C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO07__LPI2C7_SCL = IOMUX_PAD(0x1DC, 0x002C, 6, 0x3F8, 0, 0), + MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 = IOMUX_PAD(0x1DC, 0x002C, 7, 0x388, 0, 0), + + MX93_PAD_GPIO_IO08__GPIO2_IO08 = IOMUX_PAD(0x1E0, 0x0030, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__LPSPI3_PCS0 = IOMUX_PAD(0x1E0, 0x0030, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 = IOMUX_PAD(0x1E0, 0x0030, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 = IOMUX_PAD(0x1E0, 0x0030, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__TPM6_CH0 = IOMUX_PAD(0x1E0, 0x0030, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__LPUART7_TX = IOMUX_PAD(0x1E0, 0x0030, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO08__LPI2C7_SDA = IOMUX_PAD(0x1E0, 0x0030, 6, 0x3FC, 1, 0), + MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 = IOMUX_PAD(0x1E0, 0x0030, 7, 0x38C, 0, 0), + + MX93_PAD_GPIO_IO09__GPIO2_IO09 = IOMUX_PAD(0x1E4, 0x0034, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__LPSPI3_SIN = IOMUX_PAD(0x1E4, 0x0034, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 = IOMUX_PAD(0x1E4, 0x0034, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 = IOMUX_PAD(0x1E4, 0x0034, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__TPM3_EXTCLK = IOMUX_PAD(0x1E4, 0x0034, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__LPUART7_RX = IOMUX_PAD(0x1E4, 0x0034, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO09__LPI2C7_SCL = IOMUX_PAD(0x1E4, 0x0034, 6, 0x3F8, 1, 0), + MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 = IOMUX_PAD(0x1E4, 0x0034, 7, 0x390, 0, 0), + + MX93_PAD_GPIO_IO10__GPIO2_IO10 = IOMUX_PAD(0x1E8, 0x0038, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__LPSPI3_SOUT = IOMUX_PAD(0x1E8, 0x0038, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 = IOMUX_PAD(0x1E8, 0x0038, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 = IOMUX_PAD(0x1E8, 0x0038, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__TPM4_EXTCLK = IOMUX_PAD(0x1E8, 0x0038, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__LPUART7_CTS_B = IOMUX_PAD(0x1E8, 0x0038, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO10__LPI2C8_SDA = IOMUX_PAD(0x1E8, 0x0038, 6, 0x404, 0, 0), + MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x1E8, 0x0038, 7, 0x394, 0, 0), + + MX93_PAD_GPIO_IO11__GPIO2_IO11 = IOMUX_PAD(0x1EC, 0x003C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__LPSPI3_SCK = IOMUX_PAD(0x1EC, 0x003C, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 = IOMUX_PAD(0x1EC, 0x003C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 = IOMUX_PAD(0x1EC, 0x003C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__TPM5_EXTCLK = IOMUX_PAD(0x1EC, 0x003C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__LPUART7_RTS_B = IOMUX_PAD(0x1EC, 0x003C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO11__LPI2C8_SCL = IOMUX_PAD(0x1EC, 0x003C, 6, 0x400, 0, 0), + MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x1EC, 0x003C, 7, 0x398, 0, 0), + + MX93_PAD_GPIO_IO12__GPIO2_IO12 = IOMUX_PAD(0x1F0, 0x0040, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__TPM3_CH2 = IOMUX_PAD(0x1F0, 0x0040, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 = IOMUX_PAD(0x1F0, 0x0040, 2, 0x440, 0, 0), + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 = IOMUX_PAD(0x1F0, 0x0040, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__LPSPI8_PCS0 = IOMUX_PAD(0x1F0, 0x0040, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__LPUART8_TX = IOMUX_PAD(0x1F0, 0x0040, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO12__LPI2C8_SDA = IOMUX_PAD(0x1F0, 0x0040, 6, 0x404, 1, 0), + MX93_PAD_GPIO_IO12__SAI3_RX_SYNC = IOMUX_PAD(0x1F0, 0x0040, 7, 0x450, 0, 0), + + MX93_PAD_GPIO_IO13__GPIO2_IO13 = IOMUX_PAD(0x1F4, 0x0044, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__TPM4_CH2 = IOMUX_PAD(0x1F4, 0x0044, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 = IOMUX_PAD(0x1F4, 0x0044, 2, 0x444, 0, 0), + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 = IOMUX_PAD(0x1F4, 0x0044, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__LPSPI8_SIN = IOMUX_PAD(0x1F4, 0x0044, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__LPUART8_RX = IOMUX_PAD(0x1F4, 0x0044, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO13__LPI2C8_SCL = IOMUX_PAD(0x1F4, 0x0044, 6, 0x400, 1, 0), + MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x1F4, 0x0044, 7, 0x39C, 0, 0), + + MX93_PAD_GPIO_IO14__GPIO2_IO14 = IOMUX_PAD(0x1F8, 0x0048, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__LPUART3_TX = IOMUX_PAD(0x1F8, 0x0048, 1, 0x41C, 0, 0), + MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 = IOMUX_PAD(0x1F8, 0x0048, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 = IOMUX_PAD(0x1F8, 0x0048, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__LPSPI8_SOUT = IOMUX_PAD(0x1F8, 0x0048, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__LPUART8_CTS_B = IOMUX_PAD(0x1F8, 0x0048, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO14__LPUART4_TX = IOMUX_PAD(0x1F8, 0x0048, 6, 0x428, 0, 0), + MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x1F8, 0x0048, 7, 0x3A0, 0, 0), + + MX93_PAD_GPIO_IO15__GPIO2_IO15 = IOMUX_PAD(0x1FC, 0x004C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__LPUART3_RX = IOMUX_PAD(0x1FC, 0x004C, 1, 0x418, 0, 0), + MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 = IOMUX_PAD(0x1FC, 0x004C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 = IOMUX_PAD(0x1FC, 0x004C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__LPSPI8_SCK = IOMUX_PAD(0x1FC, 0x004C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__LPUART8_RTS_B = IOMUX_PAD(0x1FC, 0x004C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO15__LPUART4_RX = IOMUX_PAD(0x1FC, 0x004C, 6, 0x424, 0, 0), + MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x1FC, 0x004C, 7, 0x3A4, 0, 0), + + MX93_PAD_GPIO_IO16__GPIO2_IO16 = IOMUX_PAD(0x200, 0x0050, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK = IOMUX_PAD(0x200, 0x0050, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 = IOMUX_PAD(0x200, 0x0050, 2, 0x440, 1, 0), + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 = IOMUX_PAD(0x200, 0x0050, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO16__LPUART3_CTS_B = IOMUX_PAD(0x200, 0x0050, 4, 0x414, 0, 0), + MX93_PAD_GPIO_IO16__LPSPI4_PCS2 = IOMUX_PAD(0x200, 0x0050, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO16__LPUART4_CTS_B = IOMUX_PAD(0x200, 0x0050, 6, 0x420, 0, 0), + MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x200, 0x0050, 7, 0x3A8, 0, 0), + + MX93_PAD_GPIO_IO17__GPIO2_IO17 = IOMUX_PAD(0x204, 0x0054, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__SAI3_MCLK = IOMUX_PAD(0x204, 0x0054, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 = IOMUX_PAD(0x204, 0x0054, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 = IOMUX_PAD(0x204, 0x0054, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__LPUART3_RTS_B = IOMUX_PAD(0x204, 0x0054, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__LPSPI4_PCS1 = IOMUX_PAD(0x204, 0x0054, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__LPUART4_RTS_B = IOMUX_PAD(0x204, 0x0054, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x204, 0x0054, 7, 0x3AC, 0, 0), + + MX93_PAD_GPIO_IO18__GPIO2_IO18 = IOMUX_PAD(0x208, 0x0058, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__SAI3_RX_BCLK = IOMUX_PAD(0x208, 0x0058, 1, 0x44C, 0, 0), + MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 = IOMUX_PAD(0x208, 0x0058, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 = IOMUX_PAD(0x208, 0x0058, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__LPSPI5_PCS0 = IOMUX_PAD(0x208, 0x0058, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__LPSPI4_PCS0 = IOMUX_PAD(0x208, 0x0058, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__TPM5_CH2 = IOMUX_PAD(0x208, 0x0058, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x208, 0x0058, 7, 0x3B0, 0, 0), + + MX93_PAD_GPIO_IO19__GPIO2_IO19 = IOMUX_PAD(0x20C, 0x005C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__SAI3_RX_SYNC = IOMUX_PAD(0x20C, 0x005C, 1, 0x450, 1, 0), + MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 = IOMUX_PAD(0x20C, 0x005C, 2, 0x444, 1, 0), + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 = IOMUX_PAD(0x20C, 0x005C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__LPSPI5_SIN = IOMUX_PAD(0x20C, 0x005C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__LPSPI4_SIN = IOMUX_PAD(0x20C, 0x005C, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__TPM6_CH2 = IOMUX_PAD(0x20C, 0x005C, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 = IOMUX_PAD(0x20C, 0x005C, 7, 0x0000, 0, 0), + + MX93_PAD_GPIO_IO20__GPIO2_IO20 = IOMUX_PAD(0x210, 0x0060, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 = IOMUX_PAD(0x210, 0x0060, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 = IOMUX_PAD(0x210, 0x0060, 2, 0x438, 1, 0), + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 = IOMUX_PAD(0x210, 0x0060, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__LPSPI5_SOUT = IOMUX_PAD(0x210, 0x0060, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__LPSPI4_SOUT = IOMUX_PAD(0x210, 0x0060, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__TPM3_CH1 = IOMUX_PAD(0x210, 0x0060, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x210, 0x0060, 7, 0x3B4, 0, 0), + + MX93_PAD_GPIO_IO21__GPIO2_IO21 = IOMUX_PAD(0x214, 0x0064, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 = IOMUX_PAD(0x214, 0x0064, 1, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__PDM_CLK = IOMUX_PAD(0x214, 0x0064, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 = IOMUX_PAD(0x214, 0x0064, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__LPSPI5_SCK = IOMUX_PAD(0x214, 0x0064, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__LPSPI4_SCK = IOMUX_PAD(0x214, 0x0064, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__TPM4_CH1 = IOMUX_PAD(0x214, 0x0064, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO21__SAI3_RX_BCLK = IOMUX_PAD(0x214, 0x0064, 7, 0x44C, 1, 0), + + MX93_PAD_GPIO_IO22__GPIO2_IO22 = IOMUX_PAD(0x218, 0x0068, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO22__USDHC3_CLK = IOMUX_PAD(0x218, 0x0068, 1, 0x458, 0, 0), + MX93_PAD_GPIO_IO22__SPDIF_IN = IOMUX_PAD(0x218, 0x0068, 2, 0x454, 0, 0), + MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 = IOMUX_PAD(0x218, 0x0068, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO22__TPM5_CH1 = IOMUX_PAD(0x218, 0x0068, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO22__TPM6_EXTCLK = IOMUX_PAD(0x218, 0x0068, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO22__LPI2C5_SDA = IOMUX_PAD(0x218, 0x0068, 6, 0x3EC, 1, 0), + MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x218, 0x0068, 7, 0x3B8, 0, 0), + + MX93_PAD_GPIO_IO23__GPIO2_IO23 = IOMUX_PAD(0x21C, 0x006C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO23__USDHC3_CMD = IOMUX_PAD(0x21C, 0x006C, 1, 0x45C, 0, 0), + MX93_PAD_GPIO_IO23__SPDIF_OUT = IOMUX_PAD(0x21C, 0x006C, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 = IOMUX_PAD(0x21C, 0x006C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO23__TPM6_CH1 = IOMUX_PAD(0x21C, 0x006C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO23__LPI2C5_SCL = IOMUX_PAD(0x21C, 0x006C, 6, 0x3E8, 1, 0), + MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x21C, 0x006C, 7, 0x3BC, 0, 0), + + MX93_PAD_GPIO_IO24__GPIO2_IO24 = IOMUX_PAD(0x220, 0x0070, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__USDHC3_DATA0 = IOMUX_PAD(0x220, 0x0070, 1, 0x460, 0, 0), + MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 = IOMUX_PAD(0x220, 0x0070, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__TPM3_CH3 = IOMUX_PAD(0x220, 0x0070, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__JTAG_MUX_TDO = IOMUX_PAD(0x220, 0x0070, 5, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__LPSPI6_PCS1 = IOMUX_PAD(0x220, 0x0070, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x220, 0x0070, 7, 0x3C0, 0, 0), + + MX93_PAD_GPIO_IO25__GPIO2_IO25 = IOMUX_PAD(0x224, 0x0074, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__USDHC3_DATA1 = IOMUX_PAD(0x224, 0x0074, 1, 0x464, 0, 0), + MX93_PAD_GPIO_IO25__CAN2_TX = IOMUX_PAD(0x224, 0x0074, 2, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 = IOMUX_PAD(0x224, 0x0074, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__TPM4_CH3 = IOMUX_PAD(0x224, 0x0074, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__JTAG_MUX_TCK = IOMUX_PAD(0x224, 0x0074, 5, 0x3D4, 1, 0), + MX93_PAD_GPIO_IO25__LPSPI7_PCS1 = IOMUX_PAD(0x224, 0x0074, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x224, 0x0074, 7, 0x3C4, 0, 0), + + MX93_PAD_GPIO_IO26__GPIO2_IO26 = IOMUX_PAD(0x228, 0x0078, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO26__USDHC3_DATA2 = IOMUX_PAD(0x228, 0x0078, 1, 0x468, 0, 0), + MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 = IOMUX_PAD(0x228, 0x0078, 2, 0x43C, 1, 0), + MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 = IOMUX_PAD(0x228, 0x0078, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO26__TPM5_CH3 = IOMUX_PAD(0x228, 0x0078, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO26__JTAG_MUX_TDI = IOMUX_PAD(0x228, 0x0078, 5, 0x3D8, 1, 0), + MX93_PAD_GPIO_IO26__LPSPI8_PCS1 = IOMUX_PAD(0x228, 0x0078, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC = IOMUX_PAD(0x228, 0x0078, 7, 0x0000, 0, 0), + + MX93_PAD_GPIO_IO27__GPIO2_IO27 = IOMUX_PAD(0x22C, 0x007C, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO27__USDHC3_DATA3 = IOMUX_PAD(0x22C, 0x007C, 1, 0x46C, 0, 0), + MX93_PAD_GPIO_IO27__CAN2_RX = IOMUX_PAD(0x22C, 0x007C, 2, 0x364, 1, 0), + MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 = IOMUX_PAD(0x22C, 0x007C, 3, 0x0000, 0, 0), + MX93_PAD_GPIO_IO27__TPM6_CH3 = IOMUX_PAD(0x22C, 0x007C, 4, 0x0000, 0, 0), + MX93_PAD_GPIO_IO27__JTAG_MUX_TMS = IOMUX_PAD(0x22C, 0x007C, 5, 0x3DC, 1, 0), + MX93_PAD_GPIO_IO27__LPSPI5_PCS1 = IOMUX_PAD(0x22C, 0x007C, 6, 0x0000, 0, 0), + MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x22C, 0x007C, 7, 0x3C8, 0, 0), + + MX93_PAD_GPIO_IO28__GPIO2_IO28 = IOMUX_PAD(0x230, 0x0080, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO28__LPI2C3_SDA = IOMUX_PAD(0x230, 0x0080, 1, 0x3E4, 1, 0), + MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 = IOMUX_PAD(0x230, 0x0080, 7, 0x0000, 0, 0), + + MX93_PAD_GPIO_IO29__GPIO2_IO29 = IOMUX_PAD(0x234, 0x0084, 0, 0x0000, 0, 0), + MX93_PAD_GPIO_IO29__LPI2C3_SCL = IOMUX_PAD(0x234, 0x0084, 1, 0x3E0, 1, 0), + MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 = IOMUX_PAD(0x234, 0x0084, 7, 0x0000, 0, 0), + + MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x238, 0x0088, 0, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 = IOMUX_PAD(0x238, 0x0088, 4, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO1__GPIO3_IO26 = IOMUX_PAD(0x238, 0x0088, 5, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO2__GPIO3_IO27 = IOMUX_PAD(0x23C, 0x008C, 5, 0x0000, 0, 0), + + MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x23C, 0x008C, 0, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x23C, 0x008C, 4, 0x3C8, 1, 0), + + MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 = IOMUX_PAD(0x240, 0x0090, 0, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 = IOMUX_PAD(0x240, 0x0090, 4, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO3__GPIO4_IO28 = IOMUX_PAD(0x240, 0x0090, 5, 0x0000, 0, 0), + + MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 = IOMUX_PAD(0x244, 0x0094, 0, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 = IOMUX_PAD(0x244, 0x0094, 4, 0x0000, 0, 0), + MX93_PAD_CCM_CLKO4__GPIO4_IO29 = IOMUX_PAD(0x244, 0x0094, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_MDC__ENET_QOS_MDC = IOMUX_PAD(0x248, 0x0098, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_MDC__LPUART3_DCB_B = IOMUX_PAD(0x248, 0x0098, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_MDC__I3C2_SCL = IOMUX_PAD(0x248, 0x0098, 2, 0x3CC, 0, 0), + MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 = IOMUX_PAD(0x248, 0x0098, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 = IOMUX_PAD(0x248, 0x0098, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_MDC__GPIO4_IO00 = IOMUX_PAD(0x248, 0x0098, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO = IOMUX_PAD(0x24C, 0x009C, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_MDIO__LPUART3_RIN_B = IOMUX_PAD(0x24C, 0x009C, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_MDIO__I3C2_SDA = IOMUX_PAD(0x24C, 0x009C, 2, 0x3D0, 0, 0), + MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 = IOMUX_PAD(0x24C, 0x009C, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 = IOMUX_PAD(0x24C, 0x009C, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_MDIO__GPIO4_IO01 = IOMUX_PAD(0x24C, 0x009C, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 = IOMUX_PAD(0x250, 0x00A0, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TD3__CAN2_TX = IOMUX_PAD(0x250, 0x00A0, 2, 0x0000, 0, 0), + MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 = IOMUX_PAD(0x250, 0x00A0, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 = IOMUX_PAD(0x250, 0x00A0, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TD3__GPIO4_IO02 = IOMUX_PAD(0x250, 0x00A0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x254, 0x00A4, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK = IOMUX_PAD(0x254, 0x00A4, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_TD2__CAN2_RX = IOMUX_PAD(0x254, 0x00A4, 2, 0x364, 2, 0), + MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 = IOMUX_PAD(0x254, 0x00A4, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 = IOMUX_PAD(0x254, 0x00A4, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TD2__GPIO4_IO03 = IOMUX_PAD(0x254, 0x00A4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 = IOMUX_PAD(0x258, 0x00A8, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__LPUART3_RTS_B = IOMUX_PAD(0x258, 0x00A8, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__I3C2_PUR = IOMUX_PAD(0x258, 0x00A8, 2, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 = IOMUX_PAD(0x258, 0x00A8, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 = IOMUX_PAD(0x258, 0x00A8, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__GPIO4_IO04 = IOMUX_PAD(0x258, 0x00A8, 5, 0x0000, 0, 0), + MX93_PAD_ENET1_TD1__I3C2_PUR_B = IOMUX_PAD(0x258, 0x00A8, 6, 0x0000, 0, 0), + + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 = IOMUX_PAD(0x25C, 0x00AC, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TD0__LPUART3_TX = IOMUX_PAD(0x25C, 0x00AC, 1, 0x41C, 1, 0), + MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 = IOMUX_PAD(0x25C, 0x00AC, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TD0__GPIO4_IO05 = IOMUX_PAD(0x25C, 0x00AC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL = IOMUX_PAD(0x260, 0x00B0, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B = IOMUX_PAD(0x260, 0x00B0, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 = IOMUX_PAD(0x260, 0x00B0, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 = IOMUX_PAD(0x260, 0x00B0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK = IOMUX_PAD(0x264, 0x00B4, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER = IOMUX_PAD(0x264, 0x00B4, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 = IOMUX_PAD(0x264, 0x00B4, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_TXC__GPIO4_IO07 = IOMUX_PAD(0x264, 0x00B4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL = IOMUX_PAD(0x268, 0x00B8, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B = IOMUX_PAD(0x268, 0x00B8, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 = IOMUX_PAD(0x268, 0x00B8, 3, 0x0000, 0, 0), + MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 = IOMUX_PAD(0x268, 0x00B8, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 = IOMUX_PAD(0x268, 0x00B8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK = IOMUX_PAD(0x26C, 0x00BC, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER = IOMUX_PAD(0x26C, 0x00BC, 1, 0x0000, 0, 0), + MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 = IOMUX_PAD(0x26C, 0x00BC, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RXC__GPIO4_IO09 = IOMUX_PAD(0x26C, 0x00BC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 = IOMUX_PAD(0x270, 0x00C0, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RD0__LPUART3_RX = IOMUX_PAD(0x270, 0x00C0, 1, 0x418, 1, 0), + MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 = IOMUX_PAD(0x270, 0x00C0, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RD0__GPIO4_IO10 = IOMUX_PAD(0x270, 0x00C0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 = IOMUX_PAD(0x274, 0x00C4, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RD1__LPUART3_CTS_B = IOMUX_PAD(0x274, 0x00C4, 1, 0x414, 1, 0), + MX93_PAD_ENET1_RD1__LPTMR2_ALT1 = IOMUX_PAD(0x274, 0x00C4, 3, 0x408, 0, 0), + MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 = IOMUX_PAD(0x274, 0x00C4, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RD1__GPIO4_IO11 = IOMUX_PAD(0x274, 0x00C4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 = IOMUX_PAD(0x278, 0x00C8, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RD2__LPTMR2_ALT2 = IOMUX_PAD(0x278, 0x00C8, 3, 0x40C, 0, 0), + MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 = IOMUX_PAD(0x278, 0x00C8, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RD2__GPIO4_IO12 = IOMUX_PAD(0x278, 0x00C8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 = IOMUX_PAD(0x27C, 0x00CC, 0, 0x0000, 0, 0), + MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER = IOMUX_PAD(0x27C, 0x00CC, 2, 0x0000, 0, 0), + MX93_PAD_ENET1_RD3__LPTMR2_ALT3 = IOMUX_PAD(0x27C, 0x00CC, 3, 0x410, 0, 0), + MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 = IOMUX_PAD(0x27C, 0x00CC, 4, 0x0000, 0, 0), + MX93_PAD_ENET1_RD3__GPIO4_IO13 = IOMUX_PAD(0x27C, 0x00CC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_MDC__ENET1_MDC = IOMUX_PAD(0x280, 0x00D0, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_MDC__LPUART4_DCB_B = IOMUX_PAD(0x280, 0x00D0, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_MDC__SAI2_RX_SYNC = IOMUX_PAD(0x280, 0x00D0, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 = IOMUX_PAD(0x280, 0x00D0, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_MDC__GPIO4_IO14 = IOMUX_PAD(0x280, 0x00D0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_MDIO__ENET1_MDIO = IOMUX_PAD(0x284, 0x00D4, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_MDIO__LPUART4_RIN_B = IOMUX_PAD(0x284, 0x00D4, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK = IOMUX_PAD(0x284, 0x00D4, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 = IOMUX_PAD(0x284, 0x00D4, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_MDIO__GPIO4_IO15 = IOMUX_PAD(0x284, 0x00D4, 5, 0x0000, 0, 0), + MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 = IOMUX_PAD(0x288, 0x00D8, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 = IOMUX_PAD(0x288, 0x00D8, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TD3__GPIO4_IO16 = IOMUX_PAD(0x288, 0x00D8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x288, 0x00D8, 0, 0x0000, 0, 0), + + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x28C, 0x00DC, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TD2__ENET1_TX_CLK = IOMUX_PAD(0x28C, 0x00DC, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 = IOMUX_PAD(0x28C, 0x00DC, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 = IOMUX_PAD(0x28C, 0x00DC, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TD2__GPIO4_IO17 = IOMUX_PAD(0x28C, 0x00DC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x290, 0x00E0, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TD1__LPUART4_RTS_B = IOMUX_PAD(0x290, 0x00E0, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 = IOMUX_PAD(0x290, 0x00E0, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 = IOMUX_PAD(0x290, 0x00E0, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TD1__GPIO4_IO18 = IOMUX_PAD(0x290, 0x00E0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x294, 0x00E4, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TD0__LPUART4_TX = IOMUX_PAD(0x294, 0x00E4, 1, 0x428, 1, 0), + MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 = IOMUX_PAD(0x294, 0x00E4, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 = IOMUX_PAD(0x294, 0x00E4, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TD0__GPIO4_IO19 = IOMUX_PAD(0x294, 0x00E4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x298, 0x00E8, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B = IOMUX_PAD(0x298, 0x00E8, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC = IOMUX_PAD(0x298, 0x00E8, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 = IOMUX_PAD(0x298, 0x00E8, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 = IOMUX_PAD(0x298, 0x00E8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x29C, 0x00EC, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_TXC__ENET1_TX_ER = IOMUX_PAD(0x29C, 0x00EC, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x29C, 0x00EC, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 = IOMUX_PAD(0x29C, 0x00EC, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_TXC__GPIO4_IO21 = IOMUX_PAD(0x29C, 0x00EC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x2A0, 0x00F0, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B = IOMUX_PAD(0x2A0, 0x00F0, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 = IOMUX_PAD(0x2A0, 0x00F0, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 = IOMUX_PAD(0x2A0, 0x00F0, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 = IOMUX_PAD(0x2A0, 0x00F0, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x2A4, 0x00F4, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RXC__ENET1_RX_ER = IOMUX_PAD(0x2A4, 0x00F4, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 = IOMUX_PAD(0x2A4, 0x00F4, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 = IOMUX_PAD(0x2A4, 0x00F4, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RXC__GPIO4_IO23 = IOMUX_PAD(0x2A4, 0x00F4, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x2A8, 0x00F8, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RD0__LPUART4_RX = IOMUX_PAD(0x2A8, 0x00F8, 1, 0x424, 1, 0), + MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 = IOMUX_PAD(0x2A8, 0x00F8, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 = IOMUX_PAD(0x2A8, 0x00F8, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RD0__GPIO4_IO24 = IOMUX_PAD(0x2A8, 0x00F8, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x2AC, 0x00FC, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RD1__SPDIF_IN = IOMUX_PAD(0x2AC, 0x00FC, 1, 0x454, 1, 0), + MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 = IOMUX_PAD(0x2AC, 0x00FC, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 = IOMUX_PAD(0x2AC, 0x00FC, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RD1__GPIO4_IO25 = IOMUX_PAD(0x2AC, 0x00FC, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x2B0, 0x100, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RD2__LPUART4_CTS_B = IOMUX_PAD(0x2B0, 0x100, 1, 0x420, 1, 0), + MX93_PAD_ENET2_RD2__SAI2_MCLK = IOMUX_PAD(0x2B0, 0x100, 2, 0x0000, 0, 0), + MX93_PAD_ENET2_RD2__MQS2_RIGHT = IOMUX_PAD(0x2B0, 0x100, 3, 0x0000, 0, 0), + MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 = IOMUX_PAD(0x2B0, 0x100, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RD2__GPIO4_IO26 = IOMUX_PAD(0x2B0, 0x100, 5, 0x0000, 0, 0), + + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x2B4, 0x104, 0, 0x0000, 0, 0), + MX93_PAD_ENET2_RD3__SPDIF_OUT = IOMUX_PAD(0x2B4, 0x104, 1, 0x0000, 0, 0), + MX93_PAD_ENET2_RD3__SPDIF_IN = IOMUX_PAD(0x2B4, 0x104, 2, 0x454, 2, 0), + MX93_PAD_ENET2_RD3__MQS2_LEFT = IOMUX_PAD(0x2B4, 0x104, 3, 0x0000, 0, 0), + MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 = IOMUX_PAD(0x2B4, 0x104, 4, 0x0000, 0, 0), + MX93_PAD_ENET2_RD3__GPIO4_IO27 = IOMUX_PAD(0x2B4, 0x104, 5, 0x0000, 0, 0), + MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 = IOMUX_PAD(0x2B8, 0x108, 4, 0x38C, 1, 0), + MX93_PAD_SD1_CLK__GPIO3_IO08 = IOMUX_PAD(0x2B8, 0x108, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x2B8, 0x108, 0, 0x0000, 0, 0), + + MX93_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x2BC, 0x10C, 0, 0x0000, 0, 0), + MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 = IOMUX_PAD(0x2BC, 0x10C, 4, 0x390, 1, 0), + MX93_PAD_SD1_CMD__GPIO3_IO09 = IOMUX_PAD(0x2BC, 0x10C, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x2C0, 0x110, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x2C0, 0x110, 4, 0x394, 1, 0), + MX93_PAD_SD1_DATA0__GPIO3_IO10 = IOMUX_PAD(0x2C0, 0x110, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x2C4, 0x114, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x2C4, 0x114, 4, 0x398, 1, 0), + MX93_PAD_SD1_DATA1__GPIO3_IO11 = IOMUX_PAD(0x2C4, 0x114, 5, 0x0000, 0, 0), + MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x2C4, 0x114, 6, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x2C8, 0x118, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 = IOMUX_PAD(0x2C8, 0x118, 4, 0x0000, 0, 0), + MX93_PAD_SD1_DATA2__GPIO3_IO12 = IOMUX_PAD(0x2C8, 0x118, 5, 0x0000, 0, 0), + MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x2C8, 0x118, 6, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x2CC, 0x11C, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B = IOMUX_PAD(0x2CC, 0x11C, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x2CC, 0x11C, 4, 0x39C, 1, 0), + MX93_PAD_SD1_DATA3__GPIO3_IO13 = IOMUX_PAD(0x2CC, 0x11C, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x2D0, 0x120, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 = IOMUX_PAD(0x2D0, 0x120, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x2D0, 0x120, 4, 0x3A0, 1, 0), + MX93_PAD_SD1_DATA4__GPIO3_IO14 = IOMUX_PAD(0x2D0, 0x120, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x2D4, 0x124, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 = IOMUX_PAD(0x2D4, 0x124, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA5__USDHC1_RESET_B = IOMUX_PAD(0x2D4, 0x124, 2, 0x0000, 0, 0), + MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x2D4, 0x124, 4, 0x3A4, 1, 0), + MX93_PAD_SD1_DATA5__GPIO3_IO15 = IOMUX_PAD(0x2D4, 0x124, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x2D8, 0x128, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 = IOMUX_PAD(0x2D8, 0x128, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA6__USDHC1_CD_B = IOMUX_PAD(0x2D8, 0x128, 2, 0x0000, 0, 0), + MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x2D8, 0x128, 4, 0x3A8, 1, 0), + MX93_PAD_SD1_DATA6__GPIO3_IO16 = IOMUX_PAD(0x2D8, 0x128, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x2DC, 0x12C, 0, 0x0000, 0, 0), + MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 = IOMUX_PAD(0x2DC, 0x12C, 1, 0x0000, 0, 0), + MX93_PAD_SD1_DATA7__USDHC1_WP = IOMUX_PAD(0x2DC, 0x12C, 2, 0x0000, 0, 0), + MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x2DC, 0x12C, 4, 0x3AC, 1, 0), + MX93_PAD_SD1_DATA7__GPIO3_IO17 = IOMUX_PAD(0x2DC, 0x12C, 5, 0x0000, 0, 0), + + MX93_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x2E0, 0x130, 0, 0x0000, 0, 0), + MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS = IOMUX_PAD(0x2E0, 0x130, 1, 0x0000, 0, 0), + MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x2E0, 0x130, 4, 0x3B0, 1, 0), + MX93_PAD_SD1_STROBE__GPIO3_IO18 = IOMUX_PAD(0x2E0, 0x130, 5, 0x0000, 0, 0), + + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT = IOMUX_PAD(0x2E4, 0x134, 0, 0x0000, 0, 0), + MX93_PAD_SD2_VSELECT__USDHC2_WP = IOMUX_PAD(0x2E4, 0x134, 1, 0x0000, 0, 0), + MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 = IOMUX_PAD(0x2E4, 0x134, 2, 0x410, 1, 0), + MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 = IOMUX_PAD(0x2E4, 0x134, 4, 0x0000, 0, 0), + MX93_PAD_SD2_VSELECT__GPIO3_IO19 = IOMUX_PAD(0x2E4, 0x134, 5, 0x0000, 0, 0), + MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x2E4, 0x134, 6, 0x368, 0, 0), + + MX93_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x2E8, 0x138, 0, 0x458, 1, 0), + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK = IOMUX_PAD(0x2E8, 0x138, 1, 0x0000, 0, 0), + MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x2E8, 0x138, 4, 0x3B4, 1, 0), + MX93_PAD_SD3_CLK__GPIO3_IO20 = IOMUX_PAD(0x2E8, 0x138, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x2EC, 0x13C, 0, 0x45C, 1, 0), + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B = IOMUX_PAD(0x2EC, 0x13C, 1, 0x0000, 0, 0), + MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 = IOMUX_PAD(0x2EC, 0x13C, 4, 0x0000, 0, 0), + MX93_PAD_SD3_CMD__GPIO3_IO21 = IOMUX_PAD(0x2EC, 0x13C, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_DATA0__USDHC3_DATA0 = IOMUX_PAD(0x2F0, 0x140, 0, 0x460, 1, 0), + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 = IOMUX_PAD(0x2F0, 0x140, 1, 0x0000, 0, 0), + MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x2F0, 0x140, 4, 0x3B8, 1, 0), + MX93_PAD_SD3_DATA0__GPIO3_IO22 = IOMUX_PAD(0x2F0, 0x140, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_DATA1__USDHC3_DATA1 = IOMUX_PAD(0x2F4, 0x144, 0, 0x464, 1, 0), + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 = IOMUX_PAD(0x2F4, 0x144, 1, 0x0000, 0, 0), + MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x2F4, 0x144, 4, 0x3BC, 1, 0), + MX93_PAD_SD3_DATA1__GPIO3_IO23 = IOMUX_PAD(0x2F4, 0x144, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_DATA2__USDHC3_DATA2 = IOMUX_PAD(0x2F8, 0x148, 0, 0x468, 1, 0), + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 = IOMUX_PAD(0x2F8, 0x148, 1, 0x0000, 0, 0), + MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x2F8, 0x148, 4, 0x3C0, 1, 0), + MX93_PAD_SD3_DATA2__GPIO3_IO24 = IOMUX_PAD(0x2F8, 0x148, 5, 0x0000, 0, 0), + + MX93_PAD_SD3_DATA3__USDHC3_DATA3 = IOMUX_PAD(0x2FC, 0x14C, 0, 0x46C, 1, 0), + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 = IOMUX_PAD(0x2FC, 0x14C, 1, 0x0000, 0, 0), + MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x2FC, 0x14C, 4, 0x3C4, 1, 0), + MX93_PAD_SD3_DATA3__GPIO3_IO25 = IOMUX_PAD(0x2FC, 0x14C, 5, 0x0000, 0, 0), + + MX93_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x300, 0x150, 0, 0x0000, 0, 0), + MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN = IOMUX_PAD(0x300, 0x150, 1, 0x0000, 0, 0), + MX93_PAD_SD2_CD_B__I3C2_SCL = IOMUX_PAD(0x300, 0x150, 2, 0x3CC, 1, 0), + MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 = IOMUX_PAD(0x300, 0x150, 4, 0x36C, 1, 0), + MX93_PAD_SD2_CD_B__GPIO3_IO00 = IOMUX_PAD(0x300, 0x150, 5, 0x0000, 0, 0), + + MX93_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x304, 0x154, 0, 0x0000, 0, 0), + MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT = IOMUX_PAD(0x304, 0x154, 1, 0x0000, 0, 0), + MX93_PAD_SD2_CLK__I3C2_SDA = IOMUX_PAD(0x304, 0x154, 2, 0x3D0, 1, 0), + MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 = IOMUX_PAD(0x304, 0x154, 4, 0x370, 1, 0), + MX93_PAD_SD2_CLK__GPIO3_IO01 = IOMUX_PAD(0x304, 0x154, 5, 0x0000, 0, 0), + MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x304, 0x154, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x308, 0x158, 0, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x308, 0x158, 1, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__I3C2_PUR = IOMUX_PAD(0x308, 0x158, 2, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__I3C2_PUR_B = IOMUX_PAD(0x308, 0x158, 3, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 = IOMUX_PAD(0x308, 0x158, 4, 0x374, 1, 0), + MX93_PAD_SD2_CMD__GPIO3_IO02 = IOMUX_PAD(0x308, 0x158, 5, 0x0000, 0, 0), + MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x308, 0x158, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x30C, 0x15C, 0, 0x0000, 0, 0), + MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x30C, 0x15C, 1, 0x0000, 0, 0), + MX93_PAD_SD2_DATA0__CAN2_TX = IOMUX_PAD(0x30C, 0x15C, 2, 0x0000, 0, 0), + MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 = IOMUX_PAD(0x30C, 0x15C, 4, 0x378, 1, 0), + MX93_PAD_SD2_DATA0__GPIO3_IO03 = IOMUX_PAD(0x30C, 0x15C, 5, 0x0000, 0, 0), + MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x30C, 0x15C, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x310, 0x160, 0, 0x0000, 0, 0), + MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x310, 0x160, 1, 0x0000, 0, 0), + MX93_PAD_SD2_DATA1__CAN2_RX = IOMUX_PAD(0x310, 0x160, 2, 0x364, 3, 0), + MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 = IOMUX_PAD(0x310, 0x160, 4, 0x37C, 1, 0), + MX93_PAD_SD2_DATA1__GPIO3_IO04 = IOMUX_PAD(0x310, 0x160, 5, 0x0000, 0, 0), + MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x310, 0x160, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x314, 0x164, 0, 0x0000, 0, 0), + MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x314, 0x164, 1, 0x0000, 0, 0), + MX93_PAD_SD2_DATA2__MQS2_RIGHT = IOMUX_PAD(0x314, 0x164, 2, 0x0000, 0, 0), + MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 = IOMUX_PAD(0x314, 0x164, 4, 0x380, 1, 0), + MX93_PAD_SD2_DATA2__GPIO3_IO05 = IOMUX_PAD(0x314, 0x164, 5, 0x0000, 0, 0), + MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x314, 0x164, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x318, 0x168, 0, 0x0000, 0, 0), + MX93_PAD_SD2_DATA3__LPTMR2_ALT1 = IOMUX_PAD(0x318, 0x168, 1, 0x408, 1, 0), + MX93_PAD_SD2_DATA3__MQS2_LEFT = IOMUX_PAD(0x318, 0x168, 2, 0x0000, 0, 0), + MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 = IOMUX_PAD(0x318, 0x168, 4, 0x384, 1, 0), + MX93_PAD_SD2_DATA3__GPIO3_IO06 = IOMUX_PAD(0x318, 0x168, 5, 0x0000, 0, 0), + MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x318, 0x168, 6, 0x0000, 0, 0), + + MX93_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x31C, 0x16C, 0, 0x0000, 0, 0), + MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 = IOMUX_PAD(0x31C, 0x16C, 1, 0x40C, 1, 0), + MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 = IOMUX_PAD(0x31C, 0x16C, 4, 0x388, 1, 0), + MX93_PAD_SD2_RESET_B__GPIO3_IO07 = IOMUX_PAD(0x31C, 0x16C, 5, 0x0000, 0, 0), + MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x31C, 0x16C, 6, 0x0000, 0, 0), + + MX93_PAD_I2C1_SCL__LPI2C1_SCL = IOMUX_PAD(0x320, 0x170, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C1_SCL__I3C1_SCL = IOMUX_PAD(0x320, 0x170, 1, 0x0000, 0, 0), + MX93_PAD_I2C1_SCL__LPUART1_DCB_B = IOMUX_PAD(0x320, 0x170, 2, 0x0000, 0, 0), + MX93_PAD_I2C1_SCL__TPM2_CH0 = IOMUX_PAD(0x320, 0x170, 3, 0x0000, 0, 0), + MX93_PAD_I2C1_SCL__GPIO1_IO00 = IOMUX_PAD(0x320, 0x170, 5, 0x0000, 0, 0), + + MX93_PAD_I2C1_SDA__LPI2C1_SDA = IOMUX_PAD(0x324, 0x174, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C1_SDA__I3C1_SDA = IOMUX_PAD(0x324, 0x174, 1, 0x0000, 0, 0), + MX93_PAD_I2C1_SDA__LPUART1_RIN_B = IOMUX_PAD(0x324, 0x174, 2, 0x0000, 0, 0), + MX93_PAD_I2C1_SDA__TPM2_CH1 = IOMUX_PAD(0x324, 0x174, 3, 0x0000, 0, 0), + MX93_PAD_I2C1_SDA__GPIO1_IO01 = IOMUX_PAD(0x324, 0x174, 5, 0x0000, 0, 0), + + MX93_PAD_I2C2_SCL__LPI2C2_SCL = IOMUX_PAD(0x328, 0x178, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__I3C1_PUR = IOMUX_PAD(0x328, 0x178, 1, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__LPUART2_DCB_B = IOMUX_PAD(0x328, 0x178, 2, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__TPM2_CH2 = IOMUX_PAD(0x328, 0x178, 3, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__SAI1_RX_SYNC = IOMUX_PAD(0x328, 0x178, 4, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__GPIO1_IO02 = IOMUX_PAD(0x328, 0x178, 5, 0x0000, 0, 0), + MX93_PAD_I2C2_SCL__I3C1_PUR_B = IOMUX_PAD(0x328, 0x178, 6, 0x0000, 0, 0), + + MX93_PAD_I2C2_SDA__LPI2C2_SDA = IOMUX_PAD(0x32C, 0x17C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + MX93_PAD_I2C2_SDA__LPUART2_RIN_B = IOMUX_PAD(0x32C, 0x17C, 2, 0x0000, 0, 0), + MX93_PAD_I2C2_SDA__TPM2_CH3 = IOMUX_PAD(0x32C, 0x17C, 3, 0x0000, 0, 0), + MX93_PAD_I2C2_SDA__SAI1_RX_BCLK = IOMUX_PAD(0x32C, 0x17C, 4, 0x0000, 0, 0), + MX93_PAD_I2C2_SDA__GPIO1_IO03 = IOMUX_PAD(0x32C, 0x17C, 5, 0x0000, 0, 0), + + MX93_PAD_UART1_RXD__LPUART1_RX = IOMUX_PAD(0x330, 0x180, 0, 0x0000, 0, 0), + MX93_PAD_UART1_RXD__S400_UART_RX = IOMUX_PAD(0x330, 0x180, 1, 0x0000, 0, 0), + MX93_PAD_UART1_RXD__LPSPI2_SIN = IOMUX_PAD(0x330, 0x180, 2, 0x0000, 0, 0), + MX93_PAD_UART1_RXD__TPM1_CH0 = IOMUX_PAD(0x330, 0x180, 3, 0x0000, 0, 0), + MX93_PAD_UART1_RXD__GPIO1_IO04 = IOMUX_PAD(0x330, 0x180, 5, 0x0000, 0, 0), + + MX93_PAD_UART1_TXD__LPUART1_TX = IOMUX_PAD(0x334, 0x184, 0, 0x0000, 0, 0), + MX93_PAD_UART1_TXD__S400_UART_TX = IOMUX_PAD(0x334, 0x184, 1, 0x0000, 0, 0), + MX93_PAD_UART1_TXD__LPSPI2_PCS0 = IOMUX_PAD(0x334, 0x184, 2, 0x0000, 0, 0), + MX93_PAD_UART1_TXD__TPM1_CH1 = IOMUX_PAD(0x334, 0x184, 3, 0x0000, 0, 0), + MX93_PAD_UART1_TXD__GPIO1_IO05 = IOMUX_PAD(0x334, 0x184, 5, 0x0000, 0, 0), + + MX93_PAD_UART2_RXD__LPUART2_RX = IOMUX_PAD(0x338, 0x188, 0, 0x0000, 0, 0), + MX93_PAD_UART2_RXD__LPUART1_CTS_B = IOMUX_PAD(0x338, 0x188, 1, 0x0000, 0, 0), + MX93_PAD_UART2_RXD__LPSPI2_SOUT = IOMUX_PAD(0x338, 0x188, 2, 0x0000, 0, 0), + MX93_PAD_UART2_RXD__TPM1_CH2 = IOMUX_PAD(0x338, 0x188, 3, 0x0000, 0, 0), + MX93_PAD_UART2_RXD__SAI1_MCLK = IOMUX_PAD(0x338, 0x188, 4, 0x448, 0, 0), + MX93_PAD_UART2_RXD__GPIO1_IO06 = IOMUX_PAD(0x338, 0x188, 5, 0x0000, 0, 0), + + MX93_PAD_UART2_TXD__LPUART2_TX = IOMUX_PAD(0x33C, 0x18C, 0, 0x0000, 0, 0), + MX93_PAD_UART2_TXD__LPUART1_RTS_B = IOMUX_PAD(0x33C, 0x18C, 1, 0x0000, 0, 0), + MX93_PAD_UART2_TXD__LPSPI2_SCK = IOMUX_PAD(0x33C, 0x18C, 2, 0x0000, 0, 0), + MX93_PAD_UART2_TXD__TPM1_CH3 = IOMUX_PAD(0x33C, 0x18C, 3, 0x0000, 0, 0), + MX93_PAD_UART2_TXD__GPIO1_IO07 = IOMUX_PAD(0x33C, 0x18C, 5, 0x0000, 0, 0), + + MX93_PAD_PDM_CLK__PDM_CLK = IOMUX_PAD(0x340, 0x190, 0, 0x0000, 0, 0), + MX93_PAD_PDM_CLK__MQS1_LEFT = IOMUX_PAD(0x340, 0x190, 1, 0x0000, 0, 0), + MX93_PAD_PDM_CLK__LPTMR1_ALT1 = IOMUX_PAD(0x340, 0x190, 4, 0x0000, 0, 0), + MX93_PAD_PDM_CLK__GPIO1_IO08 = IOMUX_PAD(0x340, 0x190, 5, 0x0000, 0, 0), + MX93_PAD_PDM_CLK__CAN1_TX = IOMUX_PAD(0x340, 0x190, 6, 0x0000, 0, 0), + + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 = IOMUX_PAD(0x344, 0x194, 0, 0x438, 2, 0), + MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT = IOMUX_PAD(0x344, 0x194, 1, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 = IOMUX_PAD(0x344, 0x194, 2, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK = IOMUX_PAD(0x344, 0x194, 3, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 = IOMUX_PAD(0x344, 0x194, 4, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 = IOMUX_PAD(0x344, 0x194, 5, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX = IOMUX_PAD(0x344, 0x194, 6, 0x360, 0, 0), + + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 = IOMUX_PAD(0x348, 0x198, 0, 0x43C, 2, 0), + MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI = IOMUX_PAD(0x348, 0x198, 1, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 = IOMUX_PAD(0x348, 0x198, 2, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK = IOMUX_PAD(0x348, 0x198, 3, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 = IOMUX_PAD(0x348, 0x198, 4, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 = IOMUX_PAD(0x348, 0x198, 5, 0x0000, 0, 0), + MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x348, 0x198, 6, 0x368, 1, 0), + + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x34C, 0x19C, 0, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 = IOMUX_PAD(0x34C, 0x19C, 1, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 = IOMUX_PAD(0x34C, 0x19C, 2, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__LPUART2_DTR_B = IOMUX_PAD(0x34C, 0x19C, 3, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__MQS1_LEFT = IOMUX_PAD(0x34C, 0x19C, 4, 0x0000, 0, 0), + MX93_PAD_SAI1_TXFS__GPIO1_IO11 = IOMUX_PAD(0x34C, 0x19C, 5, 0x0000, 0, 0), + + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x350, 0x1A0, 0, 0x0000, 0, 0), + MX93_PAD_SAI1_TXC__LPUART2_CTS_B = IOMUX_PAD(0x350, 0x1A0, 1, 0x0000, 0, 0), + MX93_PAD_SAI1_TXC__LPSPI1_SIN = IOMUX_PAD(0x350, 0x1A0, 2, 0x0000, 0, 0), + MX93_PAD_SAI1_TXC__LPUART1_DSR_B = IOMUX_PAD(0x350, 0x1A0, 3, 0x0000, 0, 0), + MX93_PAD_SAI1_TXC__CAN1_RX = IOMUX_PAD(0x350, 0x1A0, 4, 0x360, 1, 0), + MX93_PAD_SAI1_TXC__GPIO1_IO12 = IOMUX_PAD(0x350, 0x1A0, 5, 0x0000, 0, 0), + + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 = IOMUX_PAD(0x354, 0x1A4, 0, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__LPUART2_RTS_B = IOMUX_PAD(0x354, 0x1A4, 1, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__LPSPI1_SCK = IOMUX_PAD(0x354, 0x1A4, 2, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__LPUART1_DTR_B = IOMUX_PAD(0x354, 0x1A4, 3, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__CAN1_TX = IOMUX_PAD(0x354, 0x1A4, 4, 0x0000, 0, 0), + MX93_PAD_SAI1_TXD0__GPIO1_IO13 = IOMUX_PAD(0x354, 0x1A4, 5, 0x0000, 0, 0), + + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 = IOMUX_PAD(0x358, 0x1A8, 0, 0x0000, 0, 0), + MX93_PAD_SAI1_RXD0__SAI1_MCLK = IOMUX_PAD(0x358, 0x1A8, 1, 0x448, 1, 0), + MX93_PAD_SAI1_RXD0__LPSPI1_SOUT = IOMUX_PAD(0x358, 0x1A8, 2, 0x0000, 0, 0), + MX93_PAD_SAI1_RXD0__LPUART2_DSR_B = IOMUX_PAD(0x358, 0x1A8, 3, 0x0000, 0, 0), + MX93_PAD_SAI1_RXD0__MQS1_RIGHT = IOMUX_PAD(0x358, 0x1A8, 4, 0x0000, 0, 0), + MX93_PAD_SAI1_RXD0__GPIO1_IO14 = IOMUX_PAD(0x358, 0x1A8, 5, 0x0000, 0, 0), + + MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY = IOMUX_PAD(0x35C, 0x1AC, 0, 0x0000, 0, 0), + MX93_PAD_WDOG_ANY__GPIO1_IO15 = IOMUX_PAD(0x35C, 0x1AC, 5, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX93_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h new file mode 100644 index 00000000000..513aa0b9581 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 NXP + */ + +#ifndef __ARCH_IMX9_SYS_PROTO_H +#define __ARCH_NMX9_SYS_PROTO_H + +#include <asm/mach-imx/sys_proto.h> + +#endif diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 231b9c027ce..0492abd298c 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -86,7 +86,16 @@ typedef u64 iomux_v3_cfg_t; #define IOMUX_CONFIG_LPSR 0x20 #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) -#ifdef CONFIG_IMX8M +#ifdef CONFIG_IMX93 +#define PAD_CTL_FSEL2 (0x2 << 7) +#define PAD_CTL_FSEL3 (0x3 << 7) +#define PAD_CTL_PUE (0x1 << 9) +#define PAD_CTL_PDE (0x1 << 10) +#define PAD_CTL_ODE (0x1 << 11) +#define PAD_CTL_HYS (0x1 << 12) +#define PAD_CTL_DSE(x) (((x) << 1) & 0x7f) + +#elif defined(CONFIG_IMX8M) #define PAD_CTL_FSEL0 (0x0 << 3) #define PAD_CTL_FSEL1 (0x1 << 3) #define PAD_CTL_FSEL2 (0x2 << 3) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index cd69384d8ef..05532ebea89 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -31,6 +31,7 @@ struct bd_info; #define is_mx7() (is_soc_type(MXC_SOC_MX7)) #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) +#define is_imx9() (is_soc_type(MXC_SOC_IMX9)) #define is_imxrt() (is_soc_type(MXC_SOC_IMXRT))

#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) @@ -81,6 +82,8 @@ struct bd_info;

#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))

+#define is_imx93() (is_cpu_type(MXC_CPU_IMX93)) + #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020)) #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index c5be63dfe4f..fd8e236af8d 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -5,7 +5,7 @@ # # (C) Copyright 2011 Freescale Semiconductor, Inc.

-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m imx9 vf610)) obj-y = iomux-v3.o endif

@@ -29,7 +29,7 @@ endif obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif -ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt)) +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imx9 imxrt)) obj-y += misc.o obj-$(CONFIG_CMD_PRIBLOB) += priblob.o obj-$(CONFIG_SPL_BUILD) += spl.o @@ -195,6 +195,10 @@ flash.bin: spl/u-boot-spl.bin FORCE endif endif

+ifeq ($(CONFIG_ARCH_IMX9), y) +SPL: +endif + else MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) @@ -240,7 +244,8 @@ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ obj-$(CONFIG_ARCH_IMX8ULP) += imx8ulp/ obj-$(CONFIG_IMX8M) += imx8m/ obj-$(CONFIG_ARCH_IMX8) += imx8/ +obj-$(CONFIG_ARCH_IMX9) += imx9/ obj-$(CONFIG_ARCH_IMXRT) += imxrt/

-obj-$(CONFIG_IMX8MN)$(CONFIG_IMX8MP)$(CONFIG_IMX8ULP) += imx_romapi.o +obj-$(CONFIG_IMX8MN)$(CONFIG_IMX8MP)$(CONFIG_IMX8ULP)$(CONFIG_IMX9) += imx_romapi.o obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig new file mode 100644 index 00000000000..ce58e41428f --- /dev/null +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -0,0 +1,17 @@ +if ARCH_IMX9 + +config IMX9 + bool + select HAS_CAAM + select ROM_UNIFIED_SECTIONS + +config IMX93 + bool + select IMX9 + select ARMV8_SPL_EXCEPTION_VECTORS + +config SYS_SOC + default "imx9" + +endif + diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile new file mode 100644 index 00000000000..773b12ee129 --- /dev/null +++ b/arch/arm/mach-imx/imx9/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2022 NXP + +obj-y += lowlevel_init.o +obj-y += soc.o clock.o diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c new file mode 100644 index 00000000000..fe89dccb316 --- /dev/null +++ b/arch/arm/mach-imx/imx9/clock.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Peng Fan peng.fan@nxp.com + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <div64.h> +#include <errno.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <log.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_lpuart_clk(void) +{ + return 24000000; +} + diff --git a/arch/arm/mach-imx/imx9/lowlevel_init.S b/arch/arm/mach-imx/imx9/lowlevel_init.S new file mode 100644 index 00000000000..1dc1dbfcddc --- /dev/null +++ b/arch/arm/mach-imx/imx9/lowlevel_init.S @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#include <config.h> + +.align 8 +.global rom_pointer +rom_pointer: + .space 256 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: +#ifndef CONFIG_SPL_BUILD + /* The firmware provided ATAG/FDT address can be found in r2/x0 */ + adr x0, rom_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 +#endif + /* Returns */ + b save_boot_params_ret diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c new file mode 100644 index 00000000000..d905fe76c91 --- /dev/null +++ b/arch/arm/mach-imx/imx9/soc.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Peng Fan peng.fan@nxp.com + */ + +#include <common.h> +#include <cpu_func.h> +#include <init.h> +#include <log.h> +#include <asm/arch/imx-regs.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/syscounter.h> +#include <asm/armv8/mmu.h> +#include <dm/uclass.h> +#include <env.h> +#include <env_internal.h> +#include <errno.h> +#include <fdt_support.h> +#include <linux/bitops.h> +#include <asm/setup.h> +#include <asm/bootm.h> +#include <asm/arch-imx/cpu.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_cpu_rev(void) +{ + return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0; +} + +static struct mm_region imx93_mem_map[] = { + { + /* ROM */ + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* OCRAM */ + .virt = 0x20480000UL, + .phys = 0x20480000UL, + .size = 0xA0000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* AIPS */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Flexible Serial Peripheral Interface */ + .virt = 0x28000000UL, + .phys = 0x28000000UL, + .size = 0x30000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* DRAM1 */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = PHYS_SDRAM_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* empty entrie to split table entry 5 if needed when TEEs are used */ + 0, + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = imx93_mem_map; + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + mac[0] = 0x1; + mac[1] = 0x2; + mac[2] = 0x3; + mac[3] = 0x4; + mac[4] = 0x5; + mac[5] = 0x6; +} + +int print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + + printf("CPU: i.MX93 rev%d.%d\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0); + + return 0; +} + +int arch_misc_init(void) +{ + return 0; +} + +int ft_system_setup(void *blob, struct bd_info *bd) +{ + return 0; +} + +int arch_cpu_init(void) +{ + return 0; +} diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index e5ad993b8d9..ef00969a5e0 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -147,7 +147,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; }

-#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) +#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMX9) /* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */ u32 spl_boot_device(void) {

From: Peng Fan peng.fan@nxp.com

Support pcal6524 IO expander driver

Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/gpio/pca953x_gpio.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c index e98e1e56dbc..4654f9e0989 100644 --- a/drivers/gpio/pca953x_gpio.c +++ b/drivers/gpio/pca953x_gpio.c @@ -43,6 +43,8 @@

#define PCA_GPIO_MASK 0x00FF #define PCA_INT 0x0100 +#define PCA_PCAL BIT(9) +#define PCA_LATCH_INT (PCA_PCAL | PCA_INT) #define PCA953X_TYPE 0x1000 #define PCA957X_TYPE 0x2000 #define PCA_TYPE_MASK 0xF000 @@ -393,6 +395,8 @@ static const struct udevice_id pca953x_ids[] = { { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },

+ { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, + { .compatible = "maxim,max7310", .data = OF_953X(8, 0), }, { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },

From: Peng Fan peng.fan@nxp.com

Add clock API to support CCM root clock and LPCG setting Set the CCM AUTHEN register to allow non-secure world to set root clock and lpcg.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx9/ccm_regs.h | 266 ++++++++ arch/arm/include/asm/arch-imx9/clock.h | 239 +++++++ arch/arm/include/asm/arch-imx9/imx-regs.h | 6 +- arch/arm/mach-imx/imx9/Makefile | 2 +- arch/arm/mach-imx/imx9/clock.c | 769 +++++++++++++++++++++- arch/arm/mach-imx/imx9/clock_root.c | 438 ++++++++++++ arch/arm/mach-imx/imx9/soc.c | 3 + 7 files changed, 1720 insertions(+), 3 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx9/ccm_regs.h create mode 100644 arch/arm/mach-imx/imx9/clock_root.c

diff --git a/arch/arm/include/asm/arch-imx9/ccm_regs.h b/arch/arm/include/asm/arch-imx9/ccm_regs.h new file mode 100644 index 00000000000..d326a6ea516 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/ccm_regs.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_CCM_REGS_H__ +#define __ASM_ARCH_IMX9_CCM_REGS_H__ +#define IMX93_CLK_ROOT_MAX 95 +#define IMX93_CLK_CCGR_MAX 127 + +#define ARM_A55_PERIPH_CLK_ROOT 0 +#define ARM_A55_MTR_BUS_CLK_ROOT 1 +#define ARM_A55_CLK_ROOT 2 +#define M33_CLK_ROOT 3 +#define SENTINEL_CLK_ROOT 4 +#define BUS_WAKEUP_CLK_ROOT 5 +#define BUS_AON_CLK_ROOT 6 +#define WAKEUP_AXI_CLK_ROOT 7 +#define SWO_TRACE_CLK_ROOT 8 +#define M33_SYSTICK_CLK_ROOT 9 +#define FLEXIO1_CLK_ROOT 10 +#define FLEXIO2_CLK_ROOT 11 +#define LPIT1_CLK_ROOT 12 +#define LPIT2_CLK_ROOT 13 +#define LPTMR1_CLK_ROOT 14 +#define LPTMR2_CLK_ROOT 15 +#define TPM1_CLK_ROOT 16 +#define TPM2_CLK_ROOT 17 +#define TPM3_CLK_ROOT 18 +#define TPM4_CLK_ROOT 19 +#define TPM5_CLK_ROOT 20 +#define TPM6_CLK_ROOT 21 +#define FLEXSPI1_CLK_ROOT 22 +#define CAN1_CLK_ROOT 23 +#define CAN2_CLK_ROOT 24 +#define LPUART1_CLK_ROOT 25 +#define LPUART2_CLK_ROOT 26 +#define LPUART3_CLK_ROOT 27 +#define LPUART4_CLK_ROOT 28 +#define LPUART5_CLK_ROOT 29 +#define LPUART6_CLK_ROOT 30 +#define LPUART7_CLK_ROOT 31 +#define LPUART8_CLK_ROOT 32 +#define LPI2C1_CLK_ROOT 33 +#define LPI2C2_CLK_ROOT 34 +#define LPI2C3_CLK_ROOT 35 +#define LPI2C4_CLK_ROOT 36 +#define LPI2C5_CLK_ROOT 37 +#define LPI2C6_CLK_ROOT 38 +#define LPI2C7_CLK_ROOT 39 +#define LPI2C8_CLK_ROOT 40 +#define LPSPI1_CLK_ROOT 41 +#define LPSPI2_CLK_ROOT 42 +#define LPSPI3_CLK_ROOT 43 +#define LPSPI4_CLK_ROOT 44 +#define LPSPI5_CLK_ROOT 45 +#define LPSPI6_CLK_ROOT 46 +#define LPSPI7_CLK_ROOT 47 +#define LPSPI8_CLK_ROOT 48 +#define I3C1_CLK_ROOT 49 +#define I3C2_CLK_ROOT 50 +#define USDHC1_CLK_ROOT 51 +#define USDHC2_CLK_ROOT 52 +#define USDHC3_CLK_ROOT 53 +#define SAI1_CLK_ROOT 54 +#define SAI2_CLK_ROOT 55 +#define SAI3_CLK_ROOT 56 +#define CCM_CKO1_CLK_ROOT 57 +#define CCM_CKO2_CLK_ROOT 58 +#define CCM_CKO3_CLK_ROOT 59 +#define CCM_CKO4_CLK_ROOT 60 +#define HSIO_CLK_ROOT 61 +#define HSIO_USB_TEST_60M_CLK_ROOT 62 +#define HSIO_ACSCAN_80M_CLK_ROOT 63 +#define HSIO_ACSCAN_480M_CLK_ROOT 64 +#define NIC_CLK_ROOT 65 +#define NIC_APB_CLK_ROOT 66 +#define ML_APB_CLK_ROOT 67 +#define ML_CLK_ROOT 68 +#define MEDIA_AXI_CLK_ROOT 69 +#define MEDIA_APB_CLK_ROOT 70 +#define MEDIA_LDB_CLK_ROOT 71 +#define MEDIA_DISP_PIX_CLK_ROOT 72 +#define CAM_PIX_CLK_ROOT 73 +#define MIPI_TEST_BYTE_CLK_ROOT 74 +#define MIPI_PHY_CFG_CLK_ROOT 75 +#define DRAM_ALT_CLK_ROOT 76 +#define DRAM_APB_CLK_ROOT 77 +#define ADC_CLK_ROOT 78 +#define PDM_CLK_ROOT 79 +#define TSTMR1_CLK_ROOT 80 +#define TSTMR2_CLK_ROOT 81 +#define MQS1_CLK_ROOT 82 +#define MQS2_CLK_ROOT 83 +#define AUDIO_XCVR_CLK_ROOT 84 +#define SPDIF_CLK_ROOT 85 +#define ENET_CLK_ROOT 86 +#define ENET_TIMER1_CLK_ROOT 87 +#define ENET_TIMER2_CLK_ROOT 88 +#define ENET_REF_CLK_ROOT 89 +#define ENET_REF_PHY_CLK_ROOT 90 +#define I3C1_SLOW_CLK_ROOT 91 +#define I3C2_SLOW_CLK_ROOT 92 +#define USB_PHY_BURUNIN_CLK_ROOT 93 +#define PAL_CAME_SCAN_CLK_ROOT 94 +#define CLK_ROOT_NUM 95 + +#define CCGR_A55 0 +#define CCGR_CM33 1 +#define CCGR_ARMTROUT 2 +#define CCGR_SENT 3 +#define CCGR_BUSM 4 +#define CCGR_BUS7 5 +#define CCGR_BUSD 6 +#define CCGR_ANAD 7 +#define CCGR_SRC 8 +#define CCGR_CCM 9 +#define CCGR_GPC 10 +#define CCGR_ADC 11 +#define CCGR_WDG1 12 +#define CCGR_WDG2 13 +#define CCGR_WDG3 14 +#define CCGR_WDG4 15 +#define CCGR_WDG5 16 +#define CCGR_SEM1 17 +#define CCGR_SEM2 18 +#define CCGR_MUA 19 +#define CCGR_MUB 20 +#define CCGR_DMA1 21 +#define CCGR_DMA2 22 +#define CCGR_ROMCA55 23 +#define CCGR_ROMCM33 24 +#define CCGR_QSP1 25 +#define CCGR_AONRDC 26 +#define CCGR_WKUPRDC 27 +#define CCGR_FUSE 28 +#define CCGR_SNVH 29 +#define CCGR_SNVS 30 +#define CCGR_TRAC 31 +#define CCGR_SWO 32 +#define CCGR_IOCG 33 +#define CCGR_PIO1 34 +#define CCGR_PIO2 35 +#define CCGR_PIO3 36 +#define CCGR_PIO4 37 +#define CCGR_FIO1 38 +#define CCGR_FIO2 39 +#define CCGR_PIT1 40 +#define CCGR_PIT2 41 +#define CCGR_GPT1 42 +#define CCGR_GPT2 43 +#define CCGR_TPM1 44 +#define CCGR_TPM2 45 +#define CCGR_TPM3 46 +#define CCGR_TPM4 47 +#define CCGR_TPM5 48 +#define CCGR_TPM6 49 +#define CCGR_CAN1 50 +#define CCGR_CAN2 51 +#define CCGR_URT1 52 +#define CCGR_URT2 53 +#define CCGR_URT3 54 +#define CCGR_URT4 55 +#define CCGR_URT5 56 +#define CCGR_URT6 57 +#define CCGR_URT7 58 +#define CCGR_URT8 59 +#define CCGR_I2C1 60 +#define CCGR_I2C2 61 +#define CCGR_I2C3 62 +#define CCGR_I2C4 63 +#define CCGR_I2C5 64 +#define CCGR_I2C6 65 +#define CCGR_I2C7 66 +#define CCGR_I2C8 67 +#define CCGR_SPI1 68 +#define CCGR_SPI2 69 +#define CCGR_SPI3 70 +#define CCGR_SPI4 71 +#define CCGR_SPI5 72 +#define CCGR_SPI6 73 +#define CCGR_SPI7 74 +#define CCGR_SPI8 75 +#define CCGR_I3C1 76 +#define CCGR_I3C2 77 +#define CCGR_USDHC1 78 +#define CCGR_USDHC2 79 +#define CCGR_USDHC3 80 +#define CCGR_SAI1 81 +#define CCGR_SAI2 82 +#define CCGR_SAI3 83 +#define CCGR_W2AO 84 +#define CCGR_AO2W 85 +#define CCGR_MIPIC 86 +#define CCGR_MIPID 87 +#define CCGR_LVDS 88 +#define CCGR_LCDIF 89 +#define CCGR_PXP 90 +#define CCGR_ISI 91 +#define CCGR_NMED 92 +#define CCGR_DFI 93 +#define CCGR_DDRC 94 +#define CCGR_DFIC 95 +#define CCGR_DSSI 96 +#define CCGR_DBYP 97 +#define CCGR_DAPB 98 +#define CCGR_DRAMP 99 +#define CCGR_DCLKC 100 +#define CCGR_NCTL 101 +#define CCGR_GIC 102 +#define CCGR_NICAPB 103 +#define CCGR_USBC 104 +#define CCGR_USBT 105 +#define CCGR_HSIO 106 +#define CCGR_PDM 107 +#define CCGR_MQS1 108 +#define CCGR_MQS2 109 +#define CCGR_AXCVR 110 +#define CCGR_MECC 111 +#define CCGR_SPDIF 112 +#define CCGR_ML2NIC 113 +#define CCGR_MED2NIC 114 +#define CCGR_HSIO2NIC 115 +#define CCGR_W2NIC 116 +#define CCGR_NIC2W 117 +#define CCGR_NIC2DDR 118 +#define CCGR_HSIO32K 119 +#define CCGR_ENET1 120 +#define CCGR_ENETQOS 121 +#define CCGR_SYSCNT 122 +#define CCGR_TSTMR1 123 +#define CCGR_TSTMR2 124 +#define CCGR_TMC 125 +#define CCGR_PMRO 126 +#define CCGR_NUM 127 + +#define SHARED_GPR_EXT_CLK 0 +#define SHARED_GPR_EXT_CLK_SEL_EXT1 0 +#define SHARED_GPR_EXT_CLK_SEL_EXT2 BIT(0) +#define SHARED_GPR_EXT_CLK_SEL_EXT3 BIT(1) +#define SHARED_GPR_EXT_CLK_SEL_EXT4 GENMASK(1, 0) + +#define SHARED_GPR_A55_CLK 1 +#define SHARED_GPR_A55_CLK_SEL_CCM 0 +#define SHARED_GPR_A55_CLK_SEL_PLL BIT(0) + +#define SHARED_GPR_DRAM_CLK 2 +#define SHARED_GPR_DRAM_CLK_SEL_PLL 0 +#define SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0) + +#define SHARED_GPR_NUM 8 +#define PRIVATE_GPR_NUM 8 + +#define CLK_ROOT_STATUS_OFF BIT(24) +#define CLK_ROOT_STATUS_CHANGING BIT(31) +#define CLK_ROOT_MUX_MASK GENMASK(9, 8) +#define CLK_ROOT_MUX_SHIFT 8 +#define CLK_ROOT_DIV_MASK GENMASK(7, 0) + +#define CCM_AUTHEN_LOCK_TZ BIT(11) +#define CCM_AUTHEN_TZ_NS BIT(9) +#define CCM_AUTHEN_TZ_USER BIT(8) +#define CCM_AUTHEN_CPULPM_MODE BIT(2) +#define CCM_AUTHEN_AUTO_CTRL BIT(3) + +#endif diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h index e69de29bb2d..fcf04d66f05 100644 --- a/arch/arm/include/asm/arch-imx9/clock.h +++ b/arch/arm/include/asm/arch-imx9/clock.h @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + * + * Peng Fan <peng.fan at nxp.com> + */ + +#ifndef __CLOCK_IMX9__ +#define __CLOCK_IMX9__ + +#include <linux/bitops.h> + +#define MHZ(x) ((x) * 1000000UL) + +enum enet_freq { + ENET_25MHZ = 0, + ENET_50MHZ, + ENET_125MHZ, +}; + +enum ccm_clk_src { + OSC_24M_CLK, + ARM_PLL, + ARM_PLL_CLK, + SYS_PLL_PG, + SYS_PLL_PFD0_PG, + SYS_PLL_PFD0, + SYS_PLL_PFD0_DIV2, + SYS_PLL_PFD1_PG, + SYS_PLL_PFD1, + SYS_PLL_PFD1_DIV2, + SYS_PLL_PFD2_PG, + SYS_PLL_PFD2, + SYS_PLL_PFD2_DIV2, + AUDIO_PLL, + AUDIO_PLL_CLK, + DRAM_PLL, + DRAM_PLL_CLK, + VIDEO_PLL, + VIDEO_PLL_CLK, + OSCPLL_END, + EXT_CLK, +}; + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_IPG_CLK, + MXC_FLEXSPI_CLK, + MXC_CSPI_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_UART_CLK, + MXC_I2C_CLK, + MXC_FEC_CLK, +}; + +struct ccm_obs { + u32 direct; + u32 reserved[31]; +}; + +struct ccm_gpr { + u32 gpr; + u32 gpr_set; + u32 gpr_clr; + u32 gpr_tog; + u32 authen; + u32 authen_set; + u32 authen_clr; + u32 authen_tog; +}; + +struct ccm_lpcg_oscpll { + u32 direct; + u32 lpm_status0; + u32 lpm_status1; + u32 reserved0; + u32 lpm0; + u32 lpm1; + u32 reserved1; + u32 lpm_cur; + u32 status0; + u32 status1; + u32 reserved2[2]; + u32 authen; + u32 reserved3[3]; +}; + +struct ccm_root { + u32 control; + u32 control_set; + u32 control_clr; + u32 control_tog; + u32 reserved[4]; + u32 status0; + u32 reserved1[3]; + u32 authen; + u32 reserved2[19]; +}; + +struct ccm_reg { + struct ccm_root clk_roots[95]; /* 0x0 */ + u32 reserved_0[1312]; + struct ccm_obs clk_obs[6]; /* 0x4400 */ + u32 reserved_1[64]; + struct ccm_gpr clk_shared_gpr[8]; /* 0x4800 */ + u32 reserved_2[192]; + struct ccm_gpr clk_private_gpr[8]; /* 0x4C00 */ + u32 reserved_3[192]; + struct ccm_lpcg_oscpll clk_oscplls[19]; /* 0x5000 */ + u32 reserved_4[2768]; + struct ccm_lpcg_oscpll clk_lpcgs[122]; /* 0x8000 */ +}; + +struct ana_pll_reg_elem { + u32 reg; + u32 reg_set; + u32 reg_clr; + u32 reg_tog; +}; + +struct ana_pll_dfs { + struct ana_pll_reg_elem dfs_ctrl; + struct ana_pll_reg_elem dfs_div; +}; + +struct ana_pll_reg { + struct ana_pll_reg_elem ctrl; + struct ana_pll_reg_elem ana_prg; + struct ana_pll_reg_elem test; + struct ana_pll_reg_elem ss; /* Spread spectrum */ + struct ana_pll_reg_elem num; /* numerator */ + struct ana_pll_reg_elem denom; /* demoninator */ + struct ana_pll_reg_elem div; + struct ana_pll_dfs dfs[4]; + u32 pll_status; + u32 dfs_status; + u32 reserved[2]; +}; + +struct anatop_reg { + u32 osc_ctrl; + u32 osc_state; + u32 reserved_0[510]; + u32 chip_version; + u32 reserved_1[511]; + struct ana_pll_reg arm_pll; + struct ana_pll_reg sys_pll; + struct ana_pll_reg audio_pll; + struct ana_pll_reg dram_pll; + struct ana_pll_reg video_pll; +}; + +#define PLL_CTRL_HW_CTRL_SEL BIT(16) +#define PLL_CTRL_CLKMUX_BYPASS BIT(2) +#define PLL_CTRL_CLKMUX_EN BIT(1) +#define PLL_CTRL_POWERUP BIT(0) + +#define PLL_STATUS_PLL_LOCK BIT(0) +#define PLL_DFS_CTRL_ENABLE BIT(31) +#define PLL_DFS_CTRL_CLKOUT BIT(30) +#define PLL_DFS_CTRL_CLKOUT_DIV2 BIT(29) +#define PLL_DFS_CTRL_BYPASS BIT(23) + +#define PLL_SS_EN BIT(15) + +struct imx_intpll_rate_table { + u32 rate; /*khz*/ + int rdiv; + int mfi; + int odiv; +}; + +struct imx_fracpll_rate_table { + u32 rate; /*khz*/ + int rdiv; + int mfi; + int odiv; + int mfn; + int mfd; +}; + +#define INT_PLL_RATE(_rate, _r, _m, _o) \ + { \ + .rate = (_rate), \ + .rdiv = (_r), \ + .mfi = (_m), \ + .odiv = (_o), \ + } + +#define FRAC_PLL_RATE(_rate, _r, _m, _o, _n, _d) \ + { \ + .rate = (_rate), \ + .rdiv = (_r), \ + .mfi = (_m), \ + .odiv = (_o), \ + .mfn = (_n), \ + .mfd = (_d), \ + } + +struct clk_root_map { + u32 clk_root_id; + u32 mux_type; +}; + +int clock_init(void); +u32 get_clk_src_rate(enum ccm_clk_src source); +u32 get_lpuart_clk(void); +void init_uart_clk(u32 index); +void init_clk_usdhc(u32 index); +int enable_i2c_clk(unsigned char enable, u32 i2c_num); +u32 imx_get_i2cclk(u32 i2c_num); +u32 mxc_get_clock(enum mxc_clock clk); + +int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable); +int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable); +int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable); +int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val); +bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll); +int ccm_clk_src_tz_access(enum ccm_clk_src oscpll, bool non_secure, bool user_mode, bool lock_tz); +int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div); +u32 ccm_clk_root_get_rate(u32 clk_root_id); +int ccm_clk_root_tz_access(u32 clk_root_id, bool non_secure, bool user_mode, bool lock_tz); +int ccm_lpcg_on(u32 lpcg, bool enable); +int ccm_lpcg_lpm(u32 lpcg, bool enable); +int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val); +bool ccm_lpcg_is_clk_on(u32 lpcg); +int ccm_lpcg_tz_access(u32 lpcg, bool non_secure, bool user_mode, bool lock_tz); +int ccm_shared_gpr_set(u32 gpr, u32 val); +int ccm_shared_gpr_get(u32 gpr, u32 *val); +int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool user_mode, bool lock_tz); + +void enable_usboh3_clk(unsigned char enable); +int set_clk_enet(enum enet_freq type); +int set_clk_eqos(enum enet_freq type); + +#endif diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h index 2adbdadf03c..50ec902987d 100644 --- a/arch/arm/include/asm/arch-imx9/imx-regs.h +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -8,6 +8,10 @@

#define ARCH_MXC

-#define IOMUXC_BASE_ADDR 0x443C0000UL +#define IOMUXC_BASE_ADDR 0x443C0000UL +#define CCM_BASE_ADDR 0x44450000UL +#define CCM_CCGR_BASE_ADDR 0x44458000UL + +#define ANATOP_BASE_ADDR 0x44480000UL

#endif diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile index 773b12ee129..7be0343d52e 100644 --- a/arch/arm/mach-imx/imx9/Makefile +++ b/arch/arm/mach-imx/imx9/Makefile @@ -3,4 +3,4 @@ # Copyright 2022 NXP

obj-y += lowlevel_init.o -obj-y += soc.o clock.o +obj-y += soc.o clock.o clock_root.o diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index fe89dccb316..55cbb40f328 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -9,6 +9,7 @@ #include <command.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/ccm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <asm/io.h> @@ -20,8 +21,774 @@

DECLARE_GLOBAL_DATA_PTR;

+static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR; + +static struct imx_intpll_rate_table imx9_intpll_tbl[] = { + INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */ + INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */ + INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */ + INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */ + INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */ +}; + +static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = { + FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */ + FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */ + FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */ + FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */ + FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */ +}; + +/* return in khz */ +static u32 decode_pll_vco(struct ana_pll_reg *reg, bool fracpll) +{ + u32 ctrl; + u32 pll_status; + u32 div; + int rdiv, mfi, mfn, mfd; + int clk = 24000; + + ctrl = readl(&reg->ctrl.reg); + pll_status = readl(&reg->pll_status); + div = readl(&reg->div.reg); + + if (!(ctrl & PLL_CTRL_POWERUP)) + return 0; + + if (!(pll_status & PLL_STATUS_PLL_LOCK)) + return 0; + + mfi = (div & GENMASK(24, 16)) >> 16; + rdiv = (div & GENMASK(15, 13)) >> 13; + + if (rdiv == 0) + rdiv = 1; + + if (fracpll) { + mfn = (int)readl(&reg->num.reg); + mfn >>= 2; + mfd = (int)(readl(&reg->denom.reg) & GENMASK(29, 0)); + + clk = clk * (mfi * mfd + mfn) / mfd / rdiv; + } else { + clk = clk * mfi / rdiv; + } + + return (u32)clk; +} + +/* return in khz */ +static u32 decode_pll_out(struct ana_pll_reg *reg, bool fracpll) +{ + u32 ctrl = readl(&reg->ctrl.reg); + u32 div; + + if (ctrl & PLL_CTRL_CLKMUX_BYPASS) + return 24000; + + if (!(ctrl & PLL_CTRL_CLKMUX_EN)) + return 0; + + div = readl(&reg->div.reg); + div &= 0xff; /* odiv */ + + if (div == 0) + div = 2; + else if (div == 1) + div = 3; + + return decode_pll_vco(reg, fracpll) / div; +} + +/* return in khz */ +static u32 decode_pll_pfd(struct ana_pll_reg *reg, struct ana_pll_dfs *dfs_reg, + bool div2, bool fracpll) +{ + u32 pllvco = decode_pll_vco(reg, fracpll); + u32 dfs_ctrl = readl(&dfs_reg->dfs_ctrl.reg); + u32 dfs_div = readl(&dfs_reg->dfs_div.reg); + u32 mfn, mfi; + u32 output; + + if (dfs_ctrl & PLL_DFS_CTRL_BYPASS) + return pllvco; + + if (!(dfs_ctrl & PLL_DFS_CTRL_ENABLE) || + (div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT_DIV2)) || + (!div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT))) + return 0; + + mfn = dfs_div & GENMASK(2, 0); + mfi = (dfs_div & GENMASK(15, 8)) >> 8; + + if (mfn > 3) + return 0; /* valid mfn 0-3 */ + + if (mfi == 0 || mfi == 1) + return 0; /* valid mfi 2-255 */ + + output = (pllvco * 5) / (mfi * 5 + mfn); + + if (div2) + return output >> 1; + + return output; +} + +static u32 decode_pll(enum ccm_clk_src pll) +{ + switch (pll) { + case ARM_PLL_CLK: + return decode_pll_out(&ana_regs->arm_pll, false); + case SYS_PLL_PG: + return decode_pll_out(&ana_regs->sys_pll, false); + case SYS_PLL_PFD0: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[0], false, true); + case SYS_PLL_PFD0_DIV2: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[0], true, true); + case SYS_PLL_PFD1: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[1], false, true); + case SYS_PLL_PFD1_DIV2: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[1], true, true); + case SYS_PLL_PFD2: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[2], false, true); + case SYS_PLL_PFD2_DIV2: + return decode_pll_pfd(&ana_regs->sys_pll, + &ana_regs->sys_pll.dfs[2], true, true); + case AUDIO_PLL_CLK: + return decode_pll_out(&ana_regs->audio_pll, true); + case DRAM_PLL_CLK: + return decode_pll_out(&ana_regs->dram_pll, true); + case VIDEO_PLL_CLK: + return decode_pll_out(&ana_regs->video_pll, true); + default: + printf("Invalid clock source to decode\n"); + break; + } + + return 0; +} + +int configure_intpll(enum ccm_clk_src pll, u32 freq) +{ + int i; + struct imx_intpll_rate_table *rate; + struct ana_pll_reg *reg; + u32 pll_status; + + for (i = 0; i < ARRAY_SIZE(imx9_intpll_tbl); i++) { + if (freq == imx9_intpll_tbl[i].rate) + break; + } + + if (i == ARRAY_SIZE(imx9_intpll_tbl)) { + debug("No matched freq table %u\n", freq); + return -EINVAL; + } + + rate = &imx9_intpll_tbl[i]; + + /* ROM has configured SYS PLL and PFD, no need for it */ + switch (pll) { + case ARM_PLL_CLK: + reg = &ana_regs->arm_pll; + break; + default: + return -EPERM; + } + + /* Bypass the PLL to ref */ + writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_set); + + /* disable pll and output */ + writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, &reg->ctrl.reg_clr); + + /* Program the ODIV, RDIV, MFI */ + writel((rate->odiv & GENMASK(7, 0)) | ((rate->rdiv << 13) & GENMASK(15, 13)) | + ((rate->mfi << 16) & GENMASK(24, 16)), &reg->div.reg); + + /* wait 5us */ + udelay(5); + + /* power up the PLL and wait lock (max wait time 100 us) */ + writel(PLL_CTRL_POWERUP, &reg->ctrl.reg_set); + + udelay(100); + + pll_status = readl(&reg->pll_status); + if (pll_status & PLL_STATUS_PLL_LOCK) { + writel(PLL_CTRL_CLKMUX_EN, &reg->ctrl.reg_set); + + /* clear bypass */ + writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_clr); + + } else { + debug("Fail to lock PLL %u\n", pll); + return -EIO; + } + + return 0; +} + +int configure_fracpll(enum ccm_clk_src pll, u32 freq) +{ + struct imx_fracpll_rate_table *rate; + struct ana_pll_reg *reg; + u32 pll_status; + int i; + + for (i = 0; i < ARRAY_SIZE(imx9_fracpll_tbl); i++) { + if (freq == imx9_fracpll_tbl[i].rate) + break; + } + + if (i == ARRAY_SIZE(imx9_fracpll_tbl)) { + debug("No matched freq table %u\n", freq); + return -EINVAL; + } + + rate = &imx9_fracpll_tbl[i]; + + switch (pll) { + case SYS_PLL_PG: + reg = &ana_regs->sys_pll; + break; + case DRAM_PLL_CLK: + reg = &ana_regs->dram_pll; + break; + case VIDEO_PLL_CLK: + reg = &ana_regs->video_pll; + break; + default: + return -EPERM; + } + + /* Bypass the PLL to ref */ + writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_set); + + /* disable pll and output */ + writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, &reg->ctrl.reg_clr); + + /* Program the ODIV, RDIV, MFI */ + writel((rate->odiv & GENMASK(7, 0)) | ((rate->rdiv << 13) & GENMASK(15, 13)) | + ((rate->mfi << 16) & GENMASK(24, 16)), &reg->div.reg); + + /* Set SPREAD_SPECRUM enable to 0 */ + writel(PLL_SS_EN, &reg->ss.reg_clr); + + /* Program NUMERATOR and DENOMINATOR */ + writel((rate->mfn << 2), &reg->num.reg); + writel((rate->mfd & GENMASK(29, 0)), &reg->denom.reg); + + /* wait 5us */ + udelay(5); + + /* power up the PLL and wait lock (max wait time 100 us) */ + writel(PLL_CTRL_POWERUP, &reg->ctrl.reg_set); + + udelay(100); + + pll_status = readl(&reg->pll_status); + if (pll_status & PLL_STATUS_PLL_LOCK) { + writel(PLL_CTRL_CLKMUX_EN, &reg->ctrl.reg_set); + + /* check the MFN is updated */ + pll_status = readl(&reg->pll_status); + if ((pll_status & ~0x3) != (rate->mfn << 2)) { + debug("MFN update not matched, pll_status 0x%x, mfn 0x%x\n", + pll_status, rate->mfn); + return -EIO; + } + + /* clear bypass */ + writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_clr); + + } else { + debug("Fail to lock PLL %u\n", pll); + return -EIO; + } + + return 0; +} + +int configure_pll_pfd(enum ccm_clk_src pll_pfg, u32 mfi, u32 mfn, bool div2_en) +{ + struct ana_pll_dfs *dfs; + struct ana_pll_reg *reg; + u32 dfs_status; + u32 index; + + if (mfn > 3) + return -EINVAL; /* valid mfn 0-3 */ + + if (mfi < 2 || mfi > 255) + return -EINVAL; /* valid mfi 2-255 */ + + switch (pll_pfg) { + case SYS_PLL_PFD0: + reg = &ana_regs->sys_pll; + index = 0; + break; + case SYS_PLL_PFD1: + reg = &ana_regs->sys_pll; + index = 1; + break; + case SYS_PLL_PFD2: + reg = &ana_regs->sys_pll; + index = 2; + break; + default: + return -EPERM; + } + + dfs = &reg->dfs[index]; + + /* Bypass the DFS to PLL VCO */ + writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_set); + + /* disable DFS and output */ + writel(PLL_DFS_CTRL_ENABLE | PLL_DFS_CTRL_CLKOUT | + PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_clr); + + writel(((mfi << 8) & GENMASK(15, 8)) | (mfn & GENMASK(2, 0)), &dfs->dfs_div.reg); + + writel(PLL_DFS_CTRL_CLKOUT, &dfs->dfs_ctrl.reg_set); + if (div2_en) + writel(PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_set); + writel(PLL_DFS_CTRL_ENABLE, &dfs->dfs_ctrl.reg_set); + + /* + * As HW expert said: after enabling the DFS, clock will start + * coming after 6 cycles output clock period. + * 5us is much bigger than expected, so it will be safe + */ + udelay(5); + + dfs_status = readl(&reg->dfs_status); + + if (!(dfs_status & (1 << index))) { + debug("DFS lock failed\n"); + return -EIO; + } + + /* Bypass the DFS to PLL VCO */ + writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_clr); + + return 0; +} + +int update_fracpll_mfn(enum ccm_clk_src pll, int mfn) +{ + struct ana_pll_reg *reg; + bool repoll = false; + u32 pll_status; + int count = 20; + + switch (pll) { + case AUDIO_PLL_CLK: + reg = &ana_regs->audio_pll; + break; + case DRAM_PLL_CLK: + reg = &ana_regs->dram_pll; + break; + case VIDEO_PLL_CLK: + reg = &ana_regs->video_pll; + break; + default: + printf("Invalid pll %u for update FRAC PLL MFN\n", pll); + return -EINVAL; + } + + if (readl(&reg->pll_status) & PLL_STATUS_PLL_LOCK) + repoll = true; + + mfn <<= 2; + writel(mfn, &reg->num); + + if (repoll) { + do { + pll_status = readl(&reg->pll_status); + udelay(5); + count--; + } while (((pll_status & ~0x3) != (u32)mfn) && count > 0); + + if (count <= 0) { + printf("update MFN timeout, pll_status 0x%x, mfn 0x%x\n", pll_status, mfn); + return -EIO; + } + } + + return 0; +} + +int update_pll_pfd_mfn(enum ccm_clk_src pll_pfd, u32 mfn) +{ + struct ana_pll_dfs *dfs; + u32 val; + u32 index; + + switch (pll_pfd) { + case SYS_PLL_PFD0: + case SYS_PLL_PFD0_DIV2: + index = 0; + break; + case SYS_PLL_PFD1: + case SYS_PLL_PFD1_DIV2: + index = 1; + break; + case SYS_PLL_PFD2: + case SYS_PLL_PFD2_DIV2: + index = 2; + break; + default: + printf("Invalid pfd %u for update PLL PFD MFN\n", pll_pfd); + return -EINVAL; + } + + dfs = &ana_regs->sys_pll.dfs[index]; + + val = readl(&dfs->dfs_div.reg); + val &= ~0x3; + val |= mfn & 0x3; + writel(val, &dfs->dfs_div.reg); + + return 0; +} + +/* return in khz */ +u32 get_clk_src_rate(enum ccm_clk_src source) +{ + u32 ctrl; + bool clk_on; + + switch (source) { + case ARM_PLL_CLK: + ctrl = readl(&ana_regs->arm_pll.ctrl.reg); + case AUDIO_PLL_CLK: + ctrl = readl(&ana_regs->audio_pll.ctrl.reg); + break; + case DRAM_PLL_CLK: + ctrl = readl(&ana_regs->dram_pll.ctrl.reg); + break; + case VIDEO_PLL_CLK: + ctrl = readl(&ana_regs->video_pll.ctrl.reg); + break; + case SYS_PLL_PFD0: + case SYS_PLL_PFD0_DIV2: + ctrl = readl(&ana_regs->sys_pll.dfs[0].dfs_ctrl.reg); + break; + case SYS_PLL_PFD1: + case SYS_PLL_PFD1_DIV2: + ctrl = readl(&ana_regs->sys_pll.dfs[1].dfs_ctrl.reg); + break; + case SYS_PLL_PFD2: + case SYS_PLL_PFD2_DIV2: + ctrl = readl(&ana_regs->sys_pll.dfs[2].dfs_ctrl.reg); + break; + case OSC_24M_CLK: + return 24000; + default: + printf("Invalid clock source to get rate\n"); + return 0; + } + + if (ctrl & PLL_CTRL_HW_CTRL_SEL) { + /* When using HW ctrl, check OSCPLL */ + clk_on = ccm_clk_src_is_clk_on(source); + if (clk_on) + return decode_pll(source); + else + return 0; + } else { + /* controlled by pll registers */ + return decode_pll(source); + } +} + +u32 get_arm_core_clk(void) +{ + u32 val; + + ccm_shared_gpr_get(SHARED_GPR_A55_CLK, &val); + + if (val & SHARED_GPR_A55_CLK_SEL_PLL) + return decode_pll(ARM_PLL_CLK) * 1000; + + return ccm_clk_root_get_rate(ARM_A55_CLK_ROOT); +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_arm_core_clk(); + case MXC_IPG_CLK: + return ccm_clk_root_get_rate(BUS_WAKEUP_CLK_ROOT); + case MXC_CSPI_CLK: + return ccm_clk_root_get_rate(LPSPI1_CLK_ROOT); + case MXC_ESDHC_CLK: + return ccm_clk_root_get_rate(USDHC1_CLK_ROOT); + case MXC_ESDHC2_CLK: + return ccm_clk_root_get_rate(USDHC2_CLK_ROOT); + case MXC_ESDHC3_CLK: + return ccm_clk_root_get_rate(USDHC3_CLK_ROOT); + case MXC_UART_CLK: + return ccm_clk_root_get_rate(LPUART1_CLK_ROOT); + case MXC_FLEXSPI_CLK: + return ccm_clk_root_get_rate(FLEXSPI1_CLK_ROOT); + default: + return -1; + }; + + return -1; +}; + +int enable_i2c_clk(unsigned char enable, u32 i2c_num) +{ + if (i2c_num > 7) + return -EINVAL; + + if (enable) { + /* 24M */ + ccm_lpcg_on(CCGR_I2C1 + i2c_num, false); + ccm_clk_root_cfg(LPI2C1_CLK_ROOT + i2c_num, OSC_24M_CLK, 1); + ccm_lpcg_on(CCGR_I2C1 + i2c_num, true); + } else { + ccm_lpcg_on(CCGR_I2C1 + i2c_num, false); + } + + return 0; +} + +u32 imx_get_i2cclk(u32 i2c_num) +{ + if (i2c_num > 7) + return -EINVAL; + + return ccm_clk_root_get_rate(LPUART1_CLK_ROOT + i2c_num); +} + u32 get_lpuart_clk(void) { - return 24000000; + return mxc_get_clock(MXC_UART_CLK); +} + +void init_uart_clk(u32 index) +{ + switch (index) { + case LPUART1_CLK_ROOT: + /* 24M */ + ccm_lpcg_on(CCGR_URT1, false); + ccm_clk_root_cfg(LPUART1_CLK_ROOT, OSC_24M_CLK, 1); + ccm_lpcg_on(CCGR_URT1, true); + break; + default: + break; + } +} + +void init_clk_usdhc(u32 index) +{ + /* 400 Mhz */ + switch (index) { + case 0: + ccm_lpcg_on(CCGR_USDHC1, 0); + ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, 2); + ccm_lpcg_on(CCGR_USDHC1, 1); + break; + case 1: + ccm_lpcg_on(CCGR_USDHC2, 0); + ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, 2); + ccm_lpcg_on(CCGR_USDHC2, 1); + break; + case 2: + ccm_lpcg_on(CCGR_USDHC3, 0); + ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, 2); + ccm_lpcg_on(CCGR_USDHC3, 1); + break; + default: + return; + }; }

+void enable_usboh3_clk(unsigned char enable) +{ + if (enable) { + ccm_clk_root_cfg(HSIO_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + ccm_lpcg_on(CCGR_USBC, 1); + } else { + ccm_lpcg_on(CCGR_USBC, 0); + } +} + +int clock_init(void) +{ + int i; + + /* Set A55 periphal to 333M */ + ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3); + /* Set A55 mtr bus to 133M */ + ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + + /* Sentinel to 200M */ + ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); + /* Bus_wakeup to 133M */ + ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Bus_AON to 133M */ + ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 to 200M */ + ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); + /* + * WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for + * generating MII clock at 2.5M + */ + ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2); + /* SWO TRACE to 133M */ + ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 systetick to 133M */ + ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* NIC to 400M */ + ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2); + /* NIC_APB to 133M */ + ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + + /* allow for non-secure access */ + for (i = 0; i < OSCPLL_END; i++) + ccm_clk_src_tz_access(i, true, false, false); + + for (i = 0; i < CLK_ROOT_NUM; i++) + ccm_clk_root_tz_access(i, true, false, false); + + for (i = 0; i < CCGR_NUM; i++) + ccm_lpcg_tz_access(i, true, false, false); + + for (i = 0; i < SHARED_GPR_NUM; i++) + ccm_shared_gpr_tz_access(i, true, false, false); + + return 0; +} + +int set_clk_eqos(enum enet_freq type) +{ + u32 eqos_post_div; + + switch (type) { + case ENET_125MHZ: + eqos_post_div = 2; /* 250M clock */ + break; + case ENET_50MHZ: + eqos_post_div = 5; /* 100M clock */ + break; + case ENET_25MHZ: + eqos_post_div = 10; /* 50M clock*/ + break; + default: + return -EINVAL; + } + + /* disable the clock first */ + ccm_lpcg_on(CCGR_ENETQOS, false); + + ccm_clk_root_cfg(ENET_CLK_ROOT, SYS_PLL_PFD0_DIV2, eqos_post_div); + ccm_clk_root_cfg(ENET_TIMER2_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5); + + /* enable clock */ + ccm_lpcg_on(CCGR_ENETQOS, true); + + return 0; +} + +u32 imx_get_eqos_csr_clk(void) +{ + return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT); +} + +u32 imx_get_fecclk(void) +{ + return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT); +} + +int set_clk_enet(enum enet_freq type) +{ + u32 div; + + /* disable the clock first */ + ccm_lpcg_on(CCGR_ENET1, false); + + switch (type) { + case ENET_125MHZ: + div = 2; /* 250Mhz */ + break; + case ENET_50MHZ: + div = 5; /* 100Mhz */ + break; + case ENET_25MHZ: + div = 10; /* 50Mhz */ + break; + default: + return -EINVAL; + } + + ccm_clk_root_cfg(ENET_REF_CLK_ROOT, SYS_PLL_PFD0_DIV2, div); + ccm_clk_root_cfg(ENET_TIMER1_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5); + +#ifdef CONFIG_FEC_MXC_25M_REF_CLK + ccm_clk_root_cfg(ENET_REF_PHY_CLK_ROOT, SYS_PLL_PFD0_DIV2, 20); +#endif + + /* enable clock */ + ccm_lpcg_on(CCGR_ENET1, true); + + return 0; +} + +/* + * Dump some clockes. + */ +#ifndef CONFIG_SPL_BUILD +int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + u32 freq; + + freq = decode_pll(ARM_PLL_CLK); + printf("ARM_PLL %8d MHz\n", freq / 1000); + freq = decode_pll(DRAM_PLL_CLK); + printf("DRAM_PLL %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD0); + printf("SYS_PLL_PFD0 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD0_DIV2); + printf("SYS_PLL_PFD0_DIV2 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD1); + printf("SYS_PLL_PFD1 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD1_DIV2); + printf("SYS_PLL_PFD1_DIV2 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD2); + printf("SYS_PLL_PFD2 %8d MHz\n", freq / 1000); + freq = decode_pll(SYS_PLL_PFD2_DIV2); + printf("SYS_PLL_PFD2_DIV2 %8d MHz\n", freq / 1000); + freq = mxc_get_clock(MXC_ARM_CLK); + printf("ARM CORE %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_IPG_CLK); + printf("IPG %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_UART_CLK); + printf("UART3 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_ESDHC_CLK); + printf("USDHC1 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_FLEXSPI_CLK); + printf("FLEXSPI %8d MHz\n", freq / 1000000); + + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks, + "display clocks", + "" +); +#endif + diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c new file mode 100644 index 00000000000..06b93f60996 --- /dev/null +++ b/arch/arm/mach-imx/imx9/clock_root.c @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Peng Fan peng.fan@nxp.com + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/ccm_regs.h> +#include <asm/global_data.h> +#include <linux/iopoll.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR; + +static enum ccm_clk_src clk_root_mux[][4] = { + { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, SYS_PLL_PFD2 }, /* bus */ + { OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, SYS_PLL_PFD2_DIV2 }, /* non-IO */ + { OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, VIDEO_PLL_CLK }, /* IO*/ + { OSC_24M_CLK, SYS_PLL_PFD0, AUDIO_PLL_CLK, EXT_CLK }, /* TPM */ + { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, EXT_CLK }, /* Audio */ + { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, SYS_PLL_PFD0 }, /* Video */ + { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, AUDIO_PLL_CLK }, /* CKO1 */ + { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, VIDEO_PLL_CLK }, /* CKO2 */ + { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, SYS_PLL_PFD2 }, /* CAMSCAN */ +}; + +static struct clk_root_map clk_root_array[] = { + { ARM_A55_PERIPH_CLK_ROOT, 0 }, + { ARM_A55_MTR_BUS_CLK_ROOT, 2 }, + { ARM_A55_CLK_ROOT, 0 }, + { M33_CLK_ROOT, 2 }, + { SENTINEL_CLK_ROOT, 2 }, + { BUS_WAKEUP_CLK_ROOT, 2 }, + { BUS_AON_CLK_ROOT, 2 }, + { WAKEUP_AXI_CLK_ROOT, 0 }, + { SWO_TRACE_CLK_ROOT, 2 }, + { M33_SYSTICK_CLK_ROOT, 2 }, + { FLEXIO1_CLK_ROOT, 2 }, + { FLEXIO2_CLK_ROOT, 2 }, + { LPIT1_CLK_ROOT, 2 }, + { LPIT2_CLK_ROOT, 2 }, + { LPTMR1_CLK_ROOT, 2 }, + { LPTMR2_CLK_ROOT, 2 }, + { TPM1_CLK_ROOT, 3 }, + { TPM2_CLK_ROOT, 3 }, + { TPM3_CLK_ROOT, 3 }, + { TPM4_CLK_ROOT, 3 }, + { TPM5_CLK_ROOT, 3 }, + { TPM6_CLK_ROOT, 3 }, + { FLEXSPI1_CLK_ROOT, 0 }, + { CAN1_CLK_ROOT, 2 }, + { CAN2_CLK_ROOT, 2 }, + { LPUART1_CLK_ROOT, 2 }, + { LPUART2_CLK_ROOT, 2 }, + { LPUART3_CLK_ROOT, 2 }, + { LPUART4_CLK_ROOT, 2 }, + { LPUART5_CLK_ROOT, 2 }, + { LPUART6_CLK_ROOT, 2 }, + { LPUART7_CLK_ROOT, 2 }, + { LPUART8_CLK_ROOT, 2 }, + { LPI2C1_CLK_ROOT, 2 }, + { LPI2C2_CLK_ROOT, 2 }, + { LPI2C3_CLK_ROOT, 2 }, + { LPI2C4_CLK_ROOT, 2 }, + { LPI2C5_CLK_ROOT, 2 }, + { LPI2C6_CLK_ROOT, 2 }, + { LPI2C7_CLK_ROOT, 2 }, + { LPI2C8_CLK_ROOT, 2 }, + { LPSPI1_CLK_ROOT, 2 }, + { LPSPI2_CLK_ROOT, 2 }, + { LPSPI3_CLK_ROOT, 2 }, + { LPSPI4_CLK_ROOT, 2 }, + { LPSPI5_CLK_ROOT, 2 }, + { LPSPI6_CLK_ROOT, 2 }, + { LPSPI7_CLK_ROOT, 2 }, + { LPSPI8_CLK_ROOT, 2 }, + { I3C1_CLK_ROOT, 2 }, + { I3C2_CLK_ROOT, 2 }, + { USDHC1_CLK_ROOT, 0 }, + { USDHC2_CLK_ROOT, 0 }, + { USDHC3_CLK_ROOT, 0 }, + { SAI1_CLK_ROOT, 4 }, + { SAI2_CLK_ROOT, 4 }, + { SAI3_CLK_ROOT, 4 }, + { CCM_CKO1_CLK_ROOT, 6 }, + { CCM_CKO2_CLK_ROOT, 7 }, + { CCM_CKO3_CLK_ROOT, 6 }, + { CCM_CKO4_CLK_ROOT, 7 }, + { HSIO_CLK_ROOT, 2 }, + { HSIO_USB_TEST_60M_CLK_ROOT, 2 }, + { HSIO_ACSCAN_80M_CLK_ROOT, 2 }, + { HSIO_ACSCAN_480M_CLK_ROOT, 0 }, + { NIC_CLK_ROOT, 0 }, + { NIC_APB_CLK_ROOT, 2 }, + { ML_APB_CLK_ROOT, 2 }, + { ML_CLK_ROOT, 0 }, + { MEDIA_AXI_CLK_ROOT, 0 }, + { MEDIA_APB_CLK_ROOT, 2 }, + { MEDIA_LDB_CLK_ROOT, 5 }, + { MEDIA_DISP_PIX_CLK_ROOT, 5 }, + { CAM_PIX_CLK_ROOT, 5 }, + { MIPI_TEST_BYTE_CLK_ROOT, 5 }, + { MIPI_PHY_CFG_CLK_ROOT, 5 }, + { DRAM_ALT_CLK_ROOT, 0 }, + { DRAM_APB_CLK_ROOT, 1 }, + { ADC_CLK_ROOT, 2 }, + { PDM_CLK_ROOT, 4 }, + { TSTMR1_CLK_ROOT, 2 }, + { TSTMR2_CLK_ROOT, 2 }, + { MQS1_CLK_ROOT, 4 }, + { MQS2_CLK_ROOT, 4 }, + { AUDIO_XCVR_CLK_ROOT, 1 }, + { SPDIF_CLK_ROOT, 4 }, + { ENET_CLK_ROOT, 1 }, + { ENET_TIMER1_CLK_ROOT, 2 }, + { ENET_TIMER2_CLK_ROOT, 2 }, + { ENET_REF_CLK_ROOT, 1 }, + { ENET_REF_PHY_CLK_ROOT, 2 }, + { I3C1_SLOW_CLK_ROOT, 2 }, + { I3C2_SLOW_CLK_ROOT, 2 }, + { USB_PHY_BURUNIN_CLK_ROOT, 2 }, + { PAL_CAME_SCAN_CLK_ROOT, 8 }, +}; + +int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable) +{ + u32 authen; + + if (oscpll >= OSCPLL_END) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + + /* If using cpulpm, need disable it first */ + if (authen & CCM_AUTHEN_CPULPM_MODE) + return -EPERM; + + if (enable) + writel(1, &ccm_reg->clk_oscplls[oscpll].direct); + else + writel(0, &ccm_reg->clk_oscplls[oscpll].direct); + + return 0; +} + +/* auto mode, enable = DIRECT[ON] | STATUS0[IN_USE] */ +int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable) +{ + u32 authen; + + if (oscpll >= OSCPLL_END) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + + /* AUTO CTRL and CPULPM are mutual exclusion, need disable CPULPM first */ + if (authen & CCM_AUTHEN_CPULPM_MODE) + return -EPERM; + + if (enable) + writel(authen | CCM_AUTHEN_AUTO_CTRL, &ccm_reg->clk_oscplls[oscpll].authen); + else + writel((authen & ~CCM_AUTHEN_AUTO_CTRL), &ccm_reg->clk_oscplls[oscpll].authen); + + return 0; +} + +int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable) +{ + u32 authen; + + if (oscpll >= OSCPLL_END) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + + /* AUTO CTRL and CPULPM are mutual exclusion, need disable AUTO CTRL first */ + if (authen & CCM_AUTHEN_AUTO_CTRL) + return -EPERM; + + if (enable) + writel(authen | CCM_AUTHEN_CPULPM_MODE, &ccm_reg->clk_oscplls[oscpll].authen); + else + writel((authen & ~CCM_AUTHEN_CPULPM_MODE), &ccm_reg->clk_oscplls[oscpll].authen); + + return 0; +} + +int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val) +{ + u32 lpm, authen; + + if (oscpll >= OSCPLL_END || domain >= 16) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + if (!(authen & CCM_AUTHEN_CPULPM_MODE)) + return -EPERM; + + if (domain > 7) { + lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm1); + lpm &= ~(0x3 << ((domain - 8) * 4)); + lpm |= (lpm_val & 0x3) << ((domain - 8) * 4); + writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm1); + } else { + lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm0); + lpm &= ~(0x3 << (domain * 4)); + lpm |= (lpm_val & 0x3) << (domain * 4); + writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm0); + } + + return 0; +} + +bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll) +{ + return !!(readl(&ccm_reg->clk_oscplls[oscpll].status0) & 0x1); +} + +int ccm_clk_src_tz_access(enum ccm_clk_src oscpll, bool non_secure, bool user_mode, bool lock_tz) +{ + u32 authen; + + if (oscpll >= OSCPLL_END) + return -EINVAL; + + authen = readl(&ccm_reg->clk_oscplls[oscpll].authen); + + authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0; + authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0; + authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0; + + writel(authen, &ccm_reg->clk_oscplls[oscpll].authen); + + return 0; +} + +int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div) +{ + int i; + int ret; + u32 mux, status; + + if (clk_root_id >= CLK_ROOT_NUM || div > 256 || div == 0) + return -EINVAL; + + mux = clk_root_array[clk_root_id].mux_type; + + for (i = 0; i < 4; i++) { + if (src == clk_root_mux[mux][i]) + break; + } + + if (i == 4) { + printf("Invalid source [%u] for this clk root\n", src); + return -EINVAL; + } + + writel((i << 8) | (div - 1), &ccm_reg->clk_roots[clk_root_id].control); + + ret = readl_poll_timeout(&ccm_reg->clk_roots[clk_root_id].status0, status, + !(status & CLK_ROOT_STATUS_CHANGING), 200000); + if (ret) + printf("%s: failed, status: 0x%x\n", __func__, + readl(&ccm_reg->clk_roots[clk_root_id].status0)); + + return ret; +}; + +u32 ccm_clk_root_get_rate(u32 clk_root_id) +{ + u32 mux, status, div, rate; + enum ccm_clk_src src; + + if (clk_root_id >= CLK_ROOT_NUM) + return 0; + + status = readl(&ccm_reg->clk_roots[clk_root_id].control); + + if (status & CLK_ROOT_STATUS_OFF) + return 0; /* clock is off */ + + mux = (status & CLK_ROOT_MUX_MASK) >> CLK_ROOT_MUX_SHIFT; + div = status & CLK_ROOT_DIV_MASK; + src = clk_root_mux[clk_root_array[clk_root_id].mux_type][mux]; + + rate = get_clk_src_rate(src) * 1000; + + return rate / (div + 1); /* return in hz */ +} + +int ccm_clk_root_tz_access(u32 clk_root_id, bool non_secure, bool user_mode, bool lock_tz) +{ + u32 authen; + + if (clk_root_id >= CLK_ROOT_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_roots[clk_root_id].authen); + + authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0; + authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0; + authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0; + + writel(authen, &ccm_reg->clk_roots[clk_root_id].authen); + + return 0; +} + +int ccm_lpcg_on(u32 lpcg, bool enable) +{ + u32 authen; + + if (lpcg >= CCGR_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen); + + /* If using cpulpm, need disable it first */ + if (authen & CCM_AUTHEN_CPULPM_MODE) + return -EPERM; + + if (enable) + writel(1, &ccm_reg->clk_lpcgs[lpcg].direct); + else + writel(0, &ccm_reg->clk_lpcgs[lpcg].direct); + + return 0; +} + +int ccm_lpcg_lpm(u32 lpcg, bool enable) +{ + u32 authen; + + if (lpcg >= CCGR_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen); + + if (enable) + writel(authen | CCM_AUTHEN_CPULPM_MODE, &ccm_reg->clk_lpcgs[lpcg].authen); + else + writel((authen & ~CCM_AUTHEN_CPULPM_MODE), &ccm_reg->clk_lpcgs[lpcg].authen); + + return 0; +} + +int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val) +{ + u32 lpm, authen; + + if (lpcg >= CCGR_NUM || domain >= 16) + return -EINVAL; + + authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen); + if (!(authen & CCM_AUTHEN_CPULPM_MODE)) + return -EPERM; + + if (domain > 7) { + lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm1); + lpm &= ~(0x3 << ((domain - 8) * 4)); + lpm |= (lpm_val & 0x3) << ((domain - 8) * 4); + writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm1); + } else { + lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm0); + lpm &= ~(0x3 << (domain * 4)); + lpm |= (lpm_val & 0x3) << (domain * 4); + writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm0); + } + + return 0; +} + +bool ccm_lpcg_is_clk_on(u32 lpcg) +{ + return !!(readl(&ccm_reg->clk_lpcgs[lpcg].status0) & 0x1); +} + +int ccm_lpcg_tz_access(u32 lpcg, bool non_secure, bool user_mode, bool lock_tz) +{ + u32 authen; + + if (lpcg >= CCGR_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen); + + authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0; + authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0; + authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0; + + writel(authen, &ccm_reg->clk_lpcgs[lpcg].authen); + + return 0; +} + +int ccm_shared_gpr_set(u32 gpr, u32 val) +{ + if (gpr >= SHARED_GPR_NUM) + return -EINVAL; + + writel(val, &ccm_reg->clk_shared_gpr[gpr].gpr); + + return 0; +} + +int ccm_shared_gpr_get(u32 gpr, u32 *val) +{ + if (gpr >= SHARED_GPR_NUM || !val) + return -EINVAL; + + *val = readl(&ccm_reg->clk_shared_gpr[gpr].gpr); + + return 0; +} + +int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool user_mode, bool lock_tz) +{ + u32 authen; + + if (gpr >= SHARED_GPR_NUM) + return -EINVAL; + + authen = readl(&ccm_reg->clk_shared_gpr[gpr].authen); + + authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0; + authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0; + authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0; + + writel(authen, &ccm_reg->clk_shared_gpr[gpr].authen); + + return 0; +} diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index d905fe76c91..d4a97729c67 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -123,5 +123,8 @@ int ft_system_setup(void *blob, struct bd_info *bd)

int arch_cpu_init(void) { + if (IS_ENABLED(CONFIG_SPL_BUILD)) + clock_init(); + return 0; }

From: Peng Fan peng.fan@nxp.com

Select SPL_FIT_IMAGE_TINY for i.MX9

Signed-off-by: Peng Fan peng.fan@nxp.com --- common/spl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 848237c1e85..06cbad2ca85 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -537,7 +537,7 @@ config SPL_FIT_IMAGE_TINY bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6 - default y if ARCH_IMX8M + default y if ARCH_IMX8M || ARCH_IMX9 help Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight.

From: Ye Li ye.li@nxp.com

Disable all 3 wdogs on AIPS2 and unmask SRC reset trigger for WDOG3-5

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx9/imx-regs.h | 4 ++ arch/arm/mach-imx/imx9/soc.c | 45 ++++++++++++++++++++++- 2 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h index 32c76ce9c3b..e4babed40fc 100644 --- a/arch/arm/include/asm/arch-imx9/imx-regs.h +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -15,4 +15,8 @@

#define ANATOP_BASE_ADDR 0x44480000UL

+#define WDG3_BASE_ADDR 0x42490000UL +#define WDG4_BASE_ADDR 0x424a0000UL +#define WDG5_BASE_ADDR 0x424b0000UL + #endif diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 4b8f1ca30d5..8b620832b5d 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -34,6 +34,45 @@ u32 get_cpu_rev(void) return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0; }

+#define UNLOCK_WORD 0xD928C520 /* unlock word */ +#define REFRESH_WORD 0xB480A602 /* refresh word */ + +static void disable_wdog(void __iomem *wdog_base) +{ + u32 val_cs = readl(wdog_base + 0x00); + + if (!(val_cs & 0x80)) + return; + + /* default is 32bits cmd */ + writel(REFRESH_WORD, (wdog_base + 0x04)); /* Refresh the CNT */ + + if (!(val_cs & 0x800)) { + writel(UNLOCK_WORD, (wdog_base + 0x04)); + while (!(readl(wdog_base + 0x00) & 0x800)) + ; + } + writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ + writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ + writel(0x2120, (wdog_base + 0x00)); /* Disable it and set update */ + + while (!(readl(wdog_base + 0x00) & 0x400)) + ; +} + +void init_wdog(void) +{ + u32 src_val; + + disable_wdog((void __iomem *)WDG3_BASE_ADDR); + disable_wdog((void __iomem *)WDG4_BASE_ADDR); + disable_wdog((void __iomem *)WDG5_BASE_ADDR); + + src_val = readl(0x54460018); /* reset mask */ + src_val &= ~0x1c; + writel(src_val, 0x54460018); +} + static struct mm_region imx93_mem_map[] = { { /* ROM */ @@ -123,8 +162,12 @@ int ft_system_setup(void *blob, struct bd_info *bd)

int arch_cpu_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + /* Disable wdog */ + init_wdog(); + clock_init(); + }

return 0; }

From: Ye Li ye.li@nxp.com

Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400 MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/Kconfig | 4 + arch/arm/include/asm/global_data.h | 2 +- .../asm/{arch-imx8ulp => mach-imx}/mu_hal.h | 4 +- .../asm/{arch-imx8ulp => mach-imx}/s400_api.h | 0 arch/arm/mach-imx/imx8ulp/ahab.c | 345 ++++++++++++++++++ arch/arm/mach-imx/imx8ulp/rdc.c | 4 +- arch/arm/mach-imx/imx8ulp/soc.c | 4 +- board/freescale/imx8ulp_evk/spl.c | 2 +- drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 2 + drivers/misc/imx8ulp/Makefile | 1 - drivers/misc/imx8ulp/fuse.c | 2 +- drivers/misc/sentinel/Makefile | 3 + drivers/misc/{imx8ulp => sentinel}/s400_api.c | 6 +- .../{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} | 4 +- 15 files changed, 375 insertions(+), 15 deletions(-) rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/mu_hal.h (79%) rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/s400_api.h (100%) create mode 100644 arch/arm/mach-imx/imx8ulp/ahab.c create mode 100644 drivers/misc/sentinel/Makefile rename drivers/misc/{imx8ulp => sentinel}/s400_api.c (98%) rename drivers/misc/{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} (98%)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 12ec661ac3b..29b831422ff 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -922,6 +922,8 @@ config ARCH_IMX8ULP select OF_CONTROL select SUPPORT_SPL select GPIO_EXTRA_HEADER + select MISC + select IMX_SENTINEL imply CMD_DM imply DM_EVENT

@@ -931,6 +933,8 @@ config ARCH_IMX9 select DM select MACH_IMX select SUPPORT_SPL + select MISC + select IMX_SENTINEL imply CMD_DM imply DM_EVENT

diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 085e12b5d4d..09f352269e5 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -90,7 +90,7 @@ struct arch_global_data { struct udevice *scu_dev; #endif

-#ifdef CONFIG_ARCH_IMX8ULP +#ifdef CONFIG_IMX_SENTINEL struct udevice *s400_dev; #endif

diff --git a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h b/arch/arm/include/asm/mach-imx/mu_hal.h similarity index 79% rename from arch/arm/include/asm/arch-imx8ulp/mu_hal.h rename to arch/arm/include/asm/mach-imx/mu_hal.h index 10d966d5d43..5db559c1ac5 100644 --- a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h +++ b/arch/arm/include/asm/mach-imx/mu_hal.h @@ -3,8 +3,8 @@ * Copyright 2021 NXP */

-#ifndef __IMX8ULP_MU_HAL_H__ -#define __IMX8ULP_MU_HAL_H__ +#ifndef __SNT_MU_HAL_H__ +#define __SNT_MU_HAL_H__

void mu_hal_init(ulong base); int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg); diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h similarity index 100% rename from arch/arm/include/asm/arch-imx8ulp/s400_api.h rename to arch/arm/include/asm/mach-imx/s400_api.h diff --git a/arch/arm/mach-imx/imx8ulp/ahab.c b/arch/arm/mach-imx/imx8ulp/ahab.c new file mode 100644 index 00000000000..87c4c66a087 --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/ahab.c @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include <common.h> +#include <command.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/sys_proto.h> +#include <asm/arch-imx/cpu.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/image.h> +#include <console.h> +#include <cpu_func.h> +#include <asm/mach-imx/ahab.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define IMG_CONTAINER_BASE (0x22010000UL) +#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL) + +#define AHAB_NO_AUTHENTICATION_IND 0xee +#define AHAB_BAD_KEY_HASH_IND 0xfa +#define AHAB_INVALID_KEY_IND 0xf9 +#define AHAB_BAD_SIGNATURE_IND 0xf0 +#define AHAB_BAD_HASH_IND 0xf1 + +static void display_ahab_auth_ind(u32 event) +{ + u8 resp_ind = (event >> 8) & 0xff; + + switch (resp_ind) { + case AHAB_NO_AUTHENTICATION_IND: + printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind); + break; + case AHAB_BAD_KEY_HASH_IND: + printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind); + break; + case AHAB_INVALID_KEY_IND: + printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind); + break; + case AHAB_BAD_SIGNATURE_IND: + printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind); + break; + case AHAB_BAD_HASH_IND: + printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind); + break; + default: + printf("Unknown Indicator (0x%02X)\n\n", resp_ind); + break; + } +} + +int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) +{ + int err; + u32 resp; + + memcpy((void *)IMG_CONTAINER_BASE, (const void *)container, + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); + + flush_dcache_range(IMG_CONTAINER_BASE, + IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1); + + err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp); + if (err) { + printf("Authenticate container hdr failed, return %d, resp 0x%x\n", + err, resp); + display_ahab_auth_ind(resp); + } + + return err; +} + +int ahab_auth_release(void) +{ + int err; + u32 resp; + + err = ahab_release_container(&resp); + if (err) { + printf("Error: release container failed, resp 0x%x!\n", resp); + display_ahab_auth_ind(resp); + } + + return err; +} + +int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) +{ + int err; + u32 resp; + + err = ahab_verify_image(image_index, &resp); + if (err) { + printf("Authenticate img %d failed, return %d, resp 0x%x\n", + image_index, err, resp); + display_ahab_auth_ind(resp); + return -EIO; + } + + return 0; +} + +static inline bool check_in_dram(ulong addr) +{ + int i; + struct bd_info *bd = gd->bd; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { + if (bd->bi_dram[i].size) { + if (addr >= bd->bi_dram[i].start && + addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + return true; + } + } + + return false; +} + +int authenticate_os_container(ulong addr) +{ + struct container_hdr *phdr; + int i, ret = 0; + int err; + u16 length; + struct boot_img_t *img; + unsigned long s, e; + + if (addr % 4) { + puts("Error: Image's address is not 4 byte aligned\n"); + return -EINVAL; + } + + if (!check_in_dram(addr)) { + puts("Error: Image's address is invalid\n"); + return -EINVAL; + } + + phdr = (struct container_hdr *)addr; + if (phdr->tag != 0x87 || phdr->version != 0x0) { + printf("Error: Wrong container header\n"); + return -EFAULT; + } + + if (!phdr->num_images) { + printf("Error: Wrong container, no image found\n"); + return -EFAULT; + } + + length = phdr->length_lsb + (phdr->length_msb << 8); + + debug("container length %u\n", length); + + err = ahab_auth_cntr_hdr(phdr, length); + if (err) { + ret = -EIO; + goto exit; + } + + debug("Verify images\n"); + + /* Copy images to dest address */ + for (i = 0; i < phdr->num_images; i++) { + img = (struct boot_img_t *)(addr + + sizeof(struct container_hdr) + + i * sizeof(struct boot_img_t)); + + debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n", + i, (uint32_t)img->dst, img->offset + addr, img->size); + + memcpy((void *)img->dst, (const void *)(img->offset + addr), img->size); + + s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1; + + flush_dcache_range(s, e); + + ret = ahab_verify_cntr_image(img, i); + if (ret) + goto exit; + } + +exit: + debug("ahab_auth_release, 0x%x\n", ret); + ahab_auth_release(); + + return ret; +} + +static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + + printf("Authenticate OS container at 0x%lx\n", addr); + + if (authenticate_os_container(addr)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static void display_life_cycle(u32 lc) +{ + printf("Lifecycle: 0x%08X, ", lc); + switch (lc) { + case 0x1: + printf("BLANK\n\n"); + break; + case 0x2: + printf("FAB\n\n"); + break; + case 0x4: + printf("NXP Provisioned\n\n"); + break; + case 0x8: + printf("OEM Open\n\n"); + break; + case 0x10: + printf("OEM Secure World Closed\n\n"); + break; + case 0x20: + printf("OEM closed\n\n"); + break; + case 0x40: + printf("Field Return OEM\n\n"); + break; + case 0x80: + printf("Field Return NXP\n\n"); + break; + case 0x100: + printf("OEM Locked\n\n"); + break; + case 0x200: + printf("BRICKED\n\n"); + break; + default: + printf("Unknown\n\n"); + break; + } +} + +static int confirm_close(void) +{ + puts("Warning: Please ensure your sample is in NXP closed state, " + "OEM SRK hash has been fused, \n" + " and you are able to boot a signed image successfully " + "without any SECO events reported.\n" + " If not, your sample will be unrecoverable.\n" + "\nReally perform this operation? <y/N>\n"); + + if (confirm_yesno()) + return 1; + + puts("Ahab close aborted\n"); + return 0; +} + +static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int err; + u32 resp; + + if (!confirm_close()) + return -EACCES; + + err = ahab_forward_lifecycle(8, &resp); + if (err != 0) { + printf("Error in forward lifecycle to OEM closed\n"); + return -EIO; + } + + printf("Change to OEM closed successfully\n"); + + return 0; +} + +int ahab_dump(void) +{ + u32 buffer[32]; + int ret, i = 0; + + do { + ret = ahab_dump_buffer(buffer, 32); + if (ret < 0) { + printf("Error in dump AHAB log\n"); + return -EIO; + } + + if (ret == 1) + break; + + for (i = 0; i < ret; i++) + printf("0x%x\n", buffer[i]); + } while (ret >= 21); + + return 0; +} + +static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + return ahab_dump(); +} + +static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + u32 lc; + + lc = readl(FSB_BASE_ADDR + 0x41c); + lc &= 0x3f; + + display_life_cycle(lc); + return 0; +} + +U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, + "autenticate OS container via AHAB", + "addr\n" + "addr - OS container hex address\n" +); + +U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close, + "Change AHAB lifecycle to OEM closed", + "" +); + +U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump, + "Dump AHAB log for debug", + "" +); + +U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status, + "display AHAB lifecycle only", + "" +); diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index e2eca0633e3..cc47079d8f5 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -8,8 +8,8 @@ #include <asm/types.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/mu_hal.h> -#include <asm/arch/s400_api.h> +#include <asm/mach-imx/mu_hal.h> +#include <asm/mach-imx/s400_api.h> #include <asm/arch/rdc.h> #include <div64.h>

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 529fda4594e..999fb1f301f 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -14,8 +14,8 @@ #include <event.h> #include <spl.h> #include <asm/arch/rdc.h> -#include <asm/arch/s400_api.h> -#include <asm/arch/mu_hal.h> +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/mu_hal.h> #include <cpu_func.h> #include <asm/setup.h> #include <dm.h> diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index ece9ff26e92..e672f6ee6cb 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -19,7 +19,7 @@ #include <asm/arch/ddr.h> #include <asm/arch/rdc.h> #include <asm/arch/upower.h> -#include <asm/arch/s400_api.h> +#include <asm/mach-imx/s400_api.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 28d5da49ff1..4603b54f598 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -330,6 +330,13 @@ config NPCM_OTP To compile this driver as a module, choose M here: the module will be called npcm_otp.

+config IMX_SENTINEL + bool "Enable i.MX Sentinel MU driver and API" + depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP) + help + If you say Y here to enable Message Unit driver to work with + Sentinel core on some NXP i.MX processors. + config NUVOTON_NCT6102D bool "Enable Nuvoton NCT6102D Super I/O driver" help diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 0bf05ca05ef..dcba39a15fc 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -50,6 +50,8 @@ obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ obj-$(CONFIG_IMX8ULP) += imx8ulp/ +obj-$(CONFIG_IMX8ULP) += imx8ulp/ +obj-$(CONFIG_IMX_SENTINEL) += sentinel/ obj-$(CONFIG_LED_STATUS) += status_led.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o diff --git a/drivers/misc/imx8ulp/Makefile b/drivers/misc/imx8ulp/Makefile index 927cc552163..450e615e645 100644 --- a/drivers/misc/imx8ulp/Makefile +++ b/drivers/misc/imx8ulp/Makefile @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+

-obj-y += s400_api.o imx8ulp_mu.o obj-$(CONFIG_CMD_FUSE) += fuse.o diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/imx8ulp/fuse.c index 090e702d9f7..83d2c25731f 100644 --- a/drivers/misc/imx8ulp/fuse.c +++ b/drivers/misc/imx8ulp/fuse.c @@ -10,7 +10,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/imx-regs.h> #include <env.h> -#include <asm/arch/s400_api.h> +#include <asm/mach-imx/s400_api.h> #include <asm/global_data.h>

DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/misc/sentinel/Makefile b/drivers/misc/sentinel/Makefile new file mode 100644 index 00000000000..3e2f623b278 --- /dev/null +++ b/drivers/misc/sentinel/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += s400_api.o s4mu.o diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/sentinel/s400_api.c similarity index 98% rename from drivers/misc/imx8ulp/s400_api.c rename to drivers/misc/sentinel/s400_api.c index 87f5880ccb8..3d791bc868e 100644 --- a/drivers/misc/imx8ulp/s400_api.c +++ b/drivers/misc/sentinel/s400_api.c @@ -9,7 +9,7 @@ #include <malloc.h> #include <asm/io.h> #include <dm.h> -#include <asm/arch/s400_api.h> +#include <asm/mach-imx/s400_api.h> #include <misc.h>

DECLARE_GLOBAL_DATA_PTR; @@ -275,8 +275,8 @@ int ahab_release_caam(u32 core_did, u32 *response) int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; int ret;

if (!dev) { diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c b/drivers/misc/sentinel/s4mu.c similarity index 98% rename from drivers/misc/imx8ulp/imx8ulp_mu.c rename to drivers/misc/sentinel/s4mu.c index 333ebdf5765..121a81060a6 100644 --- a/drivers/misc/imx8ulp/imx8ulp_mu.c +++ b/drivers/misc/sentinel/s4mu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2020 NXP + * Copyright 2020-2022 NXP */

#include <common.h> @@ -9,7 +9,7 @@ #include <dm/lists.h> #include <dm/root.h> #include <dm/device-internal.h> -#include <asm/arch/s400_api.h> +#include <asm/mach-imx/s400_api.h> #include <asm/arch/imx-regs.h> #include <linux/iopoll.h> #include <misc.h>

From: Ye Li ye.li@nxp.com

To support more RDC instances on i.MX93, update API to latest definition.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/mach-imx/s400_api.h | 2 +- drivers/misc/sentinel/s400_api.c | 21 +++++++++++++++++---- 2 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h index b3e6b3fa45d..d09c078df01 100644 --- a/arch/arm/include/asm/mach-imx/s400_api.h +++ b/arch/arm/include/asm/mach-imx/s400_api.h @@ -32,7 +32,7 @@ struct imx8ulp_s400_msg { u32 data[(S400_MAX_MSG - 1U)]; };

-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response); +int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response); int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response); int ahab_release_container(u32 *response); int ahab_verify_image(u32 img_id, u32 *response); diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c index 3d791bc868e..4e90171420f 100644 --- a/drivers/misc/sentinel/s400_api.c +++ b/drivers/misc/sentinel/s400_api.c @@ -14,7 +14,7 @@

DECLARE_GLOBAL_DATA_PTR;

-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response) +int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response) { struct udevice *dev = gd->arch.s400_dev; int size = sizeof(struct imx8ulp_s400_msg); @@ -30,10 +30,23 @@ int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response) msg.tag = AHAB_CMD_TAG; msg.size = 2; msg.command = AHAB_RELEASE_RDC_REQ_CID; - if (xrdc) - msg.data[0] = (0x78 << 8) | core_id; - else + switch (xrdc) { + case 0: msg.data[0] = (0x74 << 8) | core_id; + break; + case 1: + msg.data[0] = (0x78 << 8) | core_id; + break; + case 2: + msg.data[0] = (0x82 << 8) | core_id; + break; + case 3: + msg.data[0] = (0x86 << 8) | core_id; + break; + default: + printf("Error: wrong xrdc index %u\n", xrdc); + return -EINVAL; + }

ret = misc_call(dev, false, &msg, size, &msg, size); if (ret)

From: Peng Fan peng.fan@nxp.com

Introduce Sentinel API ahab_release_m33_trout to make sure sentinel release M33 trout and make sure M33 could boot.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/mach-imx/s400_api.h | 1 + drivers/misc/sentinel/s400_api.c | 25 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+)

diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h index d95f8227b29..dc176e1f619 100644 --- a/arch/arm/include/asm/mach-imx/s400_api.h +++ b/arch/arm/include/asm/mach-imx/s400_api.h @@ -55,5 +55,6 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); int ahab_dump_buffer(u32 *buffer, u32 buffer_length); int ahab_get_info(struct sentinel_get_info_data *info, u32 *response); int ahab_get_fw_status(u32 *status, u32 *response); +int ahab_release_m33_trout(void);

#endif diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c index ca7903670ed..01a673e5e13 100644 --- a/drivers/misc/sentinel/s400_api.c +++ b/drivers/misc/sentinel/s400_api.c @@ -420,3 +420,28 @@ int ahab_get_fw_status(u32 *status, u32 *response)

return ret; } + +int ahab_release_m33_trout(void) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 1; + msg.command = 0xd3; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + return ret; +}

From: Ye Li ye.li@nxp.com

Add AHAB driver for iMX9 to do authentication by calling sentinel API

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/Kconfig | 5 + arch/arm/mach-imx/imx9/Makefile | 1 + arch/arm/mach-imx/imx9/ahab.c | 346 ++++++++++++++++++++++++++++++++ 3 files changed, 352 insertions(+) create mode 100644 arch/arm/mach-imx/imx9/ahab.c

diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index ce58e41428f..dae9f658e65 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -1,5 +1,10 @@ if ARCH_IMX9

+config AHAB_BOOT + bool "Support i.MX9 AHAB features" + help + This option enables the support for AHAB secure boot. + config IMX9 bool select HAS_CAAM diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile index 0124212f266..41a22500c95 100644 --- a/arch/arm/mach-imx/imx9/Makefile +++ b/arch/arm/mach-imx/imx9/Makefile @@ -4,3 +4,4 @@

obj-y += lowlevel_init.o obj-y += soc.o clock.o clock_root.o trdc.o +obj-$(CONFIG_AHAB_BOOT) += ahab.o diff --git a/arch/arm/mach-imx/imx9/ahab.c b/arch/arm/mach-imx/imx9/ahab.c new file mode 100644 index 00000000000..6aa949619b5 --- /dev/null +++ b/arch/arm/mach-imx/imx9/ahab.c @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <command.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/mach-imx/s400_api.h> +#include <asm/mach-imx/sys_proto.h> +#include <asm/arch-imx/cpu.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/image.h> +#include <console.h> +#include <cpu_func.h> +#include <asm/mach-imx/ahab.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define IMG_CONTAINER_BASE (0x80000000UL) +#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL) + +#define AHAB_NO_AUTHENTICATION_IND 0xee +#define AHAB_BAD_KEY_HASH_IND 0xfa +#define AHAB_INVALID_KEY_IND 0xf9 +#define AHAB_BAD_SIGNATURE_IND 0xf0 +#define AHAB_BAD_HASH_IND 0xf1 + +static void display_ahab_auth_ind(u32 event) +{ + u8 resp_ind = (event >> 8) & 0xff; + + switch (resp_ind) { + case AHAB_NO_AUTHENTICATION_IND: + printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind); + break; + case AHAB_BAD_KEY_HASH_IND: + printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind); + break; + case AHAB_INVALID_KEY_IND: + printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind); + break; + case AHAB_BAD_SIGNATURE_IND: + printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind); + break; + case AHAB_BAD_HASH_IND: + printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind); + break; + default: + printf("Unknown Indicator (0x%02X)\n\n", resp_ind); + break; + } +} + +int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) +{ + int err; + u32 resp; + + memcpy((void *)IMG_CONTAINER_BASE, (const void *)container, + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); + + flush_dcache_range(IMG_CONTAINER_BASE, + IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1); + + err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp); + if (err) { + printf("Authenticate container hdr failed, return %d, resp 0x%x\n", + err, resp); + display_ahab_auth_ind(resp); + } + + return err; +} + +int ahab_auth_release(void) +{ + int err; + u32 resp; + + err = ahab_release_container(&resp); + if (err) { + printf("Error: release container failed, resp 0x%x!\n", resp); + display_ahab_auth_ind(resp); + } + + return err; +} + +int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) +{ + int err; + u32 resp; + + err = ahab_verify_image(image_index, &resp); + if (err) { + printf("Authenticate img %d failed, return %d, resp 0x%x\n", + image_index, err, resp); + display_ahab_auth_ind(resp); + + return -EIO; + } + + return 0; +} + +static inline bool check_in_dram(ulong addr) +{ + int i; + struct bd_info *bd = gd->bd; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { + if (bd->bi_dram[i].size) { + if (addr >= bd->bi_dram[i].start && + addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + return true; + } + } + + return false; +} + +int authenticate_os_container(ulong addr) +{ + struct container_hdr *phdr; + int i, ret = 0; + int err; + u16 length; + struct boot_img_t *img; + unsigned long s, e; + + if (addr % 4) { + puts("Error: Image's address is not 4 byte aligned\n"); + return -EINVAL; + } + + if (!check_in_dram(addr)) { + puts("Error: Image's address is invalid\n"); + return -EINVAL; + } + + phdr = (struct container_hdr *)addr; + if (phdr->tag != 0x87 || phdr->version != 0x0) { + printf("Error: Wrong container header\n"); + return -EFAULT; + } + + if (!phdr->num_images) { + printf("Error: Wrong container, no image found\n"); + return -EFAULT; + } + + length = phdr->length_lsb + (phdr->length_msb << 8); + + debug("container length %u\n", length); + + err = ahab_auth_cntr_hdr(phdr, length); + if (err) { + ret = -EIO; + goto exit; + } + + debug("Verify images\n"); + + /* Copy images to dest address */ + for (i = 0; i < phdr->num_images; i++) { + img = (struct boot_img_t *)(addr + + sizeof(struct container_hdr) + + i * sizeof(struct boot_img_t)); + + debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n", + i, (uint32_t)img->dst, img->offset + addr, img->size); + + memcpy((void *)img->dst, (const void *)(img->offset + addr), + img->size); + + s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1; + + flush_dcache_range(s, e); + + ret = ahab_verify_cntr_image(img, i); + if (ret) + goto exit; + } + +exit: + debug("ahab_auth_release, 0x%x\n", ret); + ahab_auth_release(); + + return ret; +} + +static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + + printf("Authenticate OS container at 0x%lx\n", addr); + + if (authenticate_os_container(addr)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static void display_life_cycle(u32 lc) +{ + printf("Lifecycle: 0x%08X, ", lc); + switch (lc) { + case 0x1: + printf("BLANK\n\n"); + break; + case 0x2: + printf("FAB\n\n"); + break; + case 0x4: + printf("NXP Provisioned\n\n"); + break; + case 0x8: + printf("OEM Open\n\n"); + break; + case 0x10: + printf("OEM Secure World Closed\n\n"); + break; + case 0x20: + printf("OEM closed\n\n"); + break; + case 0x40: + printf("Field Return OEM\n\n"); + break; + case 0x80: + printf("Field Return NXP\n\n"); + break; + case 0x100: + printf("OEM Locked\n\n"); + break; + case 0x200: + printf("BRICKED\n\n"); + break; + default: + printf("Unknown\n\n"); + break; + } +} + +static int confirm_close(void) +{ + puts("Warning: Please ensure your sample is in NXP closed state, " + "OEM SRK hash has been fused, \n" + " and you are able to boot a signed image successfully " + "without any SECO events reported.\n" + " If not, your sample will be unrecoverable.\n" + "\nReally perform this operation? <y/N>\n"); + + if (confirm_yesno()) + return 1; + + puts("Ahab close aborted\n"); + return 0; +} + +static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int err; + u32 resp; + + if (!confirm_close()) + return -EACCES; + + err = ahab_forward_lifecycle(8, &resp); + if (err != 0) { + printf("Error in forward lifecycle to OEM closed\n"); + return -EIO; + } + + printf("Change to OEM closed successfully\n"); + + return 0; +} + +int ahab_dump(void) +{ + u32 buffer[32]; + int ret, i = 0; + + do { + ret = ahab_dump_buffer(buffer, 32); + if (ret < 0) { + printf("Error in dump AHAB log\n"); + return -EIO; + } + + if (ret == 1) + break; + for (i = 0; i < ret; i++) + printf("0x%x\n", buffer[i]); + } while (ret >= 21); + + return 0; +} + +static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + return ahab_dump(); +} + +static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + u32 lc; + + lc = readl(FSB_BASE_ADDR + 0x41c); + lc &= 0x3ff; + + display_life_cycle(lc); + return 0; +} + +U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, + "autenticate OS container via AHAB", + "addr\n" + "addr - OS container hex address\n" +); + +U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close, + "Change AHAB lifecycle to OEM closed", + "" +); + +U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump, + "Dump AHAB log for debug", + "" +); + +U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status, + "display AHAB lifecycle only", + "" +);

From: Ye Li ye.li@nxp.com

Use more generic name for S40x msg structure

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/mach-imx/s400_api.h | 2 +- arch/arm/mach-imx/imx8ulp/rdc.c | 2 +- arch/arm/mach-imx/imx9/trdc.c | 2 +- drivers/misc/sentinel/s400_api.c | 44 ++++++++++++------------ drivers/misc/sentinel/s4mu.c | 6 ++-- 5 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h index dc176e1f619..89fa373d06f 100644 --- a/arch/arm/include/asm/mach-imx/s400_api.h +++ b/arch/arm/include/asm/mach-imx/s400_api.h @@ -26,7 +26,7 @@

#define S400_MAX_MSG 255U

-struct imx8ulp_s400_msg { +struct sentinel_msg { u8 version; u8 size; u8 command; diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index cc47079d8f5..e24eeff8a20 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -184,7 +184,7 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm) int release_rdc(enum rdc_type type) { ulong s_mu_base = 0x27020000UL; - struct imx8ulp_s400_msg msg; + struct sentinel_msg msg; int ret; u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;

diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c index b0881697a10..3f37ce712c0 100644 --- a/arch/arm/mach-imx/imx9/trdc.c +++ b/arch/arm/mach-imx/imx9/trdc.c @@ -315,7 +315,7 @@ bool trdc_mbc_enabled(ulong trdc_base) int release_rdc(u8 xrdc) { ulong s_mu_base = 0x47520000UL; - struct imx8ulp_s400_msg msg; + struct sentinel_msg msg; int ret; u32 rdc_id;

diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c index 01a673e5e13..65032f77362 100644 --- a/drivers/misc/sentinel/s400_api.c +++ b/drivers/misc/sentinel/s400_api.c @@ -17,8 +17,8 @@ DECLARE_GLOBAL_DATA_PTR; int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; int ret;

if (!dev) { @@ -62,8 +62,8 @@ int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response) int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; int ret;

if (!dev) { @@ -92,8 +92,8 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response) int ahab_release_container(u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; int ret;

if (!dev) { @@ -120,8 +120,8 @@ int ahab_release_container(u32 *response) int ahab_verify_image(u32 img_id, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; int ret;

if (!dev) { @@ -149,8 +149,8 @@ int ahab_verify_image(u32 img_id, u32 *response) int ahab_forward_lifecycle(u16 life_cycle, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; int ret;

if (!dev) { @@ -178,8 +178,8 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response) int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; int ret;

if (!dev) { @@ -226,8 +226,8 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respo int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; int ret;

if (!dev) { @@ -259,8 +259,8 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) int ahab_release_caam(u32 core_did, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; int ret;

if (!dev) { @@ -329,8 +329,8 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response) int ahab_dump_buffer(u32 *buffer, u32 buffer_length) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; int ret, i = 0;

if (!dev) { @@ -363,8 +363,8 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length) int ahab_get_info(struct sentinel_get_info_data *info, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; int ret;

if (!dev) { @@ -394,8 +394,8 @@ int ahab_get_info(struct sentinel_get_info_data *info, u32 *response) int ahab_get_fw_status(u32 *status, u32 *response) { struct udevice *dev = gd->arch.s400_dev; - int size = sizeof(struct imx8ulp_s400_msg); - struct imx8ulp_s400_msg msg; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; int ret;

if (!dev) { diff --git a/drivers/misc/sentinel/s4mu.c b/drivers/misc/sentinel/s4mu.c index 18aea27105e..794fc40c620 100644 --- a/drivers/misc/sentinel/s4mu.c +++ b/drivers/misc/sentinel/s4mu.c @@ -85,7 +85,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)

static int imx8ulp_mu_read(struct mu_type *base, void *data) { - struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data; + struct sentinel_msg *msg = (struct sentinel_msg *)data; int ret; u8 count = 0;

@@ -118,7 +118,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data)

static int imx8ulp_mu_write(struct mu_type *base, void *data) { - struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data; + struct sentinel_msg *msg = (struct sentinel_msg *)data; int ret; u8 count = 0;

@@ -171,7 +171,7 @@ static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg, return ret; }

- result = ((struct imx8ulp_s400_msg *)rx_msg)->data[0]; + result = ((struct sentinel_msg *)rx_msg)->data[0]; if ((result & 0xff) == 0xd6) return 0;

From: Alice Guo alice.guo@nxp.com

i.MX93 fuse can be accessed through FSB and s400-api. Add mapping tables for i.MX93. The offset address of FSB accessing OTP shadow registers is different between i.MX8ULP and i.MX93, so use macro to define the offset address instead of hardcode.

Signed-off-by: Alice Guo alice.guo@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx9/imx-regs.h | 2 ++ drivers/misc/sentinel/fuse.c | 30 ++++++++++++++++++++++- 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h index 7b84b970b75..fa6951ebbe8 100644 --- a/arch/arm/include/asm/arch-imx9/imx-regs.h +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -19,6 +19,8 @@ #define WDG4_BASE_ADDR 0x424a0000UL #define WDG5_BASE_ADDR 0x424b0000UL

+#define FSB_BASE_ADDR 0x47510000UL + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> #include <stdbool.h> diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c index 83d2c25731f..abb4c072f9b 100644 --- a/drivers/misc/sentinel/fuse.c +++ b/drivers/misc/sentinel/fuse.c @@ -31,6 +31,9 @@ struct s400_map_entry { u32 s400_index; };

+#if defined(CONFIG_IMX8ULP) +#define FSB_OTP_SHADOW 0x800 + struct fsb_map_entry fsb_mapping_table[] = { { 3, 8 }, { 4, 8 }, @@ -65,6 +68,31 @@ struct s400_map_entry s400_api_mapping_table[] = { { 23, 1, 4, 2 }, /* OTFAD */ { 25, 8 }, /* Test config2 */ }; +#elif defined(CONFIG_ARCH_IMX9) +#define FSB_OTP_SHADOW 0x8000 + +struct fsb_map_entry fsb_mapping_table[] = { + { 0, 8 }, + { 1, 8 }, + { 2, 8 }, + { -1, 8 }, + { 4, 8 }, + { 5, 8 }, + { 6, 8 }, /* UID */ + { -1, 8 }, + { 8, 8 }, + { 9, 8 }, + { 10, 8 }, +}; + +struct s400_map_entry s400_api_mapping_table[] = { + { 3, 11 }, /* 24 .. 34 */ + { 7, 8 }, + { 16, 11 }, /* 128 .. 143 */ + { 22, 8 }, + { 23, 8 }, +}; +#endif

static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy) { @@ -128,7 +156,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val)

word_index = map_fsb_fuse_index(bank, word, &redundancy); if (word_index >= 0) { - *val = readl((ulong)FSB_BASE_ADDR + 0x800 + (word_index << 2)); + *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2)); if (redundancy) *val = (*val >> ((word % 2) * 16)) & 0xFFFF;

From: Ye Li ye.li@nxp.com

Add GPIO registers structure for iMX93, so that we can enable lpgpio driver

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/Kconfig | 1 + arch/arm/include/asm/arch-imx9/gpio.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 29b831422ff..7dcf5614e9b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -933,6 +933,7 @@ config ARCH_IMX9 select DM select MACH_IMX select SUPPORT_SPL + select GPIO_EXTRA_HEADER select MISC select IMX_SENTINEL imply CMD_DM diff --git a/arch/arm/include/asm/arch-imx9/gpio.h b/arch/arm/include/asm/arch-imx9/gpio.h index e69de29bb2d..40732022e7e 100644 --- a/arch/arm/include/asm/arch-imx9/gpio.h +++ b/arch/arm/include/asm/arch-imx9/gpio.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_GPIO_H +#define __ASM_ARCH_IMX9_GPIO_H + +struct gpio_regs { + u32 gpio_pdor; + u32 gpio_psor; + u32 gpio_pcor; + u32 gpio_ptor; + u32 gpio_pdir; + u32 gpio_pddr; + u32 gpio_pidr; + u8 gpio_pxdr[32]; +}; + +#endif

From: Peng Fan peng.fan@nxp.com

To support on-demand booting M33 image from A core. SPL needs to follow M33 kick up sequence to release M33 firstly, then set M33 CPUWAIT signal. ATF will clear CPUWAIT to kick M33 to run.

The prepare function also works around the M33 TCM ECC issue by clean the TCM. Also enable sentinel handshake and WDOG1 clock for M33 stop and reset.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx9/sys_proto.h | 2 + arch/arm/mach-imx/imx9/soc.c | 51 ++++++++++++++++++++++ 2 files changed, 53 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h index 5ae7a043398..ba97f92f5ae 100644 --- a/arch/arm/include/asm/arch-imx9/sys_proto.h +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -9,4 +9,6 @@ #include <asm/mach-imx/sys_proto.h>

void soc_power_init(void); +bool m33_is_rom_kicked(void); +int m33_prepare(void); #endif diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 68f3ddd4287..2a29454d1eb 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -13,6 +13,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/ccm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/arch/trdc.h> #include <asm/mach-imx/boot_mode.h> @@ -378,3 +379,53 @@ void soc_power_init(void)

disable_isolation(); } + +static bool m33_is_rom_kicked(void) +{ + struct blk_ctrl_s_aonmix_regs *s_regs = + (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR; + + if (!(readl(&s_regs->m33_cfg) & BIT(2))) + return true; + + return false; +} + +int m33_prepare(void) +{ + struct src_mix_slice_regs *mix_regs = + (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400 * (SRC_MIX_CM33 + 1)); + struct src_general_regs *global_regs = + (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE; + struct blk_ctrl_s_aonmix_regs *s_regs = + (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR; + u32 val; + + if (m33_is_rom_kicked()) + return -EPERM; + + /* Release reset of M33 */ + setbits_le32(&global_regs->scr, BIT(0)); + + /* Check the reset released in M33 MIX func stat */ + val = readl(&mix_regs->func_stat); + while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT)) + val = readl(&mix_regs->func_stat); + + /* Release Sentinel TROUT */ + ahab_release_m33_trout(); + + /* Mask WDOG1 IRQ from A55, we use it for M33 reset */ + setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6)); + + /* Turn on WDOG1 clock */ + ccm_lpcg_on(CCGR_WDG1, 1); + + /* Set sentinel LP handshake for M33 reset */ + setbits_le32(&s_regs->lp_handshake[0], BIT(6)); + + /* Clear M33 TCM for ECC */ + memset((void *)(ulong)0x201e0000, 0, 0x40000); + + return 0; +}

From: Ye Li ye.li@nxp.com

Select env storages according to boot device at runtime

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/soc.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index ca88271564c..797d7a802ba 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -288,6 +288,40 @@ int timer_init(void) return 0; }

+enum env_location env_get_location(enum env_operation op, int prio) +{ + enum boot_device dev = get_boot_device(); + enum env_location env_loc = ENVL_UNKNOWN; + + if (prio) + return env_loc; + + switch (dev) { +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) + case QSPI_BOOT: + env_loc = ENVL_SPI_FLASH; + break; +#endif +#if defined(CONFIG_ENV_IS_IN_MMC) + case SD1_BOOT: + case SD2_BOOT: + case SD3_BOOT: + case MMC1_BOOT: + case MMC2_BOOT: + case MMC3_BOOT: + env_loc = ENVL_MMC; + break; +#endif + default: +#if defined(CONFIG_ENV_IS_NOWHERE) + env_loc = ENVL_NOWHERE; +#endif + break; + } + + return env_loc; +} + static int mix_power_init(enum mix_power_domain pd) { enum src_mix_slice_id mix_id;

From: Ye Li ye.li@nxp.com

Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M.

The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx8m/ddr.h | 6 +- arch/arm/include/asm/arch-imx9/ddr.h | 126 +++++ drivers/Makefile | 1 + drivers/ddr/imx/Kconfig | 2 + drivers/ddr/imx/imx8m/Kconfig | 1 + drivers/ddr/imx/imx8m/Makefile | 3 +- drivers/ddr/imx/imx8m/ddr_init.c | 219 ++++++++ drivers/ddr/imx/imx9/Kconfig | 21 + drivers/ddr/imx/imx9/Makefile | 10 + drivers/ddr/imx/imx9/ddr_init.c | 485 ++++++++++++++++++ drivers/ddr/imx/phy/Kconfig | 4 + drivers/ddr/imx/phy/Makefile | 9 + drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c | 0 drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c | 1 - drivers/ddr/imx/phy/ddrphy_utils.c | 169 ++++++ drivers/ddr/imx/{imx8m => phy}/helper.c | 45 +- 16 files changed, 1077 insertions(+), 25 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx9/ddr.h create mode 100644 drivers/ddr/imx/imx9/Kconfig create mode 100644 drivers/ddr/imx/imx9/Makefile create mode 100644 drivers/ddr/imx/imx9/ddr_init.c create mode 100644 drivers/ddr/imx/phy/Kconfig create mode 100644 drivers/ddr/imx/phy/Makefile rename drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c (100%) rename drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c (98%) create mode 100644 drivers/ddr/imx/phy/ddrphy_utils.c rename drivers/ddr/imx/{imx8m => phy}/helper.c (79%)

diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index 2ce8a8f2d41..2f76e7d69b9 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -725,6 +725,8 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num); void get_trained_CDD(unsigned int fsp); unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr);

+ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr); + static inline void reg32_write(unsigned long addr, u32 val) { writel(val, addr); @@ -741,9 +743,9 @@ static inline void reg32setbit(unsigned long addr, u32 bit) }

#define dwc_ddrphy_apb_wr(addr, data) \ - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data) + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data) #define dwc_ddrphy_apb_rd(addr) \ - reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr)) + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))

extern struct dram_cfg_param ddrphy_trained_csr[]; extern uint32_t ddrphy_trained_csr_num; diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h new file mode 100644 index 00000000000..62e6f7dda53 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX8M_DDR_H +#define __ASM_ARCH_IMX8M_DDR_H + +#include <asm/io.h> +#include <asm/types.h> + +#define DDR_CTL_BASE 0x4E300000 +#define DDR_PHY_BASE 0x4E100000 +#define DDRMIX_BLK_CTRL_BASE 0x4E010000 + +#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24) +#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110) +#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48) + +#define SRC_BASE_ADDR (0x44460000) +#define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400) +#define REG_SRC_DPHY_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x20) +#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x24) + +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (DDR_PHY_BASE + ((X) * 0x2000000)) +#define DDRPHY_MEM(X) (DDR_PHY_BASE + ((X) * 0x2000000) + 0x50000) + +/* PHY State */ +enum pstate { + PS0, + PS1, + PS2, + PS3, +}; + +enum msg_response { + TRAIN_SUCCESS = 0x7, + TRAIN_STREAM_START = 0x8, + TRAIN_FAIL = 0xff, +}; + +/* user data type */ +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_fsp_msg { + unsigned int drate; + enum fw_type fw_type; + struct dram_cfg_param *fsp_cfg; + unsigned int fsp_cfg_num; +}; + +struct dram_timing_info { + /* umctl2 config */ + struct dram_cfg_param *ddrc_cfg; + unsigned int ddrc_cfg_num; + /* ddrphy config */ + struct dram_cfg_param *ddrphy_cfg; + unsigned int ddrphy_cfg_num; + /* ddr fsp train info */ + struct dram_fsp_msg *fsp_msg; + unsigned int fsp_msg_num; + /* ddr phy trained CSR */ + struct dram_cfg_param *ddrphy_trained_csr; + unsigned int ddrphy_trained_csr_num; + /* ddr phy PIE */ + struct dram_cfg_param *ddrphy_pie; + unsigned int ddrphy_pie_num; + /* initialized drate table */ + unsigned int fsp_table[4]; +}; + +extern struct dram_timing_info dram_timing; + +void ddr_load_train_firmware(enum fw_type type); +int ddr_init(struct dram_timing_info *timing_info); +int ddr_cfg_phy(struct dram_timing_info *timing_info); +void load_lpddr4_phy_pie(void); +void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); +void dram_config_save(struct dram_timing_info *info, unsigned long base); +void board_dram_ecc_scrub(void); +void ddrc_inline_ecc_scrub(unsigned int start_address, + unsigned int range_address); +void ddrc_inline_ecc_scrub_end(unsigned int start_address, + unsigned int range_address); + +/* utils function for ddr phy training */ +int wait_ddrphy_training_complete(void); +void ddrphy_init_set_dfi_clk(unsigned int drate); +void ddrphy_init_read_msg_block(enum fw_type type); + +void get_trained_CDD(unsigned int fsp); + +ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr); + +static inline void reg32_write(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline u32 reg32_read(unsigned long addr) +{ + return readl(addr); +} + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} + +#define dwc_ddrphy_apb_wr(addr, data) \ + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data) +#define dwc_ddrphy_apb_rd(addr) \ + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr)) + +extern struct dram_cfg_param ddrphy_trained_csr[]; +extern u32 ddrphy_trained_csr_num; + +#endif diff --git a/drivers/Makefile b/drivers/Makefile index d63fd1c04d1..eba9940231f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/ obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/ +obj-$(CONFIG_ARCH_IMX9) += ddr/imx/imx9/ obj-$(CONFIG_SPL_DM_RESET) += reset/ obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/ diff --git a/drivers/ddr/imx/Kconfig b/drivers/ddr/imx/Kconfig index 179f34530d7..328fbabb6db 100644 --- a/drivers/ddr/imx/Kconfig +++ b/drivers/ddr/imx/Kconfig @@ -1,2 +1,4 @@ source "drivers/ddr/imx/imx8m/Kconfig" source "drivers/ddr/imx/imx8ulp/Kconfig" +source "drivers/ddr/imx/imx9/Kconfig" +source "drivers/ddr/imx/phy/Kconfig" diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig index a90b7db4940..08b6787a543 100644 --- a/drivers/ddr/imx/imx8m/Kconfig +++ b/drivers/ddr/imx/imx8m/Kconfig @@ -3,6 +3,7 @@ menu "i.MX8M DDR controllers"

config IMX8M_DRAM bool "imx8m dram" + select IMX_SNPS_DDR_PHY

config IMX8M_LPDDR4 bool "imx8m lpddr4" diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile index bd9bcb8d53b..aed91dc23f4 100644 --- a/drivers/ddr/imx/imx8m/Makefile +++ b/drivers/ddr/imx/imx8m/Makefile @@ -5,5 +5,6 @@ #

ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o ddr_init.o +obj-$(CONFIG_IMX8M_DRAM) += ddr_init.o +obj-y += ../phy/ endif diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index b70bcc383fa..d964184ddc8 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -11,6 +11,11 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h>

+static unsigned int g_cdd_rr_max[4]; +static unsigned int g_cdd_rw_max[4]; +static unsigned int g_cdd_wr_max[4]; +static unsigned int g_cdd_ww_max[4]; + void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) { int i = 0; @@ -91,6 +96,215 @@ void __weak board_dram_ecc_scrub(void) { }

+void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr, + unsigned int mr_data) +{ + unsigned int tmp; + /* + * 1. Poll MRSTAT.mr_wr_busy until it is 0. + * This checks that there is no outstanding MR transaction. + * No writes should be performed to MRCTRL0 and MRCTRL1 if + * MRSTAT.mr_wr_busy = 1. + */ + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + /* + * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and + * (for MRWs) MRCTRL1.mr_data to define the MR transaction. + */ + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4)); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data); + reg32setbit(DDRC_MRCTRL0(0), 31); +} + +unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) +{ + unsigned int tmp; + + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1); + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8)); + reg32setbit(DDRC_MRCTRL0(0), 31); + do { + tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); + } while ((tmp & 0x8) == 0); + tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); + tmp = tmp & 0xff; + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); + + return tmp; +} + +static unsigned int look_for_max(unsigned int data[], unsigned int addr_start, + unsigned int addr_end) +{ + unsigned int i, imax = 0; + + for (i = addr_start; i <= addr_end; i++) { + if (((data[i] >> 7) == 0) && data[i] > imax) + imax = data[i]; + } + + return imax; +} + +void get_trained_CDD(u32 fsp) +{ + unsigned int i, ddr_type, tmp; + unsigned int cdd_cha[12], cdd_chb[12]; + unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max; + unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max; + + ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; + if (ddr_type == 0x20) { + for (i = 0; i < 6; i++) { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54013 + i) * 4); + cdd_cha[i * 2] = tmp & 0xff; + cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff; + } + + for (i = 0; i < 7; i++) { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x5402c + i) * 4); + if (i == 0) { + cdd_cha[0] = (tmp >> 8) & 0xff; + } else if (i == 6) { + cdd_cha[11] = tmp & 0xff; + } else { + cdd_chb[i * 2 - 1] = tmp & 0xff; + cdd_chb[i * 2] = (tmp >> 8) & 0xff; + } + } + + cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1); + cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5); + cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9); + cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11); + cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1); + cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5); + cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9); + cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11); + g_cdd_rr_max[fsp] = + cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max; + g_cdd_rw_max[fsp] = + cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max; + g_cdd_wr_max[fsp] = + cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max; + g_cdd_ww_max[fsp] = + cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max; + } else { + unsigned int ddr4_cdd[64]; + + for (i = 0; i < 29; i++) { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4); + ddr4_cdd[i * 2] = tmp & 0xff; + ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff; + } + + g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12); + g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24); + g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40); + g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56); + } +} + +void update_umctl2_rank_space_setting(unsigned int pstat_num) +{ + unsigned int i, ddr_type; + unsigned int addr_slot, rdata, tmp, tmp_t; + unsigned int ddrc_w2r, ddrc_r2w, ddrc_wr_gap, ddrc_rd_gap; + + ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f; + for (i = 0; i < pstat_num; i++) { + addr_slot = i ? (i + 1) * 0x1000 : 0; + if (ddr_type == 0x20) { + /* update r2w:[13:8], w2r:[5:0] */ + rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot); + ddrc_w2r = rdata & 0x3f; + if (is_imx8mp()) + tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1); + else + tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1; + ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp; + + ddrc_r2w = (rdata >> 8) & 0x3f; + if (is_imx8mp()) + tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1); + else + tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1; + ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp; + + tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r; + reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t); + } else { + /* update w2r:[5:0] */ + rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot); + ddrc_w2r = rdata & 0x3f; + if (is_imx8mp()) + tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1); + else + tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1; + ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp; + tmp_t = (rdata & 0xffffffc0) | ddrc_w2r; + reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t); + + /* update r2w:[13:8] */ + rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot); + ddrc_r2w = (rdata >> 8) & 0x3f; + if (is_imx8mp()) + tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1); + else + tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1; + ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp; + + tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8); + reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t); + } + + if (!is_imx8mq()) { + /* + * update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) + */ + rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot); + ddrc_wr_gap = (rdata >> 8) & 0xf; + if (is_imx8mp()) + tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1); + else + tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1; + ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp; + + ddrc_rd_gap = (rdata >> 4) & 0xf; + if (is_imx8mp()) + tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1); + else + tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1; + ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp; + + tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4); + reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t); + } + } + + if (is_imx8mq()) { + /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */ + rdata = reg32_read(DDRC_RANKCTL(0)); + ddrc_wr_gap = (rdata >> 8) & 0xf; + tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1; + ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp; + + ddrc_rd_gap = (rdata >> 4) & 0xf; + tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1; + ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp; + + tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4); + reg32_write(DDRC_RANKCTL(0), tmp_t); + } +} + int ddr_init(struct dram_timing_info *dram_timing) { unsigned int tmp, initial_drate, target_freq; @@ -250,3 +464,8 @@ int ddr_init(struct dram_timing_info *dram_timing)

return 0; } + +ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr) +{ + return 4 * paddr_apb_from_ctlr; +} diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig new file mode 100644 index 00000000000..a16ddc65e01 --- /dev/null +++ b/drivers/ddr/imx/imx9/Kconfig @@ -0,0 +1,21 @@ +menu "i.MX9 DDR controllers" + depends on ARCH_IMX9 + +config IMX9_DRAM + bool "imx9 dram" + select IMX_SNPS_DDR_PHY + +config IMX9_LPDDR4X + bool "imx9 lpddr4 and lpddr4x" + select IMX9_DRAM + help + Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC. + +config SAVED_DRAM_TIMING_BASE + hex "Define the base address for saved dram timing" + help + after DRAM is trained, need to save the dram related timming + info into memory for low power use. + default 0x204DC000 + +endmenu diff --git a/drivers/ddr/imx/imx9/Makefile b/drivers/ddr/imx/imx9/Makefile new file mode 100644 index 00000000000..9403f988b32 --- /dev/null +++ b/drivers/ddr/imx/imx9/Makefile @@ -0,0 +1,10 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX9_DRAM) += ddr_init.o +obj-y += ../phy/ +endif diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c new file mode 100644 index 00000000000..16eac65105f --- /dev/null +++ b/drivers/ddr/imx/imx9/ddr_init.c @@ -0,0 +1,485 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include <common.h> +#include <errno.h> +#include <log.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <linux/delay.h> + +void ddrphy_coldreset(void) +{ + /* dramphy_apb_n default 1 , assert -> 0, de_assert -> 1 */ + /* dramphy_reset_n default 0 , assert -> 0, de_assert -> 1 */ + /* dramphy_PwrOKIn default 0 , assert -> 1, de_assert -> 0 */ + + /* src_gen_dphy_apb_sw_rst_de_assert */ + clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0)); + /* src_gen_dphy_sw_rst_de_assert */ + clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2)); + /* src_gen_dphy_PwrOKIn_sw_rst_de_assert() */ + setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0)); + mdelay(10); + + /* src_gen_dphy_apb_sw_rst_assert */ + setbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0)); + /* src_gen_dphy_sw_rst_assert */ + setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2)); + mdelay(10); + /* src_gen_dphy_PwrOKIn_sw_rst_assert */ + clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0)); + mdelay(10); + + /* src_gen_dphy_apb_sw_rst_de_assert */ + clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0)); + /* src_gen_dphy_sw_rst_de_assert() */ + clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2)); +} + +void check_ddrc_idle(void) +{ + u32 regval; + + do { + regval = readl(REG_DDRDSR_2); + if (regval & BIT(31)) + break; + } while (1); +} + +void check_dfi_init_complete(void) +{ + u32 regval; + + do { + regval = readl(REG_DDRDSR_2); + if (regval & BIT(2)) + break; + } while (1); + setbits_le32(REG_DDRDSR_2, BIT(2)); +} + +void ddrc_config(struct dram_cfg_param *ddrc_config, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + writel(ddrc_config->val, (ulong)ddrc_config->reg); + ddrc_config++; + } +} + +void get_trained_CDD(u32 fsp) +{ +} + +int ddr_init(struct dram_timing_info *dram_timing) +{ + unsigned int initial_drate; + int ret; + u32 regval; + + debug("DDRINFO: start DRAM init\n"); + + /* reset ddrphy */ + ddrphy_coldreset(); + + debug("DDRINFO: cfg clk\n"); + + initial_drate = dram_timing->fsp_msg[0].drate; + /* default to the frequency point 0 clock */ + ddrphy_init_set_dfi_clk(initial_drate); + + /* + * Start PHY initialization and training by + * accessing relevant PUB registers + */ + debug("DDRINFO:ddrphy config start\n"); + + ret = ddr_cfg_phy(dram_timing); + if (ret) + return ret; + + debug("DDRINFO: ddrphy config done\n"); + + /* rogram the ddrc registers */ + debug("DDRINFO: ddrc config start\n"); + ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + debug("DDRINFO: ddrc config done\n"); + + check_dfi_init_complete(); + + regval = readl(REG_DDR_SDRAM_CFG); + writel((regval | 0x80000000), REG_DDR_SDRAM_CFG); + + check_ddrc_idle(); + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); + + return 0; +} + +ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr) +{ + u32 paddr_apb_qual; + u32 paddr_apb_unqual_dec_22_13; + u32 paddr_apb_unqual_dec_19_13; + u32 paddr_apb_unqual_dec_12_1; + u32 paddr_apb_unqual; + u32 paddr_apb_phy; + + paddr_apb_qual = (paddr_apb_from_ctlr << 1); + paddr_apb_unqual_dec_22_13 = ((paddr_apb_qual & 0x7fe000) >> 13); + paddr_apb_unqual_dec_12_1 = ((paddr_apb_qual & 0x1ffe) >> 1); + + switch (paddr_apb_unqual_dec_22_13) { + case 0x000: + paddr_apb_unqual_dec_19_13 = 0x00; + break; + case 0x001: + paddr_apb_unqual_dec_19_13 = 0x01; + break; + case 0x002: + paddr_apb_unqual_dec_19_13 = 0x02; + break; + case 0x003: + paddr_apb_unqual_dec_19_13 = 0x03; + break; + case 0x004: + paddr_apb_unqual_dec_19_13 = 0x04; + break; + case 0x005: + paddr_apb_unqual_dec_19_13 = 0x05; + break; + case 0x006: + paddr_apb_unqual_dec_19_13 = 0x06; + break; + case 0x007: + paddr_apb_unqual_dec_19_13 = 0x07; + break; + case 0x008: + paddr_apb_unqual_dec_19_13 = 0x08; + break; + case 0x009: + paddr_apb_unqual_dec_19_13 = 0x09; + break; + case 0x00a: + paddr_apb_unqual_dec_19_13 = 0x0a; + break; + case 0x00b: + paddr_apb_unqual_dec_19_13 = 0x0b; + break; + case 0x100: + paddr_apb_unqual_dec_19_13 = 0x0c; + break; + case 0x101: + paddr_apb_unqual_dec_19_13 = 0x0d; + break; + case 0x102: + paddr_apb_unqual_dec_19_13 = 0x0e; + break; + case 0x103: + paddr_apb_unqual_dec_19_13 = 0x0f; + break; + case 0x104: + paddr_apb_unqual_dec_19_13 = 0x10; + break; + case 0x105: + paddr_apb_unqual_dec_19_13 = 0x11; + break; + case 0x106: + paddr_apb_unqual_dec_19_13 = 0x12; + break; + case 0x107: + paddr_apb_unqual_dec_19_13 = 0x13; + break; + case 0x108: + paddr_apb_unqual_dec_19_13 = 0x14; + break; + case 0x109: + paddr_apb_unqual_dec_19_13 = 0x15; + break; + case 0x10a: + paddr_apb_unqual_dec_19_13 = 0x16; + break; + case 0x10b: + paddr_apb_unqual_dec_19_13 = 0x17; + break; + case 0x200: + paddr_apb_unqual_dec_19_13 = 0x18; + break; + case 0x201: + paddr_apb_unqual_dec_19_13 = 0x19; + break; + case 0x202: + paddr_apb_unqual_dec_19_13 = 0x1a; + break; + case 0x203: + paddr_apb_unqual_dec_19_13 = 0x1b; + break; + case 0x204: + paddr_apb_unqual_dec_19_13 = 0x1c; + break; + case 0x205: + paddr_apb_unqual_dec_19_13 = 0x1d; + break; + case 0x206: + paddr_apb_unqual_dec_19_13 = 0x1e; + break; + case 0x207: + paddr_apb_unqual_dec_19_13 = 0x1f; + break; + case 0x208: + paddr_apb_unqual_dec_19_13 = 0x20; + break; + case 0x209: + paddr_apb_unqual_dec_19_13 = 0x21; + break; + case 0x20a: + paddr_apb_unqual_dec_19_13 = 0x22; + break; + case 0x20b: + paddr_apb_unqual_dec_19_13 = 0x23; + break; + case 0x300: + paddr_apb_unqual_dec_19_13 = 0x24; + break; + case 0x301: + paddr_apb_unqual_dec_19_13 = 0x25; + break; + case 0x302: + paddr_apb_unqual_dec_19_13 = 0x26; + break; + case 0x303: + paddr_apb_unqual_dec_19_13 = 0x27; + break; + case 0x304: + paddr_apb_unqual_dec_19_13 = 0x28; + break; + case 0x305: + paddr_apb_unqual_dec_19_13 = 0x29; + break; + case 0x306: + paddr_apb_unqual_dec_19_13 = 0x2a; + break; + case 0x307: + paddr_apb_unqual_dec_19_13 = 0x2b; + break; + case 0x308: + paddr_apb_unqual_dec_19_13 = 0x2c; + break; + case 0x309: + paddr_apb_unqual_dec_19_13 = 0x2d; + break; + case 0x30a: + paddr_apb_unqual_dec_19_13 = 0x2e; + break; + case 0x30b: + paddr_apb_unqual_dec_19_13 = 0x2f; + break; + case 0x010: + paddr_apb_unqual_dec_19_13 = 0x30; + break; + case 0x011: + paddr_apb_unqual_dec_19_13 = 0x31; + break; + case 0x012: + paddr_apb_unqual_dec_19_13 = 0x32; + break; + case 0x013: + paddr_apb_unqual_dec_19_13 = 0x33; + break; + case 0x014: + paddr_apb_unqual_dec_19_13 = 0x34; + break; + case 0x015: + paddr_apb_unqual_dec_19_13 = 0x35; + break; + case 0x016: + paddr_apb_unqual_dec_19_13 = 0x36; + break; + case 0x017: + paddr_apb_unqual_dec_19_13 = 0x37; + break; + case 0x018: + paddr_apb_unqual_dec_19_13 = 0x38; + break; + case 0x019: + paddr_apb_unqual_dec_19_13 = 0x39; + break; + case 0x110: + paddr_apb_unqual_dec_19_13 = 0x3a; + break; + case 0x111: + paddr_apb_unqual_dec_19_13 = 0x3b; + break; + case 0x112: + paddr_apb_unqual_dec_19_13 = 0x3c; + break; + case 0x113: + paddr_apb_unqual_dec_19_13 = 0x3d; + break; + case 0x114: + paddr_apb_unqual_dec_19_13 = 0x3e; + break; + case 0x115: + paddr_apb_unqual_dec_19_13 = 0x3f; + break; + case 0x116: + paddr_apb_unqual_dec_19_13 = 0x40; + break; + case 0x117: + paddr_apb_unqual_dec_19_13 = 0x41; + break; + case 0x118: + paddr_apb_unqual_dec_19_13 = 0x42; + break; + case 0x119: + paddr_apb_unqual_dec_19_13 = 0x43; + break; + case 0x210: + paddr_apb_unqual_dec_19_13 = 0x44; + break; + case 0x211: + paddr_apb_unqual_dec_19_13 = 0x45; + break; + case 0x212: + paddr_apb_unqual_dec_19_13 = 0x46; + break; + case 0x213: + paddr_apb_unqual_dec_19_13 = 0x47; + break; + case 0x214: + paddr_apb_unqual_dec_19_13 = 0x48; + break; + case 0x215: + paddr_apb_unqual_dec_19_13 = 0x49; + break; + case 0x216: + paddr_apb_unqual_dec_19_13 = 0x4a; + break; + case 0x217: + paddr_apb_unqual_dec_19_13 = 0x4b; + break; + case 0x218: + paddr_apb_unqual_dec_19_13 = 0x4c; + break; + case 0x219: + paddr_apb_unqual_dec_19_13 = 0x4d; + break; + case 0x310: + paddr_apb_unqual_dec_19_13 = 0x4e; + break; + case 0x311: + paddr_apb_unqual_dec_19_13 = 0x4f; + break; + case 0x312: + paddr_apb_unqual_dec_19_13 = 0x50; + break; + case 0x313: + paddr_apb_unqual_dec_19_13 = 0x51; + break; + case 0x314: + paddr_apb_unqual_dec_19_13 = 0x52; + break; + case 0x315: + paddr_apb_unqual_dec_19_13 = 0x53; + break; + case 0x316: + paddr_apb_unqual_dec_19_13 = 0x54; + break; + case 0x317: + paddr_apb_unqual_dec_19_13 = 0x55; + break; + case 0x318: + paddr_apb_unqual_dec_19_13 = 0x56; + break; + case 0x319: + paddr_apb_unqual_dec_19_13 = 0x57; + break; + case 0x020: + paddr_apb_unqual_dec_19_13 = 0x58; + break; + case 0x120: + paddr_apb_unqual_dec_19_13 = 0x59; + break; + case 0x220: + paddr_apb_unqual_dec_19_13 = 0x5a; + break; + case 0x320: + paddr_apb_unqual_dec_19_13 = 0x5b; + break; + case 0x040: + paddr_apb_unqual_dec_19_13 = 0x5c; + break; + case 0x140: + paddr_apb_unqual_dec_19_13 = 0x5d; + break; + case 0x240: + paddr_apb_unqual_dec_19_13 = 0x5e; + break; + case 0x340: + paddr_apb_unqual_dec_19_13 = 0x5f; + break; + case 0x050: + paddr_apb_unqual_dec_19_13 = 0x60; + break; + case 0x051: + paddr_apb_unqual_dec_19_13 = 0x61; + break; + case 0x052: + paddr_apb_unqual_dec_19_13 = 0x62; + break; + case 0x053: + paddr_apb_unqual_dec_19_13 = 0x63; + break; + case 0x054: + paddr_apb_unqual_dec_19_13 = 0x64; + break; + case 0x055: + paddr_apb_unqual_dec_19_13 = 0x65; + break; + case 0x056: + paddr_apb_unqual_dec_19_13 = 0x66; + break; + case 0x057: + paddr_apb_unqual_dec_19_13 = 0x67; + break; + case 0x070: + paddr_apb_unqual_dec_19_13 = 0x68; + break; + case 0x090: + paddr_apb_unqual_dec_19_13 = 0x69; + break; + case 0x190: + paddr_apb_unqual_dec_19_13 = 0x6a; + break; + case 0x290: + paddr_apb_unqual_dec_19_13 = 0x6b; + break; + case 0x390: + paddr_apb_unqual_dec_19_13 = 0x6c; + break; + case 0x0c0: + paddr_apb_unqual_dec_19_13 = 0x6d; + break; + case 0x0d0: + paddr_apb_unqual_dec_19_13 = 0x6e; + break; + default: + paddr_apb_unqual_dec_19_13 = 0x00; + break; + } + + paddr_apb_unqual = ((paddr_apb_unqual_dec_19_13 << 13) | (paddr_apb_unqual_dec_12_1 << 1)); + + paddr_apb_phy = (paddr_apb_unqual << 1); + + return paddr_apb_phy; +} diff --git a/drivers/ddr/imx/phy/Kconfig b/drivers/ddr/imx/phy/Kconfig new file mode 100644 index 00000000000..d3e589b23c4 --- /dev/null +++ b/drivers/ddr/imx/phy/Kconfig @@ -0,0 +1,4 @@ +config IMX_SNPS_DDR_PHY + bool "i.MX Snopsys DDR PHY" + help + Select the DDR PHY driver support on i.MX8M and i.MX9 SOC. diff --git a/drivers/ddr/imx/phy/Makefile b/drivers/ddr/imx/phy/Makefile new file mode 100644 index 00000000000..bb3d4ee5b74 --- /dev/null +++ b/drivers/ddr/imx/phy/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o +endif diff --git a/drivers/ddr/imx/imx8m/ddrphy_csr.c b/drivers/ddr/imx/phy/ddrphy_csr.c similarity index 100% rename from drivers/ddr/imx/imx8m/ddrphy_csr.c rename to drivers/ddr/imx/phy/ddrphy_csr.c diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c similarity index 98% rename from drivers/ddr/imx/imx8m/ddrphy_train.c rename to drivers/ddr/imx/phy/ddrphy_train.c index 08fed6178f3..cd905f952c6 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_train.c +++ b/drivers/ddr/imx/phy/ddrphy_train.c @@ -7,7 +7,6 @@ #include <log.h> #include <linux/kernel.h> #include <asm/arch/ddr.h> -#include <asm/arch/lpddr4_define.h> #include <asm/arch/sys_proto.h>

int ddr_cfg_phy(struct dram_timing_info *dram_timing) diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c new file mode 100644 index 00000000000..b852c870f90 --- /dev/null +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <errno.h> +#include <log.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/sys_proto.h> + +static inline void poll_pmu_message_ready(void) +{ + unsigned int reg; + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004)); + } while (reg & 0x1); +} + +static inline void ack_pmu_message_receive(void) +{ + unsigned int reg; + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x0); + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004)); + } while (!(reg & 0x1)); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x1); +} + +static inline unsigned int get_mail(void) +{ + unsigned int reg; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032)); + + ack_pmu_message_receive(); + + return reg; +} + +static inline unsigned int get_stream_message(void) +{ + unsigned int reg, reg2; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032)); + + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0034)); + + reg2 = (reg2 << 16) | reg; + + ack_pmu_message_receive(); + + return reg2; +} + +static inline void decode_major_message(unsigned int mail) +{ + debug("[PMU Major message = 0x%08x]\n", mail); +} + +static inline void decode_streaming_message(void) +{ + unsigned int string_index, arg __maybe_unused; + int i = 0; + + string_index = get_stream_message(); + debug("PMU String index = 0x%08x\n", string_index); + while (i < (string_index & 0xffff)) { + arg = get_stream_message(); + debug("arg[%d] = 0x%08x\n", i, arg); + i++; + } + + debug("\n"); +} + +int wait_ddrphy_training_complete(void) +{ + unsigned int mail; + + while (1) { + mail = get_mail(); + decode_major_message(mail); + if (mail == 0x08) { + decode_streaming_message(); + } else if (mail == 0x07) { + debug("Training PASS\n"); + return 0; + } else if (mail == 0xff) { + printf("Training FAILED\n"); + return -1; + } + } +} + +void ddrphy_init_set_dfi_clk(unsigned int drate) +{ + switch (drate) { + case 4000: + dram_pll_init(MHZ(1000)); + dram_disable_bypass(); + break; + case 3733: + dram_pll_init(MHZ(933)); + dram_disable_bypass(); + break; + case 3200: + dram_pll_init(MHZ(800)); + dram_disable_bypass(); + break; + case 3000: + dram_pll_init(MHZ(750)); + dram_disable_bypass(); + break; + case 2800: + dram_pll_init(MHZ(700)); + dram_disable_bypass(); + break; + case 2400: + dram_pll_init(MHZ(600)); + dram_disable_bypass(); + break; + case 1866: + dram_pll_init(MHZ(466)); + dram_disable_bypass(); + break; + case 1600: + dram_pll_init(MHZ(400)); + dram_disable_bypass(); + break; + case 1066: + dram_pll_init(MHZ(266)); + dram_disable_bypass(); + break; + case 667: + dram_pll_init(MHZ(167)); + dram_disable_bypass(); + break; + case 400: + dram_enable_bypass(MHZ(400)); + break; + case 333: + dram_enable_bypass(MHZ(333)); + break; + case 200: + dram_enable_bypass(MHZ(200)); + break; + case 100: + dram_enable_bypass(MHZ(100)); + break; + default: + return; + } +} + +void ddrphy_init_read_msg_block(enum fw_type type) +{ +} diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/phy/helper.c similarity index 79% rename from drivers/ddr/imx/imx8m/helper.c rename to drivers/ddr/imx/phy/helper.c index f23904bf712..60d650e3089 100644 --- a/drivers/ddr/imx/imx8m/helper.c +++ b/drivers/ddr/imx/phy/helper.c @@ -12,7 +12,6 @@ #include <asm/io.h> #include <asm/arch/ddr.h> #include <asm/arch/ddr.h> -#include <asm/arch/lpddr4_define.h> #include <asm/sections.h>

DECLARE_GLOBAL_DATA_PTR; @@ -46,43 +45,46 @@ void ddr_load_train_firmware(enum fw_type type) dmem_start = imem_start + IMEM_LEN;

pr_from32 = imem_start; - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + pr_to32 = IMEM_OFFSET_ADDR; for (i = 0x0; i < IMEM_LEN; ) { tmp32 = readl(pr_from32); - writew(tmp32 & 0x0000ffff, pr_to32); - pr_to32 += 4; - writew((tmp32 >> 16) & 0x0000ffff, pr_to32); - pr_to32 += 4; + writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); + pr_to32 += 1; + writew((tmp32 >> 16) & 0x0000ffff, + DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); + pr_to32 += 1; pr_from32 += 4; i += 4; }

pr_from32 = dmem_start; - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + pr_to32 = DMEM_OFFSET_ADDR; for (i = 0x0; i < DMEM_LEN; ) { tmp32 = readl(pr_from32); - writew(tmp32 & 0x0000ffff, pr_to32); - pr_to32 += 4; - writew((tmp32 >> 16) & 0x0000ffff, pr_to32); - pr_to32 += 4; + writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); + pr_to32 += 1; + writew((tmp32 >> 16) & 0x0000ffff, + DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); + pr_to32 += 1; pr_from32 += 4; i += 4; }

debug("check ddr_pmu_train_imem code\n"); pr_from32 = imem_start; - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + pr_to32 = IMEM_OFFSET_ADDR; for (i = 0x0; i < IMEM_LEN; ) { - tmp32 = (readw(pr_to32) & 0x0000ffff); - pr_to32 += 4; - tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff); + pr_to32 += 1; + tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR + + ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16);

if (tmp32 != readl(pr_from32)) { debug("%lx %lx\n", pr_from32, pr_to32); error++; } pr_from32 += 4; - pr_to32 += 4; + pr_to32 += 1; i += 4; } if (error) @@ -92,17 +94,18 @@ void ddr_load_train_firmware(enum fw_type type)

debug("check ddr4_pmu_train_dmem code\n"); pr_from32 = dmem_start; - pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + pr_to32 = DMEM_OFFSET_ADDR; for (i = 0x0; i < DMEM_LEN;) { - tmp32 = (readw(pr_to32) & 0x0000ffff); - pr_to32 += 4; - tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff); + pr_to32 += 1; + tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR + + ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16); if (tmp32 != readl(pr_from32)) { debug("%lx %lx\n", pr_from32, pr_to32); error++; } pr_from32 += 4; - pr_to32 += 4; + pr_to32 += 1; i += 4; }

From: Peng Fan peng.fan@nxp.com

Add the DTSi file and DT header files for i.MX93 SoC

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Alice Guo alice.guo@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/dts/imx93.dtsi | 688 ++++++++++++++++++++++++ include/dt-bindings/clock/imx93-clock.h | 203 +++++++ include/dt-bindings/power/imx93-power.h | 12 + 3 files changed, 903 insertions(+) create mode 100644 arch/arm/dts/imx93.dtsi create mode 100644 include/dt-bindings/clock/imx93-clock.h create mode 100644 include/dt-bindings/power/imx93-power.h

diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi new file mode 100644 index 00000000000..28026ccecc8 --- /dev/null +++ b/arch/arm/dts/imx93.dtsi @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include <dt-bindings/clock/imx93-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/power/imx93-power.h> +#include <dt-bindings/usb/pd.h> + +#include "imx93-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + ethernet0 = &fec; + ethernet1 = &eqos; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48040000 0 0xc0000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x80000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mu1: mailbox@44230000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x44230000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + anomix_ns_gpr: blk-ctrl-anomix@42420000 { + compatible = "syscon"; + reg = <0x44210000 0x1000>; + }; + + system_counter: timer@44290000 { + compatible = "nxp,sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc_24m>; + clock-names = "per"; + }; + + i3c1: i3c-master@44330000 { + #address-cells = <3>; + #size-cells = <0>; + compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; + reg = <0x44330000 0x10000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C1_GATE>, + <&clk IMX93_CLK_LPI2C1_GATE>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C2_GATE>, + <&clk IMX93_CLK_LPI2C2_GATE>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI1_GATE>, + <&clk IMX93_CLK_LPSPI1_GATE>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI2_GATE>, + <&clk IMX93_CLK_LPSPI2_GATE>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART2_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + iomuxc: pinctrl@443c0000 { + compatible = "fsl,imx93-iomuxc"; + reg = <0x443c0000 0x10000>; + }; + + clk: clock-controller@44450000 { + compatible = "fsl,imx93-ccm"; + reg = <0x44450000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; + clock-names = "osc_32k", "osc_24m", "clk_ext1"; + assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <393216000>; + status = "okay"; + }; + + anatop: anatop@44480000 { + compatible = "fsl,imx93-anatop", "syscon"; + reg = <0x44480000 0x10000>; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_ADC1_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + }; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + wakeupmix_gpr: blk-ctrl-wakeupmix@42420000 { + compatible = "syscon"; + reg = <0x42420000 0x1000>; + }; + + mu2: mailbox@42440000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x42440000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + wdog3: wdog@42490000 { + compatible = "fsl,imx93-wdt"; + reg = <0x42490000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WDOG3_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm4: pwm@424f0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424f0000 0x1000>; + clocks = <&clk IMX93_CLK_TPM4_GATE>; + assigned-clocks = <&clk IMX93_CLK_TPM4>; + assigned-clock-parents = <&clk IMX93_CLK_24M>; + assigned-clock-rates = <24000000>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c2: i3c-master@42520000 { + #address-cells = <3>; + #size-cells = <0>; + compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; + reg = <0x42520000 0x10000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c3: i2c@42530000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42530000 0x10000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C3_GATE>, + <&clk IMX93_CLK_LPI2C3_GATE>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c4: i2c@42540000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42540000 0x10000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C4_GATE>, + <&clk IMX93_CLK_LPI2C4_GATE>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi3: spi@42550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42550000 0x10000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI3_GATE>, + <&clk IMX93_CLK_LPSPI3_GATE>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42560000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI4_GATE>, + <&clk IMX93_CLK_LPSPI4_GATE>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpuart3: serial@42570000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42570000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART3_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@42580000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42580000 0x1000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART4_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@42590000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42590000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART5_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x425a0000 0x1000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART6_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + flexspi: spi@425e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "fspi", "fspi_en"; + status = "disabled"; + }; + + lpuart7: serial@42690000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42690000 0x1000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART7_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x426a0000 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART8_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpi2c5: i2c@426b0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426b0000 0x10000>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C5_GATE>, + <&clk IMX93_CLK_LPI2C5_GATE>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c6: i2c@426c0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426c0000 0x10000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPI2C6_GATE>, + <&clk IMX93_CLK_LPI2C6_GATE>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usdhc1: mmc@42850000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42850000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC1_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42860000 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC2_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + fec: ethernet@42890000 { + compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec"; + reg = <0x42890000 0x10000>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <250000000>, <50000000>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + fsl,wakeup_irq = <2>; + status = "disabled"; + }; + + eqos: ethernet@428a0000 { + compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x428a0000 0x10000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>, + <&clk IMX93_CLK_WAKEUP_AXI>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; + intf_mode = <&wakeupmix_gpr 0x28>; + clk_csr = <0>; + status = "disabled"; + }; + + usdhc3: mmc@428b0000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x428b0000 0x10000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC3_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43810080 0x1000>, <0x43810040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 32 32>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43820080 0x1000>, <0x43820040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 64 32>; + }; + + gpio4: gpio@43830000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43830080 0x1000>, <0x43830040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 96 32>; + }; + + gpio1: gpio@47400000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x47400080 0x1000>, <0x47400040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 0 32>; + }; + + ocotp: efuse@47510000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx93-ocotp", "syscon"; + reg = <0x47510000 0x1000>; + status = "disabled"; + }; + + s4muap: s4muap@47520000 { + compatible = "fsl,imx93-mu-s4"; + reg = <0x47520000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "txirq", "rxirq"; + #mbox-cells = <2>; + status = "okay"; + }; + + sentnl_mu: sentnl-mu { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx-sentnl"; + mboxes = <&s4muap 0 0 &s4muap 1 0>; + mbox-names = "tx", "rx"; + fsl,sentnl_mu_id = <2>; + fsl,sentnl_mu_max_users = <4>; + status = "okay"; + dma-ranges = <0x80000000 0x80000000 0x20000000>; + }; + + ddr-pmu@4e300e00 { + compatible = "fsl,imx93-ddr-pmu"; + reg = <0x4e300dc0 0x200>; /* _dc0 ~ _eb8 */ + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbotg1: usb@4c100000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x4c100000 0x200>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + assigned-clock-parents = <&clk IMX93_CLK_HSIO>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x4c100200 0x200>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbotg2: usb@4c200000 { + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + reg = <0x4c200000 0x200>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + clock-names = "usb2_ctrl_root_clk"; + assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>; + assigned-clock-parents = <&clk IMX93_CLK_HSIO>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x4c200200 0x200>; + }; + }; +}; diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h new file mode 100644 index 00000000000..4ea6864b418 --- /dev/null +++ b/include/dt-bindings/clock/imx93-clock.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * Copyright 2021 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H +#define __DT_BINDINGS_CLOCK_IMX93_CLK_H + +#define IMX93_CLK_DUMMY 0 +#define IMX93_CLK_24M 1 +#define IMX93_CLK_EXT1 2 +#define IMX93_CLK_SYS_PLL_PFD0 3 +#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4 +#define IMX93_CLK_SYS_PLL_PFD1 5 +#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6 +#define IMX93_CLK_SYS_PLL_PFD2 7 +#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8 +#define IMX93_CLK_AUDIO_PLL 9 +#define IMX93_CLK_VIDEO_PLL 10 +#define IMX93_CLK_A55_PERIPH 11 +#define IMX93_CLK_A55_MTR_BUS 12 +#define IMX93_CLK_A55 13 +#define IMX93_CLK_M33 14 +#define IMX93_CLK_BUS_WAKEUP 15 +#define IMX93_CLK_BUS_AON 16 +#define IMX93_CLK_WAKEUP_AXI 17 +#define IMX93_CLK_SWO_TRACE 18 +#define IMX93_CLK_M33_SYSTICK 19 +#define IMX93_CLK_FLEXIO1 20 +#define IMX93_CLK_FLEXIO2 21 +#define IMX93_CLK_LPIT1 22 +#define IMX93_CLK_LPIT2 23 +#define IMX93_CLK_LPTMR1 24 +#define IMX93_CLK_LPTMR2 25 +#define IMX93_CLK_TPM1 26 +#define IMX93_CLK_TPM2 27 +#define IMX93_CLK_TPM3 28 +#define IMX93_CLK_TPM4 29 +#define IMX93_CLK_TPM5 30 +#define IMX93_CLK_TPM6 31 +#define IMX93_CLK_FLEXSPI1 32 +#define IMX93_CLK_CAN1 33 +#define IMX93_CLK_CAN2 34 +#define IMX93_CLK_LPUART1 35 +#define IMX93_CLK_LPUART2 36 +#define IMX93_CLK_LPUART3 37 +#define IMX93_CLK_LPUART4 38 +#define IMX93_CLK_LPUART5 39 +#define IMX93_CLK_LPUART6 40 +#define IMX93_CLK_LPUART7 41 +#define IMX93_CLK_LPUART8 42 +#define IMX93_CLK_LPI2C1 43 +#define IMX93_CLK_LPI2C2 44 +#define IMX93_CLK_LPI2C3 45 +#define IMX93_CLK_LPI2C4 46 +#define IMX93_CLK_LPI2C5 47 +#define IMX93_CLK_LPI2C6 48 +#define IMX93_CLK_LPI2C7 49 +#define IMX93_CLK_LPI2C8 50 +#define IMX93_CLK_LPSPI1 51 +#define IMX93_CLK_LPSPI2 52 +#define IMX93_CLK_LPSPI3 53 +#define IMX93_CLK_LPSPI4 54 +#define IMX93_CLK_LPSPI5 55 +#define IMX93_CLK_LPSPI6 56 +#define IMX93_CLK_LPSPI7 57 +#define IMX93_CLK_LPSPI8 58 +#define IMX93_CLK_I3C1 59 +#define IMX93_CLK_I3C2 60 +#define IMX93_CLK_USDHC1 61 +#define IMX93_CLK_USDHC2 62 +#define IMX93_CLK_USDHC3 63 +#define IMX93_CLK_SAI1 64 +#define IMX93_CLK_SAI2 65 +#define IMX93_CLK_SAI3 66 +#define IMX93_CLK_CCM_CKO1 67 +#define IMX93_CLK_CCM_CKO2 68 +#define IMX93_CLK_CCM_CKO3 69 +#define IMX93_CLK_CCM_CKO4 70 +#define IMX93_CLK_HSIO 71 +#define IMX93_CLK_HSIO_USB_TEST_60M 72 +#define IMX93_CLK_HSIO_ACSCAN_80M 73 +#define IMX93_CLK_HSIO_ACSCAN_480M 74 +#define IMX93_CLK_ML_APB 75 +#define IMX93_CLK_ML 76 +#define IMX93_CLK_MEDIA_AXI 77 +#define IMX93_CLK_MEDIA_APB 78 +#define IMX93_CLK_MEDIA_LDB 79 +#define IMX93_CLK_MEDIA_DISP_PIX 80 +#define IMX93_CLK_CAM_PIX 81 +#define IMX93_CLK_MIPI_TEST_BYTE 82 +#define IMX93_CLK_MIPI_PHY_CFG 83 +#define IMX93_CLK_ADC 84 +#define IMX93_CLK_PDM 85 +#define IMX93_CLK_TSTMR1 86 +#define IMX93_CLK_TSTMR2 87 +#define IMX93_CLK_MQS1 88 +#define IMX93_CLK_MQS2 89 +#define IMX93_CLK_AUDIO_XCVR 90 +#define IMX93_CLK_SPDIF 91 +#define IMX93_CLK_ENET 92 +#define IMX93_CLK_ENET_TIMER1 93 +#define IMX93_CLK_ENET_TIMER2 94 +#define IMX93_CLK_ENET_REF 95 +#define IMX93_CLK_ENET_REF_PHY 96 +#define IMX93_CLK_I3C1_SLOW 97 +#define IMX93_CLK_I3C2_SLOW 98 +#define IMX93_CLK_USB_PHY_BURUNIN 99 +#define IMX93_CLK_PAL_CAME_SCAN 100 +#define IMX93_CLK_A55_GATE 101 +#define IMX93_CLK_CM33_GATE 102 +#define IMX93_CLK_ADC1_GATE 103 +#define IMX93_CLK_WDOG1_GATE 104 +#define IMX93_CLK_WDOG2_GATE 105 +#define IMX93_CLK_WDOG3_GATE 106 +#define IMX93_CLK_WDOG4_GATE 107 +#define IMX93_CLK_WDOG5_GATE 108 +#define IMX93_CLK_SEMA1_GATE 109 +#define IMX93_CLK_SEMA2_GATE 110 +#define IMX93_CLK_MU_A_GATE 111 +#define IMX93_CLK_MU_B_GATE 112 +#define IMX93_CLK_EDMA1_GATE 113 +#define IMX93_CLK_EDMA2_GATE 114 +#define IMX93_CLK_FLEXSPI1_GATE 115 +#define IMX93_CLK_GPIO1_GATE 116 +#define IMX93_CLK_GPIO2_GATE 117 +#define IMX93_CLK_GPIO3_GATE 118 +#define IMX93_CLK_GPIO4_GATE 119 +#define IMX93_CLK_FLEXIO1_GATE 120 +#define IMX93_CLK_FLEXIO2_GATE 121 +#define IMX93_CLK_LPIT1_GATE 122 +#define IMX93_CLK_LPIT2_GATE 123 +#define IMX93_CLK_LPTMR1_GATE 124 +#define IMX93_CLK_LPTMR2_GATE 125 +#define IMX93_CLK_TPM1_GATE 126 +#define IMX93_CLK_TPM2_GATE 127 +#define IMX93_CLK_TPM3_GATE 128 +#define IMX93_CLK_TPM4_GATE 129 +#define IMX93_CLK_TPM5_GATE 130 +#define IMX93_CLK_TPM6_GATE 131 +#define IMX93_CLK_CAN1_GATE 132 +#define IMX93_CLK_CAN2_GATE 133 +#define IMX93_CLK_LPUART1_GATE 134 +#define IMX93_CLK_LPUART2_GATE 135 +#define IMX93_CLK_LPUART3_GATE 136 +#define IMX93_CLK_LPUART4_GATE 137 +#define IMX93_CLK_LPUART5_GATE 138 +#define IMX93_CLK_LPUART6_GATE 139 +#define IMX93_CLK_LPUART7_GATE 140 +#define IMX93_CLK_LPUART8_GATE 141 +#define IMX93_CLK_LPI2C1_GATE 142 +#define IMX93_CLK_LPI2C2_GATE 143 +#define IMX93_CLK_LPI2C3_GATE 144 +#define IMX93_CLK_LPI2C4_GATE 145 +#define IMX93_CLK_LPI2C5_GATE 146 +#define IMX93_CLK_LPI2C6_GATE 147 +#define IMX93_CLK_LPI2C7_GATE 148 +#define IMX93_CLK_LPI2C8_GATE 149 +#define IMX93_CLK_LPSPI1_GATE 150 +#define IMX93_CLK_LPSPI2_GATE 151 +#define IMX93_CLK_LPSPI3_GATE 152 +#define IMX93_CLK_LPSPI4_GATE 153 +#define IMX93_CLK_LPSPI5_GATE 154 +#define IMX93_CLK_LPSPI6_GATE 155 +#define IMX93_CLK_LPSPI7_GATE 156 +#define IMX93_CLK_LPSPI8_GATE 157 +#define IMX93_CLK_I3C1_GATE 158 +#define IMX93_CLK_I3C2_GATE 159 +#define IMX93_CLK_USDHC1_GATE 160 +#define IMX93_CLK_USDHC2_GATE 161 +#define IMX93_CLK_USDHC3_GATE 162 +#define IMX93_CLK_SAI1_GATE 163 +#define IMX93_CLK_SAI2_GATE 164 +#define IMX93_CLK_SAI3_GATE 165 +#define IMX93_CLK_MIPI_CSI_GATE 166 +#define IMX93_CLK_MIPI_DSI_GATE 167 +#define IMX93_CLK_LVDS_GATE 168 +#define IMX93_CLK_LCDIF_GATE 169 +#define IMX93_CLK_PXP_GATE 170 +#define IMX93_CLK_ISI_GATE 171 +#define IMX93_CLK_NIC_MEDIA_GATE 172 +#define IMX93_CLK_USB_CONTROLLER_GATE 173 +#define IMX93_CLK_USB_TEST_60M_GATE 174 +#define IMX93_CLK_HSIO_TROUT_24M_GATE 175 +#define IMX93_CLK_PDM_GATE 176 +#define IMX93_CLK_MQS1_GATE 177 +#define IMX93_CLK_MQS2_GATE 178 +#define IMX93_CLK_AUD_XCVR_GATE 179 +#define IMX93_CLK_SPDIF_GATE 180 +#define IMX93_CLK_HSIO_32K_GATE 181 +#define IMX93_CLK_ENET1_GATE 182 +#define IMX93_CLK_ENET_QOS_GATE 183 +#define IMX93_CLK_SYS_CNT_GATE 184 +#define IMX93_CLK_TSTMR1_GATE 185 +#define IMX93_CLK_TSTMR2_GATE 186 +#define IMX93_CLK_TMC_GATE 187 +#define IMX93_CLK_PMRO_GATE 188 +#define IMX93_CLK_32K 189 +#define IMX93_CLK_SAI1_IPG 190 +#define IMX93_CLK_SAI2_IPG 191 +#define IMX93_CLK_SAI3_IPG 192 +#define IMX93_CLK_END 193 +#endif diff --git a/include/dt-bindings/power/imx93-power.h b/include/dt-bindings/power/imx93-power.h new file mode 100644 index 00000000000..4e27a2e2809 --- /dev/null +++ b/include/dt-bindings/power/imx93-power.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2021 NXP + */ + +#ifndef __DT_BINDINGS_IMX93_POWER_H__ +#define __DT_BINDINGS_IMX93_POWER_H__ + +#define IMX93_POWER_DOMAIN_MLMIX 0 +#define IMX93_POWER_DOMAIN_MEDIAMIX 1 + +#endif

From: Peng Fan peng.fan@nxp.com

Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC to Overdrive voltage 0.9V

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-imx9/clock.h | 4 +++- arch/arm/mach-imx/imx9/clock.c | 9 +++++++++ board/freescale/imx93_evk/spl.c | 3 +++ 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h index d96f126a1d1..336d8613181 100644 --- a/arch/arm/include/asm/arch-imx9/clock.h +++ b/arch/arm/include/asm/arch-imx9/clock.h @@ -217,6 +217,8 @@ void dram_pll_init(ulong pll_val); void dram_enable_bypass(ulong clk_val); void dram_disable_bypass(void);

+int configure_intpll(enum ccm_clk_src pll, u32 freq); + int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable); int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable); int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable); @@ -238,5 +240,5 @@ int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool user_mode, bool lock void enable_usboh3_clk(unsigned char enable); int set_clk_enet(enum enet_freq type); int set_clk_eqos(enum enet_freq type); - +void set_arm_clk(ulong freq); #endif diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 5d2bc0d2f8f..8240afc6172 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -665,6 +665,15 @@ void dram_disable_bypass(void) /* Switch from DRAM clock root from CCM to PLL */ ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL); } + +void set_arm_clk(ulong freq) +{ + /* Increase ARM clock to 1.7Ghz */ + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); + configure_intpll(ARM_PLL_CLK, 1700000000); + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); +} + #endif

int clock_init(void) diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index ca33f943424..38cfbac6ea6 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -108,6 +108,9 @@ void board_init_f(ulong dummy) } power_init_board();

+ /* 1.7GHz */ + set_arm_clk(1700000000); + /* Init power of mix */ soc_power_init();

From: Peng Fan peng.fan@nxp.com

Support build i.MX93 container image with mkimage

Signed-off-by: Peng Fan peng.fan@nxp.com --- include/imx8image.h | 15 +++++++-- tools/imx8image.c | 79 +++++++++++++++++++++++++++++++++++++-------- 2 files changed, 78 insertions(+), 16 deletions(-)

diff --git a/include/imx8image.h b/include/imx8image.h index 00c614ab6cc..32064bfeeb8 100644 --- a/include/imx8image.h +++ b/include/imx8image.h @@ -165,6 +165,7 @@ enum imx8image_core_type { CFG_M40, CFG_M41, CFG_A35, + CFG_A55, CFG_A53, CFG_A72 }; @@ -180,7 +181,9 @@ enum imx8image_fld_types { typedef enum SOC_TYPE { NONE = 0, QX, - QM + QM, + ULP, + IMX9 } soc_type_t;

typedef enum option_type { @@ -201,7 +204,9 @@ typedef enum option_type { DATA, PARTITION, FILEOFF, - MSG_BLOCK + MSG_BLOCK, + SENTINEL, + UPOWER } option_type_t;

typedef struct { @@ -221,6 +226,11 @@ typedef struct { #define CORE_CA72 5 #define CORE_SECO 6

+#define CORE_ULP_CM33 0x1 +#define CORE_ULP_CA35 0x2 +#define CORE_ULP_UPOWER 0x4 +#define CORE_ULP_SENTINEL 0x6 + #define SC_R_OTP 357U #define SC_R_DEBUG 354U #define SC_R_ROM_0 236U @@ -235,6 +245,7 @@ typedef struct { #define IMG_TYPE_DATA 0x04 /* Data image type */ #define IMG_TYPE_DCD_DDR 0x05 /* DCD/DDR image type */ #define IMG_TYPE_SECO 0x06 /* SECO image type */ +#define IMG_TYPE_SENTINEL 0x06 /* SENTINEL image type */ #define IMG_TYPE_PROV 0x07 /* Provisioning image type */ #define IMG_TYPE_DEK 0x08 /* DEK validation type */

diff --git a/tools/imx8image.c b/tools/imx8image.c index fa8f2274876..01e14869114 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -60,6 +60,7 @@ static table_entry_t imx8image_core_entries[] = { {CFG_M40, "M40", "M4 core 0", }, {CFG_M41, "M41", "M4 core 1", }, {CFG_A35, "A35", "A35 core", }, + {CFG_A55, "A55", "A55 core", }, {CFG_A53, "A53", "A53 core", }, {CFG_A72, "A72", "A72 core", }, {-1, "", "", }, @@ -117,6 +118,10 @@ static void parse_cfg_cmd(image_t *param_stack, int32_t cmd, char *token, soc = QX; } else if (!strncmp(token, "IMX8QM", 6)) { soc = QM; + } else if (!strncmp(token, "ULP", 3)) { + soc = IMX9; + } else if (!strncmp(token, "IMX9", 4)) { + soc = IMX9; } else { fprintf(stderr, "Unknown CMD_SOC_TYPE"); exit(EXIT_FAILURE); @@ -187,6 +192,7 @@ static void parse_cfg_fld(image_t *param_stack, int32_t *cmd, char *token, param_stack[p_idx].filename = token; break; case CFG_A35: + case CFG_A55: param_stack[p_idx].ext = CORE_CA35; param_stack[p_idx].option = (*cmd == CMD_DATA) ? DATA : AP; @@ -219,6 +225,7 @@ static void parse_cfg_fld(image_t *param_stack, int32_t *cmd, char *token, case CFG_M41: case CFG_A35: case CFG_A53: + case CFG_A55: case CFG_A72: param_stack[p_idx++].entry = (uint32_t)strtoll(token, NULL, 0); @@ -548,6 +555,18 @@ static void set_image_array_entry(flash_header_v3_t *container, img->dst = 0x20C00000; img->entry = 0x20000000; break; + case SENTINEL: + if (container->num_images > 0) { + fprintf(stderr, "Error: SENTINEL container only allows 1 image\n"); + return; + } + + img->hab_flags |= IMG_TYPE_SENTINEL; + img->hab_flags |= CORE_ULP_SENTINEL << BOOT_IMG_FLAGS_CORE_SHIFT; + tmp_name = "SENTINEL"; + img->dst = 0xe4000000; /* S400 IRAM base */ + img->entry = 0xe4000000; + break; case AP: if (soc == QX && core == CORE_CA35) { meta = IMAGE_A35_DEFAULT_META(custom_partition); @@ -555,6 +574,8 @@ static void set_image_array_entry(flash_header_v3_t *container, meta = IMAGE_A53_DEFAULT_META(custom_partition); } else if (soc == QM && core == CORE_CA72) { meta = IMAGE_A72_DEFAULT_META(custom_partition); + } else if (((soc == ULP) || (soc == IMX9)) && core == CORE_CA35) { + meta = 0; } else { fprintf(stderr, "Error: invalid AP core id: %" PRIu64 "\n", @@ -562,8 +583,10 @@ static void set_image_array_entry(flash_header_v3_t *container, exit(EXIT_FAILURE); } img->hab_flags |= IMG_TYPE_EXEC; - /* On B0, only core id = 4 is valid */ - img->hab_flags |= CORE_CA53 << BOOT_IMG_FLAGS_CORE_SHIFT; + if ((soc == ULP) || (soc == IMX9)) + img->hab_flags |= CORE_ULP_CA35 << BOOT_IMG_FLAGS_CORE_SHIFT; + else + img->hab_flags |= CORE_CA53 << BOOT_IMG_FLAGS_CORE_SHIFT; /* On B0, only core id = 4 is valid */ tmp_name = "AP"; img->dst = entry; img->entry = entry; @@ -572,17 +595,22 @@ static void set_image_array_entry(flash_header_v3_t *container, break; case M40: case M41: - if (core == 0) { - core = CORE_CM4_0; - meta = IMAGE_M4_0_DEFAULT_META(custom_partition); - } else if (core == 1) { - core = CORE_CM4_1; - meta = IMAGE_M4_1_DEFAULT_META(custom_partition); + if ((soc == ULP) || (soc == IMX9)) { + core = CORE_ULP_CM33; + meta = 0; } else { - fprintf(stderr, - "Error: invalid m4 core id: %" PRIu64 "\n", - core); - exit(EXIT_FAILURE); + if (core == 0) { + core = CORE_CM4_0; + meta = IMAGE_M4_0_DEFAULT_META(custom_partition); + } else if (core == 1) { + core = CORE_CM4_1; + meta = IMAGE_M4_1_DEFAULT_META(custom_partition); + } else { + fprintf(stderr, + "Error: invalid m4 core id: %" PRIu64 "\n", + core); + exit(EXIT_FAILURE); + } } img->hab_flags |= IMG_TYPE_EXEC; img->hab_flags |= core << BOOT_IMG_FLAGS_CORE_SHIFT; @@ -598,7 +626,14 @@ static void set_image_array_entry(flash_header_v3_t *container, break; case DATA: img->hab_flags |= IMG_TYPE_DATA; - img->hab_flags |= CORE_CA35 << BOOT_IMG_FLAGS_CORE_SHIFT; + if ((soc == ULP) || (soc == IMX9)) { + if (core == CORE_CM4_0) + img->hab_flags |= CORE_ULP_CM33 << BOOT_IMG_FLAGS_CORE_SHIFT; + else + img->hab_flags |= CORE_ULP_CA35 << BOOT_IMG_FLAGS_CORE_SHIFT; + } else { + img->hab_flags |= CORE_CA35 << BOOT_IMG_FLAGS_CORE_SHIFT; + } tmp_name = "DATA"; img->dst = entry; break; @@ -630,6 +665,15 @@ static void set_image_array_entry(flash_header_v3_t *container, img->dst = img->entry - 1; } break; + case UPOWER: + if (soc == ULP) { + img->hab_flags |= IMG_TYPE_EXEC; + img->hab_flags |= CORE_ULP_UPOWER << BOOT_IMG_FLAGS_CORE_SHIFT; + tmp_name = "UPOWER"; + img->dst = 0x28300200; /* UPOWER code RAM */ + img->entry = 0x28300200; + } + break; default: fprintf(stderr, "unrecognized image type (%d)\n", type); exit(EXIT_FAILURE); @@ -797,6 +841,10 @@ static int build_container(soc_type_t soc, uint32_t sector_size, fprintf(stdout, "Platform:\ti.MX8QXP B0\n"); else if (soc == QM) fprintf(stdout, "Platform:\ti.MX8QM B0\n"); + else if (soc == ULP) + fprintf(stdout, "Platform:\ti.MX8ULP A0\n"); + else if (soc == IMX9) + fprintf(stdout, "Platform:\ti.MX9\n");

set_imx_hdr_v3(&imx_header, 0); set_imx_hdr_v3(&imx_header, 1); @@ -815,6 +863,7 @@ static int build_container(soc_type_t soc, uint32_t sector_size, case M41: case SCFW: case DATA: + case UPOWER: case MSG_BLOCK: if (container < 0) { fprintf(stderr, "No container found\n"); @@ -833,6 +882,7 @@ static int build_container(soc_type_t soc, uint32_t sector_size, break;

case SECO: + case SENTINEL: if (container < 0) { fprintf(stderr, "No container found\n"); exit(EXIT_FAILURE); @@ -941,7 +991,8 @@ static int build_container(soc_type_t soc, uint32_t sector_size, if (img_sp->option == M40 || img_sp->option == M41 || img_sp->option == AP || img_sp->option == DATA || img_sp->option == SCD || img_sp->option == SCFW || - img_sp->option == SECO || img_sp->option == MSG_BLOCK) { + img_sp->option == SECO || img_sp->option == MSG_BLOCK || + img_sp->option == UPOWER || img_sp->option == SENTINEL) { copy_file_aligned(ofd, img_sp->filename, img_sp->src, sector_size); }