[U-Boot] [PATCH v6 00/10] armv8: ls2080aqds: Enable QSPI boot support
From: Yuan Yao yao.yuan@nxp.com
This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then we can switch to booting from QSPI memory space.
Yuan Yao (10): drivers: i2c: mxc: Add early init armv8: ls2080aqds: Select QSPI CLK div via SCFG configs: ls2080a_common: Remove duplicate NOR configs armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable configs: ls2080aqds: Enable QSPI flash support Changed in v6. dm: dts: ls2080aqds: Add QSPI dts node armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot configs: ls2080a: Increase load image len in NAND boot ls2080aqds_nand_defconfig: Enable QSPI & its dependence Changed in v6. armv8: ls2080aqds: Enable QSPI boot support Changed in v6.
arch/arm/dts/fsl-ls2080a-qds.dts | 14 +++++++ arch/arm/dts/fsl-ls2080a.dtsi | 10 +++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 ++ board/freescale/ls2080aqds/ls2080aqds.c | 19 ++++++++++ configs/ls2080aqds_nand_defconfig | 8 ++++ configs/ls2080aqds_qspi_defconfig | 27 ++++++++++++++ drivers/i2c/i2c_core.c | 5 +++ drivers/i2c/mxc_i2c.c | 27 ++++++++++++++ include/configs/ls2080a_common.h | 11 ++---- include/configs/ls2080a_simu.h | 7 ++++ include/configs/ls2080aqds.h | 43 +++++++++++++++++++++- include/i2c.h | 3 ++ 13 files changed, 171 insertions(+), 10 deletions(-) create mode 100644 configs/ls2080aqds_qspi_defconfig
From: Yuan Yao yao.yuan@nxp.com
Add early i2c init function with conservative divider when the exact clock rate is not available.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- New add in v3. --- drivers/i2c/i2c_core.c | 5 +++++ drivers/i2c/mxc_i2c.c | 27 +++++++++++++++++++++++++++ include/i2c.h | 3 +++ 3 files changed, 35 insertions(+)
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 41cc3b8..16b1aba 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -233,6 +233,11 @@ __weak void i2c_init_board(void) { }
+/* implement possible for i2c specific early i2c init */ +__weak void i2c_early_init_f(void) +{ +} + /* * i2c_init_all(): * diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 445fa21..f340208 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -32,6 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define IMX_I2C_REGSHIFT 2 #define VF610_I2C_REGSHIFT 0 + +#define I2C_EARLY_INIT_INDEX 0 +#ifdef CONFIG_SYS_I2C_IFDR_DIV +#define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV +#else +#define I2C_IFDR_DIV_CONSERVATIVE 0x7e +#endif + /* Register index */ #define IADR 0 #define IFDR 1 @@ -660,6 +668,25 @@ void bus_i2c_init(int index, int speed, int unused, }
/* + * Early init I2C for prepare read the clk through I2C. + */ +void i2c_early_init_f(void) +{ + ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base; + bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data + & I2C_QUIRK_FLAG ? true : false; + int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; + + /* Set I2C divider value */ + writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift)); + /* Reset module */ + writeb(I2CR_IDIS, base + (I2CR << reg_shift)); + writeb(0, base + (I2SR << reg_shift)); + /* Enable I2C */ + writeb(I2CR_IEN, base + (I2CR << reg_shift)); +} + +/* * Init I2C Bus */ static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) diff --git a/include/i2c.h b/include/i2c.h index 1f5ae45..d500445 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -701,6 +701,9 @@ extern struct i2c_bus_hose i2c_bus[]; * Initialization, must be called once on start up, may be called * repeatedly to change the speed and slave addresses. */ +#ifdef CONFIG_SYS_I2C_EARLY_INIT +void i2c_early_init_f(void); +#endif void i2c_init(int speed, int slaveaddr); void i2c_init_board(void); #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
On 06/08/2016 03:35 AM, Yuan Yao wrote:
From: Yuan Yao yao.yuan@nxp.com
Add early i2c init function with conservative divider when the exact clock rate is not available.
Signed-off-by: Yuan Yao yao.yuan@nxp.com
With minor change to commit message, v6 patch set has been applied to fsl-qoriq master. Awaiting upstream. Thanks.
York
From: Yuan Yao yao.yuan@nxp.com
QSPI module output SCLK divisor value is configured through SCFG.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + board/freescale/ls2080aqds/ls2080aqds.c | 5 +++++ 2 files changed, 6 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 65b3357..bfff2ec 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -139,6 +139,7 @@ /* Supplemental Configuration */ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 +#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */ #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index b3bd40a..d7acb48 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -26,6 +26,7 @@
#define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a +#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
@@ -219,6 +220,10 @@ int board_init(void) int board_early_init_f(void) { fsl_lsch3_early_init_f(); +#ifdef CONFIG_FSL_QSPI + /* input clk: 1/2 platform clk, output: input/20 */ + out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20); +#endif return 0; }
From: Yuan Yao yao.yuan@nxp.com
The NOR flash related configure options also appear in ls2080aqds.h and ls2080ardb.h, and the two files all have included ls2080a_common.h. This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- include/configs/ls2080a_common.h | 7 ------- include/configs/ls2080a_simu.h | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index c78aeb5..48b1e15 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -138,13 +138,6 @@ #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
-#ifndef CONFIG_SYS_NO_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_QUIET_TEST -#endif - #ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); #endif diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index 7563aaf..7f245b5 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -30,6 +30,13 @@ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#endif + /* * NOR Flash Timing Params */
From: Yuan Yao yao.yuan@nxp.com
When QSPI is enabled, NOR flash and QIXIS can't be accessed through IFC due to pin mux. So enable I2C QIXIS access and I2C early init to read the sysclk and ddrclk.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- Changed in v5: Use I2C to read the clocks instead of the hard-coded clocks. --- board/freescale/ls2080aqds/ls2080aqds.c | 3 +++ include/configs/ls2080aqds.h | 10 ++++++++++ 2 files changed, 13 insertions(+)
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index d7acb48..19bb4c6 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -219,6 +219,9 @@ int board_init(void)
int board_early_init_f(void) { +#ifdef CONFIG_SYS_I2C_EARLY_INIT + i2c_early_init_f(); +#endif fsl_lsch3_early_init_f(); #ifdef CONFIG_FSL_QSPI /* input clk: 1/2 platform clk, output: input/20 */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 4b27114..ccc987c 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -17,6 +17,16 @@ unsigned long get_board_ddr_clk(void); #endif
#define CONFIG_SYS_FSL_CLK + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_EARLY_INIT +#define CONFIG_SYS_I2C_IFDR_DIV 0x7e +#endif + +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
From: Yuan Yao yao.yuan@nxp.com
Enable QSPI flash related configure options.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- Changed in v6: remove CONFIG_CMD_SF. --- include/configs/ls2080aqds.h | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index ccc987c..8e193a6 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -289,8 +289,21 @@ unsigned long get_board_ddr_clk(void); #define I2C_MUX_CH_DEFAULT 0x8
/* SPI */ -#ifdef CONFIG_FSL_DSPI +#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) #define CONFIG_SPI_FLASH + +#ifdef CONFIG_FSL_DSPI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_EON +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ +#define FSL_QSPI_FLASH_NUM 4 +#endif + #endif
/*
From: Yuan Yao yao.yuan@nxp.com
Add QSPI controller and slave dts node for LS2080AQDS board.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++++++++++++++ arch/arm/dts/fsl-ls2080a.dtsi | 10 ++++++++++ 2 files changed, 24 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index 547ec27..0a7f1ff 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -15,6 +15,7 @@ compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
aliases { + spi0 = &qspi; spi1 = &dspi; }; }; @@ -51,3 +52,16 @@ reg = <2>; }; }; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fs256s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index a5c579c..68ed133 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -126,4 +126,14 @@ interrupts = <0 26 0x4>; /* Level high type */ num-cs = <6>; }; + + qspi: quadspi@1550000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + num-cs = <4>; + }; };
From: Yuan Yao yao.yuan@nxp.com
In order to access QSPI flash we must asserted ISO allowing the DUT to access the full IFC domain. But deasserted the unused ISO will allowing maximum performance.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++ board/freescale/ls2080aqds/ls2080aqds.c | 9 +++++++++ include/configs/ls2080aqds.h | 6 ++++++ 3 files changed, 17 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index bfff2ec..7c47cc8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -128,6 +128,8 @@ #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 #define DCFG_RCWSR13 0x130 #define DCFG_RCWSR13_DSPI (0 << 8) +#define DCFG_RCWSR15 0x138 +#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
#define DCFG_DCSR_BASE 0X700100000ULL #define DCFG_DCSR_PORCR1 0x000 diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 19bb4c6..8bdcb04 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -208,6 +208,15 @@ int board_init(void) else config_board_mux(MUX_TYPE_SDHC);
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI) + val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); + + if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) + QIXIS_WRITE(brdcfg[9], + (QIXIS_READ(brdcfg[9]) & 0xf8) | + FSL_QIXIS_BRDCFG9_QSPI); +#endif + #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 8e193a6..7152c2b 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -303,6 +303,12 @@ unsigned long get_board_ddr_clk(void); #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ #define FSL_QSPI_FLASH_NUM 4 #endif +/* + * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. + * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 + * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 + */ +#define FSL_QIXIS_BRDCFG9_QSPI 0x1
#endif
From: Yuan Yao yao.yuan@nxp.com
Freescale QSPI and DSPI driver have been converted to Driver Mode. This converting bring dtb file for u-boot and this increase the size of u-boot image. LS2080A nand boot use SPL framework. This patch increase the size of image load from NAND to RAM in SPL.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- include/configs/ls2080a_common.h | 2 +- include/configs/ls2080aqds.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 48b1e15..eab410e 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -283,7 +283,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 7152c2b..55d6c27 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
From: Yuan Yao yao.yuan@nxp.com
The Freescale QSPI driver has been converted to Driver Model. This patch enable FSL_QSPI and its dependence options, DM, DM_SPI, OF_CONTROL and so on.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- Changed in v6: Add CONFIG_CMD_SF in defconfig. --- configs/ls2080aqds_nand_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 1302313..d567878 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -6,6 +6,14 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_OF_CONTROL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DM=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y @@ -18,6 +26,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y CONFIG_E1000=y
From: Yuan Yao yao.yuan@nxp.com
This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then we can switch to booting from QSPI memory space.
Signed-off-by: Yuan Yao yao.yuan@nxp.com --- Changed in v6: Add CONFIG_CMD_SF in defconfig. Changed in v4: Merged the below patch into one: board: freescale: ls2080aqds: Enable early I2C access for QSPI boot Changed in v3: 1, Rebase to lastest code. 2, Give up to change the sequence for "show_board_info" in "init_sequence_f". --- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++++ board/freescale/ls2080aqds/ls2080aqds.c | 2 ++ configs/ls2080aqds_qspi_defconfig | 28 ++++++++++++++++++++++++++ include/configs/ls2080a_common.h | 2 ++ include/configs/ls2080aqds.h | 10 +++++++++ 5 files changed, 46 insertions(+) create mode 100644 configs/ls2080aqds_qspi_defconfig
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 702b9fa..f07a49a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -121,6 +121,8 @@ static const struct sys_mmu_table early_mmu_table[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, + { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PTE_BLOCK_NON_SHARE}, /* For IFC Region #1, only the first 4MB is cache-enabled */ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE }, @@ -175,6 +177,8 @@ static const struct sys_mmu_table final_mmu_table[] = { { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, + { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PTE_BLOCK_NON_SHARE}, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 8bdcb04..23ebcc1 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -81,6 +81,8 @@ int checkboard(void) puts("PromJet\n"); else if (sw == 0x9) puts("NAND\n"); + else if (sw == 0xf) + puts("QSPI\n"); else if (sw == 0x15) printf("IFCCard\n"); else diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig new file mode 100644 index 0000000..194d280 --- /dev/null +++ b/configs/ls2080aqds_qspi_defconfig @@ -0,0 +1,28 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080AQDS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index eab410e..71f830a 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -29,11 +29,13 @@ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
/* Link Definitions */ +#ifndef CONFIG_QSPI_BOOT #ifdef CONFIG_SPL #define CONFIG_SYS_TEXT_BASE 0x80400000 #else #define CONFIG_SYS_TEXT_BASE 0x30100000 #endif +#endif
#ifdef CONFIG_EMU #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 55d6c27..5dfba7a 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -172,11 +172,13 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 #define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_QSPI 0x0f #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RCW_SRC_NAND 0x107 +#define QIXIS_RCW_SRC_QSPI 0x62 #define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0) @@ -267,11 +269,19 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#if defined(CONFIG_QSPI_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x20010000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x2000 #endif +#endif
/* Debug Server firmware */ #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
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