Hi,

u-boot-users-admin@lists.sourceforge.net wrote on :

inside of arm_init() in the part:

It's in eth_init() ...

/* MII management start from here */ if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) { if (!(ret = PhyOps.Init (p_mac))) { printf ("MAC: error during MII initialization\n"); return 0; } } the software checks the status of a LINK-Bit. I thing the EMAC_SR register is wrong, because the EMAC_ISR has this valid LINK bit (AT91C_EMAC_LINK on bit 9).

I think you are right. Due to the AT91RM9200 datasheet (Rev. 1768B-ATRM-08/03) bit 0 of the EMAC_SR (ETH_SR) is labeld with "LINK" and not bit 9. But the description for the "LINK" bit (bit 0) is "reserved". So this bit couldn't be used at all.

Im'n not sure, if EMAC_ISR register bit 9 is suitable for testing the link satus. The datasheet says for this bit: "LINK: Set when LINK pin changes value. Optional.". Wich pin is the "link" pin? In my opinion the AT91RM9200 doesn't has such a pin . And is a LINK change really what we want to test here (a "link" to "no link" transition is also a link change, not only a "no link" to "link" transition)?

Did anybody find this problem?

No, no problem. The current code is wrong, anyway.

If not, so I will check it with our hardware and then I will prepare a patch.

This would be great!

Regards, Martin