[U-Boot] [PATCH 0/7] mmc: fsl_esdhc: clean up and shrink the driver
This patch-set is to clean up and shrink the fsl_esdhc driver.
Yangbo Lu (7): mmc: fsl_esdhc: drop controller initialization in fsl_esdhc_init() mmc: fsl_esdhc: fix voltage validation mmc: fsl_esdhc: clean up bus width configuration code mmc: fsl_esdhc: convert to use fsl_esdhc_get_cfg_common() mmc: fsl_esdhc: drop redundant code for non-removable feature mmc: fsl_esdhc: always check write protect state mmc: fsl_esdhc: clean up DM and non-DM code
drivers/mmc/fsl_esdhc.c | 370 ++++++++++++++++-------------------------------- include/fsl_esdhc.h | 14 +- 2 files changed, 129 insertions(+), 255 deletions(-)
Controller initialization is not needed in fsl_esdhc_init(). It will be done in esdhc_init() for non-DM_MMC, and in esdhc_init_common() in probe for DM_MMC.
Signed-off-by: Yangbo Lu yangbo.lu@nxp.com --- drivers/mmc/fsl_esdhc.c | 36 ------------------------------------ 1 file changed, 36 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index cd357ea..7d7236c 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -25,13 +25,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ - IRQSTATEN_CINT | \ - IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ - IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ - IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ - IRQSTATEN_DINT) - struct fsl_esdhc { uint dsaddr; /* SDMA system address register */ uint blkattr; /* Block attributes register */ @@ -648,25 +641,6 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) return timeout > 0; }
-static int esdhc_reset(struct fsl_esdhc *regs) -{ - ulong start; - - /* reset the controller */ - esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); - - /* hardware clears the bit when it is done */ - start = get_timer(0); - while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { - if (get_timer(start) > 100) { - printf("MMC/SD: Reset never completed.\n"); - return -ETIMEDOUT; - } - } - - return 0; -} - #if !CONFIG_IS_ENABLED(DM_MMC) static int esdhc_getcd(struct mmc *mmc) { @@ -711,22 +685,12 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, struct mmc_config *cfg; struct fsl_esdhc *regs; u32 caps, voltage_caps; - int ret;
if (!priv) return -EINVAL;
regs = priv->esdhc_regs;
- /* First reset the eSDHC controller */ - ret = esdhc_reset(regs); - if (ret) - return ret; - - esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | - SYSCTL_IPGEN | SYSCTL_CKEN); - - writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); cfg = &plat->cfg; #ifndef CONFIG_DM_MMC memset(cfg, '\0', sizeof(*cfg));
Voltage validation should be done by CMD8. Current comparison between mmc_cfg voltages and host voltage capabilities is meaningless. So drop current comparison and let voltage validation is through CMD8.
Signed-off-by: Yangbo Lu yangbo.lu@nxp.com --- drivers/mmc/fsl_esdhc.c | 36 ++++++++++-------------------------- include/fsl_esdhc.h | 13 +++++++------ 2 files changed, 17 insertions(+), 32 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 7d7236c..40fd6af 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -684,7 +684,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, { struct mmc_config *cfg; struct fsl_esdhc *regs; - u32 caps, voltage_caps; + u32 caps;
if (!priv) return -EINVAL; @@ -696,40 +696,24 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, memset(cfg, '\0', sizeof(*cfg)); #endif
- voltage_caps = 0; caps = esdhc_read32(®s->hostcapblt); - #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 - caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | - ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); + caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30); #endif - -/* T4240 host controller capabilities register should have VS33 bit */ #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 - caps = caps | ESDHC_HOSTCAPBLT_VS33; + caps |= HOSTCAPBLT_VS33; #endif - - if (caps & ESDHC_HOSTCAPBLT_VS18) - voltage_caps |= MMC_VDD_165_195; - if (caps & ESDHC_HOSTCAPBLT_VS30) - voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; - if (caps & ESDHC_HOSTCAPBLT_VS33) - voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; + if (caps & HOSTCAPBLT_VS18) + cfg->voltages |= MMC_VDD_165_195; + if (caps & HOSTCAPBLT_VS30) + cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; + if (caps & HOSTCAPBLT_VS33) + cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->name = "FSL_SDHC"; #if !CONFIG_IS_ENABLED(DM_MMC) cfg->ops = &esdhc_ops; #endif -#ifdef CONFIG_SYS_SD_VOLTAGE - cfg->voltages = CONFIG_SYS_SD_VOLTAGE; -#else - cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; -#endif - if ((cfg->voltages & voltage_caps) == 0) { - printf("voltage not supported by controller\n"); - return -1; - } - if (priv->bus_width == 8) cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; else if (priv->bus_width == 4) @@ -744,7 +728,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, cfg->host_caps &= ~MMC_MODE_4BIT; }
- if (caps & ESDHC_HOSTCAPBLT_HSS) + if (caps & HOSTCAPBLT_HSS) cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 33dcbee..a015df1 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -156,12 +156,13 @@ #define BLKATTR_SIZE(x) (x & 0x1fff) #define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
-#define ESDHC_HOSTCAPBLT_VS18 0x04000000 -#define ESDHC_HOSTCAPBLT_VS30 0x02000000 -#define ESDHC_HOSTCAPBLT_VS33 0x01000000 -#define ESDHC_HOSTCAPBLT_SRS 0x00800000 -#define ESDHC_HOSTCAPBLT_DMAS 0x00400000 -#define ESDHC_HOSTCAPBLT_HSS 0x00200000 +/* Host controller capabilities register */ +#define HOSTCAPBLT_VS18 0x04000000 +#define HOSTCAPBLT_VS30 0x02000000 +#define HOSTCAPBLT_VS33 0x01000000 +#define HOSTCAPBLT_SRS 0x00800000 +#define HOSTCAPBLT_DMAS 0x00400000 +#define HOSTCAPBLT_HSS 0x00200000
struct fsl_esdhc_cfg { phys_addr_t esdhc_base;
This patch is to clean up bus width setting code.
- For DM_MMC, remove getting "bus-width" from device tree. This has been done in mmc_of_parse().
- For non-DM_MMC, move bus width configuration from fsl_esdhc_init() to fsl_esdhc_initialize() which is non-DM_MMC specific. And fix up bus width configuration to support only 1-bit, 4-bit, or 8-bit. Keep using 8-bit if it's not set because many platforms use driver without providing max bus width.
- Remove bus_width member from fsl_esdhc_priv structure.
Signed-off-by: Yangbo Lu yangbo.lu@nxp.com --- drivers/mmc/fsl_esdhc.c | 70 ++++++++++++++++--------------------------------- 1 file changed, 22 insertions(+), 48 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 40fd6af..e5276f6 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -85,7 +85,6 @@ struct fsl_esdhc_priv { unsigned int sdhc_clk; struct clk per_clk; unsigned int clock; - unsigned int bus_width; #if !CONFIG_IS_ENABLED(DM_MMC) struct mmc *mmc; #endif @@ -714,28 +713,10 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, #if !CONFIG_IS_ENABLED(DM_MMC) cfg->ops = &esdhc_ops; #endif - if (priv->bus_width == 8) - cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; - else if (priv->bus_width == 4) - cfg->host_caps = MMC_MODE_4BIT; - - cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; - - if (priv->bus_width > 0) { - if (priv->bus_width < 8) - cfg->host_caps &= ~MMC_MODE_8BIT; - if (priv->bus_width < 4) - cfg->host_caps &= ~MMC_MODE_4BIT; - }
if (caps & HOSTCAPBLT_HSS) cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
-#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK - if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) - cfg->host_caps &= ~MMC_MODE_8BIT; -#endif - cfg->f_min = 400000; cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
@@ -745,24 +726,11 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, }
#if !CONFIG_IS_ENABLED(DM_MMC) -static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, - struct fsl_esdhc_priv *priv) -{ - if (!cfg || !priv) - return -EINVAL; - - priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); - priv->bus_width = cfg->max_bus_width; - priv->sdhc_clk = cfg->sdhc_clk; - priv->wp_enable = cfg->wp_enable; - - return 0; -}; - int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) { struct fsl_esdhc_plat *plat; struct fsl_esdhc_priv *priv; + struct mmc_config *mmc_cfg; struct mmc *mmc; int ret;
@@ -778,14 +746,29 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) return -ENOMEM; }
- ret = fsl_esdhc_cfg_to_priv(cfg, priv); - if (ret) { - debug("%s xlate failure\n", __func__); - free(plat); - free(priv); - return ret; + priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); + priv->sdhc_clk = cfg->sdhc_clk; + priv->wp_enable = cfg->wp_enable; + + mmc_cfg = &plat->cfg; + + if (cfg->max_bus_width == 8) { + mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | + MMC_MODE_8BIT; + } else if (cfg->max_bus_width == 4) { + mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT; + } else if (cfg->max_bus_width == 1) { + mmc_cfg->host_caps |= MMC_MODE_1BIT; + } else { + mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | + MMC_MODE_8BIT; + printf("No max bus width provided. Assume 8-bit supported.\n"); }
+#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK + if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) + mmc_cfg->host_caps &= ~MMC_MODE_8BIT; +#endif ret = fsl_esdhc_init(priv, plat); if (ret) { debug("%s init failure\n", __func__); @@ -897,7 +880,6 @@ static int fsl_esdhc_probe(struct udevice *dev) struct fsl_esdhc_plat *plat = dev_get_platdata(dev); struct fsl_esdhc_priv *priv = dev_get_priv(dev); fdt_addr_t addr; - unsigned int val; struct mmc *mmc; int ret;
@@ -911,14 +893,6 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif priv->dev = dev;
- val = dev_read_u32_default(dev, "bus-width", -1); - if (val == 8) - priv->bus_width = 8; - else if (val == 4) - priv->bus_width = 4; - else - priv->bus_width = 1; - if (dev_read_bool(dev, "non-removable")) { priv->non_removable = 1; } else {
The fsl_esdhc_init() was actually to get configuration of mmc_config. So rename it to fsl_esdhc_get_cfg_common() and make it common for both DM_MMC and non-DM_MMC.
Signed-off-by: Yangbo Lu yangbo.lu@nxp.com --- drivers/mmc/fsl_esdhc.c | 43 ++++++++----------------------------------- 1 file changed, 8 insertions(+), 35 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index e5276f6..2b7bcab 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -678,23 +678,12 @@ static const struct mmc_ops esdhc_ops = { }; #endif
-static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, - struct fsl_esdhc_plat *plat) +static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv, + struct mmc_config *cfg) { - struct mmc_config *cfg; - struct fsl_esdhc *regs; + struct fsl_esdhc *regs = priv->esdhc_regs; u32 caps;
- if (!priv) - return -EINVAL; - - regs = priv->esdhc_regs; - - cfg = &plat->cfg; -#ifndef CONFIG_DM_MMC - memset(cfg, '\0', sizeof(*cfg)); -#endif - caps = esdhc_read32(®s->hostcapblt); #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30); @@ -710,19 +699,13 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->name = "FSL_SDHC"; -#if !CONFIG_IS_ENABLED(DM_MMC) - cfg->ops = &esdhc_ops; -#endif
if (caps & HOSTCAPBLT_HSS) cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
cfg->f_min = 400000; cfg->f_max = min(priv->sdhc_clk, (u32)200000000); - cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - - return 0; }
#if !CONFIG_IS_ENABLED(DM_MMC) @@ -732,7 +715,6 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) struct fsl_esdhc_priv *priv; struct mmc_config *mmc_cfg; struct mmc *mmc; - int ret;
if (!cfg) return -EINVAL; @@ -769,20 +751,15 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) mmc_cfg->host_caps &= ~MMC_MODE_8BIT; #endif - ret = fsl_esdhc_init(priv, plat); - if (ret) { - debug("%s init failure\n", __func__); - free(plat); - free(priv); - return ret; - } + mmc_cfg->ops = &esdhc_ops; + + fsl_esdhc_get_cfg_common(priv, mmc_cfg);
- mmc = mmc_create(&plat->cfg, priv); + mmc = mmc_create(mmc_cfg, priv); if (!mmc) return -EIO;
priv->mmc = mmc; - return 0; }
@@ -927,11 +904,7 @@ static int fsl_esdhc_probe(struct udevice *dev) } }
- ret = fsl_esdhc_init(priv, plat); - if (ret) { - dev_err(dev, "fsl_esdhc_init failure\n"); - return ret; - } + fsl_esdhc_get_cfg_common(priv, &plat->cfg);
mmc_of_parse(dev, &plat->cfg);
Drop redundant code for non-removable feature. "non-removable" property has been read in mmc_of_parse().
Signed-off-by: Yangbo Lu yangbo.lu@nxp.com --- drivers/mmc/fsl_esdhc.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 2b7bcab..25a8fe3 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -75,7 +75,6 @@ struct fsl_esdhc_plat { * @mmc: mmc * Following is used when Driver Model is enabled for MMC * @dev: pointer for the device - * @non_removable: 0: removable; 1: non-removable * @wp_enable: 1: enable checking wp; 0: no check * @cd_gpio: gpio for card detection * @wp_gpio: gpio for write protection @@ -89,7 +88,6 @@ struct fsl_esdhc_priv { struct mmc *mmc; #endif struct udevice *dev; - int non_removable; int wp_enable; };
@@ -628,12 +626,6 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) if (CONFIG_ESDHC_DETECT_QUIRK) return 1; #endif - -#if CONFIG_IS_ENABLED(DM_MMC) - if (priv->non_removable) - return 1; -#endif - while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) udelay(1000);
@@ -870,12 +862,6 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif priv->dev = dev;
- if (dev_read_bool(dev, "non-removable")) { - priv->non_removable = 1; - } else { - priv->non_removable = 0; - } - priv->wp_enable = 1;
if (IS_ENABLED(CONFIG_CLK)) { @@ -919,8 +905,12 @@ static int fsl_esdhc_probe(struct udevice *dev)
static int fsl_esdhc_get_cd(struct udevice *dev) { + struct fsl_esdhc_plat *plat = dev_get_platdata(dev); struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE) + return 1; + return esdhc_getcd_common(priv); }
The QorIQ eSDHC on all platforms supports checking write protect state through register bit. So check it always.
Signed-off-by: Yangbo Lu yangbo.lu@nxp.com --- drivers/mmc/fsl_esdhc.c | 15 ++++----------- include/fsl_esdhc.h | 1 - 2 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 25a8fe3..bdc0ca6 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -75,7 +75,6 @@ struct fsl_esdhc_plat { * @mmc: mmc * Following is used when Driver Model is enabled for MMC * @dev: pointer for the device - * @wp_enable: 1: enable checking wp; 0: no check * @cd_gpio: gpio for card detection * @wp_gpio: gpio for write protection */ @@ -88,7 +87,6 @@ struct fsl_esdhc_priv { struct mmc *mmc; #endif struct udevice *dev; - int wp_enable; };
/* Return the XFERTYP flags for a given command and data packet */ @@ -231,12 +229,10 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, #endif if (wml_value > WML_WR_WML_MAX) wml_value = WML_WR_WML_MAX_VAL; - if (priv->wp_enable) { - if ((esdhc_read32(®s->prsstat) & - PRSSTAT_WPSPL) == 0) { - printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); - return -ETIMEDOUT; - } + + if (!(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) { + printf("Can not write to locked SD card.\n"); + return -EINVAL; }
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, @@ -722,7 +718,6 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); priv->sdhc_clk = cfg->sdhc_clk; - priv->wp_enable = cfg->wp_enable;
mmc_cfg = &plat->cfg;
@@ -862,8 +857,6 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif priv->dev = dev;
- priv->wp_enable = 1; - if (IS_ENABLED(CONFIG_CLK)) { /* Assigned clock already set clock */ ret = clk_get_by_name(dev, "per", &priv->per_clk); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index a015df1..8e8cd2c 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -168,7 +168,6 @@ struct fsl_esdhc_cfg { phys_addr_t esdhc_base; u32 sdhc_clk; u8 max_bus_width; - int wp_enable; int vs18_enable; /* Use 1.8V if set to 1 */ struct mmc_config cfg; };
Make DM and non-DM code clear using below structure. #if !CONFIG_IS_ENABLED(DM_MMC) <non-DM_MMC code> #else <DM_MMC code> #endif
Signed-off-by: Yangbo Lu yangbo.lu@nxp.com --- drivers/mmc/fsl_esdhc.c | 204 ++++++++++++++++++++++++------------------------ 1 file changed, 100 insertions(+), 104 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index bdc0ca6..8ff84aa 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -628,44 +628,6 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) return timeout > 0; }
-#if !CONFIG_IS_ENABLED(DM_MMC) -static int esdhc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_priv *priv = mmc->priv; - - return esdhc_getcd_common(priv); -} - -static int esdhc_init(struct mmc *mmc) -{ - struct fsl_esdhc_priv *priv = mmc->priv; - - return esdhc_init_common(priv, mmc); -} - -static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) -{ - struct fsl_esdhc_priv *priv = mmc->priv; - - return esdhc_send_cmd_common(priv, mmc, cmd, data); -} - -static int esdhc_set_ios(struct mmc *mmc) -{ - struct fsl_esdhc_priv *priv = mmc->priv; - - return esdhc_set_ios_common(priv, mmc); -} - -static const struct mmc_ops esdhc_ops = { - .getcd = esdhc_getcd, - .init = esdhc_init, - .send_cmd = esdhc_send_cmd, - .set_ios = esdhc_set_ios, -}; -#endif - static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv, struct mmc_config *cfg) { @@ -696,71 +658,6 @@ static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv, cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; }
-#if !CONFIG_IS_ENABLED(DM_MMC) -int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) -{ - struct fsl_esdhc_plat *plat; - struct fsl_esdhc_priv *priv; - struct mmc_config *mmc_cfg; - struct mmc *mmc; - - if (!cfg) - return -EINVAL; - - priv = calloc(sizeof(struct fsl_esdhc_priv), 1); - if (!priv) - return -ENOMEM; - plat = calloc(sizeof(struct fsl_esdhc_plat), 1); - if (!plat) { - free(priv); - return -ENOMEM; - } - - priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); - priv->sdhc_clk = cfg->sdhc_clk; - - mmc_cfg = &plat->cfg; - - if (cfg->max_bus_width == 8) { - mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | - MMC_MODE_8BIT; - } else if (cfg->max_bus_width == 4) { - mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT; - } else if (cfg->max_bus_width == 1) { - mmc_cfg->host_caps |= MMC_MODE_1BIT; - } else { - mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | - MMC_MODE_8BIT; - printf("No max bus width provided. Assume 8-bit supported.\n"); - } - -#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK - if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) - mmc_cfg->host_caps &= ~MMC_MODE_8BIT; -#endif - mmc_cfg->ops = &esdhc_ops; - - fsl_esdhc_get_cfg_common(priv, mmc_cfg); - - mmc = mmc_create(mmc_cfg, priv); - if (!mmc) - return -EIO; - - priv->mmc = mmc; - return 0; -} - -int fsl_esdhc_mmc_init(bd_t *bis) -{ - struct fsl_esdhc_cfg *cfg; - - cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); - cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; - cfg->sdhc_clk = gd->arch.sdhc_clk; - return fsl_esdhc_initialize(bis, cfg); -} -#endif - #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT void mmc_adapter_card_type_ident(void) { @@ -834,7 +731,106 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd) } #endif
-#if CONFIG_IS_ENABLED(DM_MMC) +#if !CONFIG_IS_ENABLED(DM_MMC) +static int esdhc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_priv *priv = mmc->priv; + + return esdhc_getcd_common(priv); +} + +static int esdhc_init(struct mmc *mmc) +{ + struct fsl_esdhc_priv *priv = mmc->priv; + + return esdhc_init_common(priv, mmc); +} + +static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct fsl_esdhc_priv *priv = mmc->priv; + + return esdhc_send_cmd_common(priv, mmc, cmd, data); +} + +static int esdhc_set_ios(struct mmc *mmc) +{ + struct fsl_esdhc_priv *priv = mmc->priv; + + return esdhc_set_ios_common(priv, mmc); +} + +static const struct mmc_ops esdhc_ops = { + .getcd = esdhc_getcd, + .init = esdhc_init, + .send_cmd = esdhc_send_cmd, + .set_ios = esdhc_set_ios, +}; + +int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) +{ + struct fsl_esdhc_plat *plat; + struct fsl_esdhc_priv *priv; + struct mmc_config *mmc_cfg; + struct mmc *mmc; + + if (!cfg) + return -EINVAL; + + priv = calloc(sizeof(struct fsl_esdhc_priv), 1); + if (!priv) + return -ENOMEM; + plat = calloc(sizeof(struct fsl_esdhc_plat), 1); + if (!plat) { + free(priv); + return -ENOMEM; + } + + priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); + priv->sdhc_clk = cfg->sdhc_clk; + + mmc_cfg = &plat->cfg; + + if (cfg->max_bus_width == 8) { + mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | + MMC_MODE_8BIT; + } else if (cfg->max_bus_width == 4) { + mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT; + } else if (cfg->max_bus_width == 1) { + mmc_cfg->host_caps |= MMC_MODE_1BIT; + } else { + mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | + MMC_MODE_8BIT; + printf("No max bus width provided. Assume 8-bit supported.\n"); + } + +#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK + if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) + mmc_cfg->host_caps &= ~MMC_MODE_8BIT; +#endif + mmc_cfg->ops = &esdhc_ops; + + fsl_esdhc_get_cfg_common(priv, mmc_cfg); + + mmc = mmc_create(mmc_cfg, priv); + if (!mmc) + return -EIO; + + priv->mmc = mmc; + return 0; +} + +int fsl_esdhc_mmc_init(bd_t *bis) +{ + struct fsl_esdhc_cfg *cfg; + + cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); + cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; + cfg->sdhc_clk = gd->arch.sdhc_clk; + return fsl_esdhc_initialize(bis, cfg); +} +#else /* DM_MMC */ #ifndef CONFIG_PPC #include <asm/arch/clock.h> #endif
Here is the CI build result. https://travis-ci.org/yangbolu1991/u-boot-test/builds/605435128
I had verified both SD and eMMC with both DM_MMC and non-DM_MMC modes. Thanks a lot.
Best regards, Yangbo Lu
-----Original Message----- From: Yangbo Lu yangbo.lu@nxp.com Sent: Thursday, October 31, 2019 6:54 PM To: u-boot@lists.denx.de; Peng Fan peng.fan@nxp.com Cc: Y.b. Lu yangbo.lu@nxp.com Subject: [PATCH 0/7] mmc: fsl_esdhc: clean up and shrink the driver
This patch-set is to clean up and shrink the fsl_esdhc driver.
Yangbo Lu (7): mmc: fsl_esdhc: drop controller initialization in fsl_esdhc_init() mmc: fsl_esdhc: fix voltage validation mmc: fsl_esdhc: clean up bus width configuration code mmc: fsl_esdhc: convert to use fsl_esdhc_get_cfg_common() mmc: fsl_esdhc: drop redundant code for non-removable feature mmc: fsl_esdhc: always check write protect state mmc: fsl_esdhc: clean up DM and non-DM code
drivers/mmc/fsl_esdhc.c | 370 ++++++++++++++++-------------------------------- include/fsl_esdhc.h | 14 +- 2 files changed, 129 insertions(+), 255 deletions(-)
-- 2.7.4
participants (2)
-
Y.b. Lu -
Yangbo Lu