[U-Boot] spd_dram.c for mpc83xx broken
The spd code for mpc83xx is so broken it isn't funny. This is what I had to do to get my Micron MT47H64M16-3. This isn't against current u-boot, but it is a start.
Jocke
PS. Sorry for the attachment, trying to use Lotus Notes as my new E-mail client and I can't find how to insert a file :(
On Tue, 17 Feb 2009 20:25:03 +0100 Joakim Tjernlund Joakim.Tjernlund@transmode.se wrote:
The spd code for mpc83xx is so broken it isn't funny. This is what I had to do to get my Micron MT47H64M16-3. This isn't against current u-boot, but it is a start.
well it applies, but it also nuked the first board I tried it on. For any new ddr work on 83xx, I'd suggest starting with porting the new common mpc8xxx ddr code.
Kim
Kim Phillips kim.phillips@freescale.com wrote on 18/02/2009 02:35:50:
On Tue, 17 Feb 2009 20:25:03 +0100 Joakim Tjernlund Joakim.Tjernlund@transmode.se wrote:
The spd code for mpc83xx is so broken it isn't funny. This is what I
had
to do to get my Micron MT47H64M16-3. This isn't against current u-boot, but it is a
start.
well it applies, but it also nuked the first board I tried it on. For any new ddr work on 83xx, I'd suggest starting with porting the new common mpc8xxx ddr code.
Won't be upgrading to latest u-boot any time soon, too much code churn.
There are a few chip specific bits in there so you probably need to revert a few chunks. Looked at the new code and it still looks wrong in a few places. Try with only these hunks applied:
ddr->cs_config[0] = ( 1 << 31 - | (odt_rd_cfg << 20) - | (odt_wr_cfg << 16) + | (odt_rd_cfg << 22) + | (odt_wr_cfg << 18) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) );
---- twr_clk = picos_to_clk(spd.twr * 250); twtr_clk = picos_to_clk(spd.twtr * 250); + if (twtr_clk < 2) + twtr_clk = 2; /* Must be at least 2 */
---- /* Convert SPD value from quarter nanos to picos. */ trtp_clk = picos_to_clk(spd.trtp * 250); - + trtp_clk += add_lat;
----- ddr->sdram_mode = (0 + | (1 << (16 + 14)) /* MRS 01 */ | (1 << (16 + 10)) /* DQS Differential disable */
On Tue, 17 Feb 2009 20:25:03 +0100 Joakim Tjernlund Joakim.Tjernlund@transmode.se wrote:
The spd code for mpc83xx is so broken it isn't funny. This is what I
had
to do to get my Micron MT47H64M16-3. This isn't against current u-boot, but it is a
start.
well it applies, but it also nuked the first board I tried it on. For any new ddr work on 83xx, I'd suggest starting with porting the new common mpc8xxx ddr code.
Guys, I have a hard time figuring out the clk adjust, cpo, wrdata delay and 2T parameters to the DDR2 controller. How do I calculate these?
Also, how does the NUM_PR setting relate to Tras?
Jocke
participants (3)
-
Joakim Tjernlund -
Kim Phillips -
Liu Dave-R63238