T4/B4 SoC's have a different version of ISBC. The secure boot functionality is different with the new version of ISBC compared to the earlier SoC's. So the version information is added in file config_mpc85xx.h

Signed-off-by: Ruchika Gupta ruchika.gupta@freescale.com Signed-off-by: Aneesh Bansal aneesh.bansal@freescale.com --- README | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 9 +++++++++ 2 files changed, 12 insertions(+)

Changes from v1: Updated the commit message

diff --git a/README b/README index aea82be..6c3a8d1 100644 --- a/README +++ b/README @@ -423,6 +423,9 @@ The following options need to be configured: CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT This value denotes start offset of DSP CCSR space.

+ CONFIG_SYS_FSL_ISBC_VER + This value indicates the major ISBC version on the platform. + CONFIG_SYS_FSL_SINGLE_SOURCE_CLK Single Source Clock is clocking mode present in some of FSL SoC's. In this mode, a single differential clock is used to supply diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 54ce2f0..ba5b6fe 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -151,6 +151,7 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ISBC_VER 1 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10

/* P1011 is single core version of P1020 */ @@ -383,6 +384,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004849 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 +#define CONFIG_SYS_FSL_ISBC_VER 1

#elif defined(CONFIG_PPC_P3041) #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -421,6 +423,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005812 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 +#define CONFIG_SYS_FSL_ISBC_VER 1

#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -470,6 +473,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005812 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 +#define CONFIG_SYS_FSL_ISBC_VER 1

#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ @@ -504,6 +508,7 @@ #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 +#define CONFIG_SYS_FSL_ISBC_VER 1

#elif defined(CONFIG_PPC_P5040) #define CONFIG_SYS_PPC64 @@ -536,6 +541,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #define CONFIG_SYS_FSL_ERRATUM_A005812 +#define CONFIG_SYS_FSL_ISBC_VER 1

#elif defined(CONFIG_BSC9131) #define CONFIG_MAX_CPUS 1 @@ -575,6 +581,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 +#define CONFIG_SYS_FSL_ISBC_VER 1

#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) #define CONFIG_E6500 @@ -631,6 +638,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_PCI_VER_3_X +#define CONFIG_SYS_FSL_ISBC_VER 2

#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) #define CONFIG_E6500 @@ -657,6 +665,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ISBC_VER 2

#ifdef CONFIG_PPC_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4