From: qianfan Zhao qianfanguijin@163.com

spi-sunxi driver will init pins based on "pinctrl-0", but the implementation is very limited.

Adding an Kconfig option if you really need this feature, or disable it and config pinmux at board's board_init.

Signed-off-by: qianfan Zhao qianfanguijin@163.com --- drivers/spi/Kconfig | 10 ++++++++++ drivers/spi/spi-sunxi.c | 4 ++++ 2 files changed, 14 insertions(+)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d07e9a28af..9c2fe96ac1 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -382,6 +382,16 @@ config SPI_SUNXI

Same controller driver can reuse in all Allwinner SoC variants.

+config SUNXI_SPI_PARSE_PINS + bool "Enable sun4i_spi_parse_pins feature" + depends on SPI_SUNXI + default y + help + Enable sun4i_spi_parse_pins support when spi driver probing. + + The default pinmux configuration for SUN50I is SUN50I_GPC_SPI0(4), + and SUNXI_GPC_SPI0(3) for others. + config STM32_QSPI bool "STM32F7 QSPI driver" depends on STM32F4 || STM32F7 || ARCH_STM32MP diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index bc2f544e86..f48562a59b 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -180,6 +180,7 @@ static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable) writel(reg, SPI_REG(priv, SPI_TCR)); }

+#if CONFIG_IS_ENABLED(SUNXI_SPI_PARSE_PINS) static int sun4i_spi_parse_pins(struct udevice *dev) { const void *fdt = gd->fdt_blob; @@ -259,6 +260,7 @@ static int sun4i_spi_parse_pins(struct udevice *dev) } return 0; } +#endif /* CONFIG_IS_ENABLED(SUNXI_SPI_PARSE_PINS) */

static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable) { @@ -506,7 +508,9 @@ static int sun4i_spi_probe(struct udevice *bus) return ret; }

+#if CONFIG_IS_ENABLED(SUNXI_SPI_PARSE_PINS) sun4i_spi_parse_pins(bus); +#endif

priv->variant = plat->variant; priv->base = plat->base;