QorIQ U-Boot binary for SD card booting compiled during build process (either u-boot.bin or u-boot-with-spl.bin) cannot be directly loaded by QorIQ pre-PBL BootROM. Compiled U-Boot binary first needs to be processed by Freescale boot_format tool as described in doc/README.mpc85xx-sd-spi-boot

BootROM requires that image on SD card must contain special boot sector. Implement support for generating this special boot sector directly in U-Boot start code. Boot sector needs to be at the beginning of the image, so when compiling only proper U-Boot without SPL then it needs to be in proper U-Boot. When compiling SPL with proper U-Boot then it needs to be only in SPL.

Support can be enabled by a new config option FSL_PREPBL_ESDHC_BOOT_SECTOR. Via other two additional options FSL_PREPBL_ESDHC_BOOT_SECTOR_START and FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA it is possible to tune how final U-Boot image could be stored on the SD card.

Signed-off-by: Pali Rohár pali@kernel.org

--- Changes in v2: * Replace addresses in start.S by named constants * Move bootsect from .text section to separate data section .bootsect which would be before TEXT_BASE. This boot sector is not used by the U-Boot nor SPL and it even is not loaded by BootROM into larget area, so it does not have to occupe data in TEXT_BASE. With this change U-Boot and SPL stay on the same addresses as before this change. --- arch/powerpc/cpu/mpc85xx/Kconfig | 53 ++++++++++++++ arch/powerpc/cpu/mpc85xx/start.S | 94 +++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 8 +++ arch/powerpc/cpu/mpc85xx/u-boot.lds | 8 +++ 4 files changed, 163 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index c308447d493a..6f8b7593d250 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -12,6 +12,59 @@ config CMD_ERRATA This enables the 'errata' command which displays a list of errata work-arounds which are enabled for the current board.

+config FSL_PREPBL_ESDHC_BOOT_SECTOR + bool "Generate QorIQ pre-PBL eSDHC boot sector" + depends on MPC85xx + depends on SYS_EXTRA_OPTIONS = SDCARD + help + With this option final image would have prepended QorIQ pre-PBL eSDHC + boot sector suitable for SD card images. This boot sector instruct + BootROM to configure L2 SRAM and eSDHC then load image from SD card + into L2 SRAM and finally jump to image entry point. + + This is alternative to Freescale boot_format tool, but works only for + SD card images and only for L2 SRAM booting. U-Boot images generated + with this option should not passed to boot_format tool. + + For other configuration like booting from eSPI or configuring SDRAM + please use Freescale boot_format tool without this option. See file + doc/README.mpc85xx-sd-spi-boot + +config FSL_PREPBL_ESDHC_BOOT_SECTOR_START + int "QorIQ pre-PBL eSDHC boot sector start offset" + depends on FSL_PREPBL_ESDHC_BOOT_SECTOR + range 0 23 + default 0 + help + QorIQ pre-PBL eSDHC boot sector may be located on one of the first + 24 SD card sectors. Select SD card sector on which final U-Boot + image (with this boot sector) would be installed. + + By default first SD card sector (0) is used. But this may be changed + to allow installing U-Boot image on some partition (with fixed start + sector). + + Please note that any sector on SD card prior this boot sector must + not contain ASCII "BOOT" bytes at sector offset 0x40. + +config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA + int "Relative data sector for QorIQ pre-PBL eSDHC boot sector" + depends on FSL_PREPBL_ESDHC_BOOT_SECTOR + default 1 + range 1 8388607 + help + Select data sector from the beginning of QorIQ pre-PBL eSDHC boot + sector on which would be stored raw U-Boot image. + + By default is it second sector (1) which is the first available free + sector (on the first sector is stored boot sector). It can be any + sector number which offset in bytes can be expressed by 32-bit number. + + In case this final U-Boot image (with this boot sector) is put on + the FAT32 partition into reserved boot area, this data sector needs + to be at least 2 (third sector) because FAT32 use second sector for + its data. + choice prompt "Target select" optional diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 796a58b929ec..3006d569b387 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -56,6 +56,100 @@ GOT_ENTRY(__bss_start) END_GOT

+#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + +/* Maximal size of the image */ +#ifdef CONFIG_SPL_BUILD +#define MAX_IMAGE_SIZE (CONFIG_SPL_MAX_SIZE - (CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512)) +#else +#define MAX_IMAGE_SIZE CONFIG_SYS_L2_SIZE +#endif + +#if defined(CONFIG_SPL_BUILD) && CONFIG_SPL_MAX_SIZE < CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 +#error "CONFIG_SPL_MAX_SIZE is too small for CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA" +#endif + +#if MAX_IMAGE_SIZE > CONFIG_SYS_L2_SIZE +#error "Image is too big" +#endif + +#define DIV_ROUND_UP(a, b) (((a) + (b) - 1) / (b)) +#define ALIGN(x, a) (DIV_ROUND_UP(x, a) * (a)) + +/* Definitions from C header file asm/immap_85xx.h */ + +#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 + +#define MPC85xx_L2CTL 0x000 +#define MPC85xx_L2CTL_L2E 0x80000000 +#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 + +#define MPC85xx_L2SRBAR0 0x100 + +#define MPC85xx_L2ERRDIS 0xe44 +#define MPC85xx_L2ERRDIS_MBECC 0x00000008 +#define MPC85xx_L2ERRDIS_SBECC 0x00000004 + +/* Definitions from C header file fsl_esdhc.h */ + +#define ESDHCCTL 0x0002e40c +#define ESDHCCTL_SNOOP 0x00000040 + +/* + * QorIQ pre-PBL eSDHC boot sector: + * Instruct BootROM to configure L2 SRAM and eSDHC then load image + * from SD card into L2 SRAM and finally jump to image entry point. + */ + .section .bootsect, "a" + .globl bootsect + +bootsect: + .org 0x40 /* BOOT signature */ + .ascii "BOOT" + + .org 0x48 /* Number of bytes to be copied, must be multiple of block size (512) */ + .long ALIGN(MAX_IMAGE_SIZE, 512) + + .org 0x50 /* Source address from the beginning of boot sector in byte address format, must be multiple of block size (512) */ + .long (CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_START + CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA) * 512 + + .org 0x58 /* Target address in the system's local memory address space */ + .long CONFIG_SYS_MONITOR_BASE + + .org 0x60 /* Execution starting address */ + .long _start + + .org 0x68 /* Number of configuration data pairs */ + .long DIV_ROUND_UP(.Lconf_pair_end - .Lconf_pair_start, 8) + + .org 0x80 /* Start of configuration */ + .Lconf_pair_start: + + .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */ + .long CONFIG_SYS_INIT_L2_ADDR + + .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */ + .long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC + + .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */ + .long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE + + .long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */ + .long ESDHCCTL_SNOOP + + .long 0x40000001 /* Command: Delay in 8 CCB clocks */ + .long 256 + + .long 0x80000001 /* End of configuration */ + .Lconf_pair_end: + + .org 0x1b8 /* Reserved for MBR/DBR */ + .org 0x200 /* End of boot sector */ + +#endif +#endif + /* * e500 Startup -- after reset only the last 4KB of the effective * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 6fd0da9f39b1..6b3c84a8d5c4 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -12,6 +12,14 @@ OUTPUT_ARCH(powerpc)

SECTIONS { +/* Optional boot sector */ +#if defined(CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR) + .bootsect IMAGE_TEXT_BASE - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 : { + KEEP(*(.bootsect)) + . = CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512; + } +#endif + . = IMAGE_TEXT_BASE; .text : { /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 9f422810bb5d..cb32aeefdc79 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -16,6 +16,14 @@ ENTRY(_start)

SECTIONS { + /* Optional boot sector */ +#if defined(CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR) && !defined(CONFIG_SPL) + .bootsect CONFIG_SYS_TEXT_BASE - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 : { + KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootsect)) + . = CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512; + } +#endif + /* Read-only sections, merged into text segment: */ .text : {

Correctly calculate offsets between SPL and proper U-Boot when new config option CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR for generating eSDHC boot sector is enabled. Otherwise SPL would not be able to boot proper U-Boot.

Signed-off-by: Pali Rohár pali@kernel.org --- Changes in v2: * rebase on top of master branch, commit 85eb5ac6efee878f3c2ab3269286250e187ca10c --- include/configs/p1_p2_rdb_pc.h | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index ba04029df8d8..d2787136681b 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -80,7 +80,11 @@ #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MMC_U_BOOT_START CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR +#define CONFIG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) +#else #define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#endif #elif defined(CONFIG_SPIFLASH) #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_SYS_TEXT_BASE

On 8/18/2022 5:03 AM, Pali Rohár wrote:

On Monday 01 August 2022 14:50:12 Pali Rohár wrote:

...

Correctly calculate offsets between SPL and proper U-Boot when new config option CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR for generating eSDHC boot sector is enabled. Otherwise SPL would not be able to boot proper U-Boot.

Signed-off-by: Pali Rohár pali@kernel.org

Changes in v2:

• rebase on top of master branch, commit 85eb5ac6efee878f3c2ab3269286250e187ca10c

PING? Are we going to wait until this patch does not apply anymore again??

Applied, sorry for late.

Thanks, Peng.

...

---

include/configs/p1_p2_rdb_pc.h | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index ba04029df8d8..d2787136681b 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -80,7 +80,11 @@ #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MMC_U_BOOT_START CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR +#define CONFIG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) +#else #define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#endif #elif defined(CONFIG_SPIFLASH) #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)

#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_SYS_TEXT_BASE

2.20.1