[U-Boot] [PATCH] spi: zynq_qspi: Add configuration to disable LQSPI feature
When the Zynq Boot ROM code loads the payload from QSPI it uses the LQSPI feature of the QSPI device, however it does not clean up its configuration before handing over to the payload which leaves the device confgured to by-pass the standard non-linear operating mode.
This ensures the Linear QSPI mode is disabled before re-enabling the device.
Signed-off-by: Nathan Rossi nathan@nathanrossi.com Cc: Jagan Teki jteki@openedev.com Cc: Siva Durga Prasad Paladugu sivadur@xilinx.com Cc: Simon Glass sjg@chromium.org --- drivers/spi/zynq_qspi.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 5825c6d..b98663c 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -30,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ +#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
/* zynq qspi Transmit Data Register */ #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */ @@ -68,6 +69,9 @@ struct zynq_qspi_regs { u32 txd1r; /* 0x80 */ u32 txd2r; /* 0x84 */ u32 txd3r; /* 0x88 */ + u32 reserved1[5]; + u32 lqspicfg; /* 0xA0 */ + u32 lqspists; /* 0xA4 */ };
/* zynq qspi platform data */ @@ -143,6 +147,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) ZYNQ_QSPI_CR_MSTREN_MASK; writel(confr, ®s->cr);
+ /* Disable the LQSPI feature */ + confr = readl(®s->lqspicfg); + confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK; + writel(confr, ®s->lqspicfg); + /* Enable SPI */ writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); }
The Device Model sequence alias feature is required by some Uclasses.
Specifically SPI which picks the bus to use based on the sequence. Without this the SPI Uclass will not probe any bus and will fail which prevents SPL from using SPI flash as a boot location.
Signed-off-by: Nathan Rossi nathan@nathanrossi.com Cc: Simon Glass sjg@chromium.org Cc: Masahiro Yamada yamada.masahiro@socionext.com Cc: Linus Walleij linus.walleij@linaro.org --- include/config_uncmd_spl.h | 1 - 1 file changed, 1 deletion(-)
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index 6e299f6..3b198ae 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -29,7 +29,6 @@ #endif
#undef CONFIG_DM_WARN -#undef CONFIG_DM_SEQ_ALIAS #undef CONFIG_DM_STDIO
#endif /* CONFIG_SPL_BUILD */
Hi Nathan,
On 8 December 2015 at 07:44, Nathan Rossi nathan@nathanrossi.com wrote:
The Device Model sequence alias feature is required by some Uclasses.
Specifically SPI which picks the bus to use based on the sequence. Without this the SPI Uclass will not probe any bus and will fail which prevents SPL from using SPI flash as a boot location.
Signed-off-by: Nathan Rossi nathan@nathanrossi.com Cc: Simon Glass sjg@chromium.org Cc: Masahiro Yamada yamada.masahiro@socionext.com Cc: Linus Walleij linus.walleij@linaro.org
include/config_uncmd_spl.h | 1 - 1 file changed, 1 deletion(-)
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index 6e299f6..3b198ae 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -29,7 +29,6 @@ #endif
#undef CONFIG_DM_WARN -#undef CONFIG_DM_SEQ_ALIAS #undef CONFIG_DM_STDIO
#endif /* CONFIG_SPL_BUILD */
2.6.2
We'd like to drop this file. Can you instead please add CONFIG_SPL_DM_SEQ_ALIAS as a new Kconfig. There is only one place in the code (device.c) that you need to change. I think for now it should default to n, but you could enable it for your board? I'm not sure of the size impact of enabling it by default.
Regards, Simon
Update the ZYBO device tree and enable config options that relate to the added devices in the device tree.
Signed-off-by: Nathan Rossi nathan@nathanrossi.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Michal Simek monstr@monstr.eu Cc: Simon Glass sjg@chromium.org --- arch/arm/dts/zynq-zybo.dts | 18 ++++++++++++++++++ configs/zynq_zybo_defconfig | 3 +++ include/configs/zynq_zybo.h | 1 + 3 files changed, 22 insertions(+)
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index dcfc00e..fbbb891 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -16,6 +16,8 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; + mmc0 = &sdhci0; };
memory { @@ -28,6 +30,10 @@ stdout-path = "serial0:115200n8"; };
+ usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; };
&clkc { @@ -45,6 +51,7 @@ };
&sdhci0 { + u-boot,dm-pre-reloc; status = "okay"; };
@@ -52,3 +59,14 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 6f0bd0b..d443e92 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -17,3 +17,6 @@ CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_ZYNQ_QSPI=y diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index 5d1a9d5..c53ba79 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -15,6 +15,7 @@
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_BOOT_FREEBSD
On 8.12.2015 15:44, Nathan Rossi wrote:
Update the ZYBO device tree and enable config options that relate to the added devices in the device tree.
Signed-off-by: Nathan Rossi nathan@nathanrossi.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Michal Simek monstr@monstr.eu Cc: Simon Glass sjg@chromium.org
arch/arm/dts/zynq-zybo.dts | 18 ++++++++++++++++++ configs/zynq_zybo_defconfig | 3 +++ include/configs/zynq_zybo.h | 1 + 3 files changed, 22 insertions(+)
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index dcfc00e..fbbb891 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -16,6 +16,8 @@ aliases { ethernet0 = &gem0; serial0 = &uart1;
spi0 = &qspi;mmc0 = &sdhci0;};
memory {
@@ -28,6 +30,10 @@ stdout-path = "serial0:115200n8"; };
- usb_phy0: phy0 {
compatible = "usb-nop-xceiv";#phy-cells = <0>;- };
};
&clkc { @@ -45,6 +51,7 @@ };
&sdhci0 {
- u-boot,dm-pre-reloc; status = "okay";
};
@@ -52,3 +59,14 @@ u-boot,dm-pre-reloc; status = "okay"; };
+&qspi {
- u-boot,dm-pre-reloc;
- status = "okay";
+};
+&usb0 {
- status = "okay";
- dr_mode = "host";
- usb-phy = <&usb_phy0>;
+}; diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 6f0bd0b..d443e92 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -17,3 +17,6 @@ CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_ZYNQ_QSPI=y diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index 5d1a9d5..c53ba79 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -15,6 +15,7 @@
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_BOOT_FREEBSD
Applied. There is a conflict with the patch I sent before this one but I will resolve it.
Thanks, Michal
Clean up the param checking, removing some code paths that will never happen.
Signed-off-by: Nathan Rossi nathan@nathanrossi.com Cc: Michal Simek michal.simek@xilinx.com Cc: Tom Rini trini@konsulko.com --- tools/zynqimage.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/tools/zynqimage.c b/tools/zynqimage.c index 25f558d..c43bd5d 100644 --- a/tools/zynqimage.c +++ b/tools/zynqimage.c @@ -212,8 +212,7 @@ static int zynqimage_check_params(struct image_tool_params *params) return -1; }
- return !((params->lflag || params->dflag) || - (params->dflag && params->eflag)); + return !(params->lflag || params->dflag); }
static int zynqimage_check_image_types(uint8_t type)
On Wed, Dec 09, 2015 at 12:44:43AM +1000, Nathan Rossi wrote:
Clean up the param checking, removing some code paths that will never happen.
Signed-off-by: Nathan Rossi nathan@nathanrossi.com Cc: Michal Simek michal.simek@xilinx.com Cc: Tom Rini trini@konsulko.com
Reported-by: Coverity (CID 133251) Reviewed-by: Tom Rini trini@konsulko.com
On 8.12.2015 16:03, Tom Rini wrote:
On Wed, Dec 09, 2015 at 12:44:43AM +1000, Nathan Rossi wrote:
Clean up the param checking, removing some code paths that will never happen.
Signed-off-by: Nathan Rossi nathan@nathanrossi.com Cc: Michal Simek michal.simek@xilinx.com Cc: Tom Rini trini@konsulko.com
Reported-by: Coverity (CID 133251) Reviewed-by: Tom Rini trini@konsulko.com
Applied.
Thanks, Michal
On 8.12.2015 15:44, Nathan Rossi wrote:
When the Zynq Boot ROM code loads the payload from QSPI it uses the LQSPI feature of the QSPI device, however it does not clean up its configuration before handing over to the payload which leaves the device confgured to by-pass the standard non-linear operating mode.
This ensures the Linear QSPI mode is disabled before re-enabling the device.
Signed-off-by: Nathan Rossi nathan@nathanrossi.com Cc: Jagan Teki jteki@openedev.com Cc: Siva Durga Prasad Paladugu sivadur@xilinx.com Cc: Simon Glass sjg@chromium.org
drivers/spi/zynq_qspi.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 5825c6d..b98663c 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -30,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ +#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
/* zynq qspi Transmit Data Register */ #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */ @@ -68,6 +69,9 @@ struct zynq_qspi_regs { u32 txd1r; /* 0x80 */ u32 txd2r; /* 0x84 */ u32 txd3r; /* 0x88 */
- u32 reserved1[5];
- u32 lqspicfg; /* 0xA0 */
- u32 lqspists; /* 0xA4 */
};
/* zynq qspi platform data */ @@ -143,6 +147,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) ZYNQ_QSPI_CR_MSTREN_MASK; writel(confr, ®s->cr);
- /* Disable the LQSPI feature */
- confr = readl(®s->lqspicfg);
- confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
- writel(confr, ®s->lqspicfg);
- /* Enable SPI */ writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
}
Applied to zynq tree.
Thanks, Michal
participants (5)
-
Michal Simek -
Michal Simek -
Nathan Rossi -
Simon Glass -
Tom Rini