[U-Boot] [PATCH 0/8] MPC85xx: Support for TQM8548-AG and TQM8548-BE
The following patch series adds support for the TQM8548-AG and TQM8548-BE modules from TQ Components GmbH (http://www.tqc.de) and fixes a few issues with TQM85xx in general.
A second patch series for FSL UPM NAND will follow to support the NAND multi-chip device on the TQM8548-BE.
Wolfgang.
As the reset vector is located at 0xfffffffc, all flash sectors from the beginning of the U-Boot binary to 0xffffffff must be protected. On the TQM8548-AG having small sectors at the end of the flash it happened that the last two sector were not protected and an "erase all" left an un-bootable system behind:
Bank # 2: CFI conformant FLASH (32 x 16) Size: 32 MB in 270 Sectors AMD Standard command set, Manufacturer ID: 0xEC, Device ID: 0x257E Erase timeout: 8192 ms, write timeout: 1 ms
FFFA0000 E RO FFFC0000 RO FFFE0000 RO FFFE4000 RO FFFE8000 RO FFFEC000 RO FFFF0000 RO FFFF4000 RO FFFF8000 E FFFFC000
The same bug seems to be in drivers/mtd/cfi_flash.c:flash_init() and many board BSPs as well.
Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- board/tqc/tqm85xx/tqm85xx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
Index: u-boot/board/tqc/tqm85xx/tqm85xx.c =================================================================== --- u-boot.orig/board/tqc/tqm85xx/tqm85xx.c +++ u-boot/board/tqc/tqm85xx/tqm85xx.c @@ -315,8 +315,7 @@ int misc_init_r (void)
/* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, 0xffffffff, &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
The TQM8548_AG module does not have the standard PCI/PCI-X interface connected but just the PCI Express interface . So far it was not possible to disable it without disabling the complete PCI interface (CONFIG_PCI) including PCI Express.
Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- board/tqc/tqm85xx/tqm85xx.c | 12 ++++++------ include/configs/TQM85xx.h | 9 +++++---- 2 files changed, 11 insertions(+), 10 deletions(-)
Index: u-boot/board/tqc/tqm85xx/tqm85xx.c =================================================================== --- u-boot.orig/board/tqc/tqm85xx/tqm85xx.c +++ u-boot/board/tqc/tqm85xx/tqm85xx.c @@ -540,9 +540,9 @@ static int first_free_busno; extern int fsl_pci_setup_inbound_windows(struct pci_region *r); extern void fsl_pci_init(struct pci_controller *hose);
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +#ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; -#endif /* CONFIG_PCI || CONFIG_PCI1 */ +#endif /* CONFIG_PCI1 */
#ifdef CONFIG_PCIE1 static struct pci_controller pcie1_hose; @@ -551,7 +551,7 @@ static struct pci_controller pcie1_hose; static inline void init_pci1(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +#ifdef CONFIG_PCI1 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; @@ -626,9 +626,9 @@ static inline void init_pci1(void) } else { puts ("PCI1: disabled\n"); } -#else /* !(CONFIG_PCI || CONFIG_PCI1) */ +#else /* !CONFIG_PCI1 */ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ -#endif /* CONFIG_PCI || CONFIG_PCI1) */ +#endif /* CONFIG_PCI1 */ }
static inline void init_pcie1(void) @@ -707,7 +707,7 @@ void ft_board_setup (void *blob, bd_t *b { ft_cpu_setup (blob, bd);
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +#ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCIE1 Index: u-boot/include/configs/TQM85xx.h =================================================================== --- u-boot.orig/include/configs/TQM85xx.h +++ u-boot/include/configs/TQM85xx.h @@ -42,13 +42,14 @@ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
#define CONFIG_PCI +#define CONFIG_PCI1 /* PCI/PCI-X controller */ +#ifdef CONFIG_TQM8548 +#define CONFIG_PCIE1 /* PCI Express interface */ +#endif + #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */ -#ifdef CONFIG_TQM8548 -#define CONFIG_PCI1 -#define CONFIG_PCIE1 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#endif
#define CONFIG_TSEC_ENET /* tsec ethernet support */
The TQM8548_BE is a variant of the TQM8548 module with NAND and CAN interface. With NAND support, the image is significantly larger and TEXT_BASE is adjusted accordingly. U-Boot can be built for this module with "$ make TQM8548_BE_config".
Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- MAKEALL | 1 + Makefile | 11 +++++++---- board/tqc/tqm85xx/config.mk | 6 ++++-- include/configs/TQM85xx.h | 12 ++++++++++-- 4 files changed, 22 insertions(+), 8 deletions(-)
Index: u-boot/Makefile =================================================================== --- u-boot.orig/Makefile +++ u-boot/Makefile @@ -2479,16 +2479,19 @@ stxssa_4M_config: unconfig TQM8540_config \ TQM8541_config \ TQM8548_config \ +TQM8548_BE_config \ TQM8555_config \ TQM8560_config: unconfig @mkdir -p $(obj)include - @CTYPE=$(subst TQM,,$(@:_config=)); \ - $(XECHO) "... TQM"$${CTYPE}; \ + @BTYPE=$(@:_config=); \ + CTYPE=$(subst TQM,,$(subst _BE,,$(@:_config=))); \ + $(XECHO) "... "$${BTYPE}" (MPC"$${CTYPE}")"; \ echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \ - echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \ + echo "#define CONFIG_$${BTYPE}">>$(obj)include/config.h; \ echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \ - echo "#define CONFIG_BOARDNAME "TQM$${CTYPE}"">>$(obj)include/config.h; + echo "#define CONFIG_BOARDNAME "$${BTYPE}"">>$(obj)include/config.h; @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc + @echo "CONFIG_$(@:_config=) = y">>$(obj)include/config.mk;
XPEDITE5200_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes Index: u-boot/include/configs/TQM85xx.h =================================================================== --- u-boot.orig/include/configs/TQM85xx.h +++ u-boot/include/configs/TQM85xx.h @@ -41,6 +41,10 @@ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
+#if defined(CONFIG_TQM8548_BE) +#define CONFIG_TQM8548 +#endif + #define CONFIG_PCI #define CONFIG_PCI1 /* PCI/PCI-X controller */ #ifdef CONFIG_TQM8548 @@ -71,7 +75,9 @@ * Warning: NAND support will likely increase the U-Boot image size * to more than 256 KB. Please adjust TEXT_BASE if necessary. */ -#undef CONFIG_NAND +#ifdef CONFIG_TQM8548_BE +#define CONFIG_NAND +#endif
/* * MPC8540 and MPC8548 don't have CPM module @@ -82,7 +88,9 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#undef CONFIG_CAN_DRIVER /* CAN Driver support */ +#ifdef CONFIG_TQM8548_BE +#define CONFIG_CAN_DRIVER /* CAN Driver support */ +#endif
/* * sysclk for MPC85xx Index: u-boot/board/tqc/tqm85xx/config.mk =================================================================== --- u-boot.orig/board/tqc/tqm85xx/config.mk +++ u-boot/board/tqc/tqm85xx/config.mk @@ -23,7 +23,9 @@
# # tqm85xx board -# default CCARBAR is at 0xff700000 -# assume U-Boot is less than 256k # +ifeq ($(CONFIG_TQM8548_BE),y) +TEXT_BASE = 0xfff80000 +else TEXT_BASE = 0xfffc0000 +endif Index: u-boot/MAKEALL =================================================================== --- u-boot.orig/MAKEALL +++ u-boot/MAKEALL @@ -387,6 +387,7 @@ LIST_85xx=" \ TQM8540 \ TQM8541 \ TQM8548 \ + TQM8548_BE \ TQM8555 \ TQM8560 \ XPEDITE5200 \
The TQM8548_AG is a variant of the TQM8548 module with 1 GiB memory, CAN and without PCI/PCI-X and RTC. U-Boot can be built for this module with "$ make TQM8548_AG_config".
Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- MAKEALL | 1 + Makefile | 3 ++- include/configs/TQM85xx.h | 11 +++++++++-- 3 files changed, 12 insertions(+), 3 deletions(-)
Index: u-boot/Makefile =================================================================== --- u-boot.orig/Makefile +++ u-boot/Makefile @@ -2479,12 +2479,13 @@ stxssa_4M_config: unconfig TQM8540_config \ TQM8541_config \ TQM8548_config \ +TQM8548_AG_config \ TQM8548_BE_config \ TQM8555_config \ TQM8560_config: unconfig @mkdir -p $(obj)include @BTYPE=$(@:_config=); \ - CTYPE=$(subst TQM,,$(subst _BE,,$(@:_config=))); \ + CTYPE=$(subst TQM,,$(subst _AG,,$(subst _BE,,$(@:_config=)))); \ $(XECHO) "... "$${BTYPE}" (MPC"$${CTYPE}")"; \ echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \ echo "#define CONFIG_$${BTYPE}">>$(obj)include/config.h; \ Index: u-boot/include/configs/TQM85xx.h =================================================================== --- u-boot.orig/include/configs/TQM85xx.h +++ u-boot/include/configs/TQM85xx.h @@ -41,12 +41,14 @@ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
-#if defined(CONFIG_TQM8548_BE) +#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) #define CONFIG_TQM8548 #endif
#define CONFIG_PCI +#ifndef CONFIG_TQM8548_AG #define CONFIG_PCI1 /* PCI/PCI-X controller */ +#endif #ifdef CONFIG_TQM8548 #define CONFIG_PCIE1 /* PCI Express interface */ #endif @@ -88,7 +90,7 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#ifdef CONFIG_TQM8548_BE +#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) #define CONFIG_CAN_DRIVER /* CAN Driver support */ #endif
@@ -144,6 +146,9 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#ifdef CONFIG_TQM8548_AG +#define CONFIG_VERY_BIG_RAM +#endif
#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 @@ -613,7 +618,9 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#ifndef CONFIG_TQM8548_AG #define CONFIG_CMD_DATE +#endif #define CONFIG_CMD_EEPROM #define CONFIG_CMD_DTT #define CONFIG_CMD_MII Index: u-boot/MAKEALL =================================================================== --- u-boot.orig/MAKEALL +++ u-boot/MAKEALL @@ -387,6 +387,7 @@ LIST_85xx=" \ TQM8540 \ TQM8541 \ TQM8548 \ + TQM8548_AG \ TQM8548_BE \ TQM8555 \ TQM8560 \
According to new TQM8548 timing specification: Refresh Recovery: 34 -> 53 clocks CKE pulse width: 1 -> 3 cycles Window for four activities: 13 -> 14 cycles
Signed-off-by: Jens Gehrlein sew_s@tqs.de Signed-off-by: Wolfgang Grandegger wg@grandegger.com ---
board/tqc/tqm85xx/sdram.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-)
Index: u-boot/board/tqc/tqm85xx/sdram.c =================================================================== --- u-boot.orig/board/tqc/tqm85xx/sdram.c +++ u-boot/board/tqc/tqm85xx/sdram.c @@ -81,21 +81,23 @@ long int sdram_setup (int casl) ddr->sdram_cfg = 0;
#ifdef CONFIG_TQM8548 + /* Timing and refresh settings for DDR2-533 and below */ + ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; ddr->cs0_config = ddr_cs_conf[0].reg; - ddr->timing_cfg_3 = 0x00010000; + ddr->timing_cfg_3 = 0x00020000;
/* TIMING CFG 1, 533MHz * PRETOACT: 4 Clocks * ACTTOPRE: 12 Clocks * ACTTORW: 4 Clocks * CASLAT: 4 Clocks - * REFREC: 34 Clocks + * REFREC: EXT_REFREC:REFREC 53 Clocks * WRREC: 4 Clocks * ACTTOACT: 3 Clocks * WRTORD: 2 Clocks */ - ddr->timing_cfg_1 = 0x4C47A432; + ddr->timing_cfg_1 = 0x4C47D432;
/* TIMING CFG 2, 533MHz * ADD_LAT: 3 Clocks @@ -103,10 +105,10 @@ long int sdram_setup (int casl) * WR_LAT: 3 Clocks * RD_TO_PRE: 2 Clocks * WR_DATA_DELAY: 1/2 Clock - * CKE_PLS: 1 Clock - * FOUR_ACT: 13 Clocks + * CKE_PLS: 3 Clock + * FOUR_ACT: 14 Clocks */ - ddr->timing_cfg_2 = 0x3318484D; + ddr->timing_cfg_2 = 0x331848CE;
/* DDR SDRAM Mode, 533MHz * MRS: Extended Mode Register
This patch add support for the 1 GiB DDR2-SDRAM on the TQM8548_AG module.
Signed-off-by: Jens Gehrlein sew_s@tqs.de Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- board/tqc/tqm85xx/law.c | 2 +- board/tqc/tqm85xx/sdram.c | 9 +++++++++ board/tqc/tqm85xx/tlb.c | 19 ++++++++++++++++--- 3 files changed, 26 insertions(+), 4 deletions(-)
Index: u-boot/board/tqc/tqm85xx/law.c =================================================================== --- u-boot.orig/board/tqc/tqm85xx/law.c +++ u-boot/board/tqc/tqm85xx/law.c @@ -66,7 +66,7 @@ #endif
struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR), SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), Index: u-boot/board/tqc/tqm85xx/sdram.c =================================================================== --- u-boot.orig/board/tqc/tqm85xx/sdram.c +++ u-boot/board/tqc/tqm85xx/sdram.c @@ -38,11 +38,20 @@ struct sdram_conf_s { typedef struct sdram_conf_s sdram_conf_t;
#ifdef CONFIG_TQM8548 +#ifdef CONFIG_TQM8548_AG +sdram_conf_t ddr_cs_conf[] = { + {(1024 << 20), 0x80044202, 0x0002D000}, /* 1024MB, 14x10(4) */ + { (512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */ + { (256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */ + { (128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */ +}; +#else /* !CONFIG_TQM8548_AG */ sdram_conf_t ddr_cs_conf[] = { {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */ {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */ {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */ }; +#endif /* CONFIG_TQM8548_AG */ #else /* !CONFIG_TQM8548 */ sdram_conf_t ddr_cs_conf[] = { {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ Index: u-boot/board/tqc/tqm85xx/tlb.c =================================================================== --- u-boot.orig/board/tqc/tqm85xx/tlb.c +++ u-boot/board/tqc/tqm85xx/tlb.c @@ -121,12 +121,25 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1),
+#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE) + /* + * TLB 7+8: 2G DDR, cache enabled + * 0x00000000 2G DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + */ + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 7, BOOKE_PAGESZ_1G, 1), + + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 8, BOOKE_PAGESZ_1G, 1), +#else /* * TLB 7+8: 512M DDR, cache disabled (needed for memory test) * 0x00000000 512M DDR System memory * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. */ SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, @@ -136,7 +149,7 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), - +#endif #ifdef CONFIG_PCIE1 /* * TLB 9: 16M Non-cacheable, guarded
This patch makes accesses to the system memory cachable by removing the caching-inhibited and guarded flags from the relevant TLB entries for the TQM8548_BE and TQM8548_AG modules. FYI, the Freescale MPC85* boards are configured similarly.
This results in a big averall performace improvement. TFTP downloads, NAND Flash accesses, kernel boots, etc. are much faster.
Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- board/tqc/tqm85xx/tlb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Index: u-boot/board/tqc/tqm85xx/tlb.c =================================================================== --- u-boot.orig/board/tqc/tqm85xx/tlb.c +++ u-boot/board/tqc/tqm85xx/tlb.c @@ -128,12 +128,12 @@ struct fsl_e_tlb_entry tlb_table[] = { * Without SPD EEPROM configured DDR, this must be setup manually. */ SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), #else /*
This patch adds the workaround for erratum DDR20 according to MPC8548 Device Errata document, Rev. 1: "CKE signal may not function correctly after assertion of HRESET". Furthermore, the bug DDR19 is fixed in processor version 2.1 and the work-around must be removed.
Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- board/tqc/tqm85xx/sdram.c | 116 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 108 insertions(+), 8 deletions(-)
Index: u-boot/board/tqc/tqm85xx/sdram.c =================================================================== --- u-boot.orig/board/tqc/tqm85xx/sdram.c +++ u-boot/board/tqc/tqm85xx/sdram.c @@ -1,3 +1,4 @@ + /* * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. @@ -78,6 +79,7 @@ long int sdram_setup (int casl) volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); #ifdef CONFIG_TQM8548 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); #else /* !CONFIG_TQM8548 */ unsigned long cfg_ddr_timing1; unsigned long cfg_ddr_mode; @@ -147,13 +149,12 @@ long int sdram_setup (int casl) ddr->sdram_interval = (1040 << 16) | 0x100;
/* - * workaround for erratum DD10 of MPC8458 family below rev. 2.0: - * DDR IO receiver must be set to an acceptable bias point by modifying - * a hidden register. + * Workaround for erratum DDR19 according to MPC8548 Device Errata + * document, Rev. 1: DDR IO receiver must be set to an acceptable + * bias point by modifying a hidden register. */ - if (SVR_REV (get_svr ()) < 0x20) { + if (SVR_REV (get_svr ()) < 0x21) gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */ - }
/* DDR SDRAM CFG 2 * FRC_SR: normal mode @@ -181,7 +182,104 @@ long int sdram_setup (int casl)
/* wait for clock stabilization */ asm ("sync;isync;msync"); - udelay(1000); + udelay (1000); + +#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) + /* + * Workaround for erratum DDR20 according to MPC8548 Device Errata + * document, Rev. 1: "CKE signal may not function correctly after + * assertion of HRESET" + */ + + /* 1. Configure DDR register as is done in normal DDR configuration. + * Do not set DDR_SDRAM_CFG[MEM_EN]. + * + * 2. Set reserved bit EEBACR[3] at offset 0x1000 + */ + ecm->eebacr |= 0x10000000; + + /* + * 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT] + * + * DDR_SDRAM_CFG_2: + * FRC_SR: normal mode + * SR_IE: no self-refresh interrupt + * DLL_RST_DIS: don't care, leave at reset value + * DQS_CFG: differential DQS signals + * ODT_CFG: assert ODT to internal IOs only during reads to DRAM + * LVWx_CFG: don't care, leave at reset value + * NUM_PR: 1 refresh will be issued at a time + * DM_CFG: don't care, leave at reset value + * D_INIT: enable data initialization + */ + ddr->sdram_cfg_2 |= 0x00000010; + + /* + * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data + * training + */ + ddr->debug_3 |= 0x00000400; + + /* + * 5. Wait 200 micro-seconds + */ + udelay (200); + + /* + * 6. Set DDR_SDRAM_CFG[MEM_EN] + * + * BTW, initialize DDR_SDRAM_CFG: + * MEM_EN: enabled + * SREN: don't care, leave at reset value + * ECC_EN: no error report + * RD_EN: no registered DIMMs + * SDRAM_TYPE: DDR2 + * DYN_PWR: no power management + * 32_BE: don't care, leave at reset value + * 8_BE: 4 beat burst + * NCAP: don't care, leave at reset value + * 2T_EN: 1T Timing + * BA_INTLV_CTL: no interleaving + * x32_EN: x16 organization + * PCHB8: MA[10] for auto-precharge + * HSE: half strength for single and 2-layer stacks + * (full strength for 3- and 4-layer stacks not + * yet considered) + * MEM_HALT: no halt + * BI: automatic initialization + */ + ddr->sdram_cfg = 0x83000008; + + /* + * 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware + */ + asm ("sync;isync;msync"); + while (ddr->sdram_cfg_2 & 0x00000010) + asm ("eieio"); + + /* + * 8. Clear D3[21] to re-enable data training + */ + ddr->debug_3 &= ~0x00000400; + + /* + * 9. Set D2(21) to force data training to run + */ + ddr->debug_2 |= 0x00000400; + + /* + * 10. Poll on D2[21] until it is cleared by hardware + */ + asm ("sync;isync;msync"); + while (ddr->debug_2 & 0x00000400) + asm ("eieio"); + + /* + * 11. Clear reserved bit EEBACR[3] at offset 0x1000 + */ + ecm->eebacr &= ~0x10000000; + +#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */
/* DDR SDRAM CLK CNTL * MEM_EN: enabled @@ -203,9 +301,11 @@ long int sdram_setup (int casl) * BI: automatic initialization */ ddr->sdram_cfg = 0x83000008; - asm ("sync; isync; msync"); - udelay(1000);
+#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */ + + asm ("sync; isync; msync"); + udelay (1000); #else /* !CONFIG_TQM8548 */ switch (casl) { case 20:
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Wolfgang Grandegger