Hello List,

I'm taking a look at the memory diagnostics, specially for PowerPC mpc85xx family CPUs. It seems to me that currently all the memory diagnostics on mpc85xx are run with cache enabled, and memory mapped using cache-enabled TLB entries. Isn't it true that in such a case all the memory reads / writes would actually land up in cache (unless they are "spaced" out), and the memory diagnostics won't really be reliable?

Are the memory diagnostics written with keeping in mind that the cache may be enabled?

The diagnostic code (post/drivers/memory.c) does give architecture code (arch/powerpc/cpu/mpc85xx/cpu.c) a chance to prepare for running memory diagnostics, but it does not look like the CPU code is really disabling the cache.

What am I missing?

Thanks,

Rajat