From: Pragnesh Patel [mailto:pragnesh.patel@sifive.com] Sent: Saturday, April 18, 2020 10:44 PM To: u-boot@lists.denx.de; Rick Jian-Zhi Chen(陳建志) Cc: atish.patra@wdc.com; palmerdabbelt@google.com; bmeng.cn@gmail.com; Paul Walmsley; Simon Glass; Trevor Woerner Subject: RE: [PATCH v2] riscv: ax25: cache: Remove SPL_RISCV_MMODE config check

Any comments on this patch ?

Thanks for reviewing. I will pull it later.

Thanks, Rick

...

-----Original Message----- From: Pragnesh Patel pragnesh.patel@sifive.com Sent: 14 March 2020 19:13 To: u-boot@lists.denx.de Cc: atish.patra@wdc.com; palmerdabbelt@google.com; bmeng.cn@gmail.com; Paul Walmsley paul.walmsley@sifive.com; rick@andestech.com; Pragnesh Patel pragnesh.patel@sifive.com; Simon Glass sjg@chromium.org; Trevor Woerner trevor@toganlabs.com Subject: [PATCH v2] riscv: ax25: cache: Remove SPL_RISCV_MMODE config check

CONFIG_IS_ENABLED(FOO) will check FOO config option for U-Boot, SPL and TPL, so remove unnecessary CONFIG_IS_ENABLED()

Signed-off-by: Pragnesh Patel pragnesh.patel@sifive.com Reviewed-by: Bin Meng bmeng.cn@gmail.com

---

arch/riscv/cpu/ax25/cache.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 9f424198b4..9df629d23c 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -12,7 +12,7 @@ #include <asm/csr.h>

#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) /* mcctlcommand */ #define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc

@@ -47,7 +47,7 @@ void flush_dcache_all(void) { #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); #endif #endif @@ -68,7 +68,7 @@ void icache_enable(void) { #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "ori t0, t1, 0x1\n\t" @@ -83,7 +83,7 @@ void icache_disable(void) { #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "fence.i\n\t" "csrr t1, mcache_ctl\n\t" @@ -99,7 +99,7 @@ void dcache_enable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "ori t0, t1, 0x2\n\t" @@ -117,7 +117,7 @@ void dcache_disable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); asm volatile ( "csrr t1, mcache_ctl\n\t" @@ -137,7 +137,7 @@ int icache_status(void) int ret = 0;

#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "andi %0, t1, 0x01\n\t" @@ -156,7 +156,7 @@ int dcache_status(void) int ret = 0;

#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "andi %0, t1, 0x02\n\t" -- 2.17.1