The timeout passed to wait_for_bit... is in milliseconds, not in CPU cycles or something similar what the setting suggested.

Rename the constant to GQSPI_TIMEOUT_MS to make it clear that the timeout is in milliseconds.

Set the timeout to 10 seconds. You'll be hard pressed to find a NOR flash that this controller cannot read front to end in 10 seconds in a reasonable configuration (i.e. a speed of 100MHz or more).

Signed-off-by: Mike Looijmans mike.looijmans@topic.nl --- drivers/spi/zynqmp_gqspi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index a72986be90..596a6a4eef 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -84,7 +84,7 @@ #define GQSPI_MAX_BAUD_RATE_VAL 7 #define GQSPI_DFLT_BAUD_RATE_VAL 2

-#define GQSPI_TIMEOUT 100000000 +#define GQSPI_TIMEOUT_MS 10000

#define GQSPI_BAUD_DIV_SHIFT 2 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5 @@ -228,7 +228,7 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, int ret = 0;

ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1, - GQSPI_TIMEOUT, 1); + GQSPI_TIMEOUT_MS, 1); if (ret) printf("%s Timeout\n", __func__);

@@ -406,7 +406,7 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)

while (size) { ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXNFULL_MASK, 1, - GQSPI_TIMEOUT, 1); + GQSPI_TIMEOUT_MS, 1); if (ret) { printf("%s: Timeout\n", __func__); return ret; @@ -551,7 +551,7 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, }

ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE, - 1, GQSPI_TIMEOUT, 1); + 1, GQSPI_TIMEOUT_MS, 1); if (ret) { printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr)); return -ETIMEDOUT;