From: Dinh Nguyen dinguyen@opensource.altera.com

The system manager on Arria10 is not used for pin muxing duties, so wrap these functions for GEN5 devices only.

Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- arch/arm/mach-socfpga/system_manager.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c index 75a65f3..9e1c3fd 100644 --- a/arch/arm/mach-socfpga/system_manager.c +++ b/arch/arm/mach-socfpga/system_manager.c @@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs = * The value is not wrote to SYSMGR.FPGAINTF.MODULE but * CONFIG_SYSMGR_ISWGRP_HANDOFF. */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static void populate_sysmgr_fpgaintf_module(void) { uint32_t handoff_val = 0; @@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable) clrbits_le32(&sysmgr_regs->romcodegrp_ctrl, SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); } +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */

From: Dinh Nguyen dinguyen@opensource.altera.com

Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX.

Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 +++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h new file mode 100644 index 0000000..7619ca2 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar s.trumtrar@pengutronix.de + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 + +/* PER0MODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define EMAC2_RESET 34 +#define USB0_RESET 35 +#define USB1_RESET 36 +#define NAND_RESET 37 +#define QSPI_RESET 38 +#define SDMMC_RESET 39 +#define EMAC0_OCP_RESET 40 +#define EMAC1_OCP_RESET 41 +#define EMAC2_OCP_RESET 42 +#define USB0_OCP_RESET 43 +#define USB1_OCP_RESET 44 +#define NAND_OCP_RESET 45 +#define QSPI_OCP_RESET 46 +#define SDMMC_OCP_RESET 47 +#define DMA_RESET 48 +#define SPIM0_RESET 49 +#define SPIM1_RESET 50 +#define SPIS0_RESET 51 +#define SPIS1_RESET 52 +#define DMA_OCP_RESET 53 +#define EMAC_PTP_RESET 54 +/* 55 is empty*/ +#define DMAIF0_RESET 56 +#define DMAIF1_RESET 57 +#define DMAIF2_RESET 58 +#define DMAIF3_RESET 59 +#define DMAIF4_RESET 60 +#define DMAIF5_RESET 61 +#define DMAIF6_RESET 62 +#define DMAIF7_RESET 63 + +/* PER1MODRST */ +#define L4WD0_RESET 64 +#define L4WD1_RESET 65 +#define L4SYSTIMER0_RESET 66 +#define L4SYSTIMER1_RESET 67 +#define SPTIMER0_RESET 68 +#define SPTIMER1_RESET 69 +/* 70-71 is reserved */ +#define I2C0_RESET 72 +#define I2C1_RESET 73 +#define I2C2_RESET 74 +#define I2C3_RESET 75 +#define I2C4_RESET 76 +/* 77-79 is reserved */ +#define UART0_RESET 80 +#define UART1_RESET 81 +/* 82-87 is reserved */ +#define GPIO0_RESET 88 +#define GPIO1_RESET 89 +#define GPIO2_RESET 90 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 +#define F2SSDRAM0_RESET 99 +#define F2SSDRAM1_RESET 100 +#define F2SSDRAM2_RESET 101 +#define DDRSCH_RESET 102 + +/* SYSMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +/* 130 is reserved */ +#define FPGAMGR_RESET 131 +#define S2F_RESET 132 +#define SYSDBG_RESET 133 +#define OCRAM_OCP_RESET 134 + +/* COLDMODRST */ +#define CLKMGRCOLD_RESET 160 +/* 161-162 is reserved */ +#define S2FCOLD_RESET 163 +#define TIMESTAMPCOLD_RESET 164 +#define TAPCOLD_RESET 165 +#define HMCCOLD_RESET 166 +#define IOMGRCOLD_RESET 167 + +/* NRSTMODRST */ +#define NRSTPINOE_RESET 192 + +/* DBGMODRST */ +#define DBG_RESET 224 +#endif

From: Dinh Nguyen dinh.linux@gmail.com

On the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.

Update the dwmac_deassert_reset function to support both GEN5 and Arria10 devices.

Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- arch/arm/mach-socfpga/include/mach/system_manager.h | 1 + arch/arm/mach-socfpga/misc.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 9ca889a..bfabf00 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -218,6 +218,7 @@ struct socfpga_system_manager {

#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL2_LSB 4 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3

/* For dedicated IO configuration */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 517f629..6ef49c3 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -22,7 +22,12 @@ #include <asm/arch/scu.h> #include <asm/pl310.h>

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #include <dt-bindings/reset/altr,rst-mgr.h> +#else +#include <dt-bindings/reset/altr,rst-mgr-a10.h> +#endif +

DECLARE_GLOBAL_DATA_PTR;

@@ -95,11 +100,17 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id) } else if (of_reset_id == EMAC1_RESET) { physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; reset = SOCFPGA_RESET(EMAC1); +#ifndef CONFIG_TARGET_SOCFPGA_GEN5 + } else if (of_reset_id == EMAC2_RESET) { + physhift = SYSMGR_EMACGRP_CTRL_PHYSEL2_LSB; + reset = SOCFPGA_RESET(EMAC2); +#endif } else { printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); return; }

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* Clearing emac0 PHY interface select to 0 */ clrbits_le32(&sysmgr_regs->emacgrp_ctrl, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); @@ -107,6 +118,15 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id) /* configure to PHY interface select choosed */ setbits_le32(&sysmgr_regs->emacgrp_ctrl, SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); +#else + /* Clearing emac0 PHY interface select to 0 */ + clrbits_le32(&sysmgr_regs->emac0 + (0x2 * physhift), + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK); + + /* configure to PHY interface to RGMII */ + setbits_le32(&sysmgr_regs->emac0 + (0x2 * physhift), + SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII); +#endif

/* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0);

From: Dinh Nguyen dinh.linux@gmail.com

The Arria10 device will not be able to re-use the GEN5 SDRAM controller, so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig option in drivers/ddr/altera/Kconfig.

Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- drivers/Kconfig | 2 ++ drivers/ddr/Kconfig | 1 + drivers/ddr/altera/Kconfig | 6 ++++++ include/configs/socfpga_common.h | 5 ----- 4 files changed, 9 insertions(+), 5 deletions(-) create mode 100644 drivers/ddr/Kconfig create mode 100644 drivers/ddr/altera/Kconfig

diff --git a/drivers/Kconfig b/drivers/Kconfig index c481e93..6b56d78 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"

source "drivers/crypto/Kconfig"

+source "drivers/ddr/Kconfig" + source "drivers/demo/Kconfig"

source "drivers/dfu/Kconfig" diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig new file mode 100644 index 0000000..b764add --- /dev/null +++ b/drivers/ddr/Kconfig @@ -0,0 +1 @@ +source "drivers/ddr/altera/Kconfig" diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig new file mode 100644 index 0000000..9554da7 --- /dev/null +++ b/drivers/ddr/altera/Kconfig @@ -0,0 +1,6 @@ +config ALTERA_SDRAM + bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices" + default y if TARGET_SOCFPGA_GEN5 + help + This is for building the SDRAM controller for the Arria5/Cyclone5 + devices. diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a09e906..30701fe 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -81,11 +81,6 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS

/* - * SDRAM controller - */ -#define CONFIG_ALTERA_SDRAM - -/* * EPCS/EPCQx1 Serial Flash Controller */ #ifdef CONFIG_ALTERA_SPI

From: Dinh Nguyen dinh.linux@gmail.com

On the Arria10 device, the bridges are not mapped through the interconnect.

Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- drivers/fpga/socfpga.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index 4448250..75368e6 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -278,8 +278,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset(1);

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* Unmap the bridges from NIC-301 */ writel(0x1, SOCFPGA_L3REGS_ADDRESS); +#endif

/* Initialize the FPGA Manager */ status = fpgamgr_program_init();

From: Dinh Nguyen dinh.linux@gmail.com

These functions are already in arch/arm/mach-socfpga/board.c

Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- board/altera/arria10-socdk/socfpga.c | 17 ----------------- 1 file changed, 17 deletions(-)

diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c index abedc22..8516633 100644 --- a/board/altera/arria10-socdk/socfpga.c +++ b/board/altera/arria10-socdk/socfpga.c @@ -5,20 +5,3 @@ */

#include <common.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) -{ -} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - return 0; -}