SMI driver fails because of low timeout values. Increasing the write mode timeout and transfer timeouts to 15 ms

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- arch/arm/include/asm/arch-spear/spr_smi.h | 4 +- drivers/mtd/spr_smi.c | 57 ++++++++++++++++++----------- 2 files changed, 38 insertions(+), 23 deletions(-)

diff --git a/arch/arm/include/asm/arch-spear/spr_smi.h b/arch/arm/include/asm/arch-spear/spr_smi.h index 06df745..0cca000 100644 --- a/arch/arm/include/asm/arch-spear/spr_smi.h +++ b/arch/arm/include/asm/arch-spear/spr_smi.h @@ -109,7 +109,7 @@ struct flash_dev { };

#define SFLASH_PAGE_SIZE 0x100 /* flash page size */ -#define XFER_FINISH_TOUT 2 /* xfer finish timeout */ -#define WMODE_TOUT 2 /* write enable timeout */ +#define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */ +#define WMODE_TOUT 15 /* write enable timeout(in ms) */

#endif diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/spr_smi.c index 9a70a19..c6ba951 100644 --- a/drivers/mtd/spr_smi.c +++ b/drivers/mtd/spr_smi.c @@ -58,13 +58,15 @@ static struct flash_dev flash_ids[] = { * * Wait until TFF is set in status register */ -static void smi_wait_xfer_finish(int timeout) +static int smi_wait_xfer_finish(int timeout) { - while (timeout--) { + do { if (readl(&smicntl->smi_sr) & TFF) - break; + return 0; udelay(1000); - } + } while (timeout--); + + return -1; }

/* @@ -82,7 +84,9 @@ static unsigned int smi_read_id(flash_info_t *info, int banknum) writel(READ_ID, &smicntl->smi_tr); writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -EIO;

value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);

@@ -104,11 +108,17 @@ static ulong flash_get_size(ulong base, int banknum) { flash_info_t *info = &flash_info[banknum]; struct flash_dev *dev; - unsigned int value; + int value; unsigned int density; int i;

value = smi_read_id(info, banknum); + + if (value < 0) { + printf("Flash id could not be read\n"); + return 0; + } + density = (value >> 16) & 0xff;

for (i = 0, dev = &flash_ids[0]; dev->density != 0x0; @@ -136,7 +146,7 @@ static ulong flash_get_size(ulong base, int banknum) * This routine will get the status register of the flash chip present at the * given bank */ -static unsigned int smi_read_sr(int bank) +static int smi_read_sr(int bank) { u32 ctrlreg1;

@@ -150,7 +160,8 @@ static unsigned int smi_read_sr(int bank) /* Performing a RSR instruction in HW mode */ writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);

- smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -1;

/* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1); @@ -169,13 +180,11 @@ static unsigned int smi_read_sr(int bank) */ static int smi_wait_till_ready(int bank, int timeout) { - int count; - unsigned int sr; + int sr;

/* One chip guarantees max 5 msec wait here after page writes, but potentially three seconds (!) after page erase. */ - for (count = 0; count < timeout; count++) { - + do { sr = smi_read_sr(bank); if (sr < 0) break; @@ -184,7 +193,8 @@ static int smi_wait_till_ready(int bank, int timeout)

/* Try again after 1m-sec */ udelay(1000); - } + } while (timeout--); + printf("SMI controller is still in wait, timeout=%d\n", timeout); return -EIO; } @@ -200,6 +210,7 @@ static int smi_write_enable(int bank) { u32 ctrlreg1; int timeout = WMODE_TOUT; + int sr;

/* Store the CTRL REG1 state */ ctrlreg1 = readl(&smicntl->smi_cr1); @@ -210,19 +221,22 @@ static int smi_write_enable(int bank) /* Give the Flash, Write Enable command */ writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);

- smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -1;

/* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1);

- while (timeout--) { - if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT))) + do { + sr = smi_read_sr(bank); + if (sr < 0) break; - udelay(1000); - } + else if (sr & (1 << (bank + WM_SHIFT))) + return 0;

- if (timeout) - return 0; + /* Try again after 1m-sec */ + udelay(1000); + } while (timeout--);

return -1; } @@ -291,7 +305,8 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector) writel(instruction, &smicntl->smi_tr); writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -EIO;

if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) return -EBUSY;

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- include/configs/spear-common.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index cc52e39..b526558 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -208,6 +208,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x00000000 -#define PHYS_SDRAM_1_MAXSIZE 0x40000000 +#define PHYS_SDRAM_1_MAXSIZE 0x08000000

#endif

Designware network driver support added. This is a Synopsys ethernet controller

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- doc/README.designware_eth | 25 ++ drivers/net/Makefile | 1 + drivers/net/designware.c | 531 +++++++++++++++++++++++++++++++++++++++++++++ drivers/net/designware.h | 264 ++++++++++++++++++++++ include/netdev.h | 1 + 5 files changed, 822 insertions(+), 0 deletions(-) create mode 100644 doc/README.designware_eth create mode 100644 drivers/net/designware.c create mode 100644 drivers/net/designware.h

diff --git a/doc/README.designware_eth b/doc/README.designware_eth new file mode 100644 index 0000000..25ec6bd --- /dev/null +++ b/doc/README.designware_eth @@ -0,0 +1,25 @@ +This driver supports Designware Ethernet Controller provided by Synopsis. + +The driver is enabled by CONFIG_DESIGNWARE_ETH. + +The driver has been developed and tested on SPEAr platforms. By default, the +MDIO interface works at 100/Full. #defining the below options in board +configuration file changes this behavior. + +Call an subroutine from respective board/.../board.c +designware_initialize(u32 id, ulong base_addr, u32 phy_addr); + +The various options suported by the driver are +1. CONFIG_DW_ALTDESCRIPTOR + Define this to use the Alternate/Enhanced Descriptor configurations. +1. CONFIG_DW_AUTONEG + Define this to autonegotiate with the host before proceeding with mac + level configuration. This obviates the definitions of CONFIG_DW_SPEED10M + and CONFIG_DW_DUPLEXHALF. +2. CONFIG_DW_SPEED10M + Define this to change the default behavior from 100Mbps to 10Mbps. +3. CONFIG_DW_DUPLEXHALF + Define this to change the default behavior from Full Duplex to Half. +4. CONFIG_DW_SEARCH_PHY + Define this to search the phy address. This would overwrite the value + passed as 3rd arg from designware_initialize routine. diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b75c02f..7a320fd 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o COBJS-$(CONFIG_CS8900) += cs8900.o COBJS-$(CONFIG_TULIP) += dc2114x.o +COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o COBJS-$(CONFIG_DNET) += dnet.o COBJS-$(CONFIG_E1000) += e1000.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c new file mode 100644 index 0000000..d0d9827 --- /dev/null +++ b/drivers/net/designware.c @@ -0,0 +1,531 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Designware ethernet IP driver for u-boot + */ + +#include <common.h> +#include <miiphy.h> +#include <malloc.h> +#include <linux/err.h> +#include <asm/io.h> +#include "designware.h" + +static void tx_descs_init(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; + char *txbuffs = &priv->txbuffs[0]; + struct dmamacdescr *desc_p; + u32 idx; + + for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->dmamac_next = &desc_table_p[idx + 1]; + +#if defined(CONFIG_DW_ALTDESCRIPTOR) + desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | + DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ + DESC_TXSTS_TXCHECKINSCTRL | \ + DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); + + desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; + desc_p->dmamac_cntl = 0; + desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); +#else + desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; + desc_p->txrx_status = 0; +#endif + } + + /* Correcting the last pointer of the chain */ + desc_p->dmamac_next = &desc_table_p[0]; + + writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); +} + +static void rx_descs_init(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; + char *rxbuffs = &priv->rxbuffs[0]; + struct dmamacdescr *desc_p; + u32 idx; + + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->dmamac_next = &desc_table_p[idx + 1]; + + desc_p->dmamac_cntl = + (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ + DESC_RXCTRL_RXCHAIN; + + desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; + } + + /* Correcting the last pointer of the chain */ + desc_p->dmamac_next = &desc_table_p[0]; + + writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); +} + +static void descs_init(struct eth_device *dev) +{ + tx_descs_init(dev); + rx_descs_init(dev); +} + +static int mac_reset(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + + int timeout = CONFIG_MACRESET_TIMEOUT; + + writel(DMAMAC_SRST, &dma_p->busmode); + writel(MII_PORTSELECT, &mac_p->conf); + + do { + if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) + return 0; + udelay(1000); + } while (timeout--); + + return -1; +} + +static int dw_write_hwaddr(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 macid_lo, macid_hi; + u8 *mac_id = &dev->enetaddr[0]; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + \ + (mac_id[2] << 16) + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; +} + +static int dw_eth_init(struct eth_device *dev, bd_t *bis) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 conf; + + /* Reset ethernet hardware */ + if (mac_reset(dev) < 0) + return -1; + + writel(FIXEDBURST | PRIORXTX_41 | BURST_16, + &dma_p->busmode); + + writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode); + writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode); + + conf = FRAMEBURSTENABLE | DISABLERXOWN; + + if (priv->speed != SPEED_1000M) + conf |= MII_PORTSELECT; + + if (priv->duplex == FULL_DUPLEX) + conf |= FULLDPLXMODE; + + writel(conf, &mac_p->conf); + + descs_init(dev); + + /* + * Start/Enable xfer at dma as well as mac level + */ + writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); + writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); + + writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf); + writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf); + + return 0; +} + +static int dw_eth_send(struct eth_device *dev, volatile void *packet, + int length) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 desc_num = priv->tx_currdescnum; + struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; + + /* Check if the descriptor is owned by CPU */ + if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { + printf("CPU not owner of tx frame\n"); + return -1; + } + + memcpy((void *)desc_p->dmamac_addr, (void *)packet, length); + +#if defined(CONFIG_DW_ALTDESCRIPTOR) + desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; + desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ + DESC_TXCTRL_SIZE1MASK; + + desc_p->txrx_status &= ~(DESC_TXSTS_MSK); + desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; +#else + desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ + DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ + DESC_TXCTRL_TXFIRST; + + desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; +#endif + + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_TX_DESCR_NUM) + desc_num = 0; + + priv->tx_currdescnum = desc_num; + + /* Start the transmission */ + writel(POLL_DATA, &dma_p->txpolldemand); + + return 0; +} + +static int dw_eth_recv(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + u32 desc_num = priv->rx_currdescnum; + struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; + + u32 status = desc_p->txrx_status; + int length = 0; + + /* Check if the owner is the CPU */ + if (!(status & DESC_RXSTS_OWNBYDMA)) { + + length = (status & DESC_RXSTS_FRMLENMSK) >> \ + DESC_RXSTS_FRMLENSHFT; + + NetReceive(desc_p->dmamac_addr, length); + + /* + * Make the current descriptor valid again and go to + * the next one + */ + desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; + + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_RX_DESCR_NUM) + desc_num = 0; + } + + priv->rx_currdescnum = desc_num; + + return length; +} + +static void dw_eth_halt(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + + mac_reset(dev); + priv->tx_currdescnum = priv->rx_currdescnum = 0; +} + +static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ + ((reg << MIIREGSHIFT) & MII_REGMSK); + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + do { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + *val = readl(&mac_p->miidata); + return 0; + } + udelay(1000); + } while (timeout--); + + return -1; +} + +static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 miiaddr; + int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; + u16 value; + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + do { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + ret = 0; + udelay(1000); + } while (timeout--); + + /* Needed as a fix for ST-Phy */ + eth_mdio_read(dev, addr, reg, &value); + + return ret; +} + +#if defined(CONFIG_DW_SEARCH_PHY) +static int find_phy(struct eth_device *dev) +{ + int phy_addr = 0; + u16 ctrl, oldctrl; + + do { + eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); + oldctrl = ctrl & PHY_BMCR_AUTON; + + ctrl ^= PHY_BMCR_AUTON; + eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl); + eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); + ctrl &= PHY_BMCR_AUTON; + + if (ctrl == oldctrl) { + phy_addr++; + } else { + ctrl ^= PHY_BMCR_AUTON; + eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl); + + return phy_addr; + } + } while (phy_addr < 32); + + return -1; +} +#endif + +static int dw_reset_phy(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + u16 ctrl; + int timeout = CONFIG_PHYRESET_TIMEOUT; + u32 phy_addr = priv->address; + + eth_mdio_write(dev, phy_addr, PHY_BMCR, PHY_BMCR_RESET); + do { + eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); + if (!(ctrl & PHY_BMCR_RESET)) + break; + udelay(1000); + } while (timeout--); + + if (timeout < 0) + return -1; + +#ifdef CONFIG_PHY_RESET_DELAY + udelay(CONFIG_PHY_RESET_DELAY); +#endif + return 0; +} + +static int configure_phy(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + int phy_addr; + u16 bmcr, ctrl; +#if defined(CONFIG_DW_AUTONEG) + u16 bmsr; + u32 timeout; + u16 anlpar, btsr; +#endif + +#if defined(CONFIG_DW_SEARCH_PHY) + phy_addr = find_phy(dev); + if (phy_addr > 0) + priv->address = phy_addr; + else + return -1; +#endif + if (dw_reset_phy(dev) < 0) + return -1; + +#if defined(CONFIG_DW_AUTONEG) + bmcr = PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | PHY_BMCR_100MB | \ + PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS; +#else + bmcr = PHY_BMCR_100MB | PHY_BMCR_DPLX; + +#if defined(CONFIG_DW_SPEED10M) + bmcr &= ~PHY_BMCR_100MB; +#endif +#if defined(CONFIG_DW_DUPLEXHALF) + bmcr &= ~PHY_BMCR_DPLX; +#endif +#endif + if (eth_mdio_write(dev, phy_addr, PHY_BMCR, bmcr) < 0) + return -1; + + /* Read the phy status register and populate priv structure */ +#if defined(CONFIG_DW_AUTONEG) + timeout = CONFIG_AUTONEG_TIMEOUT; + do { + eth_mdio_read(dev, phy_addr, PHY_BMSR, &bmsr); + if (bmsr & PHY_BMSR_AUTN_COMP) + break; + udelay(1000); + } while (timeout--); + + eth_mdio_read(dev, phy_addr, PHY_ANLPAR, &anlpar); + eth_mdio_read(dev, phy_addr, PHY_1000BTSR, &btsr); + + if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { + priv->speed = SPEED_1000M; + if (btsr & PHY_1000BTSR_1000FD) + priv->duplex = FULL_DUPLEX; + else + priv->duplex = HALF_DUPLEX; + } else { + if (anlpar & PHY_ANLPAR_100) + priv->speed = SPEED_100M; + else + priv->speed = SPEED_10M; + + if (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + priv->duplex = FULL_DUPLEX; + else + priv->duplex = HALF_DUPLEX; + } +#else + if (eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl) < 0) + return -1; + + if (ctrl & PHY_BMCR_DPLX) + priv->duplex = FULL_DUPLEX; + else + priv->duplex = HALF_DUPLEX; + + if (ctrl & PHY_BMCR_1000_MBPS) + priv->speed = SPEED_1000M; + else if (ctrl & PHY_BMCR_100_MBPS) + priv->speed = SPEED_100M; + else + priv->speed = SPEED_10M; +#endif + return 0; +} + +#if defined(CONFIG_MII) +static int dw_mii_read(char *devname, u8 addr, u8 reg, u16 *val) +{ + struct eth_device *dev; + + dev = eth_get_dev_by_name(devname); + if (dev) + eth_mdio_read(dev, addr, reg, val); + + return 0; +} + +static int dw_mii_write(char *devname, u8 addr, u8 reg, u16 val) +{ + struct eth_device *dev; + + dev = eth_get_dev_by_name(devname); + if (dev) + eth_mdio_write(dev, addr, reg, val); + + return 0; +} +#endif + +int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) +{ + struct eth_device *dev; + struct dw_eth_dev *priv; + + dev = (struct eth_device *) malloc(sizeof(struct eth_device)); + if (!dev) + return -ENOMEM; + + /* + * Since the priv structure contains the descriptors which need a strict + * buswidth alignment, memalign is used to allocate memory + */ + priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); + if (!priv) { + free(dev); + return -ENOMEM; + } + + memset(dev, 0, sizeof(struct eth_device)); + memset(priv, 0, sizeof(struct dw_eth_dev)); + + sprintf(dev->name, "mii%d", id); + dev->iobase = (int)base_addr; + dev->priv = priv; + + eth_getenv_enetaddr_by_index(id, &dev->enetaddr[0]); + + priv->dev = dev; + priv->mac_regs_p = (struct eth_mac_regs *)base_addr; + priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + + DW_DMA_BASE_OFFSET); + priv->address = phy_addr; + + if (mac_reset(dev) < 0) + return -1; + + if (configure_phy(dev) < 0) { + printf("Phy could not be configured\n"); + return -1; + } + + dev->init = dw_eth_init; + dev->send = dw_eth_send; + dev->recv = dw_eth_recv; + dev->halt = dw_eth_halt; + dev->write_hwaddr = dw_write_hwaddr; + + eth_register(dev); + +#if defined(CONFIG_MII) + miiphy_register(dev->name, dw_mii_read, dw_mii_write); +#endif + return 1; +} diff --git a/drivers/net/designware.h b/drivers/net/designware.h new file mode 100644 index 0000000..e5828a6 --- /dev/null +++ b/drivers/net/designware.h @@ -0,0 +1,264 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DW_ETH_H +#define _DW_ETH_H + +#define CONFIG_TX_DESCR_NUM 16 +#define CONFIG_RX_DESCR_NUM 16 +#define CONFIG_ETH_BUFSIZE 2048 +#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) +#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) + +#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ) + +struct eth_mac_regs { + u32 conf; /* 0x00 */ + u32 framefilt; /* 0x04 */ + u32 hashtablehigh; /* 0x08 */ + u32 hashtablelow; /* 0x0c */ + u32 miiaddr; /* 0x10 */ + u32 miidata; /* 0x14 */ + u32 flowcontrol; /* 0x18 */ + u32 vlantag; /* 0x1c */ + u32 version; /* 0x20 */ + u8 reserved_1[20]; + u32 intreg; /* 0x38 */ + u32 intmask; /* 0x3c */ + u32 macaddr0hi; /* 0x40 */ + u32 macaddr0lo; /* 0x44 */ +}; + +/* MAC configuration register definitions */ +#define FRAMEBURSTENABLE (1 << 21) +#define MII_PORTSELECT (1 << 15) +#define FES_100 (1 << 14) +#define DISABLERXOWN (1 << 13) +#define FULLDPLXMODE (1 << 11) +#define RXENABLE (1 << 2) +#define TXENABLE (1 << 3) + +/* MII address register definitions */ +#define MII_BUSY (1 << 0) +#define MII_WRITE (1 << 1) +#define MII_CLKRANGE_60_100M (0) +#define MII_CLKRANGE_100_150M (0x4) +#define MII_CLKRANGE_20_35M (0x8) +#define MII_CLKRANGE_35_60M (0xC) +#define MII_CLKRANGE_150_250M (0x10) +#define MII_CLKRANGE_250_300M (0x14) + +#define MIIADDRSHIFT (11) +#define MIIREGSHIFT (6) +#define MII_REGMSK (0x1F << 6) +#define MII_ADDRMSK (0x1F << 11) + + +struct eth_dma_regs { + u32 busmode; /* 0x00 */ + u32 txpolldemand; /* 0x04 */ + u32 rxpolldemand; /* 0x08 */ + u32 rxdesclistaddr; /* 0x0c */ + u32 txdesclistaddr; /* 0x10 */ + u32 status; /* 0x14 */ + u32 opmode; /* 0x18 */ + u32 intenable; /* 0x1c */ + u8 reserved[40]; + u32 currhosttxdesc; /* 0x48 */ + u32 currhostrxdesc; /* 0x4c */ + u32 currhosttxbuffaddr; /* 0x50 */ + u32 currhostrxbuffaddr; /* 0x54 */ +}; + +#define DW_DMA_BASE_OFFSET (0x1000) + +/* Bus mode register definitions */ +#define FIXEDBURST (1 << 16) +#define PRIORXTX_41 (3 << 14) +#define PRIORXTX_31 (2 << 14) +#define PRIORXTX_21 (1 << 14) +#define PRIORXTX_11 (0 << 14) +#define BURST_1 (1 << 8) +#define BURST_2 (2 << 8) +#define BURST_4 (4 << 8) +#define BURST_8 (8 << 8) +#define BURST_16 (16 << 8) +#define BURST_32 (32 << 8) +#define RXHIGHPRIO (1 << 1) +#define DMAMAC_SRST (1 << 0) + +/* Poll demand definitions */ +#define POLL_DATA (0xFFFFFFFF) + +/* Operation mode definitions */ +#define STOREFORWARD (1 << 21) +#define FLUSHTXFIFO (1 << 20) +#define TXSTART (1 << 13) +#define TXSECONDFRAME (1 << 2) +#define RXSTART (1 << 1) + +/* Descriptior related definitions */ +#define MAC_MAX_FRAME_SZ (2048) + +struct dmamacdescr { + u32 txrx_status; + u32 dmamac_cntl; + void *dmamac_addr; + struct dmamacdescr *dmamac_next; +}; + +/* + * txrx_status definitions + */ + +/* tx status bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_TXSTS_OWNBYDMA (1 << 31) +#define DESC_TXSTS_TXINT (1 << 30) +#define DESC_TXSTS_TXLAST (1 << 29) +#define DESC_TXSTS_TXFIRST (1 << 28) +#define DESC_TXSTS_TXCRCDIS (1 << 27) + +#define DESC_TXSTS_TXPADDIS (1 << 26) +#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22) +#define DESC_TXSTS_TXRINGEND (1 << 21) +#define DESC_TXSTS_TXCHAIN (1 << 20) +#define DESC_TXSTS_MSK (0x1FFFF << 0) + +#else + +#define DESC_TXSTS_OWNBYDMA (1 << 31) +#define DESC_TXSTS_MSK (0x1FFFF << 0) + +#endif + +/* rx status bits definitions */ +#define DESC_RXSTS_OWNBYDMA (1 << 31) +#define DESC_RXSTS_DAFILTERFAIL (1 << 30) +#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16) +#define DESC_RXSTS_FRMLENSHFT (16) + +#define DESC_RXSTS_ERROR (1 << 15) +#define DESC_RXSTS_RXTRUNCATED (1 << 14) +#define DESC_RXSTS_SAFILTERFAIL (1 << 13) +#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12) +#define DESC_RXSTS_RXDAMAGED (1 << 11) +#define DESC_RXSTS_RXVLANTAG (1 << 10) +#define DESC_RXSTS_RXFIRST (1 << 9) +#define DESC_RXSTS_RXLAST (1 << 8) +#define DESC_RXSTS_RXIPC_GIANT (1 << 7) +#define DESC_RXSTS_RXCOLLISION (1 << 6) +#define DESC_RXSTS_RXFRAMEETHER (1 << 5) +#define DESC_RXSTS_RXWATCHDOG (1 << 4) +#define DESC_RXSTS_RXMIIERROR (1 << 3) +#define DESC_RXSTS_RXDRIBBLING (1 << 2) +#define DESC_RXSTS_RXCRC (1 << 1) + +/* + * dmamac_cntl definitions + */ + +/* tx control bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0) +#define DESC_TXCTRL_SIZE1SHFT (0) +#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16) +#define DESC_TXCTRL_SIZE2SHFT (16) + +#else + +#define DESC_TXCTRL_TXINT (1 << 31) +#define DESC_TXCTRL_TXLAST (1 << 30) +#define DESC_TXCTRL_TXFIRST (1 << 29) +#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27) +#define DESC_TXCTRL_TXCRCDIS (1 << 26) +#define DESC_TXCTRL_TXRINGEND (1 << 25) +#define DESC_TXCTRL_TXCHAIN (1 << 24) + +#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0) +#define DESC_TXCTRL_SIZE1SHFT (0) +#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11) +#define DESC_TXCTRL_SIZE2SHFT (11) + +#endif + +/* rx control bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_RXCTRL_RXINTDIS (1 << 31) +#define DESC_RXCTRL_RXRINGEND (1 << 15) +#define DESC_RXCTRL_RXCHAIN (1 << 14) + +#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0) +#define DESC_RXCTRL_SIZE1SHFT (0) +#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16) +#define DESC_RXCTRL_SIZE2SHFT (16) + +#else + +#define DESC_RXCTRL_RXINTDIS (1 << 31) +#define DESC_RXCTRL_RXRINGEND (1 << 25) +#define DESC_RXCTRL_RXCHAIN (1 << 24) + +#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0) +#define DESC_RXCTRL_SIZE1SHFT (0) +#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11) +#define DESC_RXCTRL_SIZE2SHFT (11) + +#endif + +struct dw_eth_dev { + u32 address; + u32 speed; + u32 duplex; + u32 tx_currdescnum; + u32 rx_currdescnum; + u32 padding; + + struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; + struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; + + char txbuffs[TX_TOTAL_BUFSIZE]; + char rxbuffs[RX_TOTAL_BUFSIZE]; + + struct eth_mac_regs *mac_regs_p; + struct eth_dma_regs *dma_regs_p; + + struct eth_device *dev; +} __attribute__ ((aligned(8))); + +/* Speed specific definitions */ +#define SPEED_10M 1 +#define SPEED_100M 2 +#define SPEED_1000M 3 + +/* Duplex mode specific definitions */ +#define HALF_DUPLEX 1 +#define FULL_DUPLEX 2 + +#endif diff --git a/include/netdev.h b/include/netdev.h index 882642a..3abc944 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -49,6 +49,7 @@ int bfin_EMAC_initialize(bd_t *bis); int cs8900_initialize(u8 dev_num, int base_addr); int dc21x4x_initialize(bd_t *bis); int davinci_emac_initialize(void); +int designware_initialize(u32 id, ulong base_addr, u32 phy_addr); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis);

SPEAr310 and SPEAr320 SoCs have an extra ethernet controller. The driver for this device is already supported by u-boot, so configuring board configuration file and defining base addresses etc to make use of the common driver

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- arch/arm/include/asm/arch-spear/clk.h | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-spear/hardware.h | 7 +++++++ board/spear/spear310/spear310.c | 25 ++++++++++++++++++++++--- board/spear/spear320/spear320.c | 12 +++++++++--- include/configs/spear3xx.h | 13 +++++++++++++ 5 files changed, 78 insertions(+), 6 deletions(-) create mode 100644 arch/arm/include/asm/arch-spear/clk.h

diff --git a/arch/arm/include/asm/arch-spear/clk.h b/arch/arm/include/asm/arch-spear/clk.h new file mode 100644 index 0000000..a45ec18 --- /dev/null +++ b/arch/arm/include/asm/arch-spear/clk.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return 83000000; +} diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 39d64b6..9f1e154 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -56,6 +56,11 @@ #define CONFIG_SPEAR_EMIBASE (0x4F000000) #define CONFIG_SPEAR_RASBASE (0xB4000000)

+#define CONFIG_SYS_MACB0_BASE (0xB0000000) +#define CONFIG_SYS_MACB1_BASE (0xB0800000) +#define CONFIG_SYS_MACB2_BASE (0xB1000000) +#define CONFIG_SYS_MACB3_BASE (0xB1800000) + #elif defined(CONFIG_SPEAR320) #define CONFIG_SYS_I2C_BASE (0xD0180000) #define CONFIG_SPEAR_FSMCBASE (0x4C000000) @@ -63,5 +68,7 @@ #define CONFIG_SPEAR_EMIBASE (0x40000000) #define CONFIG_SPEAR_RASBASE (0xB3000000)

+#define CONFIG_SYS_MACB0_BASE (0xAA000000) + #endif #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index f25eedf..96f1e00 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -61,9 +61,28 @@ int board_nand_init(struct nand_chip *nand)

int board_eth_init(bd_t *bis) { + int ret = 0; + #if defined(CONFIG_DESIGNWARE_ETH) - return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY); -#else - return -1; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) < 0) + ret += -1; +#endif +#if defined(CONFIG_MACB) + if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, + CONFIG_MACB0_PHY) < 0) + ret += -1; + + if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE, + CONFIG_MACB1_PHY) < 0) + ret += -1; + + if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE, + CONFIG_MACB2_PHY) < 0) + ret += -1; + + if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE, + CONFIG_MACB3_PHY) < 0) + ret += -1; #endif + return ret; } diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 1ed05aa..c3208e2 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -61,9 +61,15 @@ int board_nand_init(struct nand_chip *nand)

int board_eth_init(bd_t *bis) { + int ret = 0; #if defined(CONFIG_DESIGNWARE_ETH) - return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY); -#else - return -1; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) < 0) + ret += -1; +#endif +#if defined(CONFIG_MACB) + if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, + CONFIG_MACB0_PHY) < 0) + ret += -1; #endif + return ret; } diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index 502c50f..689d914 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -44,6 +44,19 @@ /* Ethernet driver configuration */ #define CONFIG_DW_ALTDESCRIPTOR 1

+#if defined(CONFIG_SPEAR310) +#define CONFIG_MACB 1 +#define CONFIG_MACB0_PHY 0x01 +#define CONFIG_MACB1_PHY 0x03 +#define CONFIG_MACB2_PHY 0x05 +#define CONFIG_MACB3_PHY 0x07 + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_MACB 1 +#define CONFIG_MACB0_PHY 0x01 + +#endif + /* Serial Configuration (PL011) */ #define CONFIG_SYS_SERIAL0 0xD0000000

Since FSMC is a standard IP and it supports different memory interfaces, it is supported independent of spear platform and spear is configured to use that driver for interfacing with the NAND device

Spear platform uses generic FSMC driver and spear specific files i.e drivers/mtd/nand/spr_nand.c, arch/arm/include/asm/arch-spear/spr_nand.h are removed

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- arch/arm/include/asm/arch-spear/hardware.h | 8 +- arch/arm/include/asm/arch-spear/spr_nand.h | 57 ------------- board/spear/spear300/spear300.c | 7 +- board/spear/spear310/spear310.c | 7 +- board/spear/spear320/spear320.c | 7 +- board/spear/spear600/spear600.c | 7 +- drivers/mtd/nand/Makefile | 1 - drivers/mtd/nand/spr_nand.c | 124 ---------------------------- include/configs/spear-common.h | 2 +- include/configs/spear3xx.h | 4 + include/configs/spear6xx.h | 3 + 11 files changed, 28 insertions(+), 199 deletions(-) delete mode 100644 arch/arm/include/asm/arch-spear/spr_nand.h delete mode 100644 drivers/mtd/nand/spr_nand.c

diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 9f1e154..52037b6 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -38,15 +38,15 @@

#if defined(CONFIG_SPEAR600) #define CONFIG_SYS_I2C_BASE (0xD0200000) -#define CONFIG_SPEAR_FSMCBASE (0xD1800000) +#define CONFIG_SYS_FSMC_BASE (0xD1800000)

#elif defined(CONFIG_SPEAR300) #define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x94000000) +#define CONFIG_SYS_FSMC_BASE (0x94000000)

#elif defined(CONFIG_SPEAR310) #define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x44000000) +#define CONFIG_SYS_FSMC_BASE (0x44000000)

#undef CONFIG_SYS_NAND_CLE #undef CONFIG_SYS_NAND_ALE @@ -63,7 +63,7 @@

#elif defined(CONFIG_SPEAR320) #define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x4C000000) +#define CONFIG_SYS_FSMC_BASE (0x4C000000)

#define CONFIG_SPEAR_EMIBASE (0x40000000) #define CONFIG_SPEAR_RASBASE (0xB3000000) diff --git a/arch/arm/include/asm/arch-spear/spr_nand.h b/arch/arm/include/asm/arch-spear/spr_nand.h deleted file mode 100644 index 2b63dc7..0000000 --- a/arch/arm/include/asm/arch-spear/spr_nand.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SPR_NAND_H__ -#define __SPR_NAND_H__ - -struct fsmc_regs { - u32 reserved_1[0x10]; - u32 genmemctrl_pc; - u32 reserved_2; - u32 genmemctrl_comm; - u32 genmemctrl_attrib; - u32 reserved_3; - u32 genmemctrl_ecc; -}; - -/* genmemctrl_pc register definitions */ -#define FSMC_RESET (1 << 0) -#define FSMC_WAITON (1 << 1) -#define FSMC_ENABLE (1 << 2) -#define FSMC_DEVTYPE_NAND (1 << 3) -#define FSMC_DEVWID_8 (0 << 4) -#define FSMC_DEVWID_16 (1 << 4) -#define FSMC_ECCEN (1 << 6) -#define FSMC_ECCPLEN_512 (0 << 7) -#define FSMC_ECCPLEN_256 (1 << 7) -#define FSMC_TCLR_1 (1 << 9) -#define FSMC_TAR_1 (1 << 13) - -/* genmemctrl_comm register definitions */ -#define FSMC_TSET_0 (0 << 0) -#define FSMC_TWAIT_6 (6 << 8) -#define FSMC_THOLD_4 (4 << 16) -#define FSMC_THIZ_1 (1 << 24) - -extern int spear_nand_init(struct nand_chip *nand); -#endif diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index 774f466..3f7ccb8 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -25,10 +25,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h>

int board_init(void) { @@ -47,14 +47,15 @@ int board_nand_init(struct nand_chip *nand) struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;

+#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) {

- return spear_nand_init(nand); + return fsmc_nand_init(nand); } - +#endif return -1; }

diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 96f1e00..f74bbac 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -26,10 +26,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h>

int board_init(void) { @@ -48,14 +48,15 @@ int board_nand_init(struct nand_chip *nand) struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;

+#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) {

- return spear_nand_init(nand); + return fsmc_nand_init(nand); } - +#endif return -1; }

diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index c3208e2..adddfd1 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -26,10 +26,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h>

int board_init(void) { @@ -48,14 +48,15 @@ int board_nand_init(struct nand_chip *nand) struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;

+#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) {

- return spear_nand_init(nand); + return fsmc_nand_init(nand); } - +#endif return -1; }

diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index cd7ff2c..5a32b7f 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -25,10 +25,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h>

int board_init(void) { @@ -47,9 +47,10 @@ int board_nand_init(struct nand_chip *nand) struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;

+#if defined(CONFIG_NAND_FSMC) if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) - return spear_nand_init(nand); - + return fsmc_nand_init(nand); +#endif return -1; }

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 4c6b54f..36fc8b3 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -48,7 +48,6 @@ COBJS-$(CONFIG_NAND_NDFC) += ndfc.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o -COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o endif diff --git a/drivers/mtd/nand/spr_nand.c b/drivers/mtd/nand/spr_nand.c deleted file mode 100644 index 097d0c6..0000000 --- a/drivers/mtd/nand/spr_nand.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <nand.h> -#include <linux/mtd/nand_ecc.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/spr_nand.h> - -static struct fsmc_regs *const fsmc_regs_p = - (struct fsmc_regs *)CONFIG_SPEAR_FSMCBASE; - -static struct nand_ecclayout spear_nand_ecclayout = { - .eccbytes = 24, - .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, - 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, - .oobfree = { - {.offset = 8, .length = 8}, - {.offset = 24, .length = 8}, - {.offset = 40, .length = 8}, - {.offset = 56, .length = 8}, - {.offset = 72, .length = 8}, - {.offset = 88, .length = 8}, - {.offset = 104, .length = 8}, - {.offset = 120, .length = 8} - } -}; - -static void spear_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) -{ - struct nand_chip *this = mtd->priv; - ulong IO_ADDR_W; - - if (ctrl & NAND_CTRL_CHANGE) { - IO_ADDR_W = (ulong)this->IO_ADDR_W; - - IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE); - if (ctrl & NAND_CLE) - IO_ADDR_W |= CONFIG_SYS_NAND_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= CONFIG_SYS_NAND_ALE; - - if (ctrl & NAND_NCE) { - writel(readl(&fsmc_regs_p->genmemctrl_pc) | - FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc); - } else { - writel(readl(&fsmc_regs_p->genmemctrl_pc) & - ~FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc); - } - this->IO_ADDR_W = (void *)IO_ADDR_W; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int spear_read_hwecc(struct mtd_info *mtd, - const u_char *data, u_char ecc[3]) -{ - u_int ecc_tmp; - - /* read the h/w ECC */ - ecc_tmp = readl(&fsmc_regs_p->genmemctrl_ecc); - - ecc[0] = (u_char) (ecc_tmp & 0xFF); - ecc[1] = (u_char) ((ecc_tmp & 0xFF00) >> 8); - ecc[2] = (u_char) ((ecc_tmp & 0xFF0000) >> 16); - - return 0; -} - -void spear_enable_hwecc(struct mtd_info *mtd, int mode) -{ - writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~0x80, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~FSMC_ECCEN, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_ECCEN, - &fsmc_regs_p->genmemctrl_pc); -} - -int spear_nand_init(struct nand_chip *nand) -{ - writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_TCLR_1 | FSMC_TAR_1, - &fsmc_regs_p->genmemctrl_pc); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->genmemctrl_comm); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->genmemctrl_attrib); - - nand->options = 0; - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &spear_nand_ecclayout; - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.calculate = spear_read_hwecc; - nand->ecc.hwctl = spear_enable_hwecc; - nand->ecc.correct = nand_correct_data; - nand->cmd_ctrl = spear_nand_hwcontrol; - return 0; -} diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 1398837..a54d534 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -94,7 +94,7 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE

/* NAND FLASH Configuration */ -#define CONFIG_NAND_SPEAR 1 +#define CONFIG_NAND_FSMC 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1

diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index 689d914..fde505c 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -133,6 +133,10 @@

#endif

+/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP 1 +#define CONFIG_SYS_FSMC_NAND_8BIT 1 + #if defined(CONFIG_SPEAR300) #define CONFIG_SYS_NAND_BASE (0x80000000)

diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx.h index 2ad5beb..2532344 100644 --- a/include/configs/spear6xx.h +++ b/include/configs/spear6xx.h @@ -38,6 +38,9 @@ #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ (void *)CONFIG_SYS_SERIAL1 }

+/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP 1 +#define CONFIG_SYS_FSMC_NAND_8BIT 1 #define CONFIG_SYS_NAND_BASE (0xD2000000)

#endif /* __CONFIG_H */

SMI is the serial memory interface controller provided by ST.

The earlier driver was specific to spear platform. The driver files are renamed to st_smi.c and st_smi.h and moved into drivers/mtd folder for reusability by other platforms using smi controller peripheral.

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- drivers/mtd/Makefile | 2 +- drivers/mtd/{spr_smi.c => st_smi.c} | 2 +- .../arch-spear/spr_smi.h => drivers/mtd/st_smi.h | 4 ++-- include/configs/spear-common.h | 6 +++--- 4 files changed, 7 insertions(+), 7 deletions(-) rename drivers/mtd/{spr_smi.c => st_smi.c} (99%) rename arch/arm/include/asm/arch-spear/spr_smi.h => drivers/mtd/st_smi.h (99%)

diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index cbf6f15..d868d27 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -34,7 +34,7 @@ COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o -COBJS-$(CONFIG_SPEARSMI) += spr_smi.o +COBJS-$(CONFIG_ST_SMI) += st_smi.o

COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/st_smi.c similarity index 99% rename from drivers/mtd/spr_smi.c rename to drivers/mtd/st_smi.c index c6ba951..5193c1c 100644 --- a/drivers/mtd/spr_smi.c +++ b/drivers/mtd/st_smi.c @@ -27,7 +27,7 @@

#include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/spr_smi.h> +#include "st_smi.h"

#if !defined(CONFIG_SYS_NO_FLASH)

diff --git a/arch/arm/include/asm/arch-spear/spr_smi.h b/drivers/mtd/st_smi.h similarity index 99% rename from arch/arm/include/asm/arch-spear/spr_smi.h rename to drivers/mtd/st_smi.h index 0cca000..afab546 100644 --- a/arch/arm/include/asm/arch-spear/spr_smi.h +++ b/drivers/mtd/st_smi.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */

-#ifndef SPR_SMI_H -#define SPR_SMI_H +#ifndef ST_SMI_H +#define ST_SMI_H

/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 2393bdf..4aa0c15 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -61,10 +61,10 @@ #if defined(CONFIG_FLASH_PNOR) #define CONFIG_SPEAR_EMI 1 #else -#define CONFIG_SPEARSMI 1 +#define CONFIG_ST_SMI 1 #endif

-#if defined(CONFIG_SPEARSMI) +#if defined(CONFIG_ST_SMI)

#define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_BASE (0xF8000000) @@ -130,7 +130,7 @@ * U-Boot Environment placing definitions. */ #if defined(CONFIG_ENV_IS_IN_FLASH) -#ifdef CONFIG_SPEARSMI +#ifdef CONFIG_ST_SMI /* * Environment is in serial NOR flash */

spear3xx and 6xx boards can be compiled in following configurations 1. Environment placed in NAND 2. console on usb device 3. console on usb device with environment placed in NAND

Also, renaming the include/configs/spearxxx.h files to spear3xx_evb.h, spear6xx_evb.h etc to depict evaluation board configuration.

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- Makefile | 22 +++++++++++++---- board/spear/spear300/config.mk | 11 -------- board/spear/spear310/config.mk | 11 -------- board/spear/spear320/config.mk | 11 -------- board/spear/spear600/config.mk | 11 -------- doc/README.spear | 31 +++++++++++++++++------- include/configs/{spear3xx.h => spear3xx_evb.h} | 10 +++++++ include/configs/{spear6xx.h => spear6xx_evb.h} | 10 +++++++ 8 files changed, 59 insertions(+), 58 deletions(-) rename include/configs/{spear3xx.h => spear3xx_evb.h} (95%) rename include/configs/{spear6xx.h => spear6xx_evb.h} (88%)

diff --git a/Makefile b/Makefile index 7b4678e..e8b4ac9 100644 --- a/Makefile +++ b/Makefile @@ -3044,12 +3044,24 @@ smdk2410_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0

spear300_config \ +spear300_nand_config \ +spear300_usbtty_config \ +spear300_usbtty_nand_config \ spear310_config \ -spear320_config : unconfig - @$(MKCONFIG) -n $@ -t $(@:_config=) spear3xx arm arm926ejs $(@:_config=) spear spear - -spear600_config : unconfig - @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx arm arm926ejs $(@:_config=) spear spear +spear310_nand_config \ +spear310_usbtty_config \ +spear310_usbtty_nand_config \ +spear320_config \ +spear320_nand_config \ +spear320_usbtty_config \ +spear320_usbtty_nand_config : unconfig + @$(MKCONFIG) -n $@ -t $(@:_config=) spear3xx_evb arm arm926ejs $(@:_config=) spear spear + +spear600_config \ +spear600_nand_config \ +spear600_usbtty_config \ +spear600_usbtty_nand_config : unconfig + @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx_evb arm arm926ejs $(@:_config=) spear spear

suen3_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs km_arm keymile kirkwood diff --git a/board/spear/spear300/config.mk b/board/spear/spear300/config.mk index 35646f2..0bbb40f 100644 --- a/board/spear/spear300/config.mk +++ b/board/spear/spear300/config.mk @@ -26,14 +26,3 @@ TEXT_BASE = 0x00700000

ALL += $(obj)u-boot.img - -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear310/config.mk b/board/spear/spear310/config.mk index cba8436..c8264c3 100644 --- a/board/spear/spear310/config.mk +++ b/board/spear/spear310/config.mk @@ -27,18 +27,7 @@ TEXT_BASE = 0x00700000

ALL += $(obj)u-boot.img

-# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - # Support parallel flash ifeq ($(FLASH),PNOR) PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk index cba8436..c8264c3 100644 --- a/board/spear/spear320/config.mk +++ b/board/spear/spear320/config.mk @@ -27,18 +27,7 @@ TEXT_BASE = 0x00700000

ALL += $(obj)u-boot.img

-# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - # Support parallel flash ifeq ($(FLASH),PNOR) PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk index 35646f2..0bbb40f 100644 --- a/board/spear/spear600/config.mk +++ b/board/spear/spear600/config.mk @@ -26,14 +26,3 @@ TEXT_BASE = 0x00700000

ALL += $(obj)u-boot.img - -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/doc/README.spear b/doc/README.spear index a6ff7fd..3161e64 100644 --- a/doc/README.spear +++ b/doc/README.spear @@ -6,9 +6,9 @@ SPEAr600 is also known as SPEArPlus and SPEAr300 is also known as SPEArBasic The SPEAr SoC family embeds a customizable logic that can be programmed one-time by a customer at silicon mask level (i.e. not at runtime!).

-We are now adding the support in u-boot for two SoC: SPEAr600 and SPEAr3xx. +U-Boot supports four SoCs: SPEAr600, SPEAr3xx

-All 4 SoCs share common peripherals. +All 4 SoCs (SPEAr3xx and SPEAr600) share common peripherals.

1. ARM926ejs core based (sp600 has two cores, the 2nd handled only in Linux) 2. FastEthernet (sp600 has Gbit version, but same controller - GMAC) @@ -22,7 +22,7 @@ All 4 SoCs share common peripherals. 10. others ..

Everything is supported in Linux. -u-boot is not currently supporting all peripeharls (just a few as listed below). +u-boot is currently not supporting all peripeharls (just a few as listed below). 1. USB Device 2. NAND controller (FSMC) 3. Serial Memory Interface @@ -32,17 +32,30 @@ u-boot is not currently supporting all peripeharls (just a few as listed below).

Build options make spear600_config + spear600 build with environment variables placed at default + location i.e. Serial NOR device + make spear600_nand_config + spear600 build with environment variables placed in NAND device + make spear600_usbtty_config + spear600 build with usbtty terminal as default and environment + placed at default location + make spear600_usbtty_nand_config + Build with usbtty terminal as default and environment placed in + NAND device make spear300_config + make spear300_nand_config + make spear300_usbtty_config + make spear300_usbtty_nand_config make spear310_config + make spear310_nand_config + make spear310_usbtty_config + make spear310_usbtty_nand_config make spear320_config + make spear320_nand_config + make spear320_usbtty_config + make spear320_usbtty_nand_config

Further options - make ENV=NAND (supported by all 4 SoCs) - - This option generates a uboot image that saves environment inn NAND - - make CONSOLE=USB (supported by all 4 SoCs) - - This option generates a uboot image for using usbdevice as a tty i/f - make FLASH=PNOR (supported by SPEAr310 and SPEAr320) - This option generates a uboot image that supports emi controller for CFI compliant parallel NOR flash diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx_evb.h similarity index 95% rename from include/configs/spear3xx.h rename to include/configs/spear3xx_evb.h index fde505c..f0c915e 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx_evb.h @@ -39,6 +39,16 @@ #define CONFIG_SPEAR320 1 #endif

+#if defined(CONFIG_MK_usbtty) +#define CONFIG_SPEAR_USBTTY 1 +#endif + +#if defined(CONFIG_MK_nand) +#define CONFIG_ENV_IS_IN_NAND 1 +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + #include <configs/spear-common.h>

/* Ethernet driver configuration */ diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx_evb.h similarity index 88% rename from include/configs/spear6xx.h rename to include/configs/spear6xx_evb.h index 2532344..82d24df 100644 --- a/include/configs/spear6xx.h +++ b/include/configs/spear6xx_evb.h @@ -30,6 +30,16 @@ */ #define CONFIG_SPEAR600 1

+#if defined(CONFIG_MK_usbtty) +#define CONFIG_SPEAR_USBTTY 1 +#endif + +#if defined(CONFIG_MK_nand) +#define CONFIG_ENV_IS_IN_NAND 1 +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + #include <configs/spear-common.h>

/* Serial Configuration (PL011) */

SPEAr1300 SoC support contains basic spear1300 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 6 + arch/arm/include/asm/arch-spear13xx/hardware.h | 8 +- board/spear/common/Makefile | 10 +- board/spear/spear1300/Makefile | 51 ++++++ board/spear/spear1300/config.mk | 28 ++++ board/spear/spear1300/spear1300.c | 88 ++++++++++ board/spear/spear1300/spr_lowlevel_init.S | 38 +++++ doc/README.spear | 11 +- include/configs/spear13xx_evb.h | 202 ++++++++++++++++++++++++ 11 files changed, 436 insertions(+), 8 deletions(-) create mode 100644 board/spear/spear1300/Makefile create mode 100644 board/spear/spear1300/config.mk create mode 100644 board/spear/spear1300/spear1300.c create mode 100644 board/spear/spear1300/spr_lowlevel_init.S create mode 100644 include/configs/spear13xx_evb.h

diff --git a/MAINTAINERS b/MAINTAINERS index 5cbc845..9275279 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -650,6 +650,7 @@ Prakash Kumar prakash@embedx.com

Vipin Kumar vipin.kumar@st.com

+ spear1300 ARM CORTEX-A9 (spear1300 Soc) spear300 ARM926EJS (spear300 Soc) spear310 ARM926EJS (spear310 Soc) spear320 ARM926EJS (spear320 Soc) diff --git a/MAKEALL b/MAKEALL index bb09627..d098b35 100755 --- a/MAKEALL +++ b/MAKEALL @@ -651,6 +651,7 @@ LIST_ARM_CORTEX_A8=" \ omap3_zoom1 \ omap3_zoom2 \ smdkc100 \ + spear1300 \ "

######################################################################### diff --git a/Makefile b/Makefile index e8b4ac9..5f1da2f 100644 --- a/Makefile +++ b/Makefile @@ -3063,6 +3063,12 @@ spear600_usbtty_config \ spear600_usbtty_nand_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx_evb arm arm926ejs $(@:_config=) spear spear

+spear1300_config \ +spear1300_nand_config \ +spear1300_usbtty_config \ +spear1300_usbtty_nand_config : unconfig + @$(MKCONFIG) -n $@ -t $(@:_config=) spear13xx_evb arm arm_cortexa8 spear1300 spear spear13xx + suen3_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs km_arm keymile kirkwood

diff --git a/arch/arm/include/asm/arch-spear13xx/hardware.h b/arch/arm/include/asm/arch-spear13xx/hardware.h index 020ab2a..e3dd6e5 100644 --- a/arch/arm/include/asm/arch-spear13xx/hardware.h +++ b/arch/arm/include/asm/arch-spear13xx/hardware.h @@ -24,10 +24,10 @@ #ifndef _ASM_ARCH_SPEAR13XX_HARDWARE_H #define _ASM_ARCH_SPEAR13XX_HARDWARE_H

-#define CONFIG_SYS_USBD_BASE (0xE1100000) -#define CONFIG_SYS_PLUG_BASE (0xE1200000) -#define CONFIG_SYS_FIFO_BASE (0xE1000800) -#define CONFIG_SYS_SMI_BASE (0xFC000000) +#define CONFIG_SYS_USBD_BASE (0xE3800000) +#define CONFIG_SYS_PLUG_BASE (0xE2800000) +#define CONFIG_SYS_FIFO_BASE (0xE3000800) +#define CONFIG_SYS_SMI_BASE (0xEA000000) #define CONFIG_SPEAR_TIMERBASE (0xE0380000) #define CONFIG_SPEAR_MISCBASE (0xE0700000) #define CONFIG_SYS_I2C_BASE (0xE0280000) diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile index 4f8959f..1ae4fd4 100644 --- a/board/spear/common/Makefile +++ b/board/spear/common/Makefile @@ -29,8 +29,14 @@ endif

LIB = $(obj)lib$(VENDOR).a

-COBJS := spr_misc.o -SOBJS := spr_lowlevel_init.o +COBJS-$(CONFIG_SPEAR3XX) += spr_misc.o +COBJS-$(CONFIG_SPEAR600) += spr_misc.o + +SOBJS-$(CONFIG_SPEAR3XX) += spr_lowlevel_init.o +SOBJS-$(CONFIG_SPEAR600) += spr_lowlevel_init.o + +COBJS := $(COBJS-y) +SOBJS := $(SOBJS-y)

SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/spear/spear1300/Makefile b/board/spear/spear1300/Makefile new file mode 100644 index 0000000..fb66895 --- /dev/null +++ b/board/spear/spear1300/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := spear1300.o +SOBJS := spr_lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/spear1300/config.mk b/board/spear/spear1300/config.mk new file mode 100644 index 0000000..4bd519c --- /dev/null +++ b/board/spear/spear1300/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2010 +# Vipin Kumar, ST Microelectronics vipin.kumar@st.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +TEXT_BASE = 0x00700000 + +ALL += $(obj)u-boot.img diff --git a/board/spear/spear1300/spear1300.c b/board/spear/spear1300/spear1300.c new file mode 100644 index 0000000..09a5c8d --- /dev/null +++ b/board/spear/spear1300/spear1300.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <nand.h> +#include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_SPEAR1300; + gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR; + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1, + PHYS_SDRAM_1_MAXSIZE); + + return 0; +} + +int misc_init_r(void) +{ + setenv("verify", "n"); + +#if defined(CONFIG_SPEAR_USBTTY) + setenv("stdin", "usbtty"); + setenv("stdout", "usbtty"); + setenv("stderr", "usbtty"); +#endif + return 0; +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +int board_nand_init(struct nand_chip *nand) +{ +#if defined(CONFIG_NAND_FSMC) + return fsmc_nand_init(nand); +#else + return -1; +#endif +} + +#if defined(CONFIG_CMD_NET) +int board_eth_init(bd_t *bis) +{ + /* + * Board specific ethernet initialization comes here. eg. gmac clock + * configuration etc + */ + + return designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY); +} +#endif diff --git a/board/spear/spear1300/spr_lowlevel_init.S b/board/spear/spear1300/spr_lowlevel_init.S new file mode 100644 index 0000000..13e0372 --- /dev/null +++ b/board/spear/spear1300/spr_lowlevel_init.S @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + +/* + * platform specific initializations are already done in Xloader + * Initializations already done include + * DDR, PLLs, IP's clock enable and reset release etc + */ +.globl lowlevel_init +lowlevel_init: + /* By default, U-Boot switches CPU to low-vector */ + /* Revert this as we work in high vector even in U-Boot */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00002000 + mcr p15, 0, r0, c1, c0, 0 + mov pc, lr diff --git a/doc/README.spear b/doc/README.spear index 3161e64..94b492f 100644 --- a/doc/README.spear +++ b/doc/README.spear @@ -6,9 +6,10 @@ SPEAr600 is also known as SPEArPlus and SPEAr300 is also known as SPEArBasic The SPEAr SoC family embeds a customizable logic that can be programmed one-time by a customer at silicon mask level (i.e. not at runtime!).

-U-Boot supports four SoCs: SPEAr600, SPEAr3xx +U-Boot supports five spear SoCs: SPEAr600, SPEAr3xx, SPEAr1300

-All 4 SoCs (SPEAr3xx and SPEAr600) share common peripherals. +4 SoCs (SPEAr3xx and SPEAr600) share common peripherals. SPEAr1300 is based on +ARM CortexA9 core and other peripherals are common

1. ARM926ejs core based (sp600 has two cores, the 2nd handled only in Linux) 2. FastEthernet (sp600 has Gbit version, but same controller - GMAC) @@ -29,6 +30,7 @@ u-boot is currently not supporting all peripeharls (just a few as listed below). 4. EMI (Parallel NOR interface) 4. I2C 5. UART +6. Network

Build options make spear600_config @@ -55,6 +57,11 @@ Build options make spear320_usbtty_config make spear320_usbtty_nand_config

+ make spear1300_config + make spear1300_nand_config + make spear1300_usbtty_config + make spear1300_usbtty_nand_config + Further options make FLASH=PNOR (supported by SPEAr310 and SPEAr320) - This option generates a uboot image that supports emi controller for diff --git a/include/configs/spear13xx_evb.h b/include/configs/spear13xx_evb.h new file mode 100644 index 0000000..82e30c6 --- /dev/null +++ b/include/configs/spear13xx_evb.h @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if defined(CONFIG_MK_spear1300) +#define CONFIG_SPEAR13XX 1 +#define CONFIG_SPEAR1300 1 +#endif + +#if defined(CONFIG_MK_usbtty) +#define CONFIG_SPEAR_USBTTY 1 +#endif + +#if defined(CONFIG_MK_nand) +#define CONFIG_ENV_IS_IN_NAND 1 +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + +/* Ethernet configuration */ +#define CONFIG_MII +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_NET_MULTI +#define CONFIG_DW_ALTDESCRIPTOR 1 +#define CONFIG_DW_SEARCH_PHY 1 +#define CONFIG_DW0_PHY 1 +#define CONFIG_PHY_RESET_DELAY (10000) /* in usec */ + +/* USBD driver configuration */ +#define CONFIG_DW_UDC +#define CONFIG_USB_DEVICE +#define CONFIG_USB_TTY + +#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" +#define CONFIG_USBD_MANUFACTURER "ST Microelectronics" + +#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" + +/* Timer, HZ specific defines */ +#define CONFIG_SYS_HZ (1000) + +/* Flash configuration */ +#define CONFIG_ST_SMI 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BASE (0xE6000000) +#define CONFIG_SYS_CS1_FLASH_BASE (0xE7000000) +#define CONFIG_SYS_FLASH_BANK_SIZE (0x01000000) +#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) + +/* + * Serial Configuration (PL011) + */ +#define CONFIG_PL011_SERIAL +#define CONFIG_SYS_SERIAL0 0xE0000000 +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ + 57600, 115200 } + +#define CONFIG_SYS_LOADS_BAUD_CHANGE +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} + +/* + * NAND FLASH Configuration + */ +#define CONFIG_NAND_FSMC 1 +#define CONFIG_SYS_FSMC_NAND_LP 1 +#define CONFIG_SYS_FSMC_NAND_8BIT 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_SYS_NAND_BASE (0xA0000000) + +/* + * Command support defines + */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_RUN +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <config_cmd_default.h> + +/* + * Default Environment Varible definitions + */ +#if defined(CONFIG_SPEAR_USBTTY) +/* This disbales autobooting and stops at uboot prompt */ +#define CONFIG_BOOTDELAY -1 +#else +#define CONFIG_BOOTDELAY 1 +#endif + +/* + * Environment placing + */ +#if defined(CONFIG_ENV_IS_IN_FLASH) +/* + * Environment is in serial NOR flash + */ +#define CONFIG_SYS_MONITOR_LEN 0x00040000 +#define CONFIG_ENV_SECT_SIZE 0x00010000 +#define CONFIG_FSMTDBLK "/dev/mtdblock8 " + +#define CONFIG_BOOTCOMMAND "bootm 0xe6050000" + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#elif defined(CONFIG_ENV_IS_IN_NAND) +/* + * Environment is in NAND + */ + +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_RANGE 0x10000 +#define CONFIG_FSMTDBLK "/dev/mtdblock12 " + +#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \ + "0x80000 0x4C0000; " \ + "bootm 0x1600000" +#endif + +#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \ + "console=ttyAMA0 init=/bin/sh" +#define CONFIG_BOOTARGS "console=ttyAMA0 mem=128M " \ + "root="CONFIG_FSMTDBLK \ + "rootfstype=jffs2" + +#define CONFIG_ENV_SIZE 0x02000 + +/* Miscellaneous configurable options */ +#define CONFIG_ARCH_CPU_INIT 1 +#define CONFIG_DISPLAY_CPUINFO 1 + +#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_PROMPT \ + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay + +#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x04000000 +#define CONFIG_SYS_MALLOC_LEN (1024*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_IDENT_STRING "-SPEAr" +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "u-boot> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 +#define CONFIG_SYS_64BIT_VSPRINTF 1 + +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_MAXSIZE 0x40000000 + +#endif

This patch fixes a few bugs in USB device controller driver. The fixes are as follows 1. Adding error condition checks eg. NULL return 2. Endpoint other than endpoint 0 (control endpoint) are initialized only if usb state machine reaches STATE_ADDRESSED or above 3. Zero length packet handling corrected 4. Dead code removed 5. Bulk out endpoint returns after servicing 1 interrupt and returns back to service if more interrupts are pending

Signed-off-by: Vipin Kumar vipin.kumar@st.com --- drivers/usb/gadget/designware_udc.c | 59 ++++++++++++++++++++++------------ 1 files changed, 38 insertions(+), 21 deletions(-)

diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c index aee44aa..3c20f3d 100644 --- a/drivers/usb/gadget/designware_udc.c +++ b/drivers/usb/gadget/designware_udc.c @@ -497,16 +497,24 @@ static void dw_udc_epn_tx(int ep) { struct usb_endpoint_instance *endpoint = dw_find_ep(ep);

+ if (!endpoint) + return; + /* * We need to transmit a terminating zero-length packet now if * we have sent all of the data in this URB and the transfer * size was an exact multiple of the packet size. */ - if (endpoint && endpoint->tx_urb && endpoint->tx_urb->actual_length) { - if (endpoint->last == endpoint->tx_packetSize) { - /* handle zero length packet here */ - writel(0x0, &inep_regs_p[ep].write_done); - } + if (endpoint->tx_urb && + (endpoint->last == endpoint->tx_packetSize) && + (endpoint->tx_urb->actual_length - endpoint->sent - + endpoint->last == 0)) { + /* handle zero length packet here */ + writel(0x0, &inep_regs_p[ep].write_done); + + } + + if (endpoint->tx_urb && endpoint->tx_urb->actual_length) { /* retire the data that was just sent */ usbd_tx_complete(endpoint); /* @@ -548,8 +556,6 @@ int udc_init(void)

readl(&plug_regs_p->plug_pending);

- udc_disconnect(); - for (i = 0; i < UDC_INIT_MDELAY; i++) udelay(1000);

@@ -561,10 +567,9 @@ int udc_init(void) writel(~0x0, &udc_regs_p->endp_int_mask);

writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW | - /* Dev_Conf_SYNCFRAME | */ DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);

- writel(0x0, &udc_regs_p->dev_cntl); + writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl);

/* Clear all interrupts pending */ writel(DEV_INT_MSK, &udc_regs_p->dev_int); @@ -588,6 +593,9 @@ void udc_setup_ep(struct usb_device_instance *device, char *tt; u32 endp_intmask;

+ if ((ep != 0) && (udc_device->device_state < STATE_ADDRESSED)) + return; + tt = getenv("usbtty"); if (!tt) tt = "generic"; @@ -647,9 +655,6 @@ void udc_setup_ep(struct usb_device_instance *device, writel(packet_size | ((buffer_size / sizeof(int)) << 16), &out_p->endp_maxpacksize);

- writel((packet_size << 19) | ENDP_EPTYPE_CNTL, - &udc_regs_p->udc_endp_reg[ep_num]); - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { /* Setup the IN endpoint */ writel(0x0, &in_p->endp_status); @@ -708,7 +713,17 @@ void udc_setup_ep(struct usb_device_instance *device, /* Turn on the USB connection by enabling the pullup resistor */ void udc_connect(void) { - u32 plug_st; + u32 plug_st, dev_cntl; + + dev_cntl = readl(&udc_regs_p->dev_cntl); + dev_cntl |= DEV_CNTL_SOFTDISCONNECT; + writel(dev_cntl, &udc_regs_p->dev_cntl); + + udelay(1000); + + dev_cntl = readl(&udc_regs_p->dev_cntl); + dev_cntl &= ~DEV_CNTL_SOFTDISCONNECT; + writel(dev_cntl, &udc_regs_p->dev_cntl);

plug_st = readl(&plug_regs_p->plug_state); plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); @@ -720,6 +735,8 @@ void udc_disconnect(void) { u32 plug_st;

+ writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl); + plug_st = readl(&plug_regs_p->plug_state); plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); writel(plug_st, &plug_regs_p->plug_state); @@ -789,11 +806,6 @@ void dw_udc_plug_irq(void) UDCDBG("device attached and powered"); udc_state_transition(udc_device->device_state, STATE_POWERED); } else { - /* - * USB cable detached - * Reset the PHY and switch the mode. - */ - udc_disconnect(); writel(~0x0, &udc_regs_p->dev_int_mask);

UDCDBG("device detached or unpowered"); @@ -809,13 +821,18 @@ void dw_udc_dev_irq(void) if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) { writel(~0x0, &udc_regs_p->endp_int_mask);

- udc_connect(); - writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH, &inep_regs_p[0].endp_cntl);

writel(DEV_INT_USBRESET, &udc_regs_p->dev_int);

+ /* + * This endpoint0 specific register can be programmed only + * after the phy clock is initialized + */ + writel((EP0_MAX_PACKET_SIZE << 19) | ENDP_EPTYPE_CNTL, + &udc_regs_p->udc_endp_reg[0]); + UDCDBG("device reset in progess"); udc_state_transition(udc_device->device_state, STATE_DEFAULT); } @@ -902,7 +919,7 @@ void dw_udc_endpoint_irq(void) writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int); }

- while (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) { + if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) { u32 epnum = 0; u32 ep_int = readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK;