[PATCH 0/5] xilinx: Sync DTs with Xilinx tree
Hi,
I am sending patches which I found are not sent out yet. These 5 patches are fixing typos or incorrect device description or adding already defined properties.
Thanks, Michal
Amit Kumar Mahapatra (1): arm64: versal: Add no-wp DT property in OSPI flash node
Michal Simek (1): arm64: zynqmp: Rename xlnx,mio_bank to xlnx,mio-bank for DLC21
Saeed Nowshadi (1): arm64: zynqmp: Fix i2c address for si570_user1 clock
Srinivas Neeli (1): arm64: zynqmp: Add resets property for CAN nodes
Thippeswamy Havalige (1): arm64: zynqmp: Update ECAM size to discover up to 256 buses
arch/arm/dts/versal-mini-ospi.dtsi | 1 + arch/arm/dts/versal-net-mini-ospi.dtsi | 1 + arch/arm/dts/zynqmp-dlc21-revA.dts | 4 ++-- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 7 ++++--- arch/arm/dts/zynqmp.dtsi | 4 +++- 5 files changed, 11 insertions(+), 6 deletions(-)
xlnx,mio_bank was used in past but it was renamed to xlnx,mio-bank because '_' in property shoudln't be used. There is no impact on the platform because if the properly is not defined bank 0 is default. Bank 0 and 1 have the same configuration that's why there shouldn't be any issue.
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-dlc21-revA.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 1b247bfa8944..016081ef7b99 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -61,14 +61,14 @@ non-removable; disable-wp; bus-width = <8>; - xlnx,mio_bank = <0>; + xlnx,mio-bank = <0>; };
&sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; - xlnx,mio_bank = <1>; + xlnx,mio-bank = <1>; };
&psgtr {
From: Amit Kumar Mahapatra amit.kumar-mahapatra@amd.com
Added no-wp DT property in OSPI flash node for all board dts & dtsi files on which the WP# signal of the OSPI flash device is not connected. If this property is set, then the software will avoid setting the status register write disable (SRWD) bit in status register during status register write operation.
Signed-off-by: Amit Kumar Mahapatra amit.kumar-mahapatra@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/versal-mini-ospi.dtsi | 1 + arch/arm/dts/versal-net-mini-ospi.dtsi | 1 + 2 files changed, 2 insertions(+)
diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi index 19caea7368a0..5683a2306bde 100644 --- a/arch/arm/dts/versal-mini-ospi.dtsi +++ b/arch/arm/dts/versal-mini-ospi.dtsi @@ -57,6 +57,7 @@ spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; + no-wp; }; }; }; diff --git a/arch/arm/dts/versal-net-mini-ospi.dtsi b/arch/arm/dts/versal-net-mini-ospi.dtsi index ce8e2158f6ed..5d188db62d92 100644 --- a/arch/arm/dts/versal-net-mini-ospi.dtsi +++ b/arch/arm/dts/versal-net-mini-ospi.dtsi @@ -72,6 +72,7 @@ spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; + no-wp; }; }; };
From: Saeed Nowshadi saeed.nowshadi@amd.com
Correct the i2c address for si570 oscillator that generates the si570_user1 clock. i2c address was changed by commit b6a8c603d680 ("arm64: zynqmp: Fix i2c addresses for vck190 SC") because address in node name wasn't aligned with reg property. But actual 0x5f address is correct which is quite rare because all other si570s are at 0x5d.
Signed-off-by: Saeed Nowshadi saeed.nowshadi@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index bf6ffb778b6a..bf7569c6dda5 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019 - 2021, Xilinx, Inc. + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek michal.simek@amd.com */ @@ -460,10 +461,10 @@ #address-cells = <1>; #size-cells = <0>; reg = <6>; - si570_user1: clock-generator@5d { /* u205 */ + si570_user1: clock-generator@5f { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; - reg = <0x5d>; + reg = <0x5f>; temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>;
From: Srinivas Neeli srinivas.neeli@amd.com
Added resets property for CAN nodes.
Signed-off-by: Srinivas Neeli srinivas.neeli@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 355f360281b5..a71875755bc0 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -262,6 +262,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>; power-domains = <&zynqmp_firmware PD_CAN_0>; };
@@ -274,6 +275,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>; power-domains = <&zynqmp_firmware PD_CAN_1>; };
From: Thippeswamy Havalige thippeswamy.havalige@amd.com
Update ECAM size to discover up to 256 buses
Signed-off-by: Thippeswamy Havalige thippeswamy.havalige@amd.com Acked-by: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index a71875755bc0..79c5af241104 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -678,7 +678,7 @@ msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
On 9/11/23 16:10, Michal Simek wrote:
Hi,
I am sending patches which I found are not sent out yet. These 5 patches are fixing typos or incorrect device description or adding already defined properties.
Thanks, Michal
Amit Kumar Mahapatra (1): arm64: versal: Add no-wp DT property in OSPI flash node
Michal Simek (1): arm64: zynqmp: Rename xlnx,mio_bank to xlnx,mio-bank for DLC21
Saeed Nowshadi (1): arm64: zynqmp: Fix i2c address for si570_user1 clock
Srinivas Neeli (1): arm64: zynqmp: Add resets property for CAN nodes
Thippeswamy Havalige (1): arm64: zynqmp: Update ECAM size to discover up to 256 buses
arch/arm/dts/versal-mini-ospi.dtsi | 1 + arch/arm/dts/versal-net-mini-ospi.dtsi | 1 + arch/arm/dts/zynqmp-dlc21-revA.dts | 4 ++-- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 7 ++++--- arch/arm/dts/zynqmp.dtsi | 4 +++- 5 files changed, 11 insertions(+), 6 deletions(-)
Applied. M
participants (1)
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Michal Simek