From: Stefan Agner stefan.agner@toradex.com

This converts CONFIG_NAND_MXS to Kconfig.

Signed-off-by: Stefan Agner stefan.agner@toradex.com ---

Changes in v2: - Extend the patchset with "Convert CONFIG_NAND_MXS to Kconfig" patch

configs/apx4devkit_defconfig | 3 ++- configs/aristainetos2_defconfig | 3 ++- configs/aristainetos2b_defconfig | 3 ++- configs/aristainetos_defconfig | 3 ++- configs/cm_fx6_defconfig | 11 ++--------- configs/colibri_imx7_defconfig | 3 ++- configs/gwventana_nand_defconfig | 3 ++- configs/m28evk_defconfig | 3 ++- configs/mx28evk_auart_console_defconfig | 3 ++- configs/mx28evk_defconfig | 3 ++- configs/mx28evk_nand_defconfig | 3 ++- configs/mx28evk_spi_defconfig | 3 ++- configs/mx6sabreauto_defconfig | 3 ++- configs/mx6sxsabreauto_defconfig | 3 ++- configs/pcm058_defconfig | 3 ++- configs/pfla02_defconfig | 3 +++ configs/platinum_picon_defconfig | 3 ++- configs/platinum_titanium_defconfig | 3 ++- configs/titanium_defconfig | 3 ++- include/configs/aristainetos-common.h | 1 - include/configs/cm_fx6.h | 1 - include/configs/colibri_imx7.h | 2 -- include/configs/gw_ventana.h | 1 - include/configs/mx6sabreauto.h | 1 - include/configs/mx6sxsabreauto.h | 1 - include/configs/mxs.h | 1 - include/configs/pcm058.h | 1 - include/configs/pfla02.h | 1 - include/configs/platinum.h | 1 - include/configs/titanium.h | 1 - 30 files changed, 39 insertions(+), 38 deletions(-)

diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig index 47a4ee9e26..cc6da42066 100644 --- a/configs/apx4devkit_defconfig +++ b/configs/apx4devkit_defconfig @@ -13,7 +13,6 @@ CONFIG_SPL=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -27,6 +26,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y CONFIG_MMC_MXS=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 288dab0d3c..c0daed6b22 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -14,7 +14,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y @@ -31,6 +30,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MTD_UBI_FASTMAP=y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig index 115ae07ad6..fbb2c1c38d 100644 --- a/configs/aristainetos2b_defconfig +++ b/configs/aristainetos2b_defconfig @@ -14,7 +14,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y @@ -31,6 +30,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MTD_UBI_FASTMAP=y diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig index cad8b4af8a..13f4d6eb52 100644 --- a/configs/aristainetos_defconfig +++ b/configs/aristainetos_defconfig @@ -14,7 +14,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y @@ -31,6 +30,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MTD_UBI_FASTMAP=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 6b1c0a823c..995baabd5d 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -20,9 +20,7 @@ CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd" CONFIG_SPL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 CONFIG_SPL_I2C_SUPPORT=y -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CM-FX6 # " -CONFIG_CMD_BOOTZ=y # CONFIG_CMD_XIMG is not set CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y @@ -35,20 +33,13 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_SATA=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768k(uboot),256k(uboot-environment),-(reserved)" @@ -57,6 +48,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index efc4ccb0f6..7880f7733b 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_NAND_TORTURE=y CONFIG_CMD_USB=y @@ -45,6 +44,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index be6cf0cbde..fbfd352054 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y @@ -57,6 +56,8 @@ CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_DWC_AHSATA=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_PHYLIB=y CONFIG_NETDEVICES=y CONFIG_E1000=y diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig index 3bc6b1835f..77d67a9916 100644 --- a/configs/m28evk_defconfig +++ b/configs/m28evk_defconfig @@ -21,7 +21,6 @@ CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -41,6 +40,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(u-boot),512k(env1),512k(env2),14m CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y CONFIG_MMC_MXS=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_USB=y diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig index c4977564e4..09273333f3 100644 --- a/configs/mx28evk_auart_console_defconfig +++ b/configs/mx28evk_auart_console_defconfig @@ -16,7 +16,6 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -36,6 +35,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),5 CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_MMC=y CONFIG_MMC_MXS=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_USB=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 40c9df2809..21d01bc8c6 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -16,7 +16,6 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -36,6 +35,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),5 CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_MMC=y CONFIG_MMC_MXS=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_USB=y diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig index ea97f401d1..3e4ba39e32 100644 --- a/configs/mx28evk_nand_defconfig +++ b/configs/mx28evk_nand_defconfig @@ -15,7 +15,6 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -35,6 +34,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),5 CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y CONFIG_MMC_MXS=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_USB=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig index 34e9927c0f..dab5394943 100644 --- a/configs/mx28evk_spi_defconfig +++ b/configs/mx28evk_spi_defconfig @@ -15,7 +15,6 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -35,6 +34,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),5 CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MMC_MXS=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_USB=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 215700bc3f..0a713d5b10 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_PART=y CONFIG_CMD_SF=y @@ -40,6 +39,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index a2c4830795..43b6ab9c6c 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -10,7 +10,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y @@ -31,6 +30,8 @@ CONFIG_DM_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index 99713c26b2..daca54dbc3 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_SF=y CONFIG_CMD_DHCP=y @@ -48,6 +47,8 @@ CONFIG_EFI_PARTITION=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig index 029c9de2ce..a9daccfd6a 100644 --- a/configs/pfla02_defconfig +++ b/configs/pfla02_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_NAND is not set CONFIG_CMD_SF=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -45,6 +46,8 @@ CONFIG_EFI_PARTITION=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DM=y CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig index 54d88b2dc0..c45ce14268 100644 --- a/configs/platinum_picon_defconfig +++ b/configs/platinum_picon_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -41,6 +40,8 @@ CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),495M(ubi0),14M(res0),2M(res1),512k(res2),512k(res3),-(ubi1)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_PHYLIB=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig index c5f6b7ab62..9ef0b80a2c 100644 --- a/configs/platinum_titanium_defconfig +++ b/configs/platinum_titanium_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -41,6 +40,8 @@ CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),-(ubi)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig index c47702ed4e..3a721cdfa5 100644 --- a/configs/titanium_defconfig +++ b/configs/titanium_defconfig @@ -11,7 +11,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -29,6 +28,8 @@ CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:16M(uboot),512k(env1),512k(env2),-(ubi)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index 397afbb408..9b1a39d4fd 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -176,7 +176,6 @@ #define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} }

/* NAND stuff */ -#define CONFIG_NAND_MXS #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index da870b9baa..90cf024bdb 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -182,7 +182,6 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_MXS #define CONFIG_SYS_NAND_ONFI_DETECTION /* APBH DMA is required for NAND support */ #define CONFIG_APBH_DMA diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 8030ca69e7..d4aaff61fd 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -158,8 +158,6 @@ #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE #endif

-#define CONFIG_NAND_MXS - /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index d2944b5db2..517ad08423 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -67,7 +67,6 @@ #elif defined(CONFIG_SPL_NAND_SUPPORT) /* Enable NAND support */ #ifdef CONFIG_CMD_NAND - #define CONFIG_NAND_MXS #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 64d54b6751..9982685f67 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -66,7 +66,6 @@ #define CONFIG_SYS_I2C_SPEED 100000

/* NAND stuff */ -#define CONFIG_NAND_MXS #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 9e46c397a4..02d6acf47e 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -119,7 +119,6 @@ #define CONFIG_SYS_I2C_SPEED 100000

/* NAND stuff */ -#define CONFIG_NAND_MXS #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 3a27c15060..21e51fca41 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -136,7 +136,6 @@

/* NAND */ #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_MXS #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x60000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 3067fc63ef..6c0902abd4 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -58,7 +58,6 @@

#ifndef CONFIG_SPL_BUILD /* Enable NAND support */ -#define CONFIG_NAND_MXS #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h index ae03310040..83198a1065 100644 --- a/include/configs/pfla02.h +++ b/include/configs/pfla02.h @@ -57,7 +57,6 @@ #define CONFIG_CMD_NAND /* Enable NAND support */ #define CONFIG_CMD_NAND_TRIMFFS -#define CONFIG_NAND_MXS #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE diff --git a/include/configs/platinum.h b/include/configs/platinum.h index 453c37d3f8..24c8de932f 100644 --- a/include/configs/platinum.h +++ b/include/configs/platinum.h @@ -66,7 +66,6 @@ #ifdef CONFIG_CMD_NAND

/* NAND config */ -#define CONFIG_NAND_MXS #ifndef CONFIG_SYS_NAND_MAX_CHIPS #define CONFIG_SYS_NAND_MAX_CHIPS 2 #endif diff --git a/include/configs/titanium.h b/include/configs/titanium.h index cc655f2960..ea18cb63e2 100644 --- a/include/configs/titanium.h +++ b/include/configs/titanium.h @@ -142,7 +142,6 @@ #ifdef CONFIG_CMD_NAND

/* NAND stuff */ -#define CONFIG_NAND_MXS #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE

From: Stefan Agner stefan.agner@toradex.com

Instead of completing initialization via scan_bbt callback use NAND self init to initialize the GPMI (MXS) NAND controller.

Suggested-by: Scott Wood oss@buserror.net Signed-off-by: Stefan Agner stefan.agner@toradex.com ---

Changes in v2: None

drivers/mtd/nand/Kconfig | 1 + drivers/mtd/nand/mxs_nand.c | 52 +++++++++++++++++++++++++-------------------- 2 files changed, 30 insertions(+), 23 deletions(-)

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 97ec6cf5f9..9fea8fbd1f 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -141,6 +141,7 @@ config NAND_MXC config NAND_MXS bool "MXS NAND support" depends on MX6 || MX7 + select SYS_NAND_SELF_INIT imply CMD_NAND help This enables NAND driver for the NAND flash controller on the diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index bed9b65ef4..cf96584fa8 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -18,6 +18,7 @@ #include <linux/mtd/rawnand.h> #include <linux/types.h> #include <malloc.h> +#include <nand.h> #include <linux/errno.h> #include <asm/io.h> #include <asm/arch/clock.h> @@ -47,6 +48,7 @@ #define MXS_NAND_BCH_TIMEOUT 10000

struct mxs_nand_info { + struct nand_chip chip; int cur_chip;

uint32_t cmd_queue_len; @@ -972,20 +974,15 @@ static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs) }

/* - * Nominally, the purpose of this function is to look for or create the bad - * block table. In fact, since the we call this function at the very end of - * the initialization process started by nand_scan(), and we doesn't have a - * more formal mechanism, we "hook" this function to continue init process. - * * At this point, the physical NAND Flash chips have been identified and * counted, so we know the physical geometry. This enables us to make some * important configuration decisions. * * The return value of this function propagates directly back to this driver's - * call to nand_scan(). Anything other than zero will cause this driver to + * board_nand_init(). Anything other than zero will cause this driver to * tear everything down and declare failure. */ -static int mxs_nand_scan_bbt(struct mtd_info *mtd) +static int mxs_nand_setup_ecc(struct mtd_info *mtd) { struct nand_chip *nand = mtd_to_nand(mtd); struct mxs_nand_info *nand_info = nand_get_controller_data(nand); @@ -1047,8 +1044,7 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd) mtd->_block_markbad = mxs_nand_hook_block_markbad; }

- /* We use the reference implementation for bad block management. */ - return nand_default_bbt(mtd); + return 0; }

/* @@ -1150,27 +1146,22 @@ err1: return ret; }

-/*! - * This function is called during the driver binding process. - * - * @param pdev the device structure used to store device specific - * information that is used by the suspend, resume and - * remove functions - * - * @return The function always returns 0. - */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init(void) { + struct mtd_info *mtd; struct mxs_nand_info *nand_info; + struct nand_chip *nand; int err;

nand_info = malloc(sizeof(struct mxs_nand_info)); if (!nand_info) { printf("MXS NAND: Failed to allocate private data\n"); - return -ENOMEM; + return; } memset(nand_info, 0, sizeof(struct mxs_nand_info));

+ nand = &nand_info->chip; + mtd = nand_to_mtd(nand); err = mxs_nand_alloc_buffers(nand_info); if (err) goto err1; @@ -1189,13 +1180,19 @@ int board_nand_init(struct nand_chip *nand) nand->dev_ready = mxs_nand_device_ready; nand->select_chip = mxs_nand_select_chip; nand->block_bad = mxs_nand_block_bad; - nand->scan_bbt = mxs_nand_scan_bbt;

nand->read_byte = mxs_nand_read_byte;

nand->read_buf = mxs_nand_read_buf; nand->write_buf = mxs_nand_write_buf;

+ /* first scan to find the device and get the page size */ + if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) + goto err2; + + if (mxs_nand_setup_ecc(mtd)) + goto err2; + nand->ecc.read_page = mxs_nand_ecc_read_page; nand->ecc.write_page = mxs_nand_ecc_write_page; nand->ecc.read_oob = mxs_nand_ecc_read_oob; @@ -1207,12 +1204,21 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.size = 512; nand->ecc.strength = 8;

- return 0; + /* second phase scan */ + err = nand_scan_tail(mtd); + if (err) + goto err2; + + err = nand_register(0, mtd); + if (err) + goto err2; + + return;

err2: free(nand_info->data_buf); free(nand_info->cmd_buf); err1: free(nand_info); - return err; + return; }

From: Stefan Agner stefan.agner@toradex.com

Calculate BCH geometry at start and store the information in a structure. This avoids recalculation on every page access and allows to calculate ECC relevant information in one place. This patch does not change ECC layout or driver behavior in any way.

The patch aligns the driver somewhat with the Linux GPMI NAND driver which drives the same IP.

Signed-off-by: Stefan Agner stefan.agner@toradex.com ---

Changes in v2: None

drivers/mtd/nand/mxs_nand.c | 182 +++++++++++++++++++++++--------------------- 1 file changed, 95 insertions(+), 87 deletions(-)

diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index 1fe7a712d2..5b9398bd98 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -30,7 +30,6 @@

#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4

-#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512 #if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2 #else @@ -47,12 +46,35 @@

#define MXS_NAND_BCH_TIMEOUT 10000

+/** + * @gf_len: The length of Galois Field. (e.g., 13 or 14) + * @ecc_strength: A number that describes the strength of the ECC + * algorithm. + * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note + * the first chunk in the page includes both data and + * metadata, so it's a bit larger than this value. + * @ecc_chunk_count: The number of ECC chunks in the page, + * @block_mark_byte_offset: The byte offset in the ECC-based page view at + * which the underlying physical block mark appears. + * @block_mark_bit_offset: The bit offset into the ECC-based page view at + * which the underlying physical block mark appears. + */ +struct bch_geometry { + unsigned int gf_len; + unsigned int ecc_strength; + unsigned int ecc_chunk_size; + unsigned int ecc_chunk_count; + unsigned int block_mark_byte_offset; + unsigned int block_mark_bit_offset; +}; + struct mxs_nand_info { struct nand_chip chip; int cur_chip;

uint32_t cmd_queue_len; uint32_t data_buf_size; + struct bch_geometry bch_geometry;

uint8_t *cmd_buf; uint8_t *data_buf; @@ -75,8 +97,6 @@ struct mxs_nand_info { };

struct nand_ecclayout fake_ecc_layout; -static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE; -static int galois_field = 13;

/* * Cache management functions @@ -137,61 +157,21 @@ static void mxs_nand_return_dma_descs(struct mxs_nand_info *info) info->desc_index = 0; }

-static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size) -{ - return page_data_size / chunk_data_size; -} - -static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength) -{ - return ecc_strength * galois_field; -} - static uint32_t mxs_nand_aux_status_offset(void) { return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3; }

-static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, - uint32_t page_oob_size) +static inline int mxs_nand_calc_mark_offset(struct bch_geometry *geo, + uint32_t page_data_size) { - int ecc_strength; - int max_ecc_strength_supported; - - /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ - if (is_mx6sx() || is_mx7()) - max_ecc_strength_supported = 62; - else - max_ecc_strength_supported = 40; - - /* - * Determine the ECC layout with the formula: - * ECC bits per chunk = (total page spare data bits) / - * (bits per ECC level) / (chunks per page) - * where: - * total page spare data bits = - * (page oob size - meta data size) * (bits per byte) - */ - ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8) - / (galois_field * - mxs_nand_ecc_chunk_cnt(page_data_size)); - - return min(round_down(ecc_strength, 2), max_ecc_strength_supported); -} - -static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, - uint32_t ecc_strength) -{ - uint32_t chunk_data_size_in_bits; - uint32_t chunk_ecc_size_in_bits; + uint32_t chunk_data_size_in_bits = geo->ecc_chunk_size * 8; + uint32_t chunk_ecc_size_in_bits = geo->ecc_strength * geo->gf_len; uint32_t chunk_total_size_in_bits; uint32_t block_mark_chunk_number; uint32_t block_mark_chunk_bit_offset; uint32_t block_mark_bit_offset;

- chunk_data_size_in_bits = chunk_data_size * 8; - chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength); - chunk_total_size_in_bits = chunk_data_size_in_bits + chunk_ecc_size_in_bits;

@@ -216,7 +196,7 @@ static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, (block_mark_chunk_number * chunk_total_size_in_bits);

if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) - return 1; + return -EINVAL;

/* * Now that we know the chunk number in which the block mark appears, @@ -225,21 +205,59 @@ static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, block_mark_bit_offset -= block_mark_chunk_number * chunk_ecc_size_in_bits;

- return block_mark_bit_offset; -} + geo->block_mark_byte_offset = block_mark_bit_offset >> 3; + geo->block_mark_bit_offset = block_mark_bit_offset & 0x7;

-static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd) -{ - uint32_t ecc_strength; - ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize); - return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3; + return 0; }

-static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd) +static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo, + struct mtd_info *mtd) { - uint32_t ecc_strength; - ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize); - return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7; + unsigned int max_ecc_strength_supported; + + /* The default for the length of Galois Field. */ + geo->gf_len = 13; + + /* The default for chunk size. */ + geo->ecc_chunk_size = 512; + + if (geo->ecc_chunk_size < mtd->oobsize) { + geo->gf_len = 14; + geo->ecc_chunk_size *= 2; + } + + if (mtd->oobsize > geo->ecc_chunk_size) { + printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", + geo->ecc_chunk_size); + return -EINVAL; + } + + geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size; + + /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ + if (is_mx6sx() || is_mx7()) + max_ecc_strength_supported = 62; + else + max_ecc_strength_supported = 40; + + /* + * Determine the ECC layout with the formula: + * ECC bits per chunk = (total page spare data bits) / + * (bits per ECC level) / (chunks per page) + * where: + * total page spare data bits = + * (page oob size - meta data size) * (bits per byte) + */ + geo->ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8) + / (geo->gf_len * geo->ecc_chunk_count); + + geo->ecc_strength = min(round_down(geo->ecc_strength, 2), max_ecc_strength_supported); + + if (mxs_nand_calc_mark_offset(geo, mtd->writesize) < 0) + return -EINVAL; + + return 0; }

/* @@ -380,18 +398,15 @@ static void mxs_nand_select_chip(struct mtd_info *mtd, int chip) * swapping the block mark, or swapping it *back* -- but it doesn't matter * because the the operation is the same. */ -static void mxs_nand_swap_block_mark(struct mtd_info *mtd, - uint8_t *data_buf, uint8_t *oob_buf) +static void mxs_nand_swap_block_mark(struct bch_geometry *geo, + uint8_t *data_buf, uint8_t *oob_buf) { - uint32_t bit_offset; - uint32_t buf_offset; + uint32_t bit_offset = geo->block_mark_bit_offset; + uint32_t buf_offset = geo->block_mark_byte_offset;

uint32_t src; uint32_t dst;

- bit_offset = mxs_nand_mark_bit_offset(mtd); - buf_offset = mxs_nand_mark_byte_offset(mtd); - /* * Get the byte from the data area that overlays the block mark. Since * the ECC engine applies its own view to the bits in the page, the @@ -567,6 +582,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, int page) { struct mxs_nand_info *nand_info = nand_get_controller_data(nand); + struct bch_geometry *geo = &nand_info->bch_geometry; struct mxs_dma_desc *d; uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; uint32_t corrected = 0, failed = 0; @@ -665,11 +681,11 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, mxs_nand_inval_data_buf(nand_info);

/* Read DMA completed, now do the mark swapping. */ - mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf); + mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);

/* Loop over status bytes, accumulating ECC status. */ status = nand_info->oob_buf + mxs_nand_aux_status_offset(); - for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) { + for (i = 0; i < geo->ecc_chunk_count; i++) { if (status[i] == 0x00) continue;

@@ -717,6 +733,7 @@ static int mxs_nand_ecc_write_page(struct mtd_info *mtd, int oob_required, int page) { struct mxs_nand_info *nand_info = nand_get_controller_data(nand); + struct bch_geometry *geo = &nand_info->bch_geometry; struct mxs_dma_desc *d; uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; int ret; @@ -725,7 +742,7 @@ static int mxs_nand_ecc_write_page(struct mtd_info *mtd, memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);

/* Handle block mark swapping. */ - mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf); + mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);

/* Compile the DMA descriptor - write data. */ d = mxs_nand_get_dma_desc(nand_info); @@ -986,39 +1003,30 @@ static int mxs_nand_setup_ecc(struct mtd_info *mtd) { struct nand_chip *nand = mtd_to_nand(mtd); struct mxs_nand_info *nand_info = nand_get_controller_data(nand); + struct bch_geometry *geo = &nand_info->bch_geometry; struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; uint32_t tmp;

- if (mtd->oobsize > MXS_NAND_CHUNK_DATA_CHUNK_SIZE) { - galois_field = 14; - chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 2; - } - - if (mtd->oobsize > chunk_data_size) { - printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", chunk_data_size); + if (mxs_nand_calc_ecc_layout(geo, mtd)) return -EINVAL; - }

/* Configure BCH and set NFC geometry */ mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);

/* Configure layout 0 */ - tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1) - << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; + tmp = (geo->ecc_chunk_count - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET; - tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1) - << BCH_FLASHLAYOUT0_ECC0_OFFSET; - tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; - tmp |= (14 == galois_field ? 1 : 0) << + tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET; + tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; + tmp |= (geo->gf_len == 14 ? 1 : 0) << BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET; writel(tmp, &bch_regs->hw_bch_flash0layout0);

tmp = (mtd->writesize + mtd->oobsize) << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET; - tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1) - << BCH_FLASHLAYOUT1_ECCN_OFFSET; - tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; - tmp |= (14 == galois_field ? 1 : 0) << + tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET; + tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; + tmp |= (geo->gf_len == 14 ? 1 : 0) << BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET; writel(tmp, &bch_regs->hw_bch_flash0layout1);

From: Stefan Agner stefan.agner@toradex.com

Add support for minimum ECC strength supported by the NAND chip. This aligns with the behavior when using the fsl,use-minimum-ecc device tree property in Linux.

Signed-off-by: Stefan Agner stefan.agner@toradex.com ---

Changes in v2: None

drivers/mtd/nand/Kconfig | 8 +++++ drivers/mtd/nand/mxs_nand.c | 71 ++++++++++++++++++++++++++++++++++++--------- 2 files changed, 65 insertions(+), 14 deletions(-)

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 9fea8fbd1f..51577ddc10 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -147,6 +147,14 @@ config NAND_MXS This enables NAND driver for the NAND flash controller on the MXS processors.

+if NAND_MXS + +config NAND_MXS_USE_MINIMUM_ECC + bool "Use minimum ECC strength supported by the controller" + default false + +endif + config NAND_ZYNQ bool "Support for Zynq Nand controller" select SYS_NAND_SELF_INIT diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index 2d84bab717..cdd5a86fe2 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -211,11 +211,52 @@ static inline int mxs_nand_calc_mark_offset(struct bch_geometry *geo, return 0; }

+static inline unsigned int mxs_nand_max_ecc_strength_supported(void) +{ + /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ + if (is_mx6sx() || is_mx7()) + return 62; + else + return 40; +} + +static inline int mxs_nand_calc_ecc_layout_by_info(struct bch_geometry *geo, + struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + + if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0)) + return -ENOTSUPP; + + switch (chip->ecc_step_ds) { + case SZ_512: + geo->gf_len = 13; + break; + case SZ_1K: + geo->gf_len = 14; + break; + default: + return -EINVAL; + } + + geo->ecc_chunk_size = chip->ecc_step_ds; + geo->ecc_strength = round_up(chip->ecc_strength_ds, 2); + + /* Keep the C >= O */ + if (geo->ecc_chunk_size < mtd->oobsize) + return -EINVAL; + + if (geo->ecc_strength > mxs_nand_max_ecc_strength_supported()) + return -EINVAL; + + geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size; + + return 0; +} + static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo, struct mtd_info *mtd) { - unsigned int max_ecc_strength_supported; - /* The default for the length of Galois Field. */ geo->gf_len = 13;

@@ -235,12 +276,6 @@ static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo,

geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;

- /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ - if (is_mx6sx() || is_mx7()) - max_ecc_strength_supported = 62; - else - max_ecc_strength_supported = 40; - /* * Determine the ECC layout with the formula: * ECC bits per chunk = (total page spare data bits) / @@ -252,10 +287,8 @@ static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo, geo->ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8) / (geo->gf_len * geo->ecc_chunk_count);

- geo->ecc_strength = min(round_down(geo->ecc_strength, 2), max_ecc_strength_supported); - - if (mxs_nand_calc_mark_offset(geo, mtd->writesize) < 0) - return -EINVAL; + geo->ecc_strength = min(round_down(geo->ecc_strength, 2), + mxs_nand_max_ecc_strength_supported());

return 0; } @@ -1006,9 +1039,19 @@ static int mxs_nand_setup_ecc(struct mtd_info *mtd) struct bch_geometry *geo = &nand_info->bch_geometry; struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; uint32_t tmp; + int ret = -ENOTSUPP;

- if (mxs_nand_calc_ecc_layout(geo, mtd)) - return -EINVAL; +#ifdef CONFIG_NAND_MXS_USE_MINIMUM_ECC + ret = mxs_nand_calc_ecc_layout_by_info(geo, mtd); +#endif + + if (ret == -ENOTSUPP) + ret = mxs_nand_calc_ecc_layout(geo, mtd); + + if (ret) + return ret; + + mxs_nand_calc_mark_offset(geo, mtd->writesize);

/* Configure BCH and set NFC geometry */ mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);