[PATCH v2] board: gateworks: venice: determine dram size at runtime
The SPL does not update the memory node with the dram size from EEPROM but instead we can use get_ram_size which does a simple memory test to determine the available RAM. Update PHYS_SDRAM_SIZE to 4GiB as that is the max used on the Venice boards.
Signed-off-by: Tim Harvey tharvey@gateworks.com Reviewed-by: Fabio Estevam festevam@denx.de --- v2: - bump PHYS_SDRAM_SIZE for imx8mn_venice to account for boards that have more than 1GiB of DRAM - added Fabio's rb tag --- board/gateworks/venice/venice.c | 13 ++----------- include/configs/imx8mm_venice.h | 2 +- include/configs/imx8mn_venice.h | 2 +- 3 files changed, 4 insertions(+), 13 deletions(-)
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 4e05802b6ff1..5334500ef6a7 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -21,19 +21,10 @@ DECLARE_GLOBAL_DATA_PTR;
int board_phys_sdram_size(phys_size_t *size) { - const fdt64_t *val; - int offset; - int len; - - /* get size from dt which SPL updated per EEPROM config */ - offset = fdt_path_offset(gd->fdt_blob, "/memory"); - if (offset < 0) + if (!size) return -EINVAL;
- val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); - if (len < sizeof(*val) * 2) - return -EINVAL; - *size = get_unaligned_be64(&val[1]); + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0; } diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 1ec27f40f2b5..a3649702e955 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -83,7 +83,7 @@
/* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ +#define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */ diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index c01a590c8af6..c68cc96a7300 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -80,7 +80,7 @@
/* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE SZ_1G +#define PHYS_SDRAM_SIZE SZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
Hi Tim,
On Wed, Mar 30, 2022 at 5:39 PM Tim Harvey tharvey@gateworks.com wrote:
The SPL does not update the memory node with the dram size from EEPROM but instead we can use get_ram_size which does a simple memory test to determine the available RAM. Update PHYS_SDRAM_SIZE to 4GiB as that is the max used on the Venice boards.
Signed-off-by: Tim Harvey tharvey@gateworks.com Reviewed-by: Fabio Estevam festevam@denx.de
Is this 2022.04 material?
On Wed, Mar 30, 2022 at 1:58 PM Fabio Estevam festevam@gmail.com wrote:
Hi Tim,
On Wed, Mar 30, 2022 at 5:39 PM Tim Harvey tharvey@gateworks.com wrote:
The SPL does not update the memory node with the dram size from EEPROM but instead we can use get_ram_size which does a simple memory test to determine the available RAM. Update PHYS_SDRAM_SIZE to 4GiB as that is the max used on the Venice boards.
Signed-off-by: Tim Harvey tharvey@gateworks.com Reviewed-by: Fabio Estevam festevam@denx.de
Is this 2022.04 material?
Fabio,
Probably a good idea - without it the DRAM size is set to something that may not be appropriate and if larger than what's actually on the board could cause a crash if someone tried to allocate that memory.
Fixes: 692c25ee30efd "(board: gateworks: venice: get mem size from dt)"
Thanks,
Tim
On Wed, Mar 30, 2022 at 01:39:02PM -0700, Tim Harvey wrote:
The SPL does not update the memory node with the dram size from EEPROM but instead we can use get_ram_size which does a simple memory test to determine the available RAM. Update PHYS_SDRAM_SIZE to 4GiB as that is the max used on the Venice boards.
Signed-off-by: Tim Harvey tharvey@gateworks.com Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot/master, thanks!
participants (3)
-
Fabio Estevam -
Tim Harvey -
Tom Rini