[U-Boot] Mainline u-boot SPL for socfpga
Hello
I am trying to understand the state of the socfpga preloader in mainline u-boot.
From what I see, this is broken and perhaps has never worked.
When I build the code in u-boot-socfpga I get a healthy working u-boot-spl.bin of approx 45kbytes.
When I build the mainline u-boot code I get a broken u-boot-spl.bin of approx 3kbytes.
It seems the mainline u-boot is missing stuff, including the all-critical sdram initialisation without which the SPL is useless.
So, I have a few related questions:
1. The SDRAM init code, like other SocFPGA "hand-off" files is generated by the Altera tools. Since it is not hand written, and is not compliant with u-boot coding style. Is it more important to preserve coding style and have a broken SPL than it is to have a working SPL and broken code?
2. Is there a practical "half-way" compromise whereby the generated code is run through lindent and we just accept that this is as good as it gets?
3. Can we get some sort of coding style waiver, considering that this code is off in a board file and does not impact on anyone working on anything other than socfpga (indeed nobody even working on socfpga even reads it).
Clearly significant hand editing generated code makes for a very broken workflow, but running it through an automated step like lindent is Ok from a workflow point of view.
Unless this can be resolved we end up with a situation where people working on SocFPGA are forced to fork for practical reasons.
Regards
Charles
Hi Charles,
On Tue, 2014-05-06 at 12:22 +1200, Charles Manning wrote:
Hello
I am trying to understand the state of the socfpga preloader in mainline u-boot.
From what I see, this is broken and perhaps has never worked.
When I build the code in u-boot-socfpga I get a healthy working u-boot-spl.bin of approx 45kbytes.
When I build the mainline u-boot code I get a broken u-boot-spl.bin of approx 3kbytes.
It seems the mainline u-boot is missing stuff, including the all-critical sdram initialisation without which the SPL is useless.
As of now, we have most of the drivers already upstreamed to main line. The missing piece here are the SDRAM driver. The SDRAM driver poses a big challenge as its now licensed under BSD-3 clause. I am still working with legal team to look into potential to make it GPL license.
So, I have a few related questions:
- The SDRAM init code, like other SocFPGA "hand-off" files is
generated by the Altera tools. Since it is not hand written, and is not compliant with u-boot coding style. Is it more important to preserve coding style and have a broken SPL than it is to have a working SPL and broken code?
The SDRAM handoff files generated by tools is not compliance as the original code developer doesn't familiar with open source world. But if you look into the SDRAM handoff files within rocketboard.org git, the existing code already updated. I enhanced the code to ensure it meet with basic coding standard. But further enhancement is needed and on-going now.
- Is there a practical "half-way" compromise whereby the generated
code is run through lindent and we just accept that this is as good as it gets?
The on-going plan now is to use the enhanced SDRAM handoff file at rocketboard.org. From there, we want to streamline the driver by removing unused code. Once its ready, we will upstream this file.
- Can we get some sort of coding style waiver, considering that this
code is off in a board file and does not impact on anyone working on anything other than socfpga (indeed nobody even working on socfpga even reads it).
Clearly significant hand editing generated code makes for a very broken workflow, but running it through an automated step like lindent is Ok from a workflow point of view.
Unless this can be resolved we end up with a situation where people working on SocFPGA are forced to fork for practical reasons.
I believe it would be tough to get the waiver. Nevertheless, we are further enhancing the handoff files to a state which is good for upstreaming. At same time, I am also working with tools team to ensure all these enhancement is putting back to original code.
Thanks
Chin Liang
Regards
Charles
On Thu, May 8, 2014 at 10:24 PM, Chin Liang See clsee@altera.com wrote:
Hi Charles,
On Tue, 2014-05-06 at 12:22 +1200, Charles Manning wrote:
Hello
I am trying to understand the state of the socfpga preloader in mainline u-boot.
From what I see, this is broken and perhaps has never worked.
When I build the code in u-boot-socfpga I get a healthy working u-boot-spl.bin of approx 45kbytes.
When I build the mainline u-boot code I get a broken u-boot-spl.bin of approx 3kbytes.
It seems the mainline u-boot is missing stuff, including the all-critical sdram initialisation without which the SPL is useless.
As of now, we have most of the drivers already upstreamed to main line. The missing piece here are the SDRAM driver. The SDRAM driver poses a big challenge as its now licensed under BSD-3 clause. I am still working with legal team to look into potential to make it GPL license.
So, I have a few related questions:
- The SDRAM init code, like other SocFPGA "hand-off" files is
generated by the Altera tools. Since it is not hand written, and is not compliant with u-boot coding style. Is it more important to preserve coding style and have a broken SPL than it is to have a working SPL and broken code?
The SDRAM handoff files generated by tools is not compliance as the original code developer doesn't familiar with open source world. But if you look into the SDRAM handoff files within rocketboard.org git, the existing code already updated. I enhanced the code to ensure it meet with basic coding standard. But further enhancement is needed and on-going now.
What is really needed is that the hand-off files are actually generated as compliant code.
Enhancing and hand-editing then checking in machine generated code is a broken work-flow because:
1) It has to be redone every time the code is regenerated. 2) There are so many changes that it is impossible to check for errors and diff for changes.
- Is there a practical "half-way" compromise whereby the generated
code is run through lindent and we just accept that this is as good as it gets?
The on-going plan now is to use the enhanced SDRAM handoff file at rocketboard.org. From there, we want to streamline the driver by removing unused code. Once its ready, we will upstream this file.
That might work if it is a once-off exercise that places the sdram code
in arch/arm/cpu/armv7/socfpga
The only stuff that should really be in a board/xxx directory is board-specific stuff and "tuning files".
In other words: * sequence.c (a file of over 11000 lines of C code) should be in arch/.../scofpga * sequencer_auto_ac_init.c (300 lines of board-specific register config values) should be in board/.../socfpga
- Can we get some sort of coding style waiver, considering that this
code is off in a board file and does not impact on anyone working on anything other than socfpga (indeed nobody even working on socfpga even reads it).
Clearly significant hand editing generated code makes for a very broken workflow, but running it through an automated step like lindent is Ok from a workflow point of view.
Unless this can be resolved we end up with a situation where people working on SocFPGA are forced to fork for practical reasons.
I believe it would be tough to get the waiver. Nevertheless, we are further enhancing the handoff files to a state which is good for upstreaming. At same time, I am also working with tools team to ensure all these enhancement is putting back to original code.
Maybe splitting the code better as I suggest above would make this far simpler.
If the board specific part of the hand-offs is reduced to just header files and register config tables, then it is a trivial matter to run them through an extra **automated** step to produce a compliant file.
Apart from gaining the mainstreaming, this would also make it far easier to create configs for different boards (eg. sockit board would just become a few hundred lines of register configs and not 13 thousand lines of code - most of that duplicated between platforms).
Regards
Charles
Hi!
I am trying to understand the state of the socfpga preloader in mainline u-boot.
From what I see, this is broken and perhaps has never worked.
That's correct AFAICT.
When I build the code in u-boot-socfpga I get a healthy working u-boot-spl.bin of approx 45kbytes.
When I build the mainline u-boot code I get a broken u-boot-spl.bin of approx 3kbytes.
It seems the mainline u-boot is missing stuff, including the all-critical sdram initialisation without which the SPL is useless.
Are you able to build working u-boot proper from recent sources?
I know u-boot SPL misses critical parts, but I was told that u-boot proper should have everything. Only... I was not able to get it to work. [I'm attempting to load recent u-boot from patched/old u-boot; I know this is not exactly recommended, but due to spl/proper split, it should work AFAIK... and does for old versions.]
Any ideas?
Thanks, Pavel
On Thursday 15 May 2014 04:42:58 Pavel Machek wrote:
Hi!
I am trying to understand the state of the socfpga preloader in mainline u-boot.
From what I see, this is broken and perhaps has never worked.
That's correct AFAICT.
When I build the code in u-boot-socfpga I get a healthy working u-boot-spl.bin of approx 45kbytes.
When I build the mainline u-boot code I get a broken u-boot-spl.bin of approx 3kbytes.
It seems the mainline u-boot is missing stuff, including the all-critical sdram initialisation without which the SPL is useless.
Are you able to build working u-boot proper from recent sources?
I know u-boot SPL misses critical parts, but I was told that u-boot proper should have everything. Only... I was not able to get it to work. [I'm attempting to load recent u-boot from patched/old u-boot; I know this is not exactly recommended, but due to spl/proper split, it should work AFAIK... and does for old versions.]
I have not tried booting u-boot proper from mainline. It just seemed pointless to me to be working from 2 source trees to make a single product.
I will give it a go though.
As Chin Liang See has said, there are two issues thwarting this: legal AND source conformance. The code we can fix, the legal can only be fixed by bending Altera - I am going to do that too.
Regards
Charles
Hi,
On Thu, 2014-05-15 at 07:01 +1200, Charles Manning wrote:
On Thursday 15 May 2014 04:42:58 Pavel Machek wrote:
Hi!
I am trying to understand the state of the socfpga preloader in mainline u-boot.
From what I see, this is broken and perhaps has never worked.
That's correct AFAICT.
Yup, Preloader without the SDRAM would not work correctly.
When I build the code in u-boot-socfpga I get a healthy working u-boot-spl.bin of approx 45kbytes.
When I build the mainline u-boot code I get a broken u-boot-spl.bin of approx 3kbytes.
It seems the mainline u-boot is missing stuff, including the all-critical sdram initialisation without which the SPL is useless.
Are you able to build working u-boot proper from recent sources?
I know u-boot SPL misses critical parts, but I was told that u-boot proper should have everything. Only... I was not able to get it to work. [I'm attempting to load recent u-boot from patched/old u-boot; I know this is not exactly recommended, but due to spl/proper split, it should work AFAIK... and does for old versions.]
I have not tried booting u-boot proper from mainline. It just seemed pointless to me to be working from 2 source trees to make a single product.
I will give it a go though.
Actually the U-Boot is working. You just need to #undef CONFIG_SOCFPGA_VIRTUAL_TARGET and build it. I loaded it using a working Preloader and I can reach the U-Boot console.
U-Boot SPL 2013.01.01 (May 16 2014 - 10:42:39) BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 25000 KHz CLOCK: EOSC2 clock 25000 KHz CLOCK: F2S_SDR_REF clock 0 KHz CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 925 MHz CLOCK: DDR clock 400 MHz CLOCK: UART clock 100000 KHz CLOCK: MMC clock 50000 KHz CLOCK: QSPI clock 370000 KHz INFO : Watchdog enabled SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SDRAM: 1024 MiB SDRAM: ECC Enabled ALTERA DWMMC: 0 reading u-boot.img reading u-boot.img
U-Boot 2014.07-rc1-00079-g2072e72-dirty (May 16 2014 - 15:54:55)
CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone5 Board DRAM: 1 GiB WARNING: Caches not enabled Using default environment
In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Wrong Image Format for bootm command ERROR: can't get kernel image! SOCFPGA_CYCLONE5 # help ? - alias for 'help' base - print or set address offset bdinfo - print Board Info structure boot - boot default, i.e., run 'bootcmd' bootd - boot default, i.e., run 'bootcmd' bootm - boot application image from memory bootp - boot image via network using BOOTP/TFTP protocol cmp - memory compare coninfo - print console devices and information cp - memory copy crc32 - checksum calculation echo - echo args to console editenv - edit environment variable env - environment handling commands exit - exit script false - do nothing, unsuccessfully fatinfo - print information about filesystem fatload - load binary file from a dos filesystem fatls - list files in a directory (default /) fdt - flattened device tree utility commands go - start application at address 'addr' help - print command description/usage iminfo - print header information for application image imxtract- extract a part of a multi-image itest - return true/false on integer compare loadb - load binary file over serial line (kermit mode) loads - load S-Record file over serial line loadx - load binary file over serial line (xmodem mode) loady - load binary file over serial line (ymodem mode) loop - infinite loop on address range md - memory display mm - memory modify (auto-incrementing address) mw - memory write (fill) nfs - boot image via network using NFS protocol nm - memory modify (constant address) printenv- print environment variables reset - Perform RESET of the CPU run - run commands in an environment variable setenv - set environment variables showvar - print local hushshell variables sleep - delay execution for some time source - run script from memory test - minimal test like /bin/sh tftpboot- boot image via network using TFTP protocol true - do nothing, successfully version - print monitor, compiler and linker version SOCFPGA_CYCLONE5 #
As Chin Liang See has said, there are two issues thwarting this: legal AND source conformance. The code we can fix, the legal can only be fixed by bending Altera - I am going to do that too.
We are making some progress on this. Once we have final green light, we will start the upstreaming of SDRAM code. :)
Thanks
Chin Liang
Regards
Charles
Hi!
(Sorry for the delay)
I know u-boot SPL misses critical parts, but I was told that u-boot proper should have everything. Only... I was not able to get it to work. [I'm attempting to load recent u-boot from patched/old u-boot; I know this is not exactly recommended, but due to spl/proper split, it should work AFAIK... and does for old versions.]
I have not tried booting u-boot proper from mainline. It just seemed pointless to me to be working from 2 source trees to make a single product.
I will give it a go though.
Actually the U-Boot is working. You just need to #undef CONFIG_SOCFPGA_VIRTUAL_TARGET and build it. I loaded it using a working Preloader and I can reach the U-Boot console.
Aha, you are right, I forgot about VIRTUAL_TARGET define.
U-Boot 2014.07-rc1-00079-g2072e72-dirty (May 16 2014 - 15:54:55)
CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone5 Board DRAM: 1 GiB WARNING: Caches not enabled Using default environment
In: serial Out: serial Err: serial Net: No ethernet found.
Do you have any hints how to get ethernet to work?
Plus, for me it says:
tertiary u-boot 13.760972 Warning: Your board does not use generic board. Please read tertiary u-boot 13.770775 doc/README.generic-board and take action. Boards not tertiary u-boot 13.779813 upgraded by the late 2014 may break or be removed.
As Chin Liang See has said, there are two issues thwarting this: legal AND source conformance. The code we can fix, the legal can only be fixed by bending Altera - I am going to do that too.
We are making some progress on this. Once we have final green light, we will start the upstreaming of SDRAM code. :)
Looking forward :-).
Thanks, Pavel
Socfpga u-boot works fine with CONFIG_SYS_GENERIC_BOARD, so enable that option as documentation suggests.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 2fc16ef..72d77f4 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -16,6 +16,8 @@ /* Virtual target or real hardware */ #define CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_ARMV7 #define CONFIG_SYS_DCACHE_OFF #undef CONFIG_USE_IRQ
Hi Pavel,
On Tue, 2014-05-27 at 14:50 +0200, ZY - pavel wrote:
Socfpga u-boot works fine with CONFIG_SYS_GENERIC_BOARD, so enable that option as documentation suggests.
Yup, it works well for me without modification.
Acked-by: Chin Liang See clsee@altera.com
Thanks Chin Liang
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 2fc16ef..72d77f4 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -16,6 +16,8 @@ /* Virtual target or real hardware */ #define CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_ARMV7 #define CONFIG_SYS_DCACHE_OFF #undef CONFIG_USE_IRQ
Hi Pavel,
On Tue, 27 May 2014 14:50:30 +0200, Pavel Machek pavel@denx.de wrote:
Socfpga u-boot works fine with CONFIG_SYS_GENERIC_BOARD, so enable that option as documentation suggests.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 2fc16ef..72d77f4 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -16,6 +16,8 @@ /* Virtual target or real hardware */ #define CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_ARMV7 #define CONFIG_SYS_DCACHE_OFF #undef CONFIG_USE_IRQ
Sorry, I let this last too long before I reviewed it and now it does not apply cleanly at all. Can you have a look?
Amicalement,
Socfpga u-boot works fine with CONFIG_SYS_GENERIC_BOARD, so enable that option as documentation suggests.
Signed-off-by: Pavel Machek pavel@denx.de
---
Sorry, I let this last too long before I reviewed it and now it does not apply cleanly at all. Can you have a look?
Here you go.
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 5d145cd..d3d1e48 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -11,6 +11,8 @@ #include "../../board/altera/socfpga/iocsr_config.h" #include "../../board/altera/socfpga/pll_config.h"
+#define CONFIG_SYS_GENERIC_BOARD + /* * High level configuration */
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index e320c01..5503059 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -14,6 +14,19 @@ DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS;
+#define RSTMGR_PERMODRST_L4WD0_LSB 6 + +/* Disable the watchdog (toggle reset to watchdog) */ +void watchdog_disable(void) +{ + /* assert reset for watchdog */ + setbits_le32(&reset_manager_base->per_mod_reset, + (1<<RSTMGR_PERMODRST_L4WD0_LSB)); + /* deassert watchdog from reset (watchdog in not running state) */ + clrbits_le32(&reset_manager_base->per_mod_reset, + (1<<RSTMGR_PERMODRST_L4WD0_LSB)); +} + /* * Write the reset manager register to cause reset */ diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 3e95476..eb95c5b 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -10,6 +10,8 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void);
+void watchdog_disable(void); + struct socfpga_reset_manager { u32 status; u32 ctrl;
Add base addresses for more subsystems.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 2d3152d..39a7874 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -7,9 +7,15 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_
+#define SOCFPGA_EMAC0_ADDRESS 0xff700000 +#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 #define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_SDR_ADDRESS 0xffc20000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 #define SOCFPGA_L4WD0_ADDRESS 0xffd02000 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
Old saying says that more than three exclamation marks in a row are sign of mental disease. Cleanup micrel.c.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 5d7e3be..06a31b0 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -25,8 +25,7 @@ static struct phy_driver KSZ804_driver = { #ifndef CONFIG_PHY_MICREL_KSZ9021 /* * I can't believe Micrel used the exact same part number - * for the KSZ9021 - * Shame Micrel, Shame!!!!! + * for the KSZ9021. Shame Micrel, Shame! */ static struct phy_driver KS8721_driver = { .name = "Micrel KS8721BL", @@ -40,7 +39,7 @@ static struct phy_driver KS8721_driver = { #endif
-/** +/* * KSZ9021 - KSZ9031 common */
@@ -69,8 +68,8 @@ static int ksz90xx_startup(struct phy_device *phydev) phydev->speed = SPEED_10; return 0; } -#ifdef CONFIG_PHY_MICREL_KSZ9021
+#ifdef CONFIG_PHY_MICREL_KSZ9021 /* * KSZ9021 */
On Tue, 2014-09-09 at 14:26 +0200, ZY - pavel wrote:
Old saying says that more than three exclamation marks in a row are sign of mental disease. Cleanup micrel.c.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 5d7e3be..06a31b0 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -25,8 +25,7 @@ static struct phy_driver KSZ804_driver = { #ifndef CONFIG_PHY_MICREL_KSZ9021 /*
- I can't believe Micrel used the exact same part number
- for the KSZ9021
- Shame Micrel, Shame!!!!!
*/
- for the KSZ9021. Shame Micrel, Shame!
static struct phy_driver KS8721_driver = { .name = "Micrel KS8721BL", @@ -40,7 +39,7 @@ static struct phy_driver KS8721_driver = { #endif
-/** +/*
- KSZ9021 - KSZ9031 common
*/
@@ -69,8 +68,8 @@ static int ksz90xx_startup(struct phy_device *phydev) phydev->speed = SPEED_10; return 0; } -#ifdef CONFIG_PHY_MICREL_KSZ9021
+#ifdef CONFIG_PHY_MICREL_KSZ9021 /*
- KSZ9021
*/
Acked-by: Chin Liang See clsee@altera.com
On Tue, 2014-09-09 at 14:05 +0200, ZY - pavel wrote:
Add base addresses for more subsystems.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 2d3152d..39a7874 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -7,9 +7,15 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_
+#define SOCFPGA_EMAC0_ADDRESS 0xff700000 +#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 #define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_SDR_ADDRESS 0xffc20000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 #define SOCFPGA_L4WD0_ADDRESS 0xffd02000 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
Acked-by: Chin Liang See clsee@altera.com
Fix compilation of socfpga_dw_mmc.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 1f96382..d8da7f5 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -16,6 +16,8 @@ static const struct socfpga_clock_manager *clock_manager_base = static const struct socfpga_system_manager *system_manager_base = (void *)SOCFPGA_SYSMGR_ADDRESS;
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK (1 << 8) + static void socfpga_dwmci_clksel(struct dwmci_host *host) { unsigned int drvsel;
On Tuesday, September 09, 2014 at 02:08:13 PM, Pavel Machek wrote:
Fix compilation of socfpga_dw_mmc.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 1f96382..d8da7f5 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -16,6 +16,8 @@ static const struct socfpga_clock_manager *clock_manager_base = static const struct socfpga_system_manager *system_manager_base = (void *)SOCFPGA_SYSMGR_ADDRESS;
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK (1 << 8)
static void socfpga_dwmci_clksel(struct dwmci_host *host) { unsigned int drvsel;
This macro should go into arch/arm/include/asm/arch-socfpga/clock_manager.h
Best regards, Marek Vasut
On Tuesday, September 09, 2014 at 02:03:28 PM, Pavel Machek wrote:
This adds watchdog disable. It is neccessary for running Linux kernel.
Why do we not enable WDT in Linux instead ? Also, I recall there was a call to explicitly enable the L4 watchdog, so why do we not get rid of that instead ?
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index e320c01..5503059 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -14,6 +14,19 @@ DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS;
+#define RSTMGR_PERMODRST_L4WD0_LSB 6
+/* Disable the watchdog (toggle reset to watchdog) */ +void watchdog_disable(void) +{
- /* assert reset for watchdog */
- setbits_le32(&reset_manager_base->per_mod_reset,
(1<<RSTMGR_PERMODRST_L4WD0_LSB));- /* deassert watchdog from reset (watchdog in not running state) */
- clrbits_le32(&reset_manager_base->per_mod_reset,
(1<<RSTMGR_PERMODRST_L4WD0_LSB));+}
/*
- Write the reset manager register to cause reset
*/ diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 3e95476..eb95c5b 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -10,6 +10,8 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void);
+void watchdog_disable(void);
struct socfpga_reset_manager { u32 status; u32 ctrl;
Best regards, Marek Vasut
On Tue 2014-09-09 14:20:23, Marek Vasut wrote:
On Tuesday, September 09, 2014 at 02:03:28 PM, Pavel Machek wrote:
This adds watchdog disable. It is neccessary for running Linux kernel.
Why do we not enable WDT in Linux instead ? Also, I recall there was a call to explicitly enable the L4 watchdog, so why do we not get rid of that instead ?
Booting linux kernel without watchdog support should be valid operation. Pavel
On Tuesday, September 09, 2014 at 02:30:01 PM, Pavel Machek wrote:
On Tue 2014-09-09 14:20:23, Marek Vasut wrote:
On Tuesday, September 09, 2014 at 02:03:28 PM, Pavel Machek wrote:
This adds watchdog disable. It is neccessary for running Linux kernel.
Why do we not enable WDT in Linux instead ? Also, I recall there was a call to explicitly enable the L4 watchdog, so why do we not get rid of that instead ?
Booting linux kernel without watchdog support should be valid operation.
If you watchdog is enabled, then not so much. Also, why can we not just disable the WDT in U-Boot instead using a config option ?
Best regards, Marek Vasut
On Tue 2014-09-09 14:31:46, Marek Vasut wrote:
On Tuesday, September 09, 2014 at 02:30:01 PM, Pavel Machek wrote:
On Tue 2014-09-09 14:20:23, Marek Vasut wrote:
On Tuesday, September 09, 2014 at 02:03:28 PM, Pavel Machek wrote:
This adds watchdog disable. It is neccessary for running Linux kernel.
Why do we not enable WDT in Linux instead ? Also, I recall there was a call to explicitly enable the L4 watchdog, so why do we not get rid of that instead ?
Booting linux kernel without watchdog support should be valid operation.
If you watchdog is enabled, then not so much. Also, why can we not just disable the WDT in U-Boot instead using a config option ?
It seems that watchdog is enabled by default (by hardware or SPL), so yes, watchdog disable operation (and this patch) in u-boot is a good idea.
Pavel
On Tuesday, September 09, 2014 at 03:09:48 PM, Pavel Machek wrote:
On Tue 2014-09-09 14:31:46, Marek Vasut wrote:
On Tuesday, September 09, 2014 at 02:30:01 PM, Pavel Machek wrote:
On Tue 2014-09-09 14:20:23, Marek Vasut wrote:
On Tuesday, September 09, 2014 at 02:03:28 PM, Pavel Machek wrote:
This adds watchdog disable. It is neccessary for running Linux kernel.
Why do we not enable WDT in Linux instead ? Also, I recall there was a call to explicitly enable the L4 watchdog, so why do we not get rid of that instead ?
Booting linux kernel without watchdog support should be valid operation.
If you watchdog is enabled, then not so much. Also, why can we not just disable the WDT in U-Boot instead using a config option ?
It seems that watchdog is enabled by default (by hardware or SPL), so yes, watchdog disable operation (and this patch) in u-boot is a good idea.
OK.
Best regards, Marek Vasut
Hi Pavel,
On Tue, 2014-09-09 at 15:09 +0200, ZY - pavel wrote:
On Tue 2014-09-09 14:31:46, Marek Vasut wrote:
On Tuesday, September 09, 2014 at 02:30:01 PM, Pavel Machek wrote:
On Tue 2014-09-09 14:20:23, Marek Vasut wrote:
On Tuesday, September 09, 2014 at 02:03:28 PM, Pavel Machek wrote:
This adds watchdog disable. It is neccessary for running Linux kernel.
Why do we not enable WDT in Linux instead ? Also, I recall there was a call to explicitly enable the L4 watchdog, so why do we not get rid of that instead ?
Booting linux kernel without watchdog support should be valid operation.
If you watchdog is enabled, then not so much. Also, why can we not just disable the WDT in U-Boot instead using a config option ?
It seems that watchdog is enabled by default (by hardware or SPL), so yes, watchdog disable operation (and this patch) in u-boot is a good idea.
If refer to http://rocketboards.org/gitweb/?p=u-boot-socfpga.git;a=blob_plain;f=arch/arm..., its current disable during U-Boot initialization, s_init. Thanks
Chin Liang
Pavel
Hi Pavel,
On Tue, 2014-09-09 at 14:03 +0200, ZY - pavel wrote:
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index e320c01..5503059 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -14,6 +14,19 @@ DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS;
+#define RSTMGR_PERMODRST_L4WD0_LSB 6
Would suggest to put this into header file. Thanks
Chin Liang
+/* Disable the watchdog (toggle reset to watchdog) */ +void watchdog_disable(void) +{
- /* assert reset for watchdog */
- setbits_le32(&reset_manager_base->per_mod_reset,
(1<<RSTMGR_PERMODRST_L4WD0_LSB));- /* deassert watchdog from reset (watchdog in not running state) */
- clrbits_le32(&reset_manager_base->per_mod_reset,
(1<<RSTMGR_PERMODRST_L4WD0_LSB));+}
/*
- Write the reset manager register to cause reset
*/ diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 3e95476..eb95c5b 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -10,6 +10,8 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void);
+void watchdog_disable(void);
struct socfpga_reset_manager { u32 status; u32 ctrl;
On Friday, September 12, 2014 at 08:10:22 AM, Chin Liang See wrote:
Hi Pavel,
On Tue, 2014-09-09 at 14:03 +0200, ZY - pavel wrote:
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek pavel@denx.de
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index e320c01..5503059 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -14,6 +14,19 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;+#define RSTMGR_PERMODRST_L4WD0_LSB 6
Would suggest to put this into header file. Thanks
I agree. We're currently working on a proper cleanup, so please give us a few days to prepare a series.
Best regards, Marek Vasut
On Tue, 2014-09-09 at 13:25 +0200, ZY - pavel wrote:
Socfpga u-boot works fine with CONFIG_SYS_GENERIC_BOARD, so enable that option as documentation suggests.
Signed-off-by: Pavel Machek pavel@denx.de
Acked-by: Chin Liang See clsee@altera.com
Sorry, I let this last too long before I reviewed it and now it does not apply cleanly at all. Can you have a look?
Here you go.
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 5d145cd..d3d1e48 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -11,6 +11,8 @@ #include "../../board/altera/socfpga/iocsr_config.h" #include "../../board/altera/socfpga/pll_config.h"
+#define CONFIG_SYS_GENERIC_BOARD
/*
- High level configuration
*/
Hi Pavel,
On Tue, 2014-05-27 at 14:40 +0200, ZY - pavel wrote:
Hi!
(Sorry for the delay)
I know u-boot SPL misses critical parts, but I was told that u-boot proper should have everything. Only... I was not able to get it to work. [I'm attempting to load recent u-boot from patched/old u-boot; I know this is not exactly recommended, but due to spl/proper split, it should work AFAIK... and does for old versions.]
I have not tried booting u-boot proper from mainline. It just seemed pointless to me to be working from 2 source trees to make a single product.
I will give it a go though.
Actually the U-Boot is working. You just need to #undef CONFIG_SOCFPGA_VIRTUAL_TARGET and build it. I loaded it using a working Preloader and I can reach the U-Boot console.
Aha, you are right, I forgot about VIRTUAL_TARGET define.
U-Boot 2014.07-rc1-00079-g2072e72-dirty (May 16 2014 - 15:54:55)
CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone5 Board DRAM: 1 GiB WARNING: Caches not enabled Using default environment
In: serial Out: serial Err: serial Net: No ethernet found.
Do you have any hints how to get ethernet to work?
I yet to upstream the ethernet part yet. I plan to do that once I upstreamed all the minimum SPL code to run on dev kit.
Plus, for me it says:
tertiary u-boot 13.760972 Warning: Your board does not use generic board. Please read tertiary u-boot 13.770775 doc/README.generic-board and take action. Boards not tertiary u-boot 13.779813 upgraded by the late 2014 may break or be removed.
I believe your patch already resolved this :)
As Chin Liang See has said, there are two issues thwarting this: legal AND source conformance. The code we can fix, the legal can only be fixed by bending Altera - I am going to do that too.
We are making some progress on this. Once we have final green light, we will start the upstreaming of SDRAM code. :)
Looking forward :-).
Yup, work in progress. It slightly time consuming especially removing some unused code :)
Thanks Chin Liang
Thanks, Pavel
Hi!
U-Boot 2014.07-rc1-00079-g2072e72-dirty (May 16 2014 - 15:54:55)
CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone5 Board DRAM: 1 GiB WARNING: Caches not enabled Using default environment
In: serial Out: serial Err: serial Net: No ethernet found.
Do you have any hints how to get ethernet to work?
I yet to upstream the ethernet part yet. I plan to do that once I upstreamed all the minimum SPL code to run on dev kit.
I tried to get it to work, but did not succeed so far.
First, designware.c patches are for version before rewrite -- so I reverted to that version. For some reason, it detects phy at all possible places -- seems like the controller is not listening in the address space?
Then, it seems ethernet address reading depends on i2c, so I added that, and that in turn depends on clock framework.
This is what my current diff. If you have any ideas, let me know.
Best regards, Pavel
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index f564046..c8e925a 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -14,5 +14,8 @@ #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_EMAC0_ADDRESS 0xff700000 +#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +
#endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 33946b6..fd68aa9 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -7,11 +7,39 @@ #include <common.h> #include <asm/arch/reset_manager.h> #include <asm/io.h> +#ifndef CONFIG_SPL_BUILD +#include <phy.h> +#include <micrel.h> +#include <miiphy.h> +#include <netdev.h> +#include "../../../drivers/net/designware.h" +#endif
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
+static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; + +#define RSTMGR_PERMODRST_EMAC0_LSB 0 +#define RSTMGR_PERMODRST_EMAC1_LSB 1 + +#define CONFIG_SYSMGR_EMAC_CTRL (SOCFPGA_SYSMGR_ADDRESS + 0x60) + +/* Enumeration: sysmgr::emacgrp::ctrl::physel::enum */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003 + +/* EMAC controller and PHY used */ +#define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE +#define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR +#define CONFIG_PHY_INTERFACE_MODE SOCFPGA_PHYSEL_ENUM_RGMII + #if defined(CONFIG_DISPLAY_CPUINFO) /* * Print CPU information @@ -64,8 +92,152 @@ int overwrite_console(void) /* * DesignWare Ethernet initialization */ + +int designware_board_phy_init(struct eth_device *dev, int phy_addr, + int (*mii_write)(struct eth_device *, u8, u8, u16), + int (*dw_reset_phy)(struct eth_device *)) +{ + struct dw_eth_dev *priv = dev->priv; + struct phy_device *phydev; + struct mii_dev *bus; + + printf("Back to board file\n"); + + if ((*dw_reset_phy)(dev) < 0) + return -1; + + bus = mdio_get_current_dev(); + printf("Board file: bus %lx\n", bus); + + /* +struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, +phy_interface_t interface) + */ + + phydev = phy_connect(bus, phy_addr, dev, + priv->interface); + + printf("Board file: bus %lx\n", phydev); + /* Micrel PHY is connected to EMAC1 */ + if (strcasecmp(phydev->drv->name, "Micrel ksz9021") == 0 && + ((phydev->drv->uid & phydev->drv->mask) == + (phydev->phy_id & phydev->drv->mask))) { + + printf("Configuring PHY skew timing for %s\n", + phydev->drv->name); + + /* min rx data delay */ + if (ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + getenv_ulong(CONFIG_KSZ9021_DATA_SKEW_ENV, 16, + CONFIG_KSZ9021_DATA_SKEW_VAL)) < 0) + return -1; + /* min tx data delay */ + if (ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + getenv_ulong(CONFIG_KSZ9021_DATA_SKEW_ENV, 16, + CONFIG_KSZ9021_DATA_SKEW_VAL)) < 0) + return -1; + /* max rx/tx clock delay, min rx/tx control */ + if (ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + getenv_ulong(CONFIG_KSZ9021_CLK_SKEW_ENV, 16, + CONFIG_KSZ9021_CLK_SKEW_VAL)) < 0) + return -1; + + if (phydev->drv->config) + phydev->drv->config(phydev); + } + return 0; +} + +/* Change the reset state for EMAC0 */ +void emac0_reset_enable(uint state) +{ + if (state) + setbits_le32(&reset_manager_base->per_mod_reset, + (1 << RSTMGR_PERMODRST_EMAC0_LSB)); + else + clrbits_le32(&reset_manager_base->per_mod_reset, + (1 << RSTMGR_PERMODRST_EMAC0_LSB)); +} + +/* Change the reset state for EMAC1 */ +void emac1_reset_enable(uint state) +{ + if (state) + setbits_le32(&reset_manager_base->per_mod_reset, + (1 << RSTMGR_PERMODRST_EMAC1_LSB)); + else + clrbits_le32(&reset_manager_base->per_mod_reset, + (1 << RSTMGR_PERMODRST_EMAC1_LSB)); +} + + /* We know all the init functions have been run now */ int board_eth_init(bd_t *bis) { - return 0; + printf("Board_eth_init\n"); +#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && \ +!defined(CONFIG_SPL_BUILD) + + /* Initialize EMAC */ + + /* + * Putting the EMAC controller to reset when configuring the PHY + * interface select at System Manager + */ + printf("enabling resets...\n"); + emac0_reset_enable(1); + emac1_reset_enable(1); + + /* Clearing emac0 PHY interface select to 0 */ + clrbits_le32(CONFIG_SYSMGR_EMAC_CTRL, + (SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << +#if (CONFIG_EMAC_BASE == CONFIG_EMAC0_BASE) + SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB)); +#elif (CONFIG_EMAC_BASE == CONFIG_EMAC1_BASE) + SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB)); +#endif + + /* configure to PHY interface select choosed */ + setbits_le32(CONFIG_SYSMGR_EMAC_CTRL, +#if (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_GMII) + (SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII << +#elif (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_MII) + (SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII << +#elif (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_RGMII) + (SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << +#elif (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_RMII) + (SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII << +#endif +#if (CONFIG_EMAC_BASE == CONFIG_EMAC0_BASE) + SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB)); + printf("enabling emac0...\n"); + /* Release the EMAC controller from reset */ + emac0_reset_enable(0); +#elif (CONFIG_EMAC_BASE == CONFIG_EMAC1_BASE) + SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB)); + printf("enabling emac1...\n"); + /* Release the EMAC controller from reset */ + emac1_reset_enable(0); +#endif + + /* initialize and register the emac */ + int rval = designware_initialize(0, CONFIG_EMAC_BASE, + CONFIG_EPHY_PHY_ADDR, +#if (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_GMII) + PHY_INTERFACE_MODE_GMII); +#elif (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_MII) + PHY_INTERFACE_MODE_MII); +#elif (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_RGMII) + PHY_INTERFACE_MODE_RGMII); +#elif (CONFIG_PHY_INTERFACE_MODE == SOCFPGA_PHYSEL_ENUM_RMII) + PHY_INTERFACE_MODE_RMII); +#endif + printf("board_eth_init %d\n", rval); + return rval; +#else + return 0; +#endif } diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c index 43a4330..cfc64fe 100644 --- a/board/bf609-ezkit/bf609-ezkit.c +++ b/board/bf609-ezkit/bf609-ezkit.c @@ -41,12 +41,12 @@ int board_eth_init(bd_t *bis) if (CONFIG_DW_PORTS & 1) { static const unsigned short pins[] = P_RMII0; if (!peripheral_request_list(pins, "emac0")) - ret += designware_initialize(EMAC0_MACCFG, 0); + ret += designware_initialize(0, EMAC0_MACCFG, 1, 0); } if (CONFIG_DW_PORTS & 2) { static const unsigned short pins[] = P_RMII1; if (!peripheral_request_list(pins, "emac1")) - ret += designware_initialize(EMAC1_MACCFG, 0); + ret += designware_initialize(1, EMAC1_MACCFG, 1, 0); }
return ret; diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index 6b6bd9f..e25aba2 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -53,7 +53,8 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) ret++; #endif return ret; diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index a4c6a8e..70f9aa1 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -54,7 +54,8 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) ret++; #endif #if defined(CONFIG_MACB) diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index ab732a7..f6b1fdd 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -65,7 +65,8 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) ret++; #endif #if defined(CONFIG_MACB) diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index 8472002..e996a0e 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -51,7 +51,8 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DW_AUTONEG) interface = PHY_INTERFACE_MODE_GMII; #endif - if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) ret++; #endif return ret; diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c index b8edfcd..044d204 100644 --- a/board/spear/x600/x600.c +++ b/board/spear/x600/x600.c @@ -67,32 +67,31 @@ void board_nand_init(void) fsmc_nand_init(nand); }
-int board_phy_config(struct phy_device *phydev) +int designware_board_phy_init(struct eth_device *dev, int phy_addr, + int (*mii_write)(struct eth_device *, u8, u8, u16), + int dw_reset_phy(struct eth_device *)) { /* Extended PHY control 1, select GMII */ - phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); + mii_write(dev, phy_addr, 23, 0x0020);
/* Software reset necessary after GMII mode selction */ - phy_reset(phydev); + dw_reset_phy(dev);
/* Enable extended page register access */ - phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); + mii_write(dev, phy_addr, 31, 0x0001);
/* 17e: Enhanced LED behavior, needs to be written twice */ - phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); - phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + mii_write(dev, phy_addr, 17, 0x09ff); + mii_write(dev, phy_addr, 17, 0x09ff);
/* 16e: Enhanced LED method select */ - phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); + mii_write(dev, phy_addr, 16, 0xe0ea);
/* Disable extended page register access */ - phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); + mii_write(dev, phy_addr, 31, 0x0000);
/* Enable clock output pin */ - phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); - - if (phydev->drv->config) - phydev->drv->config(phydev); + mii_write(dev, phy_addr, 18, 0x0049);
return 0; } @@ -101,7 +100,7 @@ int board_eth_init(bd_t *bis) { int ret = 0;
- if (designware_initialize(CONFIG_SPEAR_ETHBASE, + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, PHY_INTERFACE_MODE_GMII) >= 0) ret++;
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 78751b2..965b033 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -17,75 +17,7 @@ #include <asm/io.h> #include "designware.h"
-#if !defined(CONFIG_PHYLIB) -# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" -#endif - -static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) -{ - struct eth_mac_regs *mac_p = bus->priv; - ulong start; - u16 miiaddr; - int timeout = CONFIG_MDIO_TIMEOUT; - - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | - ((reg << MIIREGSHIFT) & MII_REGMSK); - - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) - return readl(&mac_p->miidata); - udelay(10); - }; - - return -1; -} - -static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, - u16 val) -{ - struct eth_mac_regs *mac_p = bus->priv; - ulong start; - u16 miiaddr; - int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; - - writel(val, &mac_p->miidata); - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | - ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; - - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - ret = 0; - break; - } - udelay(10); - }; - - return ret; -} - -static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p) -{ - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate MDIO bus\n"); - return -1; - } - - bus->read = dw_mdio_read; - bus->write = dw_mdio_write; - sprintf(bus->name, name); - - bus->priv = (void *)mac_regs_p; - - return mdio_register(bus); -} +static int configure_phy(struct eth_device *dev);
static void tx_descs_init(struct eth_device *dev) { @@ -170,59 +102,53 @@ static void rx_descs_init(struct eth_device *dev) priv->rx_currdescnum = 0; }
-static int dw_write_hwaddr(struct eth_device *dev) +static void descs_init(struct eth_device *dev) { - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - u32 macid_lo, macid_hi; - u8 *mac_id = &dev->enetaddr[0]; - - macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + - (mac_id[3] << 24); - macid_hi = mac_id[4] + (mac_id[5] << 8); - - writel(macid_hi, &mac_p->macaddr0hi); - writel(macid_lo, &mac_p->macaddr0lo); - - return 0; + tx_descs_init(dev); + rx_descs_init(dev); }
-static void dw_adjust_link(struct eth_mac_regs *mac_p, - struct phy_device *phydev) +static int mac_reset(struct eth_device *dev) { - u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p;
- if (!phydev->link) { - printf("%s: No link.\n", phydev->dev->name); - return; - } + ulong start; + int timeout = CONFIG_MACRESET_TIMEOUT;
- if (phydev->speed != 1000) - conf |= MII_PORTSELECT; + writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
- if (phydev->speed == 100) - conf |= FES_100; + if (priv->interface != PHY_INTERFACE_MODE_RGMII) + writel(MII_PORTSELECT, &mac_p->conf);
- if (phydev->duplex) - conf |= FULLDPLXMODE; + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) + return 0;
- writel(conf, &mac_p->conf); + /* Try again after 10usec */ + udelay(10); + };
- printf("Speed: %d, %s duplex%s\n", phydev->speed, - (phydev->duplex) ? "full" : "half", - (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); + return -1; }
-static void dw_eth_halt(struct eth_device *dev) +static int dw_write_hwaddr(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; - struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 macid_lo, macid_hi; + u8 *mac_id = &dev->enetaddr[0];
- writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); - writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); + macid_lo = mac_id[0] + (mac_id[1] << 8) + \ + (mac_id[2] << 16) + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8);
- phy_shutdown(priv->phydev); + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; }
static int dw_eth_init(struct eth_device *dev, bd_t *bis) @@ -230,43 +156,60 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; struct eth_dma_regs *dma_p = priv->dma_regs_p; - unsigned int start; + u32 conf;
- writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); + if (priv->phy_configured != 1) { + int ret = configure_phy(dev); + if (ret < 0) { + printf("failed to configure phy: %d\n", ret); + return ret; + } + }
- start = get_timer(0); - while (readl(&dma_p->busmode) & DMAMAC_SRST) { - if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) - return -1; + /* Print link status only once */ + if (!priv->link_printed) { + printf("ENET Speed is %d Mbps - %s duplex connection\n", + priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); + priv->link_printed = 1; + }
- mdelay(100); - }; + /* Reset ethernet hardware */ + if (mac_reset(dev) < 0) + return -1;
- /* Soft reset above clears HW address registers. - * So we have to set it here once again */ + /* Resore the HW MAC address as it has been lost during MAC reset */ dw_write_hwaddr(dev);
- rx_descs_init(dev); - tx_descs_init(dev); + writel(FIXEDBURST | PRIORXTX_41 | BURST_16, + &dma_p->busmode);
- writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | + TXSECONDFRAME, &dma_p->opmode);
- writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, - &dma_p->opmode); + conf = FRAMEBURSTENABLE | DISABLERXOWN;
- writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); + if (priv->speed != 1000) + conf |= MII_PORTSELECT;
- /* Start up the PHY */ - if (phy_startup(priv->phydev)) { - printf("Could not initialize PHY %s\n", - priv->phydev->dev->name); - return -1; + if ((priv->interface != PHY_INTERFACE_MODE_MII) && + (priv->interface != PHY_INTERFACE_MODE_GMII)) { + + if (priv->speed == 100) + conf |= FES_100; }
- dw_adjust_link(mac_p, priv->phydev); + if (priv->duplex == FULL) + conf |= FULLDPLXMODE;
- if (!priv->phydev->link) - return -1; + writel(conf, &mac_p->conf); + + descs_init(dev); + + /* + * Start/Enable xfer at dma as well as mac level + */ + writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); + writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
@@ -376,36 +319,271 @@ static int dw_eth_recv(struct eth_device *dev) return length; }
-static int dw_phy_init(struct eth_device *dev) +static void dw_eth_halt(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; - struct phy_device *phydev; - int mask = 0xffffffff;
-#ifdef CONFIG_PHY_ADDR - mask = 1 << CONFIG_PHY_ADDR; + mac_reset(dev); + priv->tx_currdescnum = priv->rx_currdescnum = 0; +} + +static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + ulong start; + u32 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ + ((reg << MIIREGSHIFT) & MII_REGMSK); + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + *val = readl(&mac_p->miidata); + return 0; + } + + /* Try again after 10usec */ + udelay(10); + }; + + return -1; +} + +static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + ulong start; + u32 miiaddr; + int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; + u16 value; + + printf("eth_mdio_write %lx\n", &mac_p->miidata); + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + ret = 0; + break; + } + + /* Try again after 10usec */ + udelay(10); + }; + + /* Needed as a fix for ST-Phy */ + eth_mdio_read(dev, addr, reg, &value); + + return ret; +} + +#if defined(CONFIG_DW_SEARCH_PHY) +static int find_phy(struct eth_device *dev) +{ + int phy_addr = 1; + u16 ctrl, oldctrl; + + do { + printf("Searching at %d\n", phy_addr); + eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); + oldctrl = ctrl & BMCR_ANENABLE; + + ctrl ^= BMCR_ANENABLE; + eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); + eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); + ctrl &= BMCR_ANENABLE; + + if (ctrl == oldctrl) { + phy_addr++; + } else { + ctrl ^= BMCR_ANENABLE; + eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); + printf("Found at %d\n", phy_addr); + + return phy_addr; + } + } while (phy_addr < 32); + + return -1; +} +#endif + +static int dw_reset_phy(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + u16 ctrl; + ulong start; + int timeout = CONFIG_PHYRESET_TIMEOUT; + u32 phy_addr = priv->address; + + eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); + + start = get_timer(0); + while (get_timer(start) < timeout) { + eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); + if (!(ctrl & BMCR_RESET)) + break; + + /* Try again after 10usec */ + udelay(10); + }; + + if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT) { + printf("timed out waiting for phy reset %x\n", ctrl); + return -1; + } + + // phydev->supported &= PHY_GBIT_FEATURES; +#ifdef CONFIG_PHY_RESET_DELAY + udelay(CONFIG_PHY_RESET_DELAY); +#endif + return 0; +} + +/* + * Add weak default function for board specific PHY configuration + */ +int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr, + int (*mii_write)(struct eth_device *, u8, u8, u16), + int dw_reset_phy(struct eth_device *)) +{ + return 0; +} + +static int configure_phy(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + int phy_addr; + u16 bmcr; +#if defined(CONFIG_DW_AUTONEG) + u16 bmsr; + u32 timeout; + ulong start; #endif
- phydev = phy_find_by_mask(priv->bus, mask, priv->interface); - if (!phydev) + printf("configure_phy\n"); + +#if defined(CONFIG_DW_SEARCH_PHY) + printf("finding phy\n"); + phy_addr = find_phy(dev); + if (phy_addr >= 0) + priv->address = phy_addr; + else + return -1; +#else + phy_addr = priv->address; +#endif + + /* + * Some boards need board specific PHY initialization. This is + * after the main driver init code but before the auto negotiation + * is run. + */ + if (designware_board_phy_init(dev, phy_addr, + eth_mdio_write, dw_reset_phy) < 0) + return -1; + +#if 0 + if (dw_reset_phy(dev) < 0) return -1; +#endif
- phy_connect_dev(phydev, dev); +#if defined(CONFIG_DW_AUTONEG) + /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */ + eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1);
- phydev->supported &= PHY_GBIT_FEATURES; - phydev->advertising = phydev->supported; + bmcr = BMCR_ANENABLE | BMCR_ANRESTART; +#else + bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;
- priv->phydev = phydev; - phy_config(phydev); +#if defined(CONFIG_DW_SPEED10M) + bmcr &= ~BMCR_SPEED100; +#endif +#if defined(CONFIG_DW_DUPLEXHALF) + bmcr &= ~BMCR_FULLDPLX; +#endif +#endif + if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) + return -1;
- return 1; + /* Read the phy status register and populate priv structure */ +#if defined(CONFIG_DW_AUTONEG) + timeout = CONFIG_AUTONEG_TIMEOUT; + start = get_timer(0); + puts("Waiting for PHY auto negotiation to complete"); + while (get_timer(start) < timeout) { + eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); + if (bmsr & BMSR_ANEGCOMPLETE) { + priv->phy_configured = 1; + break; + } + + /* Print dot all 1s to show progress */ + if ((get_timer(start) % 1000) == 0) + putc('.'); + + /* Try again after 1msec */ + udelay(1000); + }; + + if (!(bmsr & BMSR_ANEGCOMPLETE)) + puts(" TIMEOUT!\n"); + else + puts(" done\n"); +#else + priv->phy_configured = 1; +#endif + +#ifndef CONFIG_MII +#error Need config_phy +#endif + priv->speed = miiphy_speed(dev->name, phy_addr); + priv->duplex = miiphy_duplex(dev->name, phy_addr); + + return 0; }
-int designware_initialize(ulong base_addr, u32 interface) +#if defined(CONFIG_MII) +static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val) +{ + struct eth_device *dev; + + dev = eth_get_dev_by_name(devname); + if (dev) + eth_mdio_read(dev, addr, reg, val); + + return 0; +} + +static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) +{ + struct eth_device *dev; + + dev = eth_get_dev_by_name(devname); + if (dev) + eth_mdio_write(dev, addr, reg, val); + + return 0; +} +#endif + +int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) { struct eth_device *dev; struct dw_eth_dev *priv;
+ printf("dw_initalize\n"); dev = (struct eth_device *) malloc(sizeof(struct eth_device)); if (!dev) return -ENOMEM; @@ -423,14 +601,20 @@ int designware_initialize(ulong base_addr, u32 interface) memset(dev, 0, sizeof(struct eth_device)); memset(priv, 0, sizeof(struct dw_eth_dev));
- sprintf(dev->name, "dwmac.%lx", base_addr); + sprintf(dev->name, "mii%d", id); dev->iobase = (int)base_addr; dev->priv = priv;
+ printf("Get address\n"); + eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]); + priv->dev = dev; priv->mac_regs_p = (struct eth_mac_regs *)base_addr; priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + DW_DMA_BASE_OFFSET); + priv->address = phy_addr; + priv->phy_configured = 0; + priv->interface = interface;
dev->init = dw_eth_init; dev->send = dw_eth_send; @@ -438,12 +622,13 @@ int designware_initialize(ulong base_addr, u32 interface) dev->halt = dw_eth_halt; dev->write_hwaddr = dw_write_hwaddr;
+ printf("Get eth register\n"); eth_register(dev);
- priv->interface = interface; +#if defined(CONFIG_MII) + printf("Get eth miiphy_register\n");
- dw_mdio_init(dev->name, priv->mac_regs_p); - priv->bus = miiphy_get_dev_by_name(dev->name); - - return dw_phy_init(dev); + miiphy_register(dev->name, dw_mii_read, dw_mii_write); +#endif + return 1; } diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 382b0c7..60b1103 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -16,6 +16,8 @@
#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ)
struct eth_mac_regs { u32 conf; /* 0x00 */ @@ -215,9 +217,14 @@ struct dmamacdescr { #endif
struct dw_eth_dev { + u32 address; u32 interface; + u32 speed; + u32 duplex; u32 tx_currdescnum; u32 rx_currdescnum; + u32 phy_configured; + u32 link_printed;
struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; @@ -229,8 +236,15 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p;
struct eth_device *dev; - struct phy_device *phydev; - struct mii_dev *bus; };
+/* Speed specific definitions */ +#define SPEED_10M 1 +#define SPEED_100M 2 +#define SPEED_1000M 3 + +/* Duplex mode specific definitions */ +#define HALF_DUPLEX 1 +#define FULL_DUPLEX 2 + #endif diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 5d7e3be..506efb2 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -53,6 +53,8 @@ static struct phy_driver KS8721_driver = { static int ksz90xx_startup(struct phy_device *phydev) { unsigned phy_ctl; + + printf("ksz90xx_startup\n"); genphy_update_link(phydev); phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
@@ -215,6 +217,7 @@ static struct phy_driver ksz9031_driver = {
int phy_micrel_init(void) { + printf("phy_micrel_init\n"); phy_register(&KSZ804_driver); #ifdef CONFIG_PHY_MICREL_KSZ9021 phy_register(&ksz9021_driver); diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 12192ff..1a43e1b 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -72,13 +72,12 @@ #define CONFIG_NET_MULTI #define CONFIG_HOSTNAME "bf609-ezkit" #define CONFIG_DESIGNWARE_ETH -#define CONFIG_PHY_ADDR 1 #define CONFIG_DW_PORTS 1 +#define CONFIG_DW_AUTONEG #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_MII -#define CONFIG_PHYLIB
/* i2c Settings */ #define CONFIG_BFIN_TWI_I2C diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 56f993a..ded6cb6 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -206,6 +206,46 @@ #define CONFIG_ENV_IS_NOWHERE
/* + * network support + */ +#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_DESIGNWARE_ETH 1 +#endif + +#ifdef CONFIG_DESIGNWARE_ETH +#define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS +#define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS +/* console support for network */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +/* designware */ +#define CONFIG_NET_MULTI +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_MII +#define CONFIG_PHY_GIGE +#define CONFIG_DW_AUTONEG +#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +/* phy */ +#define CONFIG_EPHY0_PHY_ADDR 0 +#define CONFIG_EPHY1_PHY_ADDR 4 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 +/* Type of PHY available */ +#define SOCFPGA_PHYSEL_ENUM_GMII 0x0 +#define SOCFPGA_PHYSEL_ENUM_MII 0x1 +#define SOCFPGA_PHYSEL_ENUM_RGMII 0x2 +#define SOCFPGA_PHYSEL_ENUM_RMII 0x3 +#endif /* CONFIG_DESIGNWARE_ETH */ + +/* * SPL "Second Program Loader" aka Initial Software */
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index c0eba37..55f100a 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -17,9 +17,11 @@ /* Ethernet driver configuration */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_DW0_PHY 1 #define CONFIG_NET_MULTI -#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ +#define CONFIG_DW_AUTONEG #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
/* USBD driver configuration */ diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h index 28dddcc..7f4dc58 100644 --- a/include/configs/spear6xx_evb.h +++ b/include/configs/spear6xx_evb.h @@ -37,9 +37,6 @@ #define CONFIG_SYS_FSMC_NAND_8BIT #define CONFIG_SYS_NAND_BASE 0xD2000000
-/* Ethernet PHY configuration */ -#define CONFIG_PHY_NATSEMI - /* Environment Settings */ #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
diff --git a/include/netdev.h b/include/netdev.h index e211f18..72a0503 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -36,7 +36,7 @@ int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); int davinci_emac_initialize(void); int dc21x4x_initialize(bd_t *bis); -int designware_initialize(ulong base_addr, u32 interface); +int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface); int dm9000_initialize(bd_t *bis); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis);
participants (5)
-
Albert ARIBAUD -
Charles Manning -
Chin Liang See -
Marek Vasut -
Pavel Machek