[PATCH 0/3] Marvell SheevaPlug : convert Ethernet and SATA to Driver Model.
- Add DM_ETH, SATA_MV and associated configs to sheevaplug_defconfig - Remove IDE, and add SATA configs in board file sheevaplug.h - Replace old device name "egiga0" with Ethernet PHY name from device tree. - Replace the old Ethernet PHY addr lookup with a device tree parsing lookup function. Note that all Kirkwood SoCs boards use the same binding for Ethernet port 0 and 1 nodes from kirkwood.dtsi. Thus the new lookup function fdt_get_phy_addr() in this patch series probably should be factored out to a common fdt support function and used in other Kirkwood boards.
Tony Dinh (3): Marvell Sheevaplug: Add DM Ethernet and DM SATA configs Marvell Sheevaplug: Use Ethernet PHY name and address from device tree Marvell Sheevaplug: Add DM SATA and remove IDE configs
board/Marvell/sheevaplug/sheevaplug.c | 54 +++++++++++++++++++++------ configs/sheevaplug_defconfig | 6 ++- include/configs/sheevaplug.h | 9 ++--- 3 files changed, 51 insertions(+), 18 deletions(-)
Add DM_ETH, SATA_MV and associated configs to sheevaplug_defconfig
Signed-off-by: Tony Dinh mibodhi@gmail.com ---
configs/sheevaplug_defconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 676c47af27..4c7259e6d7 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -17,7 +17,6 @@ CONFIG_USE_PREBOOT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y @@ -53,3 +52,8 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LZMA=y CONFIG_BZIP2=y +CONFIG_BLK=y +CONFIG_DM_ETH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CMD_SATA=y +CONFIG_SATA_MV=y
- In DM Ethernet, the old "egiga0" name is no longer valid, so replace it with Ethernet PHY name from device tree. Also, Ethernet PHY address is available so read it from device tree.
Signed-off-by: Tony Dinh mibodhi@gmail.com ---
board/Marvell/sheevaplug/sheevaplug.c | 54 +++++++++++++++++++++------ 1 file changed, 42 insertions(+), 12 deletions(-)
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 0cc7f2b392..7ba56a44e4 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright (C) 2021 Tony Dinh mibodhi@gmail.com * (C) Copyright 2009 * Marvell Semiconductor <www.marvell.com> * Written-by: Prafulla Wadaskar prafulla@marvell.com @@ -100,36 +101,65 @@ int board_init(void) return 0; }
+static int fdt_get_phy_addr(const char *path) +{ + const void *fdt = gd->fdt_blob; + const u32 *reg; + const u32 *val; + int node, phandle, addr; + + /* Find the node by its full path */ + node = fdt_path_offset(fdt, path); + if (node >= 0) { + /* Look up phy-handle */ + val = fdt_getprop(fdt, node, "phy-handle", NULL); + if (val) { + phandle = fdt32_to_cpu(*val); + if (!phandle) + return -1; + /* Follow it to its node */ + node = fdt_node_offset_by_phandle(fdt, phandle); + if (node) { + /* Look up reg */ + reg = fdt_getprop(fdt, node, "reg", NULL); + if (reg) { + addr = fdt32_to_cpu(*reg); + return addr; + } + } + } + } + return -1; +} + #ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E1116 PHY */ void reset_phy(void) { u16 reg; - u16 devadr; - char *name = "egiga0"; + u16 phyaddr; + char *name = "ethernet-controller@72000"; + char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
if (miiphy_set_current_dev(name)) return;
- /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __FUNCTION__); + phyaddr = fdt_get_phy_addr(eth0_path); + if (phyaddr < 0) return; - }
/* * Enable RGMII delay on Tx and Rx for CPU port * Ref: sec 4.7.2 of chip datasheet */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
/* reset the phy */ - miiphy_reset(name, devadr); + miiphy_reset(name, phyaddr);
printf("88E1116 Initialized on %s\n", name); }
- In DM Ethernet, the old "egiga0" name is no longer valid, so replace it with Ethernet PHY name from device tree. Also, Ethernet PHY address is available so read it from device tree.
Signed-off-by: Tony Dinh mibodhi@gmail.com ---
board/Marvell/sheevaplug/sheevaplug.c | 54 +++++++++++++++++++++------ 1 file changed, 42 insertions(+), 12 deletions(-)
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 0cc7f2b392..5952d158b2 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright (C) 2021 Tony Dinh mibodhi@gmail.com * (C) Copyright 2009 * Marvell Semiconductor <www.marvell.com> * Written-by: Prafulla Wadaskar prafulla@marvell.com @@ -100,36 +101,65 @@ int board_init(void) return 0; }
+static int fdt_get_phy_addr(const char *path) +{ + const void *fdt = gd->fdt_blob; + const u32 *reg; + const u32 *val; + int node, phandle, addr; + + /* Find the node by its full path */ + node = fdt_path_offset(fdt, path); + if (node >= 0) { + /* Look up phy-handle */ + val = fdt_getprop(fdt, node, "phy-handle", NULL); + if (val) { + phandle = fdt32_to_cpu(*val); + if (!phandle) + return -1; + /* Follow it to its node */ + node = fdt_node_offset_by_phandle(fdt, phandle); + if (node) { + /* Look up reg */ + reg = fdt_getprop(fdt, node, "reg", NULL); + if (reg) { + addr = fdt32_to_cpu(*reg); + return addr; + } + } + } + } + return -1; +} + #ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E1116 PHY */ void reset_phy(void) { u16 reg; - u16 devadr; - char *name = "egiga0"; + int phyaddr; + char *name = "ethernet-controller@72000"; + char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
if (miiphy_set_current_dev(name)) return;
- /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __FUNCTION__); + phyaddr = fdt_get_phy_addr(eth0_path); + if (phyaddr < 0) return; - }
/* * Enable RGMII delay on Tx and Rx for CPU port * Ref: sec 4.7.2 of chip datasheet */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
/* reset the phy */ - miiphy_reset(name, devadr); + miiphy_reset(name, phyaddr);
printf("88E1116 Initialized on %s\n", name); }
Enable DM SATA, removed IDE driver, and add SATA MV driver.
Signed-off-by: Tony Dinh mibodhi@gmail.com ---
include/configs/sheevaplug.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 41ba799659..e28f98458e 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -53,10 +53,9 @@ /* * SATA driver configuration */ -#ifdef CONFIG_IDE -#define __io -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /* CONFIG_IDE */ +#ifdef CONFIG_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_LBA48 +#endif /* CONFIG_SATA */
#endif /* _CONFIG_SHEEVAPLUG_H */
On 14.07.21 06:35, Tony Dinh wrote:
- Add DM_ETH, SATA_MV and associated configs to sheevaplug_defconfig
- Remove IDE, and add SATA configs in board file sheevaplug.h
- Replace old device name "egiga0" with Ethernet PHY name from device
tree.
- Replace the old Ethernet PHY addr lookup with a device tree parsing
lookup function. Note that all Kirkwood SoCs boards use the same binding for Ethernet port 0 and 1 nodes from kirkwood.dtsi. Thus the new lookup function fdt_get_phy_addr() in this patch series probably should be factored out to a common fdt support function and used in other Kirkwood boards.
Tony Dinh (3): Marvell Sheevaplug: Add DM Ethernet and DM SATA configs Marvell Sheevaplug: Use Ethernet PHY name and address from device tree Marvell Sheevaplug: Add DM SATA and remove IDE configs
board/Marvell/sheevaplug/sheevaplug.c | 54 +++++++++++++++++++++------ configs/sheevaplug_defconfig | 6 ++- include/configs/sheevaplug.h | 9 ++--- 3 files changed, 51 insertions(+), 18 deletions(-)
Applied to u-boot-marvell/master
Thanks, Stefan
participants (2)
-
Stefan Roese -
Tony Dinh