[U-Boot] [PATCH v3 01/60] mpc83xx: Introduce ARCH_MPC830*
Replace CONFIG_MPC830* with proper CONFIG_ARCH_MPC830* Kconfig options.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Removed config options from whitelist
--- arch/powerpc/cpu/mpc83xx/Kconfig | 17 +++++++++ arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- arch/powerpc/cpu/mpc83xx/speed.c | 38 ++++++++++---------- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 2 +- arch/powerpc/include/asm/fsl_lbc.h | 2 +- arch/powerpc/include/asm/global_data.h | 6 ++-- arch/powerpc/include/asm/immap_83xx.h | 10 +++--- arch/powerpc/include/asm/mpc8xxx_spi.h | 2 +- board/keymile/km83xx/km83xx.c | 2 +- drivers/qe/qe.c | 2 +- drivers/ram/mpc83xx_sdram.c | 4 +-- include/configs/MPC8308RDB.h | 2 -- include/configs/hrcon.h | 2 -- include/configs/km/km8309-common.h | 2 -- include/configs/km/km83xx-common.h | 2 +- include/configs/mpc8308_p1m.h | 2 -- include/configs/strider.h | 2 -- include/linux/immap_qe.h | 2 +- include/mpc83xx.h | 24 ++++++------- scripts/config_whitelist.txt | 3 -- 20 files changed, 66 insertions(+), 62 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 571cf8fc2ef..142b9247860 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -10,6 +10,7 @@ choice
config TARGET_MPC8308_P1M bool "Support mpc8308_p1m" + select ARCH_MPC8308
config TARGET_SBC8349 bool "Support sbc8349" @@ -22,6 +23,7 @@ config TARGET_VME8349
config TARGET_MPC8308RDB bool "Support MPC8308RDB" + select ARCH_MPC8308 select SYS_FSL_ERRATUM_ESDHC111
config TARGET_MPC8313ERDB @@ -74,6 +76,8 @@ config TARGET_KM8360
config TARGET_SUVD3 bool "Support suvd3" + select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMTEGR1" + select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMVECT1" imply CMD_CRAMFS imply FS_CRAMFS
@@ -87,15 +91,28 @@ config TARGET_TQM834X
config TARGET_HRCON bool "Support hrcon" + select ARCH_MPC8308 select SYS_FSL_ERRATUM_ESDHC111
config TARGET_STRIDER bool "Support strider" + select ARCH_MPC8308 select SYS_FSL_ERRATUM_ESDHC111 imply CMD_PCA953X
endchoice
+config ARCH_MPC830X + bool + +config ARCH_MPC8308 + bool + select ARCH_MPC830X + +config ARCH_MPC8309 + bool + select ARCH_MPC830X + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 328a018eb6f..97ef77121b5 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -31,7 +31,7 @@ void board_add_ram_info(int use_default) printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) puts(", 16-bit"); else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 39bc1c53406..d537af5130a 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -85,12 +85,12 @@ int get_clocks(void) u32 lcrr;
u32 csb_clk; -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) u32 usbdr_clk; #endif #ifdef CONFIG_MPC834x @@ -107,7 +107,7 @@ int get_clocks(void) #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) u32 enc_clk; #endif u32 lbiu_clk; @@ -122,7 +122,7 @@ int get_clocks(void) u32 qe_clk; u32 brg_clk; #endif -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) u32 pciexp1_clk; u32 pciexp2_clk; @@ -155,7 +155,7 @@ int get_clocks(void)
sccr = im->clk.sccr;
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: @@ -176,7 +176,7 @@ int get_clocks(void) } #endif
-#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: @@ -197,7 +197,7 @@ int get_clocks(void) } #endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: @@ -252,7 +252,7 @@ int get_clocks(void) return -6; } #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { case 0: enc_clk = 0; @@ -317,20 +317,20 @@ int get_clocks(void) i2c1_clk = csb_clk; #elif defined(CONFIG_MPC832x) i2c1_clk = enc_clk; -#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; #elif defined(CONFIG_MPC837x) i2c1_clk = enc_clk; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) i2c1_clk = csb_clk; #endif #if !defined(CONFIG_MPC832x) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ #endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: @@ -448,12 +448,12 @@ int get_clocks(void) #endif
gd->arch.csb_clk = csb_clk; -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; gd->arch.usbdr_clk = usbdr_clk; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) gd->arch.usbdr_clk = usbdr_clk; #endif #if defined(CONFIG_MPC834x) @@ -470,7 +470,7 @@ int get_clocks(void) #if !defined(CONFIG_MPC832x) gd->arch.i2c2_clk = i2c2_clk; #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) gd->arch.enc_clk = enc_clk; #endif gd->arch.lbiu_clk = lbiu_clk; @@ -483,7 +483,7 @@ int get_clocks(void) gd->arch.qe_clk = qe_clk; gd->arch.brg_clk = brg_clk; #endif -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) gd->arch.pciexp1_clk = pciexp1_clk; gd->arch.pciexp2_clk = pciexp2_clk; @@ -540,7 +540,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->arch.mem_sec_clk)); #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) printf(" SEC: %-4s MHz\n", strmhz(buf, gd->arch.enc_clk)); #endif @@ -558,7 +558,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->arch.sdhc_clk)); #endif -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->arch.tsec1_clk)); @@ -566,7 +566,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.tsec2_clk)); printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->arch.usbdr_clk)); -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->arch.usbdr_clk)); #endif @@ -574,7 +574,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->arch.usbmph_clk)); #endif -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->arch.pciexp1_clk)); diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 57f783ba14a..4e5a352ac67 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -6,7 +6,7 @@ /* * The MCP83xx's 1-2 GPIO controllers each with 32 bits. */ -#if defined(CONFIG_MPC8313) || defined(CONFIG_MPC8308) || \ +#if defined(CONFIG_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_MPC8315) #define MPC83XX_GPIO_CTRLRS 1 #elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index b076d5e838d..cf89e186a67 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -133,7 +133,7 @@ void lbc_sdram_init(void); #define OR_GPCM_EHTR_SHIFT 1 #define OR_GPCM_EHTR_CLEAR 0x00000000 #define OR_GPCM_EHTR_SET 0x00000002 -#if !defined(CONFIG_MPC8308) +#if !defined(CONFIG_ARCH_MPC8308) #define OR_GPCM_EAD 0x00000001 #define OR_GPCM_EAD_SHIFT 0 #endif diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index d00cee95fbb..700e2be0ee2 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -35,12 +35,12 @@ struct arch_global_data { #else /* There are other clocks in the MPC83XX */ u32 csb_clk; -# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; -# elif defined(CONFIG_MPC8309) +# elif defined(CONFIG_ARCH_MPC8309) u32 usbdr_clk; # endif # if defined(CONFIG_MPC834x) @@ -53,7 +53,7 @@ struct arch_global_data { u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; -# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) u32 pciexp1_clk; u32 pciexp2_clk; diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index afef36f2628..b10feb546c6 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -59,12 +59,12 @@ typedef struct sysconf83xx { u32 obir; /* Output Buffer Impedance Register */ u8 res8[0xC]; u32 pecr1; /* PCI Express control register 1 */ -#if defined(CONFIG_MPC830x) +#if defined(CONFIG_ARCH_MPC830X) u32 sdhccr; /* eSDHC Control Registers for MPC830x */ #else u32 pecr2; /* PCI Express control register 2 */ #endif -#if defined(CONFIG_MPC8309) +#if defined(CONFIG_ARCH_MPC8309) u32 can_dbg_ctrl; u32 res9a; u32 gpr1; @@ -604,7 +604,7 @@ typedef struct serdes83xx { * On Chip ROM */ typedef struct rom83xx { -#if defined(CONFIG_MPC8309) +#if defined(CONFIG_ARCH_MPC8309) u8 mem[0x8000]; #else u8 mem[0x10000]; @@ -714,7 +714,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t;
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ @@ -879,7 +879,7 @@ typedef struct immap { u8 res8[0xC0000]; u8 qe[0x100000]; /* QE block */ } immap_t; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 432be054696..518d0c388a7 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -10,7 +10,7 @@
#include <asm/types.h>
-#if defined(CONFIG_MPC8308) || \ +#if defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_MPC8313) || \ defined(CONFIG_MPC8315) || \ defined(CONFIG_MPC834x) || \ diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 4818a4994a0..ce5126aae6b 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -56,7 +56,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {5, 2, 1, 0, 1}, /* UART2_RTS */ {5, 3, 2, 0, 2}, /* UART2_SIN */ {5, 1, 2, 0, 3}, /* UART2_CTS */ -#elif !defined(CONFIG_MPC8309) +#elif !defined(CONFIG_ARCH_MPC8309) /* Local Bus */ {0, 16, 1, 0, 3}, /* LA00 */ {0, 17, 1, 0, 3}, /* LA01 */ diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 70d02d3f939..505ae9b45fb 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -119,7 +119,7 @@ static void qe_sdma_init(void) */ static u8 thread_snum[] = { /* Evthreads 16-29 are not supported in MPC8309 */ -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) 0x04, 0x05, 0x0c, 0x0d, 0x14, 0x15, 0x1c, 0x1d, 0x24, 0x25, 0x2c, 0x2d, diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index 441baeb6f1a..e3523299812 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -179,7 +179,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_RD_NEVER: case ODT_RD_ONLY_CURRENT: case ODT_RD_ONLY_OTHER_CS: - if (!IS_ENABLED(CONFIG_MPC830x) && + if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_MPC831x) && !IS_ENABLED(CONFIG_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { @@ -210,7 +210,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_WR_NEVER: case ODT_WR_ONLY_CURRENT: case ODT_WR_ONLY_OTHER_CS: - if (!IS_ENABLED(CONFIG_MPC830x) && + if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_MPC831x) && !IS_ENABLED(CONFIG_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 3827ea464b4..7bf91524c88 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -12,8 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC830x 1 /* MPC830x family */ -#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 52e62778a3c..23ed4e54c72 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -13,8 +13,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_MPC830x 1 /* MPC830x family */ -#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_HRCON 1 /* HRCON board specific */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h index 0e0b1b4605b..3bd334c5152 100644 --- a/include/configs/km/km8309-common.h +++ b/include/configs/km/km8309-common.h @@ -14,8 +14,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC830x 1 /* MPC830x family */ -#define CONFIG_MPC8309 1 /* MPC8309 CPU specific */
#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index a76f606e3ed..fb2a1cb39a0 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -135,7 +135,7 @@ #define CONFIG_UEC_ETH #define CONFIG_ETHPRIME "UEC0"
-#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_ARCH_MPC8309) #define CONFIG_UEC_ETH1 /* GETH1 */ #define UEC_VERBOSE_DEBUG 1 #endif diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 98f030388cd..c007877276b 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -12,8 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC830x 1 /* MPC830x family */ -#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
/* * On-board devices diff --git a/include/configs/strider.h b/include/configs/strider.h index 972543d6bd1..89e0610871e 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -13,8 +13,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_MPC830x 1 /* MPC830x family */ -#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_STRIDER 1 /* STRIDER board specific */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index 51800096b2c..f7bc503ea33 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -16,7 +16,7 @@ #define QE_MURAM_SIZE 0xc000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 -#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309) +#elif defined(CONFIG_MPC832x) || defined(CONFIG_ARCH_MPC8309) #define QE_MURAM_SIZE 0x4000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index a4c5bd38376..e93f50d0b33 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -129,7 +129,7 @@ #define SPCR_TSEC2EP 0x00000003 #define SPCR_TSEC2EP_SHIFT (31-31)
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) /* SPCR bits - MPC8308, MPC831x and MPC837x specific */ /* TSEC data priority */ @@ -336,7 +336,7 @@ #define SICRH_SPI 0x00000003 #define SICRH_SPI_SD 0x00000001
-#elif defined(CONFIG_MPC8308) +#elif defined(CONFIG_ARCH_MPC8308) /* SICRL bits - MPC8308 specific */ #define SICRL_SPI_PF0 (0 << 28) #define SICRL_SPI_PF1 (1 << 28) @@ -384,7 +384,7 @@ #define SICRH_TSOBI2_V3P3 (0 << 0) #define SICRH_TSOBI2_V2P5 (1 << 0)
-#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) /* SICR_1 */ #define SICR_1_UART1_UART1S (0 << (30-2)) #define SICR_1_UART1_UART1RTS (1 << (30-2)) @@ -639,7 +639,7 @@ #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_2 0x00000000 @@ -654,7 +654,7 @@ #define HRCWL_SVCOD_DIV_8 0x10000000 #define HRCWL_SVCOD_DIV_2 0x20000000 #define HRCWL_SVCOD_DIV_1 0x30000000 -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309)
#define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 @@ -765,7 +765,7 @@ #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 @@ -818,7 +818,7 @@ /* * RSR - Reset Status Register */ -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 @@ -986,7 +986,7 @@ #define SCCR_USBDRCM_2 0x00200000 #define SCCR_USBDRCM_3 0x00300000
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) /* SCCR bits - MPC8315/MPC8308 specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -1071,7 +1071,7 @@ #define SCCR_SATACM_1 0x00000055 #define SCCR_SATACM_2 0x000000aa #define SCCR_SATACM_3 0x000000ff -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_ARCH_MPC8309) /* SCCR bits - MPC8309 specific */ #define SCCR_SDHCCM 0x0c000000 #define SCCR_SDHCCM_SHIFT 26 @@ -1117,7 +1117,7 @@ */ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 -#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 @@ -1239,14 +1239,14 @@ #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) #define SDRAM_CFG_DBW_MASK 0x00180000 #define SDRAM_CFG_DBW_16 0x00100000 #define SDRAM_CFG_DBW_32 0x00080000 #else #define SDRAM_CFG_32_BE 0x00080000 #endif -#if !defined(CONFIG_MPC8308) +#if !defined(CONFIG_ARCH_MPC8308) #define SDRAM_CFG_8_BE 0x00040000 #endif #define SDRAM_CFG_NCAP 0x00020000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e2c2889acf9..2c2ced8e475 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1248,9 +1248,6 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC8308 -CONFIG_MPC8309 -CONFIG_MPC830x CONFIG_MPC8313 CONFIG_MPC8313ERDB CONFIG_MPC8315
Replace CONFIG_MPC833* with proper CONFIG_ARCH_MPC833* Kconfig options.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Removed config options from whitelist
--- arch/powerpc/cpu/mpc83xx/Kconfig | 15 ++++++++ arch/powerpc/cpu/mpc83xx/cpu.c | 2 +- arch/powerpc/cpu/mpc83xx/cpu_init.c | 4 +- arch/powerpc/cpu/mpc83xx/fdt.c | 6 +-- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- arch/powerpc/cpu/mpc83xx/speed.c | 40 ++++++++++---------- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 4 +- arch/powerpc/include/asm/global_data.h | 8 ++-- arch/powerpc/include/asm/immap_83xx.h | 4 +- arch/powerpc/include/asm/mpc8xxx_spi.h | 4 +- drivers/ram/mpc83xx_sdram.c | 4 +- include/configs/MPC8313ERDB.h | 2 - include/configs/MPC8315ERDB.h | 2 - include/configs/ids8313.h | 3 -- include/configs/ve8313.h | 2 - include/mpc83xx.h | 20 +++++----- scripts/config_whitelist.txt | 3 -- 17 files changed, 64 insertions(+), 61 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 142b9247860..20780ba68bd 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -17,6 +17,7 @@ config TARGET_SBC8349
config TARGET_VE8313 bool "Support ve8313" + select ARCH_MPC8313
config TARGET_VME8349 bool "Support vme8349" @@ -28,11 +29,13 @@ config TARGET_MPC8308RDB
config TARGET_MPC8313ERDB bool "Support MPC8313ERDB" + select ARCH_MPC8313 select BOARD_EARLY_INIT_F select SUPPORT_SPL
config TARGET_MPC8315ERDB bool "Support MPC8315ERDB" + select ARCH_MPC8315 select BOARD_EARLY_INIT_F
config TARGET_MPC8323ERDB @@ -65,6 +68,7 @@ config TARGET_MPC837XERDB
config TARGET_IDS8313 bool "Support ids8313" + select ARCH_MPC8313 select DM imply CMD_DM
@@ -113,6 +117,17 @@ config ARCH_MPC8309 bool select ARCH_MPC830X
+config ARCH_MPC831X + bool + +config ARCH_MPC8313 + bool + select ARCH_MPC831X + +config ARCH_MPC8315 + bool + select ARCH_MPC831X + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index b29f271e9bc..8a88068fdba 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -18,7 +18,7 @@ #include <tsec.h> #include <netdev.h> #include <fsl_esdhc.h> -#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x) +#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X) #include <linux/immap_qe.h> #include <asm/io.h> #endif diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 1555205e069..7d8d5516b4c 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -240,7 +240,7 @@ void cpu_init_f (volatile immap_t * im)
/* System General Purpose Register */ #ifdef CONFIG_SYS_SICRH -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313) +#if defined(CONFIG_MPC834x) || defined(CONFIG_ARCH_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, &im->sysconf.sicrh); @@ -312,7 +312,7 @@ void cpu_init_f (volatile immap_t * im) im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR; #endif -#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x) +#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X) uint32_t temp; struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index 0ecafd708fc..cfd391b78ab 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -16,7 +16,7 @@ extern void ft_qe_setup(void *blob); DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \ - (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) + (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X)) #include <linux/immap_qe.h>
void fdt_fixup_muram (void *blob) @@ -52,7 +52,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\ defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) -#ifdef CONFIG_MPC8313 +#ifdef CONFIG_ARCH_MPC8313 /* * mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1 * h/w (see AN3545). The base device tree in use has rev. 1 ID numbers, @@ -123,7 +123,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \ - (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) + (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X)) fdt_fixup_muram (blob); #endif } diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 97ef77121b5..3f18aadf19b 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -31,7 +31,7 @@ void board_add_ram_info(int use_default) printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) puts(", 16-bit"); else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index d537af5130a..9f09d2955f8 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -85,7 +85,7 @@ int get_clocks(void) u32 lcrr;
u32 csb_clk; -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; @@ -101,7 +101,7 @@ int get_clocks(void) #if !defined(CONFIG_MPC832x) u32 i2c2_clk; #endif -#if defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) u32 tdm_clk; #endif #if defined(CONFIG_FSL_ESDHC) @@ -122,12 +122,12 @@ int get_clocks(void) u32 qe_clk; u32 brg_clk; #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) u32 pciexp1_clk; u32 pciexp2_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; #endif
@@ -155,7 +155,7 @@ int get_clocks(void)
sccr = im->clk.sccr;
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: @@ -176,7 +176,7 @@ int get_clocks(void) } #endif
-#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: @@ -197,7 +197,7 @@ int get_clocks(void) } #endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: @@ -216,7 +216,7 @@ int get_clocks(void) /* unknown SCCR_TSEC2CM value */ return -4; } -#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) tsec2_clk = tsec1_clk;
if (!(sccr & SCCR_TSEC1ON)) @@ -291,7 +291,7 @@ int get_clocks(void) return -8; } #endif -#if defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) { case 0: tdm_clk = 0; @@ -317,7 +317,7 @@ int get_clocks(void) i2c1_clk = csb_clk; #elif defined(CONFIG_MPC832x) i2c1_clk = enc_clk; -#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; @@ -330,7 +330,7 @@ int get_clocks(void) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ #endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: @@ -369,7 +369,7 @@ int get_clocks(void) } #endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { case 0: sata_clk = 0; @@ -448,7 +448,7 @@ int get_clocks(void) #endif
gd->arch.csb_clk = csb_clk; -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; @@ -459,7 +459,7 @@ int get_clocks(void) #if defined(CONFIG_MPC834x) gd->arch.usbmph_clk = usbmph_clk; #endif -#if defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) gd->arch.tdm_clk = tdm_clk; #endif #if defined(CONFIG_FSL_ESDHC) @@ -483,12 +483,12 @@ int get_clocks(void) gd->arch.qe_clk = qe_clk; gd->arch.brg_clk = brg_clk; #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) gd->arch.pciexp1_clk = pciexp1_clk; gd->arch.pciexp2_clk = pciexp2_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) gd->arch.sata_clk = sata_clk; #endif gd->pci_clk = pci_sync_in; @@ -550,7 +550,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->arch.i2c2_clk)); #endif -#if defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) printf(" TDM: %-4s MHz\n", strmhz(buf, gd->arch.tdm_clk)); #endif @@ -558,7 +558,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->arch.sdhc_clk)); #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->arch.tsec1_clk)); @@ -574,14 +574,14 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->arch.usbmph_clk)); #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->arch.pciexp1_clk)); printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->arch.pciexp2_clk)); #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) printf(" SATA: %-4s MHz\n", strmhz(buf, gd->arch.sata_clk)); #endif diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 4e5a352ac67..74ba91a4695 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -6,8 +6,8 @@ /* * The MCP83xx's 1-2 GPIO controllers each with 32 bits. */ -#if defined(CONFIG_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ - defined(CONFIG_MPC8315) +#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ + defined(CONFIG_ARCH_MPC8315) #define MPC83XX_GPIO_CTRLRS 1 #elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) #define MPC83XX_GPIO_CTRLRS 2 diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 700e2be0ee2..0c3a4ade5c3 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -35,7 +35,7 @@ struct arch_global_data { #else /* There are other clocks in the MPC83XX */ u32 csb_clk; -# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; @@ -46,19 +46,19 @@ struct arch_global_data { # if defined(CONFIG_MPC834x) u32 usbmph_clk; # endif /* CONFIG_MPC834x */ -# if defined(CONFIG_MPC8315) +# if defined(CONFIG_ARCH_MPC8315) u32 tdm_clk; # endif u32 core_clk; u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; -# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) u32 pciexp1_clk; u32 pciexp2_clk; # endif -# if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +# if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; # endif # if defined(CONFIG_MPC8360) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index b10feb546c6..d22d887babd 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -679,7 +679,7 @@ typedef struct immap { #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 #endif
-#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ @@ -714,7 +714,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t;
-#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 518d0c388a7..3edd5610072 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -11,8 +11,8 @@ #include <asm/types.h>
#if defined(CONFIG_ARCH_MPC8308) || \ - defined(CONFIG_MPC8313) || \ - defined(CONFIG_MPC8315) || \ + defined(CONFIG_ARCH_MPC8313) || \ + defined(CONFIG_ARCH_MPC8315) || \ defined(CONFIG_MPC834x) || \ defined(CONFIG_MPC837x)
diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index e3523299812..58db7948c15 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -180,7 +180,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_RD_ONLY_CURRENT: case ODT_RD_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && - !IS_ENABLED(CONFIG_MPC831x) && + !IS_ENABLED(CONFIG_ARCH_MPC831X) && !IS_ENABLED(CONFIG_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_rd_cfg value %d invalid.\n", @@ -211,7 +211,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_WR_ONLY_CURRENT: case ODT_WR_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && - !IS_ENABLED(CONFIG_MPC831x) && + !IS_ENABLED(CONFIG_ARCH_MPC831X) && !IS_ENABLED(CONFIG_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_wr_cfg value %d invalid.\n", diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index cfa5b565248..c5a8065d6a4 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -13,8 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC831x 1 -#define CONFIG_MPC8313 1 #define CONFIG_MPC8313ERDB 1
#ifdef CONFIG_NAND diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 0ccf4acb827..b8506321af3 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -22,8 +22,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC831x 1 /* MPC831x CPU family */ -#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
/* diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 7e4c497fe0a..caa3dd1f1a6 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -14,9 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC831x -#define CONFIG_MPC8313 - #define CONFIG_FSL_ELBC
#define CONFIG_BOOT_RETRY_TIME 900 diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 85f678e5c4a..791eac363bd 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -16,8 +16,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC831x 1 -#define CONFIG_MPC8313 1
#define CONFIG_PCI_INDIRECT_BRIDGE 1 #define CONFIG_FSL_ELBC 1 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index e93f50d0b33..0da271b2f36 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -129,7 +129,7 @@ #define SPCR_TSEC2EP 0x00000003 #define SPCR_TSEC2EP_SHIFT (31-31)
-#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) /* SPCR bits - MPC8308, MPC831x and MPC837x specific */ /* TSEC data priority */ @@ -216,7 +216,7 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000
-#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) /* SICRL bits - MPC8313 specific */ #define SICRL_LBC 0x30000000 #define SICRL_UART 0x0C000000 @@ -248,7 +248,7 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8315) /* SICRL bits - MPC8315 specific */ #define SICRL_DMA_CH0 0xc0000000 #define SICRL_DMA_SPI 0x30000000 @@ -639,7 +639,7 @@ #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F
-#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_2 0x00000000 @@ -765,7 +765,7 @@ #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 @@ -818,7 +818,7 @@ /* * RSR - Reset Status Register */ -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \ +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ defined(CONFIG_MPC837x) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 @@ -965,7 +965,7 @@ #define SCCR_USBCM_2 0x00A00000 #define SCCR_USBCM_3 0x00F00000
-#elif defined(CONFIG_MPC8313) +#elif defined(CONFIG_ARCH_MPC8313) /* TSEC1 bits are for TSEC2 as well */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -986,7 +986,7 @@ #define SCCR_USBDRCM_2 0x00200000 #define SCCR_USBDRCM_3 0x00300000
-#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) /* SCCR bits - MPC8315/MPC8308 specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -1117,7 +1117,7 @@ */ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 -#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 @@ -1239,7 +1239,7 @@ #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) #define SDRAM_CFG_DBW_MASK 0x00180000 #define SDRAM_CFG_DBW_16 0x00100000 #define SDRAM_CFG_DBW_32 0x00080000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2c2ced8e475..c3227a4efa8 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1248,11 +1248,8 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC8313 CONFIG_MPC8313ERDB -CONFIG_MPC8315 CONFIG_MPC8315ERDB -CONFIG_MPC831x CONFIG_MPC832XEMDS CONFIG_MPC832x CONFIG_MPC8349
Replace CONFIG_MPC832* with proper CONFIG_ARCH_MPC832* Kconfig options.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- arch/powerpc/cpu/mpc83xx/Kconfig | 7 +++++++ arch/powerpc/cpu/mpc83xx/speed.c | 10 +++++----- arch/powerpc/include/asm/immap_83xx.h | 2 +- include/configs/MPC8323ERDB.h | 1 - include/configs/MPC832XEMDS.h | 1 - include/configs/km/km8321-common.h | 1 - include/linux/immap_qe.h | 2 +- include/mpc83xx.h | 6 +++--- scripts/config_whitelist.txt | 1 - 9 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 20780ba68bd..1b9402e024b 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -40,9 +40,11 @@ config TARGET_MPC8315ERDB
config TARGET_MPC8323ERDB bool "Support MPC8323ERDB" + select ARCH_MPC832X
config TARGET_MPC832XEMDS bool "Support MPC832XEMDS" + select ARCH_MPC832X select BOARD_EARLY_INIT_F
config TARGET_MPC8349EMDS @@ -82,11 +84,13 @@ config TARGET_SUVD3 bool "Support suvd3" select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMTEGR1" select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMVECT1" + select ARCH_MPC832X if SYS_EXTRA_OPTIONS="SUVD3" imply CMD_CRAMFS imply FS_CRAMFS
config TARGET_TUXX1 bool "Support tuxx1" + select ARCH_MPC832X imply CMD_CRAMFS imply FS_CRAMFS
@@ -128,6 +132,9 @@ config ARCH_MPC8315 bool select ARCH_MPC831X
+config ARCH_MPC832X + bool + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 9f09d2955f8..ab025af70d4 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -98,7 +98,7 @@ int get_clocks(void) #endif u32 core_clk; u32 i2c1_clk; -#if !defined(CONFIG_MPC832x) +#if !defined(CONFIG_ARCH_MPC832X) u32 i2c2_clk; #endif #if defined(CONFIG_ARCH_MPC8315) @@ -315,7 +315,7 @@ int get_clocks(void) i2c1_clk = tsec2_clk; #elif defined(CONFIG_MPC8360) i2c1_clk = csb_clk; -#elif defined(CONFIG_MPC832x) +#elif defined(CONFIG_ARCH_MPC832X) i2c1_clk = enc_clk; #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) i2c1_clk = enc_clk; @@ -326,7 +326,7 @@ int get_clocks(void) #elif defined(CONFIG_ARCH_MPC8309) i2c1_clk = csb_clk; #endif -#if !defined(CONFIG_MPC832x) +#if !defined(CONFIG_ARCH_MPC832X) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ #endif
@@ -467,7 +467,7 @@ int get_clocks(void) #endif gd->arch.core_clk = core_clk; gd->arch.i2c1_clk = i2c1_clk; -#if !defined(CONFIG_MPC832x) +#if !defined(CONFIG_ARCH_MPC832X) gd->arch.i2c2_clk = i2c2_clk; #endif #if !defined(CONFIG_ARCH_MPC8309) @@ -546,7 +546,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->arch.i2c1_clk)); -#if !defined(CONFIG_MPC832x) +#if !defined(CONFIG_ARCH_MPC832X) printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->arch.i2c2_clk)); #endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index d22d887babd..318b79d0b8a 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -843,7 +843,7 @@ typedef struct immap { u8 qe[0x100000]; /* QE block */ } immap_t;
-#elif defined(CONFIG_MPC832x) +#elif defined(CONFIG_ARCH_MPC832X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 578202f3be3..bd1b1bb0a7c 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -14,7 +14,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
/* * System Clock Setup diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 8f11d9b3a48..0bb7db9bc37 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -11,7 +11,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC832x 1 /* MPC832x CPU specific */ #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
/* diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h index 41b3ba28429..a121a445f78 100644 --- a/include/configs/km/km8321-common.h +++ b/include/configs/km/km8321-common.h @@ -26,7 +26,6 @@ * High Level Configuration Options */ #define CONFIG_QE /* Has QE */ -#define CONFIG_MPC832x /* MPC832x CPU specific */ #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index f7bc503ea33..6552d0e3c5c 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -16,7 +16,7 @@ #define QE_MURAM_SIZE 0xc000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 -#elif defined(CONFIG_MPC832x) || defined(CONFIG_ARCH_MPC8309) +#elif defined(CONFIG_ARCH_MPC832X) || defined(CONFIG_ARCH_MPC8309) #define QE_MURAM_SIZE 0x4000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 0da271b2f36..0f4466ae896 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -208,7 +208,7 @@ #define SICRH_UC2E1OBI 0x00000002 #define SICRH_UC2E2OBI 0x00000001
-#elif defined(CONFIG_MPC832x) +#elif defined(CONFIG_ARCH_MPC832X) /* SICRL bits - MPC832x specific */ #define SICRL_LDP_LCS_A 0x80000000 #define SICRL_IRQ_CKS 0x20000000 @@ -593,7 +593,7 @@ #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 #define HRCWL_CORE_TO_CSB_3X1 0x00060000
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) +#if defined(CONFIG_MPC8360) || defined(CONFIG_ARCH_MPC832X) #define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 @@ -1126,7 +1126,7 @@ #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000 #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000 #define CSCONFIG_ODT_WR_ALL 0x00040000 -#elif defined(CONFIG_MPC832x) +#elif defined(CONFIG_ARCH_MPC832X) #define CSCONFIG_ODT_RD_CFG 0x00400000 #define CSCONFIG_ODT_WR_CFG 0x00040000 #elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c3227a4efa8..2ebb293e437 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1251,7 +1251,6 @@ CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB CONFIG_MPC832XEMDS -CONFIG_MPC832x CONFIG_MPC8349 CONFIG_MPC8349ITX CONFIG_MPC834x
Replace CONFIG_MPC834* with proper CONFIG_ARCH_MPC834* Kconfig options.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Removed config option from whitelist
--- arch/powerpc/cpu/mpc83xx/Kconfig | 12 +++++++++++ arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- arch/powerpc/cpu/mpc83xx/speed.c | 22 ++++++++++---------- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 2 +- arch/powerpc/include/asm/fsl_lbc.h | 8 +++---- arch/powerpc/include/asm/global_data.h | 6 +++--- arch/powerpc/include/asm/immap_83xx.h | 6 +++--- arch/powerpc/include/asm/mpc8xxx_spi.h | 2 +- drivers/pci/pci_auto.c | 2 +- drivers/pci/pci_auto_old.c | 2 +- include/configs/MPC8349EMDS.h | 2 -- include/configs/MPC8349ITX.h | 3 --- include/configs/TQM834x.h | 2 -- include/configs/sbc8349.h | 2 -- include/configs/vme8349.h | 2 -- include/mpc83xx.h | 18 ++++++++-------- include/usb/ehci-ci.h | 2 +- scripts/config_whitelist.txt | 2 -- 19 files changed, 49 insertions(+), 50 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 1b9402e024b..6cca45e4026 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -14,6 +14,7 @@ config TARGET_MPC8308_P1M
config TARGET_SBC8349 bool "Support sbc8349" + select ARCH_MPC8349
config TARGET_VE8313 bool "Support ve8313" @@ -21,6 +22,7 @@ config TARGET_VE8313
config TARGET_VME8349 bool "Support vme8349" + select ARCH_MPC8349
config TARGET_MPC8308RDB bool "Support MPC8308RDB" @@ -49,6 +51,7 @@ config TARGET_MPC832XEMDS
config TARGET_MPC8349EMDS bool "Support MPC8349EMDS" + select ARCH_MPC8349 select BOARD_EARLY_INIT_F select SYS_FSL_DDR select SYS_FSL_DDR_BE @@ -56,6 +59,7 @@ config TARGET_MPC8349EMDS
config TARGET_MPC8349ITX bool "Support MPC8349ITX" + select ARCH_MPC8349 imply CMD_IRQ
config TARGET_MPC837XEMDS @@ -96,6 +100,7 @@ config TARGET_TUXX1
config TARGET_TQM834X bool "Support TQM834x" + select ARCH_MPC8349
config TARGET_HRCON bool "Support hrcon" @@ -135,6 +140,13 @@ config ARCH_MPC8315 config ARCH_MPC832X bool
+config ARCH_MPC834X + bool + +config ARCH_MPC8349 + bool + select ARCH_MPC834X + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 7d8d5516b4c..7c378671feb 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -240,7 +240,7 @@ void cpu_init_f (volatile immap_t * im)
/* System General Purpose Register */ #ifdef CONFIG_SYS_SICRH -#if defined(CONFIG_MPC834x) || defined(CONFIG_ARCH_MPC8313) +#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, &im->sysconf.sicrh); diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 3f18aadf19b..b3cbf9f8823 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -426,7 +426,7 @@ long int spd_sdram()
/* * Errata DDR6 work around: input enable 2 cycles earlier. - * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2. + * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2. */ if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){ if (caslat == 2) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index ab025af70d4..7cb6f3727df 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -86,14 +86,14 @@ int get_clocks(void)
u32 csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; #elif defined(CONFIG_ARCH_MPC8309) u32 usbdr_clk; #endif -#ifdef CONFIG_MPC834x +#ifdef CONFIG_ARCH_MPC834X u32 usbmph_clk; #endif u32 core_clk; @@ -156,7 +156,7 @@ int get_clocks(void) sccr = im->clk.sccr;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -177,7 +177,7 @@ int get_clocks(void) #endif
#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: usbdr_clk = 0; @@ -198,7 +198,7 @@ int get_clocks(void) #endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: tsec2_clk = 0; @@ -225,7 +225,7 @@ int get_clocks(void) tsec2_clk = 0; #endif
-#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { case 0: usbmph_clk = 0; @@ -311,7 +311,7 @@ int get_clocks(void) } #endif
-#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) i2c1_clk = tsec2_clk; #elif defined(CONFIG_MPC8360) i2c1_clk = csb_clk; @@ -449,14 +449,14 @@ int get_clocks(void)
gd->arch.csb_clk = csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; gd->arch.usbdr_clk = usbdr_clk; #elif defined(CONFIG_ARCH_MPC8309) gd->arch.usbdr_clk = usbdr_clk; #endif -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) gd->arch.usbmph_clk = usbmph_clk; #endif #if defined(CONFIG_ARCH_MPC8315) @@ -559,7 +559,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.sdhc_clk)); #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->arch.tsec1_clk)); printf(" TSEC2: %-4s MHz\n", @@ -570,7 +570,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->arch.usbdr_clk)); #endif -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->arch.usbmph_clk)); #endif diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 74ba91a4695..16997316ff0 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -9,7 +9,7 @@ #if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8315) #define MPC83XX_GPIO_CTRLRS 1 -#elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) #define MPC83XX_GPIO_CTRLRS 2 #else #define MPC83XX_GPIO_CTRLRS 0 diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index cf89e186a67..0ea44560332 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -43,10 +43,10 @@ void lbc_sdram_init(void); #define BR_MSEL 0x000000E0 #define BR_MSEL_SHIFT 5 #define BR_MS_GPCM 0x00000000 /* GPCM */ -#if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360) +#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_MPC8360) #define BR_MS_FCM 0x00000020 /* FCM */ #endif -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC8360) #define BR_MS_SDRAM 0x00000060 /* SDRAM */ #elif defined(CONFIG_MPC85xx) #define BR_MS_SDRAM 0x00000000 /* SDRAM */ @@ -54,7 +54,7 @@ void lbc_sdram_init(void); #define BR_MS_UPMA 0x00000080 /* UPMA */ #define BR_MS_UPMB 0x000000A0 /* UPMB */ #define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if !defined(CONFIG_MPC834x) +#if !defined(CONFIG_ARCH_MPC834X) #define BR_ATOM 0x0000000C #define BR_ATOM_SHIFT 2 #endif @@ -67,7 +67,7 @@ void lbc_sdram_init(void); #define UPMB 1 #define UPMC 2
-#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) #else #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 0c3a4ade5c3..cd0d76696d2 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -36,16 +36,16 @@ struct arch_global_data { /* There are other clocks in the MPC83XX */ u32 csb_clk; # if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; # elif defined(CONFIG_ARCH_MPC8309) u32 usbdr_clk; # endif -# if defined(CONFIG_MPC834x) +# if defined(CONFIG_ARCH_MPC834X) u32 usbmph_clk; -# endif /* CONFIG_MPC834x */ +# endif /* CONFIG_ARCH_MPC834X */ # if defined(CONFIG_ARCH_MPC8315) u32 tdm_clk; # endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 318b79d0b8a..bf7a4b9250c 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -625,7 +625,7 @@ typedef struct tdmdmac83xx { u8 fixme[0x2000]; } tdmdmac83xx_t;
-#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ @@ -666,7 +666,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t;
-#ifndef CONFIG_MPC834x +#ifndef CONFIG_ARCH_MPC834X #ifdef CONFIG_HAS_FSL_MPH_USB #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 @@ -946,7 +946,7 @@ typedef struct immap { #endif #define CONFIG_SYS_MPC83xx_USB1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET) -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define CONFIG_SYS_MPC83xx_USB2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET) #endif diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 3edd5610072..0c2bdb326b2 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -13,7 +13,7 @@ #if defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8313) || \ defined(CONFIG_ARCH_MPC8315) || \ - defined(CONFIG_MPC834x) || \ + defined(CONFIG_ARCH_MPC834X) || \ defined(CONFIG_MPC837x)
typedef struct spi8xxx { diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index d7237f6eee0..a673d8ae136 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -359,7 +359,7 @@ int dm_pciauto_config_device(struct udevice *dev) PCI_DEV(dm_pci_get_bdf(dev))); break; #endif -#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_VME8349) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c index e705a3072e7..90c22a08cbc 100644 --- a/drivers/pci/pci_auto_old.c +++ b/drivers/pci/pci_auto_old.c @@ -376,7 +376,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) PCI_DEV(dev)); break; #endif -#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_VME8349) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index bda477cc160..93de2cc1c07 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -16,8 +16,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_PCI_66M #ifdef CONFIG_PCI_66M diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 111023b7bee..496780d80c0 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -46,9 +46,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ -#define CONFIG_MPC8349 /* MPC8349 specific */ - #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
#define CONFIG_MISC_INIT_F diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 0942b872ac3..2b82bd82eb7 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -15,8 +15,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x specific */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */
/* IMMR Base Address Register, use Freescale default: 0xff400000 */ #define CONFIG_SYS_IMMR 0xff400000 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 9074be80f11..6ae11185cb7 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -18,8 +18,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */
/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 805f7d3df66..56955501309 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -28,8 +28,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_VME8349 1 /* ESD VME8349 board specific */
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 0f4466ae896..feb8fef6018 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -55,7 +55,7 @@ #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ #define SPRIDR_REVID 0x0000FFFF /* Revision Id */
-#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) #define REVID_MINOR(spridr) (spridr & 0x000000FF) #else @@ -108,7 +108,7 @@ #define SPCR_COREPR 0x00300000 #define SPCR_COREPR_SHIFT (31-11)
-#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) /* SPCR bits - MPC8349 specific */ /* TSEC1 data priority */ #define SPCR_TSEC1DP 0x00003000 @@ -145,7 +145,7 @@
/* SICRL/H - System I/O Configuration Register Low/High */ -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) /* SICRL bits - MPC8349 specific */ #define SICRL_LDP_A 0x80000000 #define SICRL_USB1 0x40000000 @@ -720,7 +720,7 @@ #define HRCWH_PCI_HOST_SHIFT 31 #define HRCWH_PCI_AGENT 0x00000000
-#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define HRCWH_32_BIT_PCI 0x00000000 #define HRCWH_64_BIT_PCI 0x40000000 #endif @@ -731,7 +731,7 @@ #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000
-#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
@@ -755,7 +755,7 @@
#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 #define HRCWH_ROM_LOC_PCI1 0x00100000 -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif #if defined(CONFIG_MPC837x) @@ -790,7 +790,7 @@ #define HRCWH_TSEC2M_IN_SGMII 0x00001800 #endif
-#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define HRCWH_TSEC1M_IN_RGMII 0x00000000 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 #define HRCWH_TSEC1M_IN_GMII 0x00008000 @@ -937,8 +937,8 @@ #define SCCR_PCICM 0x00010000 #define SCCR_PCICM_SHIFT 16
-#if defined(CONFIG_MPC834x) -/* SCCR bits - MPC834x specific */ +#if defined(CONFIG_ARCH_MPC834X) +/* SCCR bits - MPC834X specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC1CM_0 0x00000000 diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index e4579a5bec8..efb2eec5ce7 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -147,7 +147,7 @@
#if defined(CONFIG_MPC83xx) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR -#if defined(CONFIG_MPC834x) +#if defined(CONFIG_ARCH_MPC834X) #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR #else #define CONFIG_SYS_FSL_USB2_ADDR 0 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2ebb293e437..aa98c4c8e17 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1251,9 +1251,7 @@ CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB CONFIG_MPC832XEMDS -CONFIG_MPC8349 CONFIG_MPC8349ITX -CONFIG_MPC834x CONFIG_MPC8360 CONFIG_MPC837XEMDS CONFIG_MPC837XERDB
Replace CONFIG_MPC836* with proper CONFIG_ARCH_MPC836* Kconfig options.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Removed config option from whitelist
--- arch/powerpc/cpu/mpc83xx/Kconfig | 4 ++++ arch/powerpc/cpu/mpc83xx/speed.c | 10 +++++----- arch/powerpc/include/asm/fsl_lbc.h | 4 ++-- arch/powerpc/include/asm/global_data.h | 4 ++-- arch/powerpc/include/asm/immap_83xx.h | 2 +- board/keymile/km83xx/km83xx.c | 4 ++-- drivers/ram/mpc83xx_sdram.c | 8 ++++---- include/configs/km8360.h | 1 - include/linux/immap_qe.h | 2 +- include/mpc83xx.h | 10 +++++----- include/post.h | 2 +- scripts/config_whitelist.txt | 1 - 12 files changed, 27 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 6cca45e4026..5f9d036e371 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -80,6 +80,7 @@ config TARGET_IDS8313
config TARGET_KM8360 bool "Support km8360" + select ARCH_MPC8360 imply CMD_CRAMFS imply CMD_DIAG imply FS_CRAMFS @@ -147,6 +148,9 @@ config ARCH_MPC8349 bool select ARCH_MPC834X
+config ARCH_MPC8360 + bool + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 7cb6f3727df..ed77675a8ea 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -113,7 +113,7 @@ int get_clocks(void) u32 lbiu_clk; u32 lclk_clk; u32 mem_clk; -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) u32 mem_sec_clk; #endif #if defined(CONFIG_QE) @@ -313,7 +313,7 @@ int get_clocks(void)
#if defined(CONFIG_ARCH_MPC834X) i2c1_clk = tsec2_clk; -#elif defined(CONFIG_MPC8360) +#elif defined(CONFIG_ARCH_MPC8360) i2c1_clk = csb_clk; #elif defined(CONFIG_ARCH_MPC832X) i2c1_clk = enc_clk; @@ -407,7 +407,7 @@ int get_clocks(void) (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT)); corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
-#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) mem_sec_clk = csb_clk * (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT)); #endif @@ -476,7 +476,7 @@ int get_clocks(void) gd->arch.lbiu_clk = lbiu_clk; gd->arch.lclk_clk = lclk_clk; gd->mem_clk = mem_clk; -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) gd->arch.mem_sec_clk = mem_sec_clk; #endif #if defined(CONFIG_QE) @@ -536,7 +536,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->arch.lclk_clk)); printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk)); -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->arch.mem_sec_clk)); #endif diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 0ea44560332..3528acd627d 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -43,10 +43,10 @@ void lbc_sdram_init(void); #define BR_MSEL 0x000000E0 #define BR_MSEL_SHIFT 5 #define BR_MS_GPCM 0x00000000 /* GPCM */ -#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_MPC8360) +#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360) #define BR_MS_FCM 0x00000020 /* FCM */ #endif -#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360) #define BR_MS_SDRAM 0x00000060 /* SDRAM */ #elif defined(CONFIG_MPC85xx) #define BR_MS_SDRAM 0x00000000 /* SDRAM */ diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index cd0d76696d2..cf3ba588220 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -61,9 +61,9 @@ struct arch_global_data { # if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; # endif -# if defined(CONFIG_MPC8360) +# if defined(CONFIG_ARCH_MPC8360) u32 mem_sec_clk; -# endif /* CONFIG_MPC8360 */ +# endif /* CONFIG_ARCH_MPC8360 */ #endif #endif #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index bf7a4b9250c..f6721e7b1d5 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -803,7 +803,7 @@ typedef struct immap { rom83xx_t rom; /* On Chip ROM */ } immap_t;
-#elif defined(CONFIG_MPC8360) +#elif defined(CONFIG_ARCH_MPC8360) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index ce5126aae6b..12044ee0d70 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -33,7 +33,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
const qe_iop_conf_t qe_iop_conf_tab[] = { /* port pin dir open_drain assign */ -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) /* MDIO */ {0, 1, 3, 0, 2}, /* MDIO */ {0, 2, 1, 0, 1}, /* MDC */ @@ -148,7 +148,7 @@ int board_early_init_r(void) u32 *mxmr = &lbc->mamr; #endif
-#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) unsigned short svid; /* * Because of errata in the UCCs, we have to write to the reserved diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index 58db7948c15..3e57b13118c 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -169,7 +169,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0); switch (odt_rd_cfg) { case ODT_RD_ONLY_OTHER_DIMM: - if (!IS_ENABLED(CONFIG_MPC8360) && + if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); @@ -181,7 +181,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_RD_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && - !IS_ENABLED(CONFIG_MPC8360) && + !IS_ENABLED(CONFIG_ARCH_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); @@ -200,7 +200,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0); switch (odt_wr_cfg) { case ODT_WR_ONLY_OTHER_DIMM: - if (!IS_ENABLED(CONFIG_MPC8360) && + if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); @@ -212,7 +212,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_WR_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && - !IS_ENABLED(CONFIG_MPC8360) && + !IS_ENABLED(CONFIG_ARCH_MPC8360) && !IS_ENABLED(CONFIG_MPC837x)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); diff --git a/include/configs/km8360.h b/include/configs/km8360.h index 41ee2aecd5a..7e2876ee088 100644 --- a/include/configs/km8360.h +++ b/include/configs/km8360.h @@ -36,7 +36,6 @@ * High Level Configuration Options */ #define CONFIG_QE /* Has QE */ -#define CONFIG_MPC8360 /* MPC8360 CPU specific */
/* include common defines/options for all 83xx Keymile boards */ #include "km/km83xx-common.h" diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index 6552d0e3c5c..022771fff5d 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -12,7 +12,7 @@ #define __IMMAP_QE_H__
#ifdef CONFIG_MPC83xx -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) #define QE_MURAM_SIZE 0xc000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index feb8fef6018..94b2816a821 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -191,7 +191,7 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_MPC8360) +#elif defined(CONFIG_ARCH_MPC8360) /* SICRL bits - MPC8360 specific */ #define SICRL_LDP_A 0xC0000000 #define SICRL_LCLK_1 0x10000000 @@ -593,7 +593,7 @@ #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 #define HRCWL_CORE_TO_CSB_3X1 0x00060000
-#if defined(CONFIG_MPC8360) || defined(CONFIG_ARCH_MPC832X) +#if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X) #define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 @@ -735,7 +735,7 @@ #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
-#elif defined(CONFIG_MPC8360) +#elif defined(CONFIG_ARCH_MPC8360) #define HRCWH_PCICKDRV_DISABLE 0x00000000 #define HRCWH_PCICKDRV_ENABLE 0x10000000 #endif @@ -801,7 +801,7 @@ #define HRCWH_TSEC2M_IN_TBI 0x00003000 #endif
-#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 #endif @@ -1129,7 +1129,7 @@ #elif defined(CONFIG_ARCH_MPC832X) #define CSCONFIG_ODT_RD_CFG 0x00400000 #define CSCONFIG_ODT_WR_CFG 0x00040000 -#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_MPC837x) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 diff --git a/include/post.h b/include/post.h index 08a771e4055..eb218acde5f 100644 --- a/include/post.h +++ b/include/post.h @@ -21,7 +21,7 @@ #define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR #else
-#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) #include <linux/immap_qe.h> #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index aa98c4c8e17..a4a45c7bcdc 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1252,7 +1252,6 @@ CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB CONFIG_MPC832XEMDS CONFIG_MPC8349ITX -CONFIG_MPC8360 CONFIG_MPC837XEMDS CONFIG_MPC837XERDB CONFIG_MPC837x
Replace CONFIG_MPC837x with a proper CONFIG_ARCH_MPC837X Kconfig option.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- arch/powerpc/cpu/mpc83xx/Kconfig | 5 ++++ arch/powerpc/cpu/mpc83xx/speed.c | 30 ++++++++++---------- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 2 +- arch/powerpc/include/asm/global_data.h | 6 ++-- arch/powerpc/include/asm/immap_83xx.h | 2 +- arch/powerpc/include/asm/mpc8xxx_spi.h | 2 +- drivers/ram/mpc83xx_sdram.c | 8 +++--- include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/mpc83xx.h | 24 ++++++++-------- scripts/config_whitelist.txt | 1 - 11 files changed, 42 insertions(+), 40 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 5f9d036e371..e41f4d1f9a3 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -64,12 +64,14 @@ config TARGET_MPC8349ITX
config TARGET_MPC837XEMDS bool "Support MPC837XEMDS" + select ARCH_MPC837X select BOARD_EARLY_INIT_F imply CMD_SATA imply FSL_SATA
config TARGET_MPC837XERDB bool "Support MPC837XERDB" + select ARCH_MPC837X select BOARD_EARLY_INIT_F
config TARGET_IDS8313 @@ -151,6 +153,9 @@ config ARCH_MPC8349 config ARCH_MPC8360 bool
+config ARCH_MPC837X + bool + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index ed77675a8ea..668ed27862b 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -86,7 +86,7 @@ int get_clocks(void)
u32 csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; @@ -123,11 +123,11 @@ int get_clocks(void) u32 brg_clk; #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) u32 pciexp1_clk; u32 pciexp2_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; #endif
@@ -156,7 +156,7 @@ int get_clocks(void) sccr = im->clk.sccr;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -177,7 +177,7 @@ int get_clocks(void) #endif
#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: usbdr_clk = 0; @@ -198,7 +198,7 @@ int get_clocks(void) #endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: tsec2_clk = 0; @@ -321,7 +321,7 @@ int get_clocks(void) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; -#elif defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC837X) i2c1_clk = enc_clk; #elif defined(CONFIG_ARCH_MPC8309) i2c1_clk = csb_clk; @@ -331,7 +331,7 @@ int get_clocks(void) #endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: pciexp1_clk = 0; @@ -369,7 +369,7 @@ int get_clocks(void) } #endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { case 0: sata_clk = 0; @@ -449,7 +449,7 @@ int get_clocks(void)
gd->arch.csb_clk = csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; gd->arch.usbdr_clk = usbdr_clk; @@ -484,11 +484,11 @@ int get_clocks(void) gd->arch.brg_clk = brg_clk; #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) gd->arch.pciexp1_clk = pciexp1_clk; gd->arch.pciexp2_clk = pciexp2_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) gd->arch.sata_clk = sata_clk; #endif gd->pci_clk = pci_sync_in; @@ -559,7 +559,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.sdhc_clk)); #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->arch.tsec1_clk)); printf(" TSEC2: %-4s MHz\n", @@ -575,13 +575,13 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.usbmph_clk)); #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->arch.pciexp1_clk)); printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->arch.pciexp2_clk)); #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) printf(" SATA: %-4s MHz\n", strmhz(buf, gd->arch.sata_clk)); #endif diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 16997316ff0..b5ec50ba44c 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -9,7 +9,7 @@ #if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8315) #define MPC83XX_GPIO_CTRLRS 1 -#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) #define MPC83XX_GPIO_CTRLRS 2 #else #define MPC83XX_GPIO_CTRLRS 0 diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index cf3ba588220..b6e4dd6c807 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -36,7 +36,7 @@ struct arch_global_data { /* There are other clocks in the MPC83XX */ u32 csb_clk; # if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; @@ -54,11 +54,11 @@ struct arch_global_data { u32 lbiu_clk; u32 lclk_clk; # if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) u32 pciexp1_clk; u32 pciexp2_clk; # endif -# if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315) +# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) u32 sata_clk; # endif # if defined(CONFIG_ARCH_MPC8360) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index f6721e7b1d5..30bbd5671ba 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -759,7 +759,7 @@ typedef struct immap { u8 res12[0x1CF00]; } immap_t;
-#elif defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC837X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 0c2bdb326b2..b583a3269d6 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -14,7 +14,7 @@ defined(CONFIG_ARCH_MPC8313) || \ defined(CONFIG_ARCH_MPC8315) || \ defined(CONFIG_ARCH_MPC834X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X)
typedef struct spi8xxx { u8 res0[0x20]; /* 0x0-0x01f reserved */ diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index 3e57b13118c..f03d0428b2a 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -170,7 +170,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) switch (odt_rd_cfg) { case ODT_RD_ONLY_OTHER_DIMM: if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_MPC837x)) { + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); return -EINVAL; @@ -182,7 +182,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && !IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_MPC837x)) { + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); return -EINVAL; @@ -201,7 +201,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) switch (odt_wr_cfg) { case ODT_WR_ONLY_OTHER_DIMM: if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_MPC837x)) { + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); return -EINVAL; @@ -213,7 +213,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && !IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_MPC837x)) { + !IS_ENABLED(CONFIG_ARCH_MPC837X)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); return -EINVAL; diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 50f6df5844b..82dcb859736 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -11,7 +11,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
/* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 4ddd62ddbbc..6029d0f21bf 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -12,7 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XERDB 1
#define CONFIG_HWCONFIG diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 94b2816a821..c2a185321ab 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -130,8 +130,8 @@ #define SPCR_TSEC2EP_SHIFT (31-31)
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) -/* SPCR bits - MPC8308, MPC831x and MPC837x specific */ + defined(CONFIG_ARCH_MPC837X) +/* SPCR bits - MPC8308, MPC831x and MPC837X specific */ /* TSEC data priority */ #define SPCR_TSECDP 0x00003000 #define SPCR_TSECDP_SHIFT (31-19) @@ -283,8 +283,8 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_MPC837x) -/* SICRL bits - MPC837x specific */ +#elif defined(CONFIG_ARCH_MPC837X) +/* SICRL bits - MPC837X specific */ #define SICRL_USB_A 0xC0000000 #define SICRL_USB_B 0x30000000 #define SICRL_USB_B_SD 0x20000000 @@ -314,7 +314,7 @@ #define SICRL_LDP_A 0x00000002 #define SICRL_LDP_B 0x00000001
-/* SICRH bits - MPC837x specific */ +/* SICRH bits - MPC837X specific */ #define SICRH_DDR 0x80000000 #define SICRH_TSEC1_A 0x10000000 #define SICRH_TSEC1_B 0x08000000 @@ -647,7 +647,7 @@ #define HRCWL_SVCOD_DIV_8 0x20000000 #define HRCWL_SVCOD_DIV_1 0x30000000
-#elif defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC837X) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_4 0x00000000 @@ -758,7 +758,7 @@ #if defined(CONFIG_ARCH_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif -#if defined(CONFIG_MPC837x) +#if defined(CONFIG_ARCH_MPC837X) #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 #endif #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 @@ -766,7 +766,7 @@ #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 @@ -819,7 +819,7 @@ * RSR - Reset Status Register */ #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_MPC837x) + defined(CONFIG_ARCH_MPC837X) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 #else @@ -1032,8 +1032,8 @@ #define SCCR_TDMCM_2 0x00000020 #define SCCR_TDMCM_3 0x00000030
-#elif defined(CONFIG_MPC837x) -/* SCCR bits - MPC837x specific */ +#elif defined(CONFIG_ARCH_MPC837X) +/* SCCR bits - MPC837X specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC1CM_0 0x00000000 @@ -1129,7 +1129,7 @@ #elif defined(CONFIG_ARCH_MPC832X) #define CSCONFIG_ODT_RD_CFG 0x00400000 #define CSCONFIG_ODT_WR_CFG 0x00040000 -#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_MPC837x) +#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index a4a45c7bcdc..6f031c22033 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1254,7 +1254,6 @@ CONFIG_MPC832XEMDS CONFIG_MPC8349ITX CONFIG_MPC837XEMDS CONFIG_MPC837XERDB -CONFIG_MPC837x CONFIG_MPC83XX_GPIO CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN
The kmtegr1, kmvect1, and suvd3 boards all use the same config include file with lots of #ifdefs in it.
The Kconfig migation will become easier if we get rid of these #ifdefs first.
Hence, create distinct config include files for these boards, and unwind the #ifdef logic in these config files to only include the options necessary for each board.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Combined config creation and simplification patches.
--- arch/powerpc/cpu/mpc83xx/Kconfig | 16 +++- board/keymile/km83xx/Kconfig | 26 ++++++ configs/kmtegr1_defconfig | 2 +- configs/kmvect1_defconfig | 2 +- include/configs/kmtegr1.h | 100 +++++++++++++++++++++++ include/configs/kmvect1.h | 133 +++++++++++++++++++++++++++++++ include/configs/suvd3.h | 94 ---------------------- 7 files changed, 274 insertions(+), 99 deletions(-) create mode 100644 include/configs/kmtegr1.h create mode 100644 include/configs/kmvect1.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index e41f4d1f9a3..59e0c9a8d08 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -89,9 +89,19 @@ config TARGET_KM8360
config TARGET_SUVD3 bool "Support suvd3" - select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMTEGR1" - select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMVECT1" - select ARCH_MPC832X if SYS_EXTRA_OPTIONS="SUVD3" + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +config TARGET_KMVECT1 + bool "Support kmvect1" + select ARCH_MPC8309 + imply CMD_CRAMFS + imply FS_CRAMFS + +config TARGET_KMTEGR1 + bool "Support kmtegr1" + select ARCH_MPC8309 imply CMD_CRAMFS imply FS_CRAMFS
diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index d6c594c96ac..d52ee9117b5 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -11,6 +11,32 @@ config SYS_CONFIG_NAME
endif
+if TARGET_KMVECT1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmvect1" + +endif + +if TARGET_KMTEGR1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmtegr1" + +endif + if TARGET_SUVD3
config SYS_BOARD diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 40181758e9c..38a861b8610 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -1,7 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_SUVD3=y +CONFIG_TARGET_KMTEGR1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 74b688fb5f9..2f71ee75198 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -1,7 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_SUVD3=y +CONFIG_TARGET_KMVECT1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h new file mode 100644 index 00000000000..69397ae5ae4 --- /dev/null +++ b/include/configs/kmtegr1.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ + +/* This needs to be set prior to including km/km83xx-common.h */ + +#define CONFIG_HOSTNAME "kmtegr1" +#define CONFIG_KM_BOARD_NAME "kmtegr1" +#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" +#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" + +#define CONFIG_ENV_ADDR 0xF0100000 +#define CONFIG_ENV_OFFSET 0x100000 + +#define CONFIG_NAND_ECC_BCH +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 + +/* include common defines/options for all 8309 Keymile boards */ +#include "km/km8309-common.h" +/* must be after the include because KMBEC_FPGA is otherwise undefined */ +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ + +#define CONFIG_SYS_APP1_BASE 0xA0000000 +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local UPMA 16 bit 256MB APP1 + * 3 Local GPCM 16 bit 256MB APP2 + * + */ + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_16 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_CLEAR | \ + OR_GPCM_EHTR_CLEAR) + +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT5L (0) +#define CONFIG_SYS_IBAT5U (0) +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +/* ethernet port connected to piggy (UEC2) */ +#define CONFIG_HAS_ETH1 +#define CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 + +#endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h new file mode 100644 index 00000000000..178e769976a --- /dev/null +++ b/include/configs/kmvect1.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ + +/* This needs to be set prior to including km/km83xx-common.h */ + +#define CONFIG_HOSTNAME "kmvect1" +#define CONFIG_KM_BOARD_NAME "kmvect1" +/* at end of uboot partition, before env */ +#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 +/* include common defines/options for all 8309 Keymile boards */ +#include "km/km8309-common.h" + +#define CONFIG_SYS_APP1_BASE 0xA0000000 +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 2 Local UPMA 16 bit 256MB APP1 + * 3 Local GPCM 16 bit 256MB APP2 + * + */ + +/* + * APP1 on the local bus CS2 + */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_16 | \ + BR_MS_UPMA | \ + BR_V) +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_16 | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_3 | \ + OR_GPCM_TRLX_SET) + +#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ + 0x0000c000 | \ + MxMR_WLFx_2X) + +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +/* + * MMU Setup + */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_MV88E6352_SWITCH +#define CONFIG_KM_MVEXTSW_ADDR 0x10 + +/* ethernet port connected to simple switch 88e6122 (UEC0) */ +#define CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 + +#define CONFIG_FIXED_PHY 0xFFFFFFFF +#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */ +#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \ + {devnum, speed, duplex} +#define CONFIG_SYS_FIXED_PHY_PORTS \ + CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL) + +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 + +/* ethernet port connected to piggy (UEC2) */ +#define CONFIG_HAS_ETH1 +#define CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 + +#endif /* __CONFIG_H */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 3e88c9000c6..2a3f7ff5260 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -22,43 +22,11 @@
/* This needs to be set prior to including km/km83xx-common.h */
-#if defined(CONFIG_SUVD3) /* SUVD3 board specific */ #define CONFIG_HOSTNAME "suvd3" #define CONFIG_KM_BOARD_NAME "suvd3" /* include common defines/options for all 8321 Keymile boards */ #include "km/km8321-common.h"
-#elif defined(CONFIG_KMVECT1) /* VECT1 board specific */ -#define CONFIG_HOSTNAME "kmvect1" -#define CONFIG_KM_BOARD_NAME "kmvect1" -/* at end of uboot partition, before env */ -#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 -/* include common defines/options for all 8309 Keymile boards */ -#include "km/km8309-common.h" - -#elif defined(CONFIG_KMTEGR1) /* TEGR1 board specific */ -#define CONFIG_HOSTNAME "kmtegr1" -#define CONFIG_KM_BOARD_NAME "kmtegr1" -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" - -#define CONFIG_ENV_ADDR 0xF0100000 -#define CONFIG_ENV_OFFSET 0x100000 - -#define CONFIG_NAND_ECC_BCH -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 - -/* include common defines/options for all 8309 Keymile boards */ -#include "km/km8309-common.h" -/* must be after the include because KMBEC_FPGA is otherwise undefined */ -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ - -#else -#error Supported boards are: SUVD3, KMVECT1, KMTEGR1 -#endif - #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 @@ -77,7 +45,6 @@ * */
-#if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1) /* * APP1 on the local bus CS2 */ @@ -104,26 +71,12 @@ 0x0000c000 | \ MxMR_WLFx_2X)
-#elif defined(CONFIG_KMTEGR1) -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_CLEAR | \ - OR_GPCM_EHTR_CLEAR) - -#endif /* CONFIG_KMTEGR1 */ - #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
/* * MMU Setup */ -#if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1) /* APP1: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) @@ -132,14 +85,6 @@ #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#elif defined(CONFIG_KMTEGR1) -#define CONFIG_SYS_IBAT5L (0) -#define CONFIG_SYS_IBAT5U (0) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#endif /* CONFIG_KMTEGR1 */ - #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ @@ -148,43 +93,4 @@ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* - * QE UEC ethernet configuration - */ -#if defined(CONFIG_KMVECT1) -#define CONFIG_MV88E6352_SWITCH -#define CONFIG_KM_MVEXTSW_ADDR 0x10 - -/* ethernet port connected to simple switch 88e6122 (UEC0) */ -#define CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 - -#define CONFIG_FIXED_PHY 0xFFFFFFFF -#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */ -#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \ - {devnum, speed, duplex} -#define CONFIG_SYS_FIXED_PHY_PORTS \ - CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL) - -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif /* CONFIG_KMVECT1 */ - -#if defined(CONFIG_KMVECT1) || defined(CONFIG_KMTEGR1) -/* ethernet port connected to piggy (UEC2) */ -#define CONFIG_HAS_ETH1 -#define CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 -#endif /* CONFIG_KMVECT1 || CONFIG_KMTEGR1 */ - #endif /* __CONFIG_H */
We want to unroll several include files, while keeping include statements consistent.
To make it easier to not break the include statements, move the include files to the main configs directory. All three include files moved will be unrolled, so they won't pollute the directory for long.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- include/configs/{km => }/km8309-common.h | 0 include/configs/{km => }/km8321-common.h | 0 include/configs/km8360.h | 2 +- include/configs/{km => }/km83xx-common.h | 4 ++-- include/configs/kmtegr1.h | 4 ++-- include/configs/kmvect1.h | 4 ++-- include/configs/suvd3.h | 4 ++-- include/configs/tuxx1.h | 2 +- 8 files changed, 10 insertions(+), 10 deletions(-) rename include/configs/{km => }/km8309-common.h (100%) rename include/configs/{km => }/km8321-common.h (100%) rename include/configs/{km => }/km83xx-common.h (99%)
diff --git a/include/configs/km/km8309-common.h b/include/configs/km8309-common.h similarity index 100% rename from include/configs/km/km8309-common.h rename to include/configs/km8309-common.h diff --git a/include/configs/km/km8321-common.h b/include/configs/km8321-common.h similarity index 100% rename from include/configs/km/km8321-common.h rename to include/configs/km8321-common.h diff --git a/include/configs/km8360.h b/include/configs/km8360.h index 7e2876ee088..d6c2772825e 100644 --- a/include/configs/km8360.h +++ b/include/configs/km8360.h @@ -38,7 +38,7 @@ #define CONFIG_QE /* Has QE */
/* include common defines/options for all 83xx Keymile boards */ -#include "km/km83xx-common.h" +#include "km83xx-common.h"
/* * System IO Setup diff --git a/include/configs/km/km83xx-common.h b/include/configs/km83xx-common.h similarity index 99% rename from include/configs/km/km83xx-common.h rename to include/configs/km83xx-common.h index fb2a1cb39a0..c80169c9b68 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km83xx-common.h @@ -8,8 +8,8 @@ #define __CONFIG_KM83XX_H
/* include common defines/options for all Keymile boards */ -#include "keymile-common.h" -#include "km-powerpc.h" +#include "km/keymile-common.h" +#include "km/km-powerpc.h"
/* * System Clock Setup diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 69397ae5ae4..95a131892de 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -20,7 +20,7 @@ * High Level Configuration Options */
-/* This needs to be set prior to including km/km83xx-common.h */ +/* This needs to be set prior to including km83xx-common.h */
#define CONFIG_HOSTNAME "kmtegr1" #define CONFIG_KM_BOARD_NAME "kmtegr1" @@ -36,7 +36,7 @@ #define NAND_MAX_CHIPS 1
/* include common defines/options for all 8309 Keymile boards */ -#include "km/km8309-common.h" +#include "km8309-common.h" /* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 178e769976a..0bbf541aec7 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -20,14 +20,14 @@ * High Level Configuration Options */
-/* This needs to be set prior to including km/km83xx-common.h */ +/* This needs to be set prior to including km83xx-common.h */
#define CONFIG_HOSTNAME "kmvect1" #define CONFIG_KM_BOARD_NAME "kmvect1" /* at end of uboot partition, before env */ #define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 /* include common defines/options for all 8309 Keymile boards */ -#include "km/km8309-common.h" +#include "km8309-common.h"
#define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 2a3f7ff5260..98137392edb 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -20,12 +20,12 @@ * High Level Configuration Options */
-/* This needs to be set prior to including km/km83xx-common.h */ +/* This needs to be set prior to including km83xx-common.h */
#define CONFIG_HOSTNAME "suvd3" #define CONFIG_KM_BOARD_NAME "suvd3" /* include common defines/options for all 8321 Keymile boards */ -#include "km/km8321-common.h" +#include "km8321-common.h"
#define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 8729fc9b2ef..1301d230f6d 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -43,7 +43,7 @@ #endif
/* include common defines/options for all 8321 Keymile boards */ -#include "km/km8321-common.h" +#include "km8321-common.h"
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
To further simplify config include files, unroll the km/km8309-common.h and km/km8321-common.h include files.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- include/configs/km8309-common.h | 174 -------------------------------- include/configs/km8321-common.h | 139 ------------------------- include/configs/kmtegr1.h | 164 +++++++++++++++++++++++++++++- include/configs/kmvect1.h | 164 +++++++++++++++++++++++++++++- include/configs/suvd3.h | 116 ++++++++++++++++++++- include/configs/tuxx1.h | 115 ++++++++++++++++++++- 6 files changed, 551 insertions(+), 321 deletions(-) delete mode 100644 include/configs/km8309-common.h delete mode 100644 include/configs/km8321-common.h
diff --git a/include/configs/km8309-common.h b/include/configs/km8309-common.h deleted file mode 100644 index 3bd334c5152..00000000000 --- a/include/configs/km8309-common.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Keymile AG - * Gerlando Falauto gerlando.falauto@keymile.com - * - * Based on km8321-common.h, see respective copyright notice for credits - */ - -#ifndef __CONFIG_KM8309_COMMON_H -#define __CONFIG_KM8309_COMMON_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" - -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" - -/* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -/* between the u-boot partition and env */ -#ifndef CONFIG_SYS_QE_FW_ADDR -#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 -#endif - -/* - * System IO Config - */ -/* 0x14000180 SICR_1 */ -#define CONFIG_SYS_SICRL (0 \ - | SICR_1_UART1_UART1RTS \ - | SICR_1_I2C_CKSTOP \ - | SICR_1_IRQ_A_IRQ \ - | SICR_1_IRQ_B_IRQ \ - | SICR_1_GPIO_A_GPIO \ - | SICR_1_GPIO_B_GPIO \ - | SICR_1_GPIO_C_GPIO \ - | SICR_1_GPIO_D_GPIO \ - | SICR_1_GPIO_E_GPIO \ - | SICR_1_GPIO_F_GPIO \ - | SICR_1_USB_A_UART2S \ - | SICR_1_USB_B_UART2RTS \ - | SICR_1_FEC1_FEC1 \ - | SICR_1_FEC2_FEC2 \ - ) - -/* 0x00080400 SICR_2 */ -#define CONFIG_SYS_SICRH (0 \ - | SICR_2_FEC3_FEC3 \ - | SICR_2_HDLC1_A_HDLC1 \ - | SICR_2_ELBC_A_LA \ - | SICR_2_ELBC_B_LCLK \ - | SICR_2_HDLC2_A_HDLC2 \ - | SICR_2_USB_D_GPIO \ - | SICR_2_PCI_PCI \ - | SICR_2_HDLC1_B_HDLC1 \ - | SICR_2_HDLC1_C_HDLC1 \ - | SICR_2_HDLC2_B_GPIO \ - | SICR_2_HDLC2_C_HDLC2 \ - | SICR_2_QUIESCE_B \ - ) - -/* GPR_1 */ -#define CONFIG_SYS_GPR1 0x50008060 - -#define CONFIG_SYS_GP1DIR 0x00000000 -#define CONFIG_SYS_GP1ODR 0x00000000 -#define CONFIG_SYS_GP2DIR 0xFF000000 -#define CONFIG_SYS_GP2ODR 0x00000000 - -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_RD_NEVER | \ - CSCONFIG_ODT_WR_ONLY_CURRENT | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -#endif /* __CONFIG_KM8309_COMMON_H */ diff --git a/include/configs/km8321-common.h b/include/configs/km8321-common.h deleted file mode 100644 index a121a445f78..00000000000 --- a/include/configs/km8321-common.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu daveliu@freescale.com - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada peterb@logicpd.com - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov avorontsov@ru.mvista.com - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010 - * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * - * (C) Copyright 2010-2011 - * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com - */ - -#ifndef __CONFIG_KM8321_COMMON_H -#define __CONFIG_KM8321_COMMON_H - -/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" - -/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -#endif /* __CONFIG_KM8321_COMMON_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 95a131892de..27e3905c2b4 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -35,8 +35,168 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1
-/* include common defines/options for all 8309 Keymile boards */ -#include "km8309-common.h" +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +/* between the u-boot partition and env */ +#ifndef CONFIG_SYS_QE_FW_ADDR +#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 +#endif + +/* + * System IO Config + */ +/* 0x14000180 SICR_1 */ +#define CONFIG_SYS_SICRL (0 \ + | SICR_1_UART1_UART1RTS \ + | SICR_1_I2C_CKSTOP \ + | SICR_1_IRQ_A_IRQ \ + | SICR_1_IRQ_B_IRQ \ + | SICR_1_GPIO_A_GPIO \ + | SICR_1_GPIO_B_GPIO \ + | SICR_1_GPIO_C_GPIO \ + | SICR_1_GPIO_D_GPIO \ + | SICR_1_GPIO_E_GPIO \ + | SICR_1_GPIO_F_GPIO \ + | SICR_1_USB_A_UART2S \ + | SICR_1_USB_B_UART2RTS \ + | SICR_1_FEC1_FEC1 \ + | SICR_1_FEC2_FEC2 \ + ) + +/* 0x00080400 SICR_2 */ +#define CONFIG_SYS_SICRH (0 \ + | SICR_2_FEC3_FEC3 \ + | SICR_2_HDLC1_A_HDLC1 \ + | SICR_2_ELBC_A_LA \ + | SICR_2_ELBC_B_LCLK \ + | SICR_2_HDLC2_A_HDLC2 \ + | SICR_2_USB_D_GPIO \ + | SICR_2_PCI_PCI \ + | SICR_2_HDLC1_B_HDLC1 \ + | SICR_2_HDLC1_C_HDLC1 \ + | SICR_2_HDLC2_B_GPIO \ + | SICR_2_HDLC2_C_HDLC2 \ + | SICR_2_QUIESCE_B \ + ) + +/* GPR_1 */ +#define CONFIG_SYS_GPR1 0x50008060 + +#define CONFIG_SYS_GP1DIR 0x00000000 +#define CONFIG_SYS_GP1ODR 0x00000000 +#define CONFIG_SYS_GP2DIR 0xFF000000 +#define CONFIG_SYS_GP2ODR 0x00000000 + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_RD_NEVER | \ + CSCONFIG_ODT_WR_ONLY_CURRENT | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + /* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 0bbf541aec7..5a0fbccadec 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -26,8 +26,168 @@ #define CONFIG_KM_BOARD_NAME "kmvect1" /* at end of uboot partition, before env */ #define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 -/* include common defines/options for all 8309 Keymile boards */ -#include "km8309-common.h" + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +/* between the u-boot partition and env */ +#ifndef CONFIG_SYS_QE_FW_ADDR +#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 +#endif + +/* + * System IO Config + */ +/* 0x14000180 SICR_1 */ +#define CONFIG_SYS_SICRL (0 \ + | SICR_1_UART1_UART1RTS \ + | SICR_1_I2C_CKSTOP \ + | SICR_1_IRQ_A_IRQ \ + | SICR_1_IRQ_B_IRQ \ + | SICR_1_GPIO_A_GPIO \ + | SICR_1_GPIO_B_GPIO \ + | SICR_1_GPIO_C_GPIO \ + | SICR_1_GPIO_D_GPIO \ + | SICR_1_GPIO_E_GPIO \ + | SICR_1_GPIO_F_GPIO \ + | SICR_1_USB_A_UART2S \ + | SICR_1_USB_B_UART2RTS \ + | SICR_1_FEC1_FEC1 \ + | SICR_1_FEC2_FEC2 \ + ) + +/* 0x00080400 SICR_2 */ +#define CONFIG_SYS_SICRH (0 \ + | SICR_2_FEC3_FEC3 \ + | SICR_2_HDLC1_A_HDLC1 \ + | SICR_2_ELBC_A_LA \ + | SICR_2_ELBC_B_LCLK \ + | SICR_2_HDLC2_A_HDLC2 \ + | SICR_2_USB_D_GPIO \ + | SICR_2_PCI_PCI \ + | SICR_2_HDLC1_B_HDLC1 \ + | SICR_2_HDLC1_C_HDLC1 \ + | SICR_2_HDLC2_B_GPIO \ + | SICR_2_HDLC2_C_HDLC2 \ + | SICR_2_QUIESCE_B \ + ) + +/* GPR_1 */ +#define CONFIG_SYS_GPR1 0x50008060 + +#define CONFIG_SYS_GP1DIR 0x00000000 +#define CONFIG_SYS_GP1ODR 0x00000000 +#define CONFIG_SYS_GP2DIR 0xFF000000 +#define CONFIG_SYS_GP2ODR 0x00000000 + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_RD_NEVER | \ + CSCONFIG_ODT_WR_ONLY_CURRENT | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 98137392edb..5fe5f3cc232 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -24,8 +24,120 @@
#define CONFIG_HOSTNAME "suvd3" #define CONFIG_KM_BOARD_NAME "suvd3" -/* include common defines/options for all 8321 Keymile boards */ -#include "km8321-common.h" + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 1301d230f6d..30db3d8f7c2 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -42,8 +42,119 @@ #error ("Board not supported") #endif
-/* include common defines/options for all 8321 Keymile boards */ -#include "km8321-common.h" +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
The kmsupx5, tuge1, kmopti2, and kmtepr2 boards all build from the same include config file with lots of #ifdef logic.
To ease Kconfig migration, create new config include files for these boards, and resolve the #ifdef logic as needed.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Combined config creation and simplification patches
--- arch/powerpc/cpu/mpc83xx/Kconfig | 24 ++++ board/keymile/km83xx/Kconfig | 52 +++++++ configs/kmopti2_defconfig | 3 +- configs/kmsupx5_defconfig | 3 +- configs/kmtepr2_defconfig | 3 +- configs/tuge1_defconfig | 3 +- configs/tuxx1_defconfig | 1 - include/configs/kmopti2.h | 234 ++++++++++++++++++++++++++++++ include/configs/kmsupx5.h | 210 +++++++++++++++++++++++++++ include/configs/kmtepr2.h | 235 +++++++++++++++++++++++++++++++ include/configs/tuge1.h | 210 +++++++++++++++++++++++++++ include/configs/tuxx1.h | 62 -------- 12 files changed, 969 insertions(+), 71 deletions(-) create mode 100644 include/configs/kmopti2.h create mode 100644 include/configs/kmsupx5.h create mode 100644 include/configs/kmtepr2.h create mode 100644 include/configs/tuge1.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 59e0c9a8d08..1ebb092f0bf 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -111,6 +111,30 @@ config TARGET_TUXX1 imply CMD_CRAMFS imply FS_CRAMFS
+config TARGET_KMSUPX5 + bool "Support kmsupx5" + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +config TARGET_TUGE1 + bool "Support tuge1" + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +config TARGET_KMOPTI2 + bool "Support kmopti2" + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + +config TARGET_KMTEPR2 + bool "Support kmtepr2" + select ARCH_MPC832X + imply CMD_CRAMFS + imply FS_CRAMFS + config TARGET_TQM834X bool "Support TQM834x" select ARCH_MPC8349 diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index d52ee9117b5..0c4fa0b7fdb 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -62,3 +62,55 @@ config SYS_CONFIG_NAME default "tuxx1"
endif + +if TARGET_KMSUPX5 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmsupx5" + +endif + +if TARGET_TUGE1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "tuge1" + +endif + +if TARGET_KMOPTI2 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmopti2" + +endif + +if TARGET_KMTEPR2 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmtepr2" + +endif diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index e8e821fb800..c0927dd4788 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_TUXX1=y +CONFIG_TARGET_KMOPTI2=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 86e2bd92378..7a00c85a841 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_TUXX1=y +CONFIG_TARGET_KMSUPX5=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 6170dc3f161..310cf5ac66f 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_TUXX1=y +CONFIG_TARGET_KMTEPR2=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index e5826719b9f..a3e04bc0f8a 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_TUXX1=y +CONFIG_TARGET_TUGE1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="TUGE1" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 204d3e4f687..d1fc62697e3 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -4,7 +4,6 @@ CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="TUXX1" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h new file mode 100644 index 00000000000..0621be3928a --- /dev/null +++ b/include/configs/kmopti2.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_KM_BOARD_NAME "kmopti2" +#define CONFIG_HOSTNAME "kmopti2" + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* + * Init Local Bus Memory Controller: + * Device on board + * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE + * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) + * + * Device on board (continued) + * Bank Bus Machine PortSz Size KMTEPR2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB NVRAM + * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) + */ + +/* + * Configuration for C2 on the local bus + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR | \ + OR_GPCM_EAD) + +/* + * Configuration for C3 on the local bus + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_16 | \ + BR_MS_GPCM | \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_SCY_4 | \ + OR_GPCM_TRLX_CLEAR | \ + OR_GPCM_EHTR_CLEAR) +/* + * MMU Setup + */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +/* 512M should also include APP2... */ +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +/* APP2: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h new file mode 100644 index 00000000000..be93b7ce89c --- /dev/null +++ b/include/configs/kmsupx5.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_KM_BOARD_NAME "kmsupx5" +#define CONFIG_HOSTNAME "kmsupx5" + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ + +/* + * Init Local Bus Memory Controller: + * Device on board + * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE + * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) + * + * Device on board (continued) + * Bank Bus Machine PortSz Size KMTEPR2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB NVRAM + * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) + */ + +/* + * Configuration for C2 on the local bus + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR | \ + OR_GPCM_EAD) + +/* + * MMU Setup + */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +/* 512M should also include APP2... */ +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_H */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h new file mode 100644 index 00000000000..f3504e5a811 --- /dev/null +++ b/include/configs/kmtepr2.h @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_KM_BOARD_NAME "kmtepr2" +#define CONFIG_HOSTNAME "kmtepr2" + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ + +/* + * Init Local Bus Memory Controller: + * Device on board + * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE + * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) + * + * Device on board (continued) + * Bank Bus Machine PortSz Size KMTEPR2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB NVRAM + * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) + */ + +/* + * Configuration for C2 on the local bus + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR | \ + OR_GPCM_EAD) + +/* + * Configuration for C3 on the local bus + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_16 | \ + BR_MS_GPCM | \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_SCY_4 | \ + OR_GPCM_TRLX_CLEAR | \ + OR_GPCM_EHTR_CLEAR) + +/* + * MMU Setup + */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +/* 512M should also include APP2... */ +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +/* APP2: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_H */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h new file mode 100644 index 00000000000..85f8e9cd30a --- /dev/null +++ b/include/configs/tuge1.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu daveliu@freescale.com + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada peterb@logicpd.com + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov avorontsov@ru.mvista.com + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * (C) Copyright 2010-2013 + * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_KM_BOARD_NAME "tuge1" +#define CONFIG_HOSTNAME "tuge1" + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2_5X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ + +/* + * Init Local Bus Memory Controller: + * Device on board + * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE + * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) + * + * Device on board (continued) + * Bank Bus Machine PortSz Size KMTEPR2 + * ----------------------------------------------------------------------------- + * 2 Local GPCM 8 bit 256MB NVRAM + * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) + */ + +/* + * Configuration for C2 on the local bus + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE +/* Window size: 256 MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ + BR_PS_8 | \ + BR_MS_GPCM | \ + BR_V) + +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR | \ + OR_GPCM_EAD) + +/* + * MMU Setup + */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_MEMCOHERENCE) +/* 512M should also include APP2... */ +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ + BATL_PP_RW | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 30db3d8f7c2..839b7a3a4d9 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -23,24 +23,8 @@ /* * High Level Configuration Options */ -#if defined(CONFIG_KMSUPX5) -#define CONFIG_KM_BOARD_NAME "kmsupx5" -#define CONFIG_HOSTNAME "kmsupx5" -#elif defined(CONFIG_TUGE1) -#define CONFIG_KM_BOARD_NAME "tuge1" -#define CONFIG_HOSTNAME "tuge1" -#elif defined(CONFIG_TUXX1) /* TUXX1 board (tuxa1/tuda1) specific */ #define CONFIG_KM_BOARD_NAME "tuxx1" #define CONFIG_HOSTNAME "tuxx1" -#elif defined(CONFIG_KMOPTI2) -#define CONFIG_KM_BOARD_NAME "kmopti2" -#define CONFIG_HOSTNAME "kmopti2" -#elif defined(CONFIG_KMTEPR2) -#define CONFIG_KM_BOARD_NAME "kmtepr2" -#define CONFIG_HOSTNAME "kmtepr2" -#else -#error ("Board not supported") -#endif
/* * High Level Configuration Options @@ -158,10 +142,8 @@
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#if defined(CONFIG_TUXX1) || defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2) #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ -#endif
/* * Init Local Bus Memory Controller: @@ -178,25 +160,6 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */
-#if defined(CONFIG_KMTEPRO2) -/* - * Configuration for C2 (NVRAM) on the local bus - */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_XACS | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_SET | \ - OR_GPCM_EAD) -#else /* * Configuration for C2 on the local bus */ @@ -217,9 +180,7 @@ OR_GPCM_TRLX_SET | \ OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD) -#endif
-#if defined(CONFIG_TUXX1) /* * Configuration for C3 on the local bus */ @@ -243,23 +204,6 @@ #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ MxMR_WLFx_2X) -#endif - -#if defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2) -/* - * Configuration for C3 on the local bus - */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V) -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ - OR_GPCM_SCY_4 | \ - OR_GPCM_TRLX_CLEAR | \ - OR_GPCM_EHTR_CLEAR) -#endif
/* * MMU Setup @@ -279,11 +223,6 @@ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#if defined(CONFIG_TUGE1) || defined(CONFIG_KMSUPX5) -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#else /* APP2: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ BATL_PP_RW | \ @@ -296,7 +235,6 @@ BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) -#endif #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#define CONFIG_SYS_IBAT7L (0)
Simplify the keymile config files once more by unrolling the km/km83xx-common.h, and resolve the #ifdef logic as needed.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- include/configs/km8360.h | 287 ++++++++++++++++++++++++++++++- include/configs/km83xx-common.h | 296 -------------------------------- include/configs/kmopti2.h | 285 +++++++++++++++++++++++++++++- include/configs/kmsupx5.h | 285 +++++++++++++++++++++++++++++- include/configs/kmtegr1.h | 284 +++++++++++++++++++++++++++++- include/configs/kmtepr2.h | 285 +++++++++++++++++++++++++++++- include/configs/kmvect1.h | 284 +++++++++++++++++++++++++++++- include/configs/suvd3.h | 287 ++++++++++++++++++++++++++++++- include/configs/tuge1.h | 285 +++++++++++++++++++++++++++++- include/configs/tuxx1.h | 285 +++++++++++++++++++++++++++++- 10 files changed, 2543 insertions(+), 320 deletions(-) delete mode 100644 include/configs/km83xx-common.h
diff --git a/include/configs/km8360.h b/include/configs/km8360.h index d6c2772825e..67d310c42cf 100644 --- a/include/configs/km8360.h +++ b/include/configs/km8360.h @@ -37,8 +37,291 @@ */ #define CONFIG_QE /* Has QE */
-/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#if !defined(CONFIG_ARCH_MPC8309) +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 +#endif + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif
/* * System IO Setup diff --git a/include/configs/km83xx-common.h b/include/configs/km83xx-common.h deleted file mode 100644 index c80169c9b68..00000000000 --- a/include/configs/km83xx-common.h +++ /dev/null @@ -1,296 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#ifndef __CONFIG_KM83XX_H -#define __CONFIG_KM83XX_H - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#if !defined(CONFIG_ARCH_MPC8309) -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 -#endif - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* - * MMU Setup - */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -#endif /* __CONFIG_KM83XX_H */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 0621be3928a..fa12d41080a 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -34,8 +34,289 @@
#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
-/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif
/* * System IO Config diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index be93b7ce89c..30898c0b75c 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -34,8 +34,289 @@
#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
-/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif
/* * System IO Config diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 27e3905c2b4..329a5cfe0fe 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -20,8 +20,6 @@ * High Level Configuration Options */
-/* This needs to be set prior to including km83xx-common.h */ - #define CONFIG_HOSTNAME "kmtegr1" #define CONFIG_KM_BOARD_NAME "kmtegr1" #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" @@ -43,8 +41,286 @@
#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
-/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif
/* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index f3504e5a811..02b72c874e1 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -34,8 +34,289 @@
#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
-/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif
/* * System IO Config diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 5a0fbccadec..c21b9ba38f1 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -20,8 +20,6 @@ * High Level Configuration Options */
-/* This needs to be set prior to including km83xx-common.h */ - #define CONFIG_HOSTNAME "kmvect1" #define CONFIG_KM_BOARD_NAME "kmvect1" /* at end of uboot partition, before env */ @@ -35,8 +33,286 @@
#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
-/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif
/* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 5fe5f3cc232..87f7390bcc2 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -20,8 +20,6 @@ * High Level Configuration Options */
-/* This needs to be set prior to including km83xx-common.h */ - #define CONFIG_HOSTNAME "suvd3" #define CONFIG_KM_BOARD_NAME "suvd3"
@@ -33,8 +31,289 @@
#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
-/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif
/* * System IO Config diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 85f8e9cd30a..1cd0985dc29 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -34,8 +34,289 @@
#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
-/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif
/* * System IO Config diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 839b7a3a4d9..0d7c571ee5f 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -34,8 +34,289 @@
#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
-/* include common defines/options for all 83xx Keymile boards */ -#include "km83xx-common.h" +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif
/* * System IO Config
The kmeter1, and kmcoge5ne boards also build from the same config file with #ifdef logic.
Create a separate include config for each board with the #ifdef logic resolved as needed.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Combined config creation and simplification patches
--- arch/powerpc/cpu/mpc83xx/Kconfig | 11 +- board/keymile/km83xx/Kconfig | 17 +- board/keymile/km83xx/km83xx.c | 2 +- configs/kmcoge5ne_defconfig | 3 +- configs/kmeter1_defconfig | 3 +- include/configs/{km8360.h => kmcoge5ne.h} | 29 -- include/configs/kmeter1.h | 458 ++++++++++++++++++++++ 7 files changed, 485 insertions(+), 38 deletions(-) rename include/configs/{km8360.h => kmcoge5ne.h} (95%) create mode 100644 include/configs/kmeter1.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 1ebb092f0bf..29d84f363d1 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -80,8 +80,15 @@ config TARGET_IDS8313 select DM imply CMD_DM
-config TARGET_KM8360 - bool "Support km8360" +config TARGET_KMETER1 + bool "Support kmeter1" + select ARCH_MPC8360 + imply CMD_CRAMFS + imply CMD_DIAG + imply FS_CRAMFS + +config TARGET_KMCOGE5NE + bool "Support kmcoge5ne" select ARCH_MPC8360 imply CMD_CRAMFS imply CMD_DIAG diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index 0c4fa0b7fdb..fbbbb17034f 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -1,4 +1,4 @@ -if TARGET_KM8360 +if TARGET_KMETER1
config SYS_BOARD default "km83xx" @@ -7,7 +7,20 @@ config SYS_VENDOR default "keymile"
config SYS_CONFIG_NAME - default "km8360" + default "kmeter1" + +endif + +if TARGET_KMCOGE5NE + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmcoge5ne"
endif
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 12044ee0d70..1fd6f919014 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -271,7 +271,7 @@ int last_stage_init(void) } #endif
-#if defined(CONFIG_KMCOGE5NE) +#if defined(CONFIG_TARGET_KMCOGE5NE) struct bfticu_iomap *base = (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK; diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index cb47b0b7fde..b7c42fa9cbe 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_KM8360=y +CONFIG_TARGET_KMCOGE5NE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 0c3fadfcf8a..1773f74358e 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_MPC83xx=y -CONFIG_TARGET_KM8360=y +CONFIG_TARGET_KMETER1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="KMETER1" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/include/configs/km8360.h b/include/configs/kmcoge5ne.h similarity index 95% rename from include/configs/km8360.h rename to include/configs/kmcoge5ne.h index 67d310c42cf..1cff0a19f1b 100644 --- a/include/configs/km8360.h +++ b/include/configs/kmcoge5ne.h @@ -12,11 +12,6 @@ #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64
-#if defined CONFIG_KMETER1 -#define CONFIG_HOSTNAME "kmeter1" -#define CONFIG_KM_BOARD_NAME "kmeter1" -#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0" -#elif defined CONFIG_KMCOGE5NE #define CONFIG_HOSTNAME "kmcoge5ne" #define CONFIG_KM_BOARD_NAME "kmcoge5ne" #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0" @@ -28,9 +23,6 @@
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" -#else -#error ("Board not supported") -#endif
/* * High Level Configuration Options @@ -165,10 +157,8 @@ #define CONFIG_UEC_ETH #define CONFIG_ETHPRIME "UEC0"
-#if !defined(CONFIG_ARCH_MPC8309) #define CONFIG_UEC_ETH1 /* GETH1 */ #define UEC_VERBOSE_DEBUG 1 -#endif
#ifdef CONFIG_UEC_ETH1 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ @@ -357,7 +347,6 @@
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#ifdef CONFIG_KMCOGE5NE /** * KMCOGE5NE has 512 MB RAM */ @@ -368,12 +357,6 @@ CSCONFIG_BANK_BIT_3 | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10) -#else -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10 | \ - CSCONFIG_ODT_WR_ONLY_CURRENT) -#endif
#define CONFIG_SYS_DDR_CLK_CNTL (\ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) @@ -453,7 +436,6 @@ OR_GPCM_TRLX | \ OR_GPCM_EAD)
-#ifdef CONFIG_KMCOGE5NE /* * BFTIC3 on the local bus CS4 */ @@ -472,7 +454,6 @@ OR_GPCM_SCY_2 |\ OR_GPCM_TRLX |\ OR_GPCM_EAD) -#endif
/* * MMU Setup @@ -498,7 +479,6 @@
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#ifdef CONFIG_KMCOGE5NE /* BFTIC3: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (\ CONFIG_SYS_BFTIC3_BASE | \ @@ -538,15 +518,6 @@ #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
-#else -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#endif - #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h new file mode 100644 index 00000000000..976255f5789 --- /dev/null +++ b/include/configs/kmeter1.h @@ -0,0 +1,458 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + * Christian Herzig, Keymile AG Switzerland, christian.herzig@keymile.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* KMBEC FPGA (PRIO) */ +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 + +#define CONFIG_HOSTNAME "kmeter1" +#define CONFIG_KM_BOARD_NAME "kmeter1" +#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0" + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ + +/* include common defines/options for all Keymile boards */ +#include "km/keymile-common.h" +#include "km/km-powerpc.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ + "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + +/* + * System IO Setup + */ +#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_CSB_TO_CLKIN_4X1 | \ + HRCWL_CORE_TO_CSB_2X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X6) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_EARLY | \ + HRCWH_LDP_CLEAR) + +/** + * DDR RAM settings + */ +#define CONFIG_SYS_DDR_SDRAM_CFG (\ + SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10 | \ + CSCONFIG_ODT_WR_ONLY_CURRENT) + +#define CONFIG_SYS_DDR_CLK_CNTL (\ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CONFIG_SYS_DDR_INTERVAL (\ + (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_Q_DRN) +#define CONFIG_SYS_DDR_MODE 0x47860452 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 (\ + (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 (\ + (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 + +/* + * PAXE on the local bus CS3 + */ +#define CONFIG_SYS_PAXE_BASE 0xA0000000 +#define CONFIG_SYS_PAXE_SIZE 256 + +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE + +#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ + +#define CONFIG_SYS_BR3_PRELIM (\ + CONFIG_SYS_PAXE_BASE | \ + (1 << BR_PS_SHIFT) | \ + BR_V) + +#define CONFIG_SYS_OR3_PRELIM (\ + MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | \ + OR_GPCM_EAD) + +/* + * MMU Setup + */ + +/* PAXE: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (\ + CONFIG_SYS_PAXE_BASE | \ + BATL_PP_10 | \ + BATL_MEMCOHERENCE) + +#define CONFIG_SYS_IBAT5U (\ + CONFIG_SYS_PAXE_BASE | \ + BATU_BL_256M | \ + BATU_VS | \ + BATU_VP) + +#define CONFIG_SYS_DBAT5L (\ + CONFIG_SYS_PAXE_BASE | \ + BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) + +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* CONFIG */
MPC8313ERDB has the option of either enabling NOR or NAND boot in its config file (by commenting out certain #ifdefs). To keep this ability after migrating options to Kconfig, we introduce two MPC8313ERDB configs: one for NOR, and one for NAND.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Combined config creation and simplification patches
--- arch/powerpc/cpu/mpc83xx/Kconfig | 10 +- board/freescale/mpc8313erdb/Kconfig | 17 +- configs/MPC8313ERDB_33_defconfig | 2 +- configs/MPC8313ERDB_66_defconfig | 2 +- configs/MPC8313ERDB_NAND_33_defconfig | 2 +- configs/MPC8313ERDB_NAND_66_defconfig | 2 +- .../{MPC8313ERDB.h => MPC8313ERDB_NAND.h} | 61 +- include/configs/MPC8313ERDB_NOR.h | 591 ++++++++++++++++++ 8 files changed, 633 insertions(+), 54 deletions(-) rename include/configs/{MPC8313ERDB.h => MPC8313ERDB_NAND.h} (90%) create mode 100644 include/configs/MPC8313ERDB_NOR.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 29d84f363d1..ede98c70da7 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -29,8 +29,14 @@ config TARGET_MPC8308RDB select ARCH_MPC8308 select SYS_FSL_ERRATUM_ESDHC111
-config TARGET_MPC8313ERDB - bool "Support MPC8313ERDB" +config TARGET_MPC8313ERDB_NOR + bool "Support MPC8313ERDB_NOR" + select ARCH_MPC8313 + select BOARD_EARLY_INIT_F + select SUPPORT_SPL + +config TARGET_MPC8313ERDB_NAND + bool "Support MPC8313ERDB_NAND" select ARCH_MPC8313 select BOARD_EARLY_INIT_F select SUPPORT_SPL diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig index 145608feab2..b6332a1368b 100644 --- a/board/freescale/mpc8313erdb/Kconfig +++ b/board/freescale/mpc8313erdb/Kconfig @@ -1,4 +1,4 @@ -if TARGET_MPC8313ERDB +if TARGET_MPC8313ERDB_NOR
config SYS_BOARD default "mpc8313erdb" @@ -7,6 +7,19 @@ config SYS_VENDOR default "freescale"
config SYS_CONFIG_NAME - default "MPC8313ERDB" + default "MPC8313ERDB_NOR" + +endif + +if TARGET_MPC8313ERDB_NAND + +config SYS_BOARD + default "mpc8313erdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8313ERDB_NAND"
endif diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 3bb680c2179..cacb5ba0774 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -1,7 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_MPC83xx=y -CONFIG_TARGET_MPC8313ERDB=y +CONFIG_TARGET_MPC8313ERDB_NOR=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index bb26a9e3813..6b29c2e5c9d 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -1,7 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_MPC83xx=y -CONFIG_TARGET_MPC8313ERDB=y +CONFIG_TARGET_MPC8313ERDB_NOR=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index ab28a78cbe5..4c8957c2742 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -3,7 +3,7 @@ CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_MPC83xx=y -CONFIG_TARGET_MPC8313ERDB=y +CONFIG_TARGET_MPC8313ERDB_NAND=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index a454ec67fc6..ff3d0dc84e9 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -3,7 +3,7 @@ CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_MPC83xx=y -CONFIG_TARGET_MPC8313ERDB=y +CONFIG_TARGET_MPC8313ERDB_NAND=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB_NAND.h similarity index 90% rename from include/configs/MPC8313ERDB.h rename to include/configs/MPC8313ERDB_NAND.h index c5a8065d6a4..976b6854e49 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -15,7 +15,6 @@ #define CONFIG_E300 1 #define CONFIG_MPC8313ERDB 1
-#ifdef CONFIG_NAND #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" @@ -40,8 +39,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #endif
-#endif /* CONFIG_NAND */ - #ifndef CONFIG_SYS_MONITOR_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif @@ -70,7 +67,7 @@
#define CONFIG_SYS_IMMR 0xE0000000
-#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_BUILD) #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR #endif
@@ -184,11 +181,11 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | OR_GPCM_XACS \ | OR_GPCM_SCY_9 \ | OR_GPCM_EHTR \ @@ -235,7 +232,7 @@ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
/* drivers/mtd/nand/raw/nand.c */ -#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL_BUILD) #define CONFIG_SYS_NAND_BASE 0xFFF00000 #else #define CONFIG_SYS_NAND_BASE 0xE2800000 @@ -248,12 +245,12 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_NAND_BASE \ | BR_DECC_CHK_GEN /* Use HW ECC */ \ | BR_PS_8 /* 8 bit port */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_NAND_OR_PRELIM \ +#define CONFIG_SYS_OR0_PRELIM \ (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ | OR_FCM_CSCT \ | OR_FCM_CST \ @@ -263,17 +260,9 @@ | OR_FCM_EHTR) /* 0xFFFF8396 */
-#ifdef CONFIG_NAND -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM -#else -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM -#endif +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) @@ -407,25 +396,12 @@ /* * Environment */ -#if defined(CONFIG_NAND) - #define CONFIG_ENV_OFFSET (512 * 1024) - #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE - #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE - #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) - #define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) -#elif !defined(CONFIG_SYS_RAMBOOT) - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 - -/* Address and size of Redundant Environment Sector */ -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif +#define CONFIG_ENV_OFFSET (512 * 1024) +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -499,17 +475,10 @@ HRCWH_TSEC2M_IN_RGMII |\ HRCWH_BIG_ENDIAN)
-#ifdef CONFIG_NAND #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ HRCWH_FROM_0XFFF00100 |\ HRCWH_ROM_LOC_NAND_SP_8BIT |\ HRCWH_RL_EXT_NAND) -#else -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY) -#endif
/* System IO Config */ #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h new file mode 100644 index 00000000000..81e92fb939f --- /dev/null +++ b/include/configs/MPC8313ERDB_NOR.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. + */ +/* + * mpc8313epb board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC8313ERDB 1 + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_FSL_ELBC 1 + +/* + * On-board devices + * + * TSEC1 is VSC switch + * TSEC2 is SoC TSEC + */ +#define CONFIG_VSC7385_ENET +#define CONFIG_TSEC2 + +#ifdef CONFIG_SYS_66MHZ +#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ +#elif defined(CONFIG_SYS_33MHZ) +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#else +#error Unknown oscillator frequency. +#endif + +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +#define CONFIG_SYS_IMMR 0xE0000000 + +#define CONFIG_SYS_MEMTEST_START 0x00001000 +#define CONFIG_SYS_MEMTEST_END 0x07f00000 + +/* Early revs of this board will lock up hard when attempting + * to access the PMC registers, unless a JTAG debugger is + * connected, or some resistor modifications are made. + */ +#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 + +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +/* + * Device configurations + */ + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + +#define CONFIG_TSEC1 + +/* The flash address and size of the VSC7385 firmware image */ +#define CONFIG_VSC7385_IMAGE 0xFE7FE000 +#define CONFIG_VSC7385_IMAGE_SIZE 8192 + +#endif + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE + +/* + * Manually set up DDR parameters, as this board does not + * seem to have the SPD connected to I2C. + */ +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (10 << TIMING_CFG1_REFREC_SHIFT) \ + | (3 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x3835a322 */ +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (5 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x129048c6 */ /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x05100500 */ +#if defined(CONFIG_DDR_2T_TIMING) +#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32 \ + | SDRAM_CFG_2T_EN) + /* 0x43088000 */ +#else +#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_DBW_32) + /* 0x43080000 */ +#endif +#define CONFIG_SYS_SDRAM_CFG2 0x00401000 +/* set burst length to 8 for 32-bit data path */ +#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0632 << SDRAM_MODE_SD_SHIFT)) + /* 0x44480632 */ +#define CONFIG_SYS_DDR_MODE_2 0x8000C000 + +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /*0x02000000*/ +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_9 \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD) + /* 0xFF006FF7 TODO SLOW 16 MB flash size */ + /* window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE + /* 16 MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ + !defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + */ +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 +#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ + | (0xFF << LBCR_BMT_SHIFT) \ + | 0xF) /* 0x0004ff0f */ + + /* LB refresh timer prescal, 266MHz/32 */ +#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ + +/* drivers/mtd/nand/nand.c */ +#define CONFIG_SYS_NAND_BASE 0xE2800000 + +#define CONFIG_MTD_PARTITION + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 +#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ + | BR_DECC_CHK_GEN /* Use HW ECC */ \ + | BR_PS_8 /* 8 bit port */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR1_PRELIM \ + (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) + /* 0xFFFF8396 */ + +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM + +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM + +/* local bus write LED / read status buffer (BCSR) mapping */ +#define CONFIG_SYS_BCSR_ADDR 0xFA000000 +#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ + /* map at 0xFA000000 on LCS3 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ + | BR_PS_8 /* 8 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + /* 0xFA000801 */ +#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFFFF8FF7 */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + + /* VSC7385 Base address on LCS2 */ +#define CONFIG_SYS_VSC7385_BASE 0xF0000000 +#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ + | BR_PS_8 /* 8 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_SETA \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFFFE09FF */ + + /* Access window base at VSC7385 base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) + +#endif + +#define CONFIG_MPC83XX_GPIO 1 + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +/* + * TSEC + */ + +#define CONFIG_GMII /* MII PHY management */ + +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x1c +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_TSEC2 +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define TSEC2_PHY_ADDR 4 +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHYIDX 0 +#endif + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * Environment + */ +#if !defined(CONFIG_SYS_RAMBOOT) + #define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ + #define CONFIG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Command line configuration. + */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#ifdef CONFIG_SYS_66MHZ + +/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ +/* 0x62040000 */ +#define CONFIG_SYS_HRCW_LOW (\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDRCM |\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_2X1) + +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) + +#elif defined(CONFIG_SYS_33MHZ) + +/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ +/* 0x65040000 */ +#define CONFIG_SYS_HRCW_LOW (\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDRCM |\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_5X1 |\ + HRCWL_CORE_TO_CSB_2X1) + +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) + +#endif + +#define CONFIG_SYS_HRCW_HIGH_BASE (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN) + +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY) + +/* System IO Config */ +#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ + /* Enable Internal USB Phy and GPIO on LCD Connector */ +#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) + +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR @ 0x00000000 */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + +/* PCI @ 0x80000000 */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + +/* PCI2 not supported on 8313 */ +#define CONFIG_SYS_IBAT3L (0) +#define CONFIG_SYS_IBAT3U (0) +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_NETDEV "eth1" + +#define CONFIG_HOSTNAME "mpc8313erdb" +#define CONFIG_ROOTPATH "/nfs/root/path" +#define CONFIG_BOOTFILE "uImage" + /* U-Boot image on TFTP server */ +#define CONFIG_UBOOTPATH "u-boot.bin" +#define CONFIG_FDTFILE "mpc8313erdb.dtb" + + /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" CONFIG_NETDEV "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize\0" \ + "fdtaddr=780000\0" \ + "fdtfile=" CONFIG_FDTFILE "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ + "$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#endif /* __CONFIG_H */
CONFIG_TARGET_VME8349 can replace CONFIG_VME8349. Hence, replace CONFIG_VME8349 with CONFIG_TARGET_VME8349, and remove CONFIG_VME8349.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- drivers/pci/pci_auto.c | 2 +- drivers/pci/pci_auto_old.c | 2 +- include/configs/vme8349.h | 1 - 3 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index a673d8ae136..f5e46842bf6 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -359,7 +359,7 @@ int dm_pciauto_config_device(struct udevice *dev) PCI_DEV(dm_pci_get_bdf(dev))); break; #endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c index 90c22a08cbc..6ab1b3b43fc 100644 --- a/drivers/pci/pci_auto_old.c +++ b/drivers/pci/pci_auto_old.c @@ -376,7 +376,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) PCI_DEV(dev)); break; #endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 56955501309..fe570abf8f7 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -28,7 +28,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
vme8349.h contains two separate boards: The vme8349 itself, and the caddy2 board. The caddy2 board is chosen by setting certain config variables. Create a proper config file for the caddy2 board to make Kconfig migration easier.
Furthermore, simplify the vme8349 and caddy2 configs by keeping only the options necessary for each board.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Combined config creation and simplification patches
--- arch/powerpc/cpu/mpc83xx/Kconfig | 4 + board/esd/vme8349/Kconfig | 13 + board/esd/vme8349/vme8349.c | 8 +- configs/caddy2_defconfig | 3 +- drivers/pci/pci_auto.c | 3 +- drivers/pci/pci_auto_old.c | 3 +- include/configs/caddy2.h | 512 +++++++++++++++++++++++++++++++ include/configs/vme8349.h | 29 -- 8 files changed, 538 insertions(+), 37 deletions(-) create mode 100644 include/configs/caddy2.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index ede98c70da7..65f4583ffea 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -24,6 +24,10 @@ config TARGET_VME8349 bool "Support vme8349" select ARCH_MPC8349
+config TARGET_CADDY2 + bool "Support caddy2" + select ARCH_MPC8349 + config TARGET_MPC8308RDB bool "Support MPC8308RDB" select ARCH_MPC8308 diff --git a/board/esd/vme8349/Kconfig b/board/esd/vme8349/Kconfig index b8d9432dcc9..ef2af40f7e8 100644 --- a/board/esd/vme8349/Kconfig +++ b/board/esd/vme8349/Kconfig @@ -10,3 +10,16 @@ config SYS_CONFIG_NAME default "vme8349"
endif + +if TARGET_CADDY2 + +config SYS_BOARD + default "vme8349" + +config SYS_VENDOR + default "esd" + +config SYS_CONFIG_NAME + default "caddy2" + +endif diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index 45ad3a83ee8..a46d0b6da63 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -60,7 +60,7 @@ int dram_init(void)
int checkboard(void) { -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 puts("Board: esd VME-CADDY/2\n"); #else puts("Board: esd VME-CPU/8349\n"); @@ -69,7 +69,7 @@ int checkboard(void) return 0; }
-#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 int board_eth_init(bd_t *bis) { return pci_eth_init(bis); @@ -102,7 +102,7 @@ int misc_init_r() * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2 * and VME-CADDY/2) have different SDRAM configurations. */ -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 #define SMALL_RAM 0xff #define LARGE_RAM 0x00 #else @@ -165,7 +165,7 @@ static spd_eeprom_t default_spd_eeprom = { SPD_VAL(0x7e, 0x1d), /* 63 */ { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' }, SPD_VAL(0x00, 0x00), /* 72 */ -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 { "vme-caddy/2 ram " } #else { "vme-cpu/2 ram " } diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 5fec4f8d499..fe0c34fc61a 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -1,10 +1,9 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_MPC83xx=y -CONFIG_TARGET_VME8349=y +CONFIG_TARGET_CADDY2=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="CADDY2" CONFIG_BOOTDELAY=6 CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index f5e46842bf6..1a3bf708347 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -359,7 +359,8 @@ int dm_pciauto_config_device(struct udevice *dev) PCI_DEV(dm_pci_get_bdf(dev))); break; #endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \ + !defined(CONFIG_TARGET_CADDY2) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c index 6ab1b3b43fc..b566705c9d9 100644 --- a/drivers/pci/pci_auto_old.c +++ b/drivers/pci/pci_auto_old.c @@ -376,7 +376,8 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) PCI_DEV(dev)); break; #endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) +#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \ + !defined(CONFIG_TARGET_CADDY2) case PCI_CLASS_BRIDGE_OTHER: /* * The host/PCI bridge 1 seems broken in 8349 - it presents diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h new file mode 100644 index 00000000000..a7bbbbdd0b3 --- /dev/null +++ b/include/configs/caddy2.h @@ -0,0 +1,512 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * esd vme8349 U-Boot configuration file + * Copyright (c) 2008, 2009 esd gmbh Hannover Germany + * + * (C) Copyright 2006-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * reinhard.arlt@esd-electronics.de + * Based on the MPC8349EMDS config. + */ + +/* + * vme8349 board configuration file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ + +/* Don't enable PCI2 on vme834x - it doesn't exist physically. */ +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ + +#define CONFIG_PCI_66M +#ifdef CONFIG_PCI_66M +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_PCI_66M +#define CONFIG_SYS_CLK_FREQ 66000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 +#else +#define CONFIG_SYS_CLK_FREQ 33000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 +#endif +#endif + +#define CONFIG_SYS_IMMR 0xE0000000 + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00100000 + +/* + * DDR Setup + */ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_READ_SPD vme8349_read_spd +#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ + | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) +#define CONFIG_DDR_2T_TIMING +#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x80080001 */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16bit */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) /* valid */ + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xffc06ff7 */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) + +#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ + | BR_PS_32 \ + | BR_MS_GPCM \ + | BR_V) + /* 0xF0001801 */ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ + | OR_GPCM_SETA) + /* 0xfffc0208 */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: no DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ + +#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ + +/* TSEC */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 +#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE +#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define PCI_64BIT +#define PCI_ONE_PCI1 +#if defined(PCI_64BIT) +#undef PCI_ALL_PCI1 +#undef PCI_TWO_PCI1 +#undef PCI_ONE_PCI1 +#endif + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0xFIXME +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_GMII /* MII PHY management */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_PHY_M88E1111 +#define TSEC1_PHY_ADDR 0x08 +#define TSEC2_PHY_ADDR 0x10 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#ifndef CONFIG_SYS_RAMBOOT + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CONFIG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Command line configuration. + */ +#define CONFIG_SYS_RTC_BUS_NUM 0x01 +#define CONFIG_SYS_I2C_RTC_ADDR 0x32 +#define CONFIG_RTC_RX8025 + +/* Pass Ethernet MAC to VxWorks */ +#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) + +#if defined(PCI_64BIT) +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII) +#else +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII) +#endif + +/* System IO Config */ +#define CONFIG_SYS_SICRH 0 +#define CONFIG_SYS_SICRL SICRL_LDP_A + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) + +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_SYS_GPIO1_PRELIM +#define CONFIG_SYS_GPIO1_DIR 0x00100000 +#define CONFIG_SYS_GPIO1_DAT 0x00100000 + +#define CONFIG_SYS_GPIO2_PRELIM +#define CONFIG_SYS_GPIO2_DIR 0x78900000 +#define CONFIG_SYS_GPIO2_DAT 0x70100000 + +#define CONFIG_HIGH_BATS /* High BATs supported */ + +/* DDR @ 0x00000000 */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#else +#define CONFIG_SYS_IBAT1L (0) +#define CONFIG_SYS_IBAT1U (0) +#define CONFIG_SYS_IBAT2L (0) +#define CONFIG_SYS_IBAT2U (0) +#endif + +#ifdef CONFIG_MPC83XX_PCI2 +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#else +#define CONFIG_SYS_IBAT3L (0) +#define CONFIG_SYS_IBAT3U (0) +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) +#endif + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ + BATU_VS | BATU_VP) + +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#if (CONFIG_SYS_DDR_SIZE == 512) +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ + BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ + BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#endif + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_HOSTNAME "VME8349" +#define CONFIG_ROOTPATH "/tftpboot/rootfs" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=vme8349\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ + "update=protect off fff00000 fff3ffff; " \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "upd=run load update\0" \ + "fdtaddr=780000\0" \ + "fdtfile=vme8349.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#ifndef __ASSEMBLY__ +int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index fe570abf8f7..6c3ad76e524 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -17,13 +17,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-/* - * Top level Makefile configuration choices - */ -#ifdef CONFIG_CADDY2 -#define VME_CADDY2 -#endif - /* * High Level Configuration Options */ @@ -91,27 +84,6 @@ /* * FLASH on the Local Bus */ -#ifdef VME_CADDY2 -#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16bit */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) /* valid */ - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffc06ff7 */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) -#else #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ @@ -131,7 +103,6 @@ /* 0xf8006ff7 */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) -#endif
#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
The LSDMR_* macros are used to configure the system bus on MPC83xx.
A few of the possible LSDMR_* macros were never defined in the respective include files. This renders the SDRAM support on the MPC8349EMDS unusable, because it uses these undefined macros.
To make the SDRAM option work, introduce these macros into the proper config file.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- arch/powerpc/include/asm/fsl_lbc.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 3528acd627d..bf352d9a561 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -428,14 +428,17 @@ void lbc_sdram_init(void); #define LSDMR_BSMA1516 (3 << (31 - 10)) #define LSDMR_BSMA1617 (4 << (31 - 10)) #define LSDMR_RFCR5 (3 << (31 - 16)) +#define LSDMR_RFCR8 (5 << (31 - 16)) #define LSDMR_RFCR16 (7 << (31 - 16)) #define LSDMR_PRETOACT3 (3 << (31 - 19)) +#define LSDMR_PRETOACT6 (5 << (31 - 19)) #define LSDMR_PRETOACT7 (7 << (31 - 19)) #define LSDMR_ACTTORW3 (3 << (31 - 22)) #define LSDMR_ACTTORW7 (7 << (31 - 22)) #define LSDMR_ACTTORW6 (6 << (31 - 22)) #define LSDMR_BL8 (1 << (31 - 23)) #define LSDMR_WRC2 (2 << (31 - 27)) +#define LSDMR_WRC3 (3 << (31 - 27)) #define LSDMR_WRC4 (0 << (31 - 27)) #define LSDMR_BUFCMD (1 << (31 - 29)) #define LSDMR_CL3 (3 << (31 - 31))
The MPC8349EMDS config file contains config options to enable SDRAM support. To keep this ability after the Kconfig migration, create a new MPC8349EMDS_SDRAM board that enables the SDRAM support and remove the SDRAM support from the original board.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Combined config creation and simplification patches
--- arch/powerpc/cpu/mpc83xx/Kconfig | 8 + board/freescale/mpc8349emds/Kconfig | 13 + configs/MPC8349EMDS_SDRAM_defconfig | 27 + include/configs/MPC8349EMDS.h | 76 --- include/configs/MPC8349EMDS_SDRAM.h | 731 ++++++++++++++++++++++++++++ 5 files changed, 779 insertions(+), 76 deletions(-) create mode 100644 configs/MPC8349EMDS_SDRAM_defconfig create mode 100644 include/configs/MPC8349EMDS_SDRAM.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 65f4583ffea..0ce1aad6d03 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -67,6 +67,14 @@ config TARGET_MPC8349EMDS select SYS_FSL_DDR_BE select SYS_FSL_HAS_DDR2
+config TARGET_MPC8349EMDS_SDRAM + bool "Support MPC8349EMDS_SDRAM" + select ARCH_MPC8349 + select BOARD_EARLY_INIT_F + select SYS_FSL_DDR + select SYS_FSL_DDR_BE + select SYS_FSL_HAS_DDR2 + config TARGET_MPC8349ITX bool "Support MPC8349ITX" select ARCH_MPC8349 diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig index 51f0b34f398..d1541180799 100644 --- a/board/freescale/mpc8349emds/Kconfig +++ b/board/freescale/mpc8349emds/Kconfig @@ -10,3 +10,16 @@ config SYS_CONFIG_NAME default "MPC8349EMDS"
endif + +if TARGET_MPC8349EMDS_SDRAM + +config SYS_BOARD + default "mpc8349emds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8349EMDS_SDRAM" + +endif diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig new file mode 100644 index 00000000000..2607dfa4f33 --- /dev/null +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -0,0 +1,27 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8349EMDS_SDRAM=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +# CONFIG_MMC is not set +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_PHY_MARVELL=y +CONFIG_NETDEVICES=y +CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_MPC8XXX_SPI=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 93de2cc1c07..fe2b81b905b 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -218,82 +218,6 @@ #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000
-/* - * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. - * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM - */ -#undef CONFIG_SYS_LB_SDRAM - -#ifdef CONFIG_SYS_LB_SDRAM -/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ - | BR_PS_32 /* 32-bit port */ \ - | BR_MS_SDRAM /* MSEL = SDRAM */ \ - | BR_V) /* Valid */ - /* 0xF0001861 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 - */ - -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ - | OR_SDRAM_XAM \ - | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ - | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ - | OR_SDRAM_EAD) - /* 0xFC006901 */ - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ - | LSDMR_BSMA1516 \ - | LSDMR_RFCR8 \ - | LSDMR_PRETOACT6 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC3 \ - | LSDMR_CL3) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) -#endif - /* * Serial Port */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h new file mode 100644 index 00000000000..b610b555a75 --- /dev/null +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -0,0 +1,731 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +/* + * mpc8349emds board configuration file + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ + +#define CONFIG_PCI_66M +#ifdef CONFIG_PCI_66M +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#endif + +#ifdef CONFIG_PCISLAVE +#define CONFIG_83XX_PCICLK 66666666 /* in Hz */ +#endif /* CONFIG_PCISLAVE */ + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_PCI_66M +#define CONFIG_SYS_CLK_FREQ 66000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 +#else +#define CONFIG_SYS_CLK_FREQ 33000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 +#endif +#endif + +#define CONFIG_SYS_IMMR 0xE0000000 + +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00100000 + +/* + * DDR Setup + */ +#define CONFIG_DDR_ECC /* support DDR ECC function */ +#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ + +/* + * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver + * unselect it to use old spd_sdram.c + */ +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x52 +#define SPD_EEPROM_ADDRESS2 0x51 +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ + | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#undef CONFIG_DDR_2T_TIMING + +/* + * DDRCDR - DDR Control Driver Register + */ +#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 + +#if defined(CONFIG_SPD_EEPROM) +/* + * Determine DDR configuration from I2C interface. + */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#else +/* + * Manually set up DDR parameters + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#if defined(CONFIG_DDR_II) +#define CONFIG_SYS_DDRCDR 0x80080001 +#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 +#define CONFIG_SYS_DDR_TIMING_0 0x00220802 +#define CONFIG_SYS_DDR_TIMING_1 0x38357322 +#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_MODE 0x47d00432 +#define CONFIG_SYS_DDR_MODE2 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 +#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#else +#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) +#define CONFIG_SYS_DDR_TIMING_1 0x36332321 +#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ + +#if defined(CONFIG_DDR_32BIT) +/* set burst length to 8 for 32-bit data path */ + /* DLL,normal,seq,4/2.5, 8 burst len */ +#define CONFIG_SYS_DDR_MODE 0x00000023 +#else +/* the default burst length is 4 - for 64-bit data path */ + /* DLL,normal,seq,4/2.5, 4 burst len */ +#define CONFIG_SYS_DDR_MODE 0x00000022 +#endif +#endif +#endif + +/* + * SDRAM on the Local Bus + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + + /* window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +/* + * BCSR register on local bus 32KB, 8-bit wide for MDS config reg + */ +#define CONFIG_SYS_BCSR 0xE2400000 + /* Access window base at BCSR base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) + /* 0x00000801 */ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_CLEAR \ + | OR_GPCM_EHTR_CLEAR) + /* 0xFFFFE8F0 */ + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. + */ + +/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 + */ + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ + | BR_PS_32 /* 32-bit port */ \ + | BR_MS_SDRAM /* MSEL = SDRAM */ \ + | BR_V) /* Valid */ + /* 0xF0001861 */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) + +/* + * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 + */ + +#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ + | OR_SDRAM_XAM \ + | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ + | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ + | OR_SDRAM_EAD) + /* 0xFC006901 */ + + /* LB sdram refresh timer, about 6us */ +#define CONFIG_SYS_LBC_LSRT 0x32000000 + /* LB refresh timer prescal, 266MHz/32 */ +#define CONFIG_SYS_LBC_MRTPR 0x20000000 + +#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ + | LSDMR_BSMA1516 \ + | LSDMR_RFCR8 \ + | LSDMR_PRETOACT6 \ + | LSDMR_ACTTORW3 \ + | LSDMR_BL8 \ + | LSDMR_WRC3 \ + | LSDMR_CL3) + +/* + * SDRAM Controller configuration sequence. + */ +#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) +#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) +#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } + +/* SPI */ +#undef CONFIG_SOFT_SPI /* SPI bit-banged */ + +/* GPIOs. Used as SPI chip selects */ +#define CONFIG_SYS_GPIO1_PRELIM +#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ +#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ + +/* TSEC */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) + +/* USB */ +#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 +#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE +#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define PCI_ONE_PCI1 +#if defined(PCI_64BIT) +#undef PCI_ALL_PCI1 +#undef PCI_TWO_PCI1 +#undef PCI_ONE_PCI1 +#endif + +#define CONFIG_83XX_PCI_STREAMING + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * Environment + */ +#ifndef CONFIG_SYS_RAMBOOT + #define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CONFIG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * Command line configuration. + */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#if 1 /*528/264*/ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*396/132*/ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_3X1) +#elif 0 /*264/132*/ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*132/132*/ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#elif 0 /*264/264 */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#endif + +#ifdef CONFIG_PCISLAVE +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII) +#else +#if defined(PCI_64BIT) +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII) +#else +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII) +#endif /* PCI_64BIT */ +#endif /* CONFIG_PCISLAVE */ + +/* + * System performance + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ +#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ +#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ +#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ +#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ + +/* System IO Config */ +#define CONFIG_SYS_SICRH 0 +#define CONFIG_SYS_SICRL SICRL_LDP_A + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ + | HID0_ENABLE_INSTRUCTION_CACHE) + +/* #define CONFIG_SYS_HID0_FINAL (\ + HID0_ENABLE_INSTRUCTION_CACHE |\ + HID0_ENABLE_M_BIT |\ + HID0_ENABLE_ADDRESS_BROADCAST) */ + +#define CONFIG_SYS_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR @ 0x00000000 */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ + | BATL_PP_RW \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + +/* PCI @ 0x80000000 */ +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ + | BATL_PP_RW \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#else +#define CONFIG_SYS_IBAT1L (0) +#define CONFIG_SYS_IBAT1U (0) +#define CONFIG_SYS_IBAT2L (0) +#define CONFIG_SYS_IBAT2U (0) +#endif + +#ifdef CONFIG_MPC83XX_PCI2 +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ + | BATL_PP_RW \ + | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) +#else +#define CONFIG_SYS_IBAT3L (0) +#define CONFIG_SYS_IBAT3U (0) +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) +#endif + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ + | BATL_PP_RW \ + | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CONFIG_SYS_IBAT6L (0xF0000000 \ + | BATL_PP_RW \ + | BATL_MEMCOHERENCE \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT6U (0xF0000000 \ + | BATU_BL_256M \ + | BATU_VS \ + | BATU_VP) + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_HOSTNAME "mpc8349emds" +#define CONFIG_ROOTPATH "/nfsroot/rootfs" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=mpc8349emds\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ + "update=protect off fe000000 fe03ffff; " \ + "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ + "upd=run load update\0" \ + "fdtaddr=780000\0" \ + "fdtfile=mpc834x_mds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ + "$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */
The mpc8315erdb has the option of either configuring the eLBC (enhanced local system bus) such that
* NOR flash is the first memory bank, and NAND flash is the second memory bank, or * NAND flash is the first memory bank, and NOR flash is the second memory bank,
by using CONFIG_SYS_NOR_{BR,OR}_PRELIM and CONFIG_SYS_NAND_{BR,OR}_PRELIM for defining CONFIG_SYS_{BR,OR}{0,1}_PRELIM.
After Kconfig migration, replacing some lines in the defconfig will have the same effect.
Hence, we will not create distinct ve8313_{NOR,NAND} configs for such a small change.
Instead, fix the current default (NOR first, NAND second), and unroll the CONFIG_SYS_NAND_{BR,OR}_PRELIM options. This will ease the Kconfig migration.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- include/configs/MPC8315ERDB.h | 40 +++++++++++++++++------------------ 1 file changed, 19 insertions(+), 21 deletions(-)
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index b8506321af3..a2b5b07ea9c 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -191,20 +191,6 @@ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -236,13 +222,26 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ | BR_DECC_CHK_GEN /* Use HW ECC */ \ | BR_PS_8 /* 8 bit port */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_NAND_OR_PRELIM \ - (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ +#define CONFIG_SYS_OR1_PRELIM \ + (OR_AM_32KB \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -251,10 +250,9 @@ | OR_FCM_EHTR) /* 0xFFFF8396 */
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
The ve8313 has the option of either configuring the eLBC (enhanced local system bus) such that
* NOR flash is the first memory bank, and NAND flash is the second memory bank, or * NAND flash is the first memory bank, and NOR flash is the second memory bank,
by using CONFIG_SYS_NOR_{BR,OR}_PRELIM and CONFIG_SYS_NAND_{BR,OR}_PRELIM for defining CONFIG_SYS_{BR,OR}{0,1}_PRELIM.
After Kconfig migration, replacing some lines in the defconfig will have the same effect.
Hence, we will not create distinct ve8313_{NOR,NAND} configs for such a small change.
Instead, fix the current default (NOR first, NAND second), and unroll the CONFIG_SYS_NAND_{BR,OR}_PRELIM options. This will ease the Kconfig migration
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- include/configs/ve8313.h | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-)
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 791eac363bd..87fbe36640b 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -115,18 +115,6 @@ #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV4 \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EAD) - /* 0xfe000c55 */ - #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
@@ -172,24 +160,35 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV4 \ + | OR_GPCM_SCY_5 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EAD) + /* 0xfe000c55 */ + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ | BR_PS_8 \ | BR_DECC_CHK_GEN \ | BR_MS_FCM \ | BR_V) /* valid */ /* 0x61000c21 */ -#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | OR_FCM_BCTLD \ | OR_FCM_CHT \ | OR_FCM_SCY_2 \ | OR_FCM_RST \ - | OR_FCM_TRLX) - /* 0xffff90ac */ + | OR_FCM_TRLX) /* 0xffff90ac */
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Use the proper CONFIG_TARGET_MPC832XEMDS Kconfig option to replace the CONFIG_MPC832XEMDS ad-hoc config option.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Removed config option from whitelist
--- board/freescale/common/pq-mds-pib.c | 6 +++--- include/configs/MPC832XEMDS.h | 1 - scripts/config_whitelist.txt | 1 - 3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index d152a7821f4..ae660398575 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -36,7 +36,7 @@ int pib_init(void) i2c_write(0x26, 0x6, 1, &val8, 1); val8 = 0x34; i2c_write(0x26, 0x7, 1, &val8, 1); -#if defined(CONFIG_MPC832XEMDS) +#if defined(CONFIG_TARGET_MPC832XEMDS) val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ #else val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */ @@ -55,7 +55,7 @@ int pib_init(void)
eieio();
-#if defined(CONFIG_MPC832XEMDS) +#if defined(CONFIG_TARGET_MPC832XEMDS) printf("PCI 32bit bus on PMC2 &PMC3\n"); #else printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n"); @@ -76,7 +76,7 @@ int pib_init(void) eieio();
printf("QOC3 ATM card on PMC0\n"); -#elif defined(CONFIG_MPC832XEMDS) +#elif defined(CONFIG_TARGET_MPC832XEMDS) val8 = 0; i2c_write(0x26, 0x7, 1, &val8, 1); val8 = 0xf7; diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 0bb7db9bc37..4cb595bb8e5 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -11,7 +11,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
/* * System Clock Setup diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 6f031c22033..cae3f97c5ce 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1250,7 +1250,6 @@ CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB -CONFIG_MPC832XEMDS CONFIG_MPC8349ITX CONFIG_MPC837XEMDS CONFIG_MPC837XERDB
Use the proper CONFIG_TARGET_MPC8349ITX Kconfig option to replace the CONFIG_MPC8349ITX ad-hoc config option.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Removed config option from whitelist
--- board/freescale/mpc8349itx/mpc8349itx.c | 2 +- configs/MPC8349ITX_LOWBOOT_defconfig | 1 - configs/MPC8349ITX_defconfig | 1 - include/configs/MPC8349ITX.h | 4 ++-- scripts/config_whitelist.txt | 1 - 5 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 3bdec1c4005..d90553384f6 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -152,7 +152,7 @@ int dram_init(void)
int checkboard(void) { -#ifdef CONFIG_MPC8349ITX +#ifdef CONFIG_TARGET_MPC8349ITX puts("Board: Freescale MPC8349E-mITX\n"); #else puts("Board: Freescale MPC8349E-mITX-GP\n"); diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 51667235487..22225e3ad6e 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -4,7 +4,6 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX" CONFIG_BOOTDELAY=6 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200" diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 55e593c1150..7f9b9cb283d 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -4,7 +4,6 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX" CONFIG_BOOTDELAY=6 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200" diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 496780d80c0..5877279adaf 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -54,7 +54,7 @@ * On-board devices */
-#ifdef CONFIG_MPC8349ITX +#ifdef CONFIG_TARGET_MPC8349ITX /* The CF card interface on the back of the board */ #define CONFIG_COMPACT_FLASH #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ @@ -642,7 +642,7 @@ boards, we say we have two, but don't display a message if we find only one. */ /* U-Boot image on TFTP server */ #define CONFIG_UBOOTPATH "u-boot.bin"
-#ifdef CONFIG_MPC8349ITX +#ifdef CONFIG_TARGET_MPC8349ITX #define CONFIG_FDTFILE "mpc8349emitx.dtb" #else #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index cae3f97c5ce..575673f6cd3 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1250,7 +1250,6 @@ CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB -CONFIG_MPC8349ITX CONFIG_MPC837XEMDS CONFIG_MPC837XERDB CONFIG_MPC83XX_GPIO
Use the proper CONFIG_TARGET_HRCON Kconfig option to replace the CONFIG_HRCON ad-hoc config option.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Combined config creation and simplification patches * Removed config option from whitelist
--- board/gdsys/common/Makefile | 2 +- board/gdsys/mpc8308/Makefile | 2 +- include/configs/hrcon.h | 1 - include/gdsys_fpga.h | 2 +- scripts/config_whitelist.txt | 1 - 5 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index af9058a5d77..67d2b310b30 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -10,7 +10,7 @@ obj-$(CONFIG_IO64) += miiphybb.o obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o -obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o +obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o obj-$(CONFIG_STRIDER) += fanctrl.o obj-$(CONFIG_STRIDER_CON) += osd.o diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile index 60d22325738..f29376fc9ed 100644 --- a/board/gdsys/mpc8308/Makefile +++ b/board/gdsys/mpc8308/Makefile @@ -4,5 +4,5 @@ # Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
obj-y := mpc8308.o sdram.o -obj-$(CONFIG_HRCON) += hrcon.o +obj-$(CONFIG_TARGET_HRCON) += hrcon.o obj-$(CONFIG_STRIDER) += strider.o diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 23ed4e54c72..cd5e883b7a1 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -13,7 +13,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_HRCON 1 /* HRCON board specific */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index db4424d3f8a..e9fb4b88b5e 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -161,7 +161,7 @@ struct ihs_fpga { }; #endif
-#if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP) +#if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP) struct ihs_fpga { u16 reflection_low; /* 0x0000 */ u16 versions; /* 0x0002 */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 575673f6cd3..9de1666d7f9 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -908,7 +908,6 @@ CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP -CONFIG_HRCON CONFIG_HRCON_DH CONFIG_HRCON_FANS CONFIG_HSMMC2_8BIT
Use the proper CONFIG_TARGET_STRIDER Kconfig option to replace the CONFIG_STRIDER ad-hoc config option.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Removed config option from whitelist
--- board/gdsys/common/Makefile | 4 ++-- board/gdsys/mpc8308/Makefile | 2 +- include/configs/strider.h | 1 - scripts/config_whitelist.txt | 1 - 4 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 67d2b310b30..9090933e345 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -11,8 +11,8 @@ obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o -obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o -obj-$(CONFIG_STRIDER) += fanctrl.o +obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o +obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o obj-$(CONFIG_STRIDER_CON) += osd.o obj-$(CONFIG_STRIDER_CON_DP) += osd.o
diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile index f29376fc9ed..dc579479f95 100644 --- a/board/gdsys/mpc8308/Makefile +++ b/board/gdsys/mpc8308/Makefile @@ -5,4 +5,4 @@
obj-y := mpc8308.o sdram.o obj-$(CONFIG_TARGET_HRCON) += hrcon.o -obj-$(CONFIG_STRIDER) += strider.o +obj-$(CONFIG_TARGET_STRIDER) += strider.o diff --git a/include/configs/strider.h b/include/configs/strider.h index 89e0610871e..c42fe8c3ece 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -13,7 +13,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_STRIDER 1 /* STRIDER board specific */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 9de1666d7f9..49fc2f9f83e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1938,7 +1938,6 @@ CONFIG_STANDALONE_LOAD_ADDR CONFIG_STATIC_BOARD_REV CONFIG_STD_DEVICES_SETTINGS CONFIG_STM32_FLASH -CONFIG_STRIDER CONFIG_STRIDER_CON CONFIG_STRIDER_CON_DP CONFIG_STRIDER_CPU
CONFIG_MPC8313ERDB is unused, and TARGET_MPC8313ERDB_NAND/TARGET_MPC8313ERDB_NOR Kconfig could replace it.
Hence, get rid of CONFIG_MPC8313ERDB.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Removed config option from whitelist
--- include/configs/MPC8313ERDB_NAND.h | 1 - include/configs/MPC8313ERDB_NOR.h | 1 - scripts/config_whitelist.txt | 1 - 3 files changed, 3 deletions(-)
diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 976b6854e49..31c29001807 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -13,7 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC8313ERDB 1
#define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 81e92fb939f..afb0586c4b9 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -13,7 +13,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC8313ERDB 1
#ifndef CONFIG_SYS_MONITOR_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 49fc2f9f83e..3691246aaee 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1247,7 +1247,6 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC8313ERDB CONFIG_MPC8315ERDB CONFIG_MPC837XEMDS CONFIG_MPC837XERDB
CONFIG_MPC8315ERDB is unused, and TARGET_MPC8315ERDB could replace it.
Hence, get rid of CONFIG_MPC8315ERDB.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Removed config option from whitelist
--- include/configs/MPC8315ERDB.h | 1 - scripts/config_whitelist.txt | 1 - 2 files changed, 2 deletions(-)
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index a2b5b07ea9c..c373a0ab4c1 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -22,7 +22,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
/* * System Clock Setup diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 3691246aaee..e13f290bfad 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1247,7 +1247,6 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC8315ERDB CONFIG_MPC837XEMDS CONFIG_MPC837XERDB CONFIG_MPC83XX_GPIO
CONFIG_MPC837XEMDS is unused, and TARGET_MPC837XEMDS could replace it.
Hence, get rid of CONFIG_MPC837XEMDS.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Removed config option from whitelist
--- include/configs/MPC837XEMDS.h | 1 - scripts/config_whitelist.txt | 1 - 2 files changed, 2 deletions(-)
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 82dcb859736..577f7ec0b2f 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -11,7 +11,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
/* * System Clock Setup diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e13f290bfad..fcfa82817a1 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1247,7 +1247,6 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC837XEMDS CONFIG_MPC837XERDB CONFIG_MPC83XX_GPIO CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION
CONFIG_MPC837XERDB is unused, and TARGET_MPC837XERDB could replace it.
Hence, get rid of CONFIG_MPC837XERDB.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Removed config option from whitelist
--- include/configs/MPC837XERDB.h | 1 - scripts/config_whitelist.txt | 1 - 2 files changed, 2 deletions(-)
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 6029d0f21bf..a8f5b013b28 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -12,7 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC837XERDB 1
#define CONFIG_HWCONFIG
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index fcfa82817a1..3483c2598ea 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1247,7 +1247,6 @@ CONFIG_MMC_SPI_SPEED CONFIG_MMC_SUNXI_SLOT CONFIG_MMU CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC837XERDB CONFIG_MPC83XX_GPIO CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN
The MPC83xx include files contain some settings of the PCI subsystem.
Migrate these to Kconfig until a proper DM PCI driver exists.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- arch/powerpc/cpu/mpc83xx/Kconfig | 26 ++++++++++++++++++++++++++ board/freescale/mpc8349emds/pci.c | 12 ++++++------ configs/MPC8349EMDS_SDRAM_defconfig | 1 + configs/MPC8349EMDS_defconfig | 1 + configs/sbc8349_PCI_33_defconfig | 1 + configs/sbc8349_PCI_66_defconfig | 1 + configs/vme8349_defconfig | 1 + include/configs/MPC8349EMDS.h | 11 ++--------- include/configs/MPC8349EMDS_SDRAM.h | 11 ++--------- include/configs/TQM834x.h | 2 +- include/configs/caddy2.h | 8 -------- include/configs/sbc8349.h | 10 +--------- include/configs/vme8349.h | 10 +--------- 13 files changed, 44 insertions(+), 51 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 0ce1aad6d03..bd4e5c14a9a 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -215,6 +215,32 @@ config ARCH_MPC8360 config ARCH_MPC837X bool
+menu "Legacy options" + +if ARCH_MPC8349 + +#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT +choice + prompt "PMC slot configuration" + +config PCI_ALL_PCI1 + bool "All PMC slots on PCI1" + +config PCI_ONE_PCI1 + bool "First PMC1 on PCI1" + +config PCI_TWO_PCI1 + bool "First two PMC1 on PCI1" + +endchoice + +config PCI_64BIT + bool "PMC2 is 64bit" + +endif + +endmenu + source "board/esd/vme8349/Kconfig" source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index a2feda855f6..005190ed87d 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -77,11 +77,11 @@ void pib_init(void) i2c_write(0x26, 0x6, 1, &val8, 1); val8 = 0x34; i2c_write(0x26, 0x7, 1, &val8, 1); -#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) val8 = 0xf4; /* PMC2:PCI1/64-bit */ -#elif defined(PCI_ALL_PCI1) +#elif defined(CONFIG_PCI_ALL_PCI1) val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ -#elif defined(PCI_ONE_PCI1) +#elif defined(CONFIG_PCI_ONE_PCI1) val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ #else val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ @@ -98,11 +98,11 @@ void pib_init(void) i2c_write(0x27, 0x3, 1, &val8, 1); asm("eieio");
-#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) printf("PCI1: 64-bit on PMC2\n"); -#elif defined(PCI_ALL_PCI1) +#elif defined(CONFIG_PCI_ALL_PCI1) printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); -#elif defined(PCI_ONE_PCI1) +#elif defined(CONFIG_PCI_ONE_PCI1) printf("PCI1: 32-bit on PMC1\n"); printf("PCI2: 32-bit on PMC2, PMC3\n"); #else diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index 2607dfa4f33..a98cc74027c 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS_SDRAM=y +CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 41a1d9609b5..bd8ff625e19 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y +CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 02d5185124c..5c2720aef14 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_33M" diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 945c5229b93..e6535dafcf7 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_66M" diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index a7d81a3a0f1..90c29b7fedf 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_MPC83xx=y CONFIG_TARGET_VME8349=y +CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index fe2b81b905b..40e5c1997da 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -285,13 +285,6 @@
#if defined(CONFIG_PCI)
-#define PCI_ONE_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - #define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100 @@ -436,7 +429,7 @@ HRCWH_TSEC1M_IN_GMII |\ HRCWH_TSEC2M_IN_GMII) #else -#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) #define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_HOST |\ HRCWH_64_BIT_PCI |\ @@ -462,7 +455,7 @@ HRCWH_ROM_LOC_LOCAL_16BIT |\ HRCWH_TSEC1M_IN_GMII |\ HRCWH_TSEC2M_IN_GMII) -#endif /* PCI_64BIT */ +#endif /* CONFIG_PCI_64BIT */ #endif /* CONFIG_PCISLAVE */
/* diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index b610b555a75..15f10492a58 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -357,13 +357,6 @@
#if defined(CONFIG_PCI)
-#define PCI_ONE_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - #define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100 @@ -508,7 +501,7 @@ HRCWH_TSEC1M_IN_GMII |\ HRCWH_TSEC2M_IN_GMII) #else -#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) #define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_HOST |\ HRCWH_64_BIT_PCI |\ @@ -534,7 +527,7 @@ HRCWH_ROM_LOC_LOCAL_16BIT |\ HRCWH_TSEC1M_IN_GMII |\ HRCWH_TSEC2M_IN_GMII) -#endif /* PCI_64BIT */ +#endif /* CONFIG_PCI_64BIT */ #endif /* CONFIG_PCISLAVE */
/* diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 2b82bd82eb7..949e370150f 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -270,7 +270,7 @@ HRCWL_VCO_1X2 |\ HRCWL_CORE_TO_CSB_2X1)
-#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) #define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_HOST |\ HRCWH_64_BIT_PCI |\ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index a7bbbbdd0b3..a8f692d5ead 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -212,14 +212,6 @@
#if defined(CONFIG_PCI)
-#define PCI_64BIT -#define PCI_ONE_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 6ae11185cb7..60eb2cf8314 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -307,14 +307,6 @@
#if defined(CONFIG_PCI)
-#define PCI_64BIT -#define PCI_ONE_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP
@@ -435,7 +427,7 @@ HRCWL_CORE_TO_CSB_1X1) #endif
-#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) #define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_HOST |\ HRCWH_64_BIT_PCI |\ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 6c3ad76e524..ea080587522 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -212,14 +212,6 @@
#if defined(CONFIG_PCI)
-#define PCI_64BIT -#define PCI_ONE_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP
@@ -316,7 +308,7 @@ HRCWL_VCO_1X2 |\ HRCWL_CORE_TO_CSB_2X1)
-#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) #define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_HOST |\ HRCWH_64_BIT_PCI |\
CONFIG_SYS_CLK_FREQ is the standard way to set the system clock frequency. On MPC83xx, CONFIG_83XX_CLKIN is used for this purpose. Hence, the obvious way is to replace CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ.
A few MPC83xx boards use the CONFIG_83XX_CLKIN variable for computing CONFIG_SYS_NS16550_CLK. This makes it harder to replace CONFIG_83XX_CLKIN.
But the value of the multiplicator can be read from the SPMR register.
Hence, replace the static calculations with a call to a new get_bus_freq function, as other architectures do.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 8 ++++++++ include/configs/MPC8315ERDB.h | 2 +- include/configs/ids8313.h | 2 +- 3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 746f1febba0..3315ee05e11 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -89,3 +89,11 @@ void puts(const char *str) while (*str) putc(*str++); } + +ulong get_bus_freq(ulong dummy) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; + + return CONFIG_83XX_CLKIN * spmf; +} diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index c373a0ab4c1..adb2bb6c2d8 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -271,7 +271,7 @@ */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index caa3dd1f1a6..4b0ec273fb7 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -301,7 +301,7 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
#define CONFIG_HAS_FSL_DR_USB #define CONFIG_SYS_SCCR_USBDRCM 3
MPC83xx uses CONFIG_83XX_CLKIN instead of CONFIG_SYS_CLK_FREQ to set the system clock. To migrate the architecture, we can replace CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ.
To do this * replace all occurrences of CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ * set CONFIG_SYS_CLK_FREQ to the old value of CONFIG_83XX_CLKIN in all MPC83xx config files
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- Kconfig | 2 +- arch/powerpc/cpu/mpc83xx/speed.c | 4 +-- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 2 +- board/freescale/mpc8349emds/MAINTAINERS | 1 + board/freescale/mpc837xerdb/MAINTAINERS | 1 + board/tqc/tqm834x/pci.c | 2 +- configs/MPC8308RDB_defconfig | 1 + configs/MPC8313ERDB_33_defconfig | 1 + configs/MPC8313ERDB_66_defconfig | 1 + configs/MPC8313ERDB_NAND_33_defconfig | 1 + configs/MPC8313ERDB_NAND_66_defconfig | 1 + configs/MPC8315ERDB_defconfig | 1 + configs/MPC8323ERDB_defconfig | 1 + configs/MPC832XEMDS_ATM_defconfig | 1 + configs/MPC832XEMDS_HOST_33_defconfig | 1 + configs/MPC832XEMDS_HOST_66_defconfig | 1 + configs/MPC832XEMDS_SLAVE_defconfig | 1 + configs/MPC832XEMDS_defconfig | 1 + configs/MPC8349EMDS_SDRAM_defconfig | 1 + configs/MPC8349EMDS_SLAVE_defconfig | 25 ++++++++++++++++++ configs/MPC8349EMDS_defconfig | 1 + configs/MPC8349ITXGP_defconfig | 2 ++ configs/MPC8349ITX_LOWBOOT_defconfig | 1 + configs/MPC8349ITX_defconfig | 1 + configs/MPC837XEMDS_HOST_defconfig | 1 + configs/MPC837XEMDS_defconfig | 1 + configs/MPC837XERDB_SLAVE_defconfig | 34 +++++++++++++++++++++++++ configs/MPC837XERDB_defconfig | 2 ++ configs/TQM834x_defconfig | 1 + configs/caddy2_defconfig | 1 + configs/hrcon_defconfig | 1 + configs/hrcon_dh_defconfig | 1 + configs/ids8313_defconfig | 1 + configs/kmcoge5ne_defconfig | 1 + configs/kmeter1_defconfig | 1 + configs/kmopti2_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmtegr1_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/kmvect1_defconfig | 1 + configs/mpc8308_p1m_defconfig | 1 + configs/sbc8349_PCI_33_defconfig | 1 + configs/sbc8349_PCI_66_defconfig | 1 + configs/sbc8349_defconfig | 1 + configs/strider_con_defconfig | 1 + configs/strider_con_dp_defconfig | 1 + configs/strider_cpu_defconfig | 1 + configs/strider_cpu_dp_defconfig | 1 + configs/suvd3_defconfig | 1 + configs/tuge1_defconfig | 1 + configs/tuxx1_defconfig | 1 + configs/ve8313_defconfig | 1 + configs/vme8349_defconfig | 1 + include/configs/MPC8308RDB.h | 6 ----- include/configs/MPC8313ERDB_NAND.h | 17 +------------ include/configs/MPC8313ERDB_NOR.h | 15 +---------- include/configs/MPC8315ERDB.h | 6 ----- include/configs/MPC8323ERDB.h | 9 ------- include/configs/MPC832XEMDS.h | 13 ---------- include/configs/MPC8349EMDS.h | 19 ++------------ include/configs/MPC8349EMDS_SDRAM.h | 19 ++------------ include/configs/MPC8349ITX.h | 7 ----- include/configs/MPC837XEMDS.h | 13 ---------- include/configs/MPC837XERDB.h | 14 ---------- include/configs/TQM834x.h | 3 --- include/configs/caddy2.h | 11 -------- include/configs/hrcon.h | 6 ----- include/configs/ids8313.h | 3 --- include/configs/kmeter1.h | 7 ----- include/configs/mpc8308_p1m.h | 6 ----- include/configs/sbc8349.h | 16 ------------ include/configs/strider.h | 6 ----- include/configs/ve8313.h | 4 --- include/configs/vme8349.h | 9 ------- 74 files changed, 119 insertions(+), 208 deletions(-) create mode 100644 configs/MPC8349EMDS_SLAVE_defconfig create mode 100644 configs/MPC837XERDB_SLAVE_defconfig
diff --git a/Kconfig b/Kconfig index 48c62e1c025..119f322bbe0 100644 --- a/Kconfig +++ b/Kconfig @@ -484,7 +484,7 @@ config SYS_TEXT_BASE
config SYS_CLK_FREQ - depends on ARC || ARCH_SUNXI + depends on ARC || ARCH_SUNXI || MPC83xx int "CPU clock frequency" help TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 668ed27862b..e870a23103b 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -137,8 +137,8 @@ int get_clocks(void) clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if (im->reset.rcwh & HRCWH_PCI_HOST) { -#if defined(CONFIG_83XX_CLKIN) - pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div); +#if defined(CONFIG_SYS_CLK_FREQ) + pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div); #else pci_sync_in = 0xDEADBEEF; #endif diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 3315ee05e11..2d6ba12e2d9 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -95,5 +95,5 @@ ulong get_bus_freq(ulong dummy) volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
- return CONFIG_83XX_CLKIN * spmf; + return CONFIG_SYS_CLK_FREQ * spmf; } diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS index e6648d66a05..f236d543ccc 100644 --- a/board/freescale/mpc8349emds/MAINTAINERS +++ b/board/freescale/mpc8349emds/MAINTAINERS @@ -4,3 +4,4 @@ S: Orphan (since 2018-05) F: board/freescale/mpc8349emds/ F: include/configs/MPC8349EMDS.h F: configs/MPC8349EMDS_defconfig +F: configs/MPC8349EMDS_SLAVE_defconfig diff --git a/board/freescale/mpc837xerdb/MAINTAINERS b/board/freescale/mpc837xerdb/MAINTAINERS index 81b4eed5ede..9f44a37a0d9 100644 --- a/board/freescale/mpc837xerdb/MAINTAINERS +++ b/board/freescale/mpc837xerdb/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/mpc837xerdb/ F: include/configs/MPC837XERDB.h F: configs/MPC837XERDB_defconfig +F: configs/MPC837XERDB_SLAVE_defconfig diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c index 34c68ac4637..c9b05e44c24 100644 --- a/board/tqc/tqm834x/pci.c +++ b/board/tqc/tqm834x/pci.c @@ -71,7 +71,7 @@ pci_init_board(void) reg32 = 0xff000000; #endif if (clk->spmr & SPMR_CKID) { - /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR + /* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR * fields accordingly */ reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 06657b2bfe9..59dde136f2c 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308RDB=y CONFIG_FIT=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index cacb5ba0774..4851611cf53 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NOR=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index 6b29c2e5c9d..fb4fddec469 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NOR=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 4c8957c2742..5fa8eba8537 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NAND=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index ff3d0dc84e9..f5dd21a943a 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x00100000 CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y +CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NAND=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index b45369e6264..15dbbe35dd1 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8315ERDB=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index a1227bfdade..c43ae8c9929 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8323ERDB=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index e4c44d90a96..a40f16d49b4 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 2b03a56245f..1031dd655ad 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 4aa34dc3314..416e0e9aeab 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index 332088934a0..29b8f1a988d 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index f3ec967b3cc..2a15e5c18e9 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index a98cc74027c..d4f6587bb38 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS_SDRAM=y CONFIG_PCI_ONE_PCI1=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig new file mode 100644 index 00000000000..11e3b144b74 --- /dev/null +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -0,0 +1,25 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666666 +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8349EMDS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" +CONFIG_BOOTDELAY=6 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +# CONFIG_MMC is not set +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_PHYLIB=y +# CONFIG_PCI is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index bd8ff625e19..9a6eebf746c 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y CONFIG_PCI_ONE_PCI1=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 95d807bac00..c7f465e4095 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -1,9 +1,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" CONFIG_BOOTDELAY=6 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitxgp:eth0:off console=ttyS0,115200" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 22225e3ad6e..7dbde3222b2 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 7f9b9cb283d..d3ab1eafeb1 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFEF00000 +CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 4ac95735b2d..15d60a2ccd3 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index 9ee8c7d8806..d5d42ab12fa 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig new file mode 100644 index 00000000000..8c2389c6989 --- /dev/null +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -0,0 +1,34 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666667 +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC837XERDB=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" +CONFIG_BOOTDELAY=6 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SATA=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_FSL_SATA=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_TSEC_ENET=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 45b68e90923..090b9e51522 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -1,9 +1,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XERDB=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="PCIE" CONFIG_BOOTDELAY=6 CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index e1a7a063064..8f68804a482 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_SYS_CLK_FREQ=66666000 CONFIG_MPC83xx=y CONFIG_TARGET_TQM834X=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index fe0c34fc61a..2d2d64d1038 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_CADDY2=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 7605c56619c..2a7b932b1e0 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_IDENT_STRING=" hrcon 0.01" +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y CONFIG_CMD_IOLOOP=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index bc51a5d02a9..3b1fbca2687 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_IDENT_STRING=" hrcon dh 0.01" +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y CONFIG_CMD_IOLOOP=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 0d055e395dd..7223af1f55f 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_IDS8313=y CONFIG_FIT=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index b7c42fa9cbe..beac453ce5c 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMCOGE5NE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 1773f74358e..2bf2c40a637 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMETER1=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index c0927dd4788..1b63b427f0f 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMOPTI2=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 7a00c85a841..df1bfaef187 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMSUPX5=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 38a861b8610..7187af77863 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMTEGR1=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 310cf5ac66f..bbd13b8bfaa 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMTEPR2=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 2f71ee75198..98dd9e2b374 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMVECT1=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index 114ffeeddba..1e50782f7cf 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFC000000 +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308_P1M=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 5c2720aef14..eca22bec3ab 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 +CONFIG_SYS_CLK_FREQ=33000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y CONFIG_PCI_64BIT=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index e6535dafcf7..fa1ec519c51 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y CONFIG_PCI_64BIT=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 82379e67d2c..d70332c785c 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 24c793dfc5d..194cebdb67f 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_IDENT_STRING=" strider con 0.01" +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y CONFIG_CMD_IOLOOP=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index c70d99a7e67..4e72582d2f6 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_IDENT_STRING=" strider con dp 0.01" +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y CONFIG_CMD_IOLOOP=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index fef58848af9..c633e030e34 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_IDENT_STRING=" strider cpu 0.01" +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y CONFIG_CMD_IOLOOP=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index fc8f39eb54a..e1d08e782d4 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_IDENT_STRING=" strider cpu dp 0.01" +CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y CONFIG_CMD_IOLOOP=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index e6b97b866dd..4744122e4ed 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SUVD3=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index a3e04bc0f8a..349b1d00094 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_TUGE1=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index d1fc62697e3..a6654c90259 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 584aafb08fb..084b1bdeaf5 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=32000000 CONFIG_MPC83xx=y CONFIG_TARGET_VE8313=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 90c29b7fedf..aae22141927 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 +CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_VME8349=y CONFIG_PCI_64BIT=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 7bf91524c88..77c30093bfd 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -27,12 +27,6 @@ #define CONFIG_TSEC1 #define CONFIG_VSC7385_ENET
-/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - /* * Hardware Reset Configuration Word * if CLKIN is 66.66MHz, then diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 31c29001807..103ace2d3a9 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -54,16 +54,6 @@ #define CONFIG_VSC7385_ENET #define CONFIG_TSEC2
-#ifdef CONFIG_SYS_66MHZ -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ -#elif defined(CONFIG_SYS_33MHZ) -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#else -#error Unknown oscillator frequency. -#endif - -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - #define CONFIG_SYS_IMMR 0xE0000000
#if !defined(CONFIG_SPL_BUILD) @@ -445,9 +435,6 @@ HRCWL_DDR_TO_SCB_CLK_2X1 |\ HRCWL_CSB_TO_CLKIN_2X1 |\ HRCWL_CORE_TO_CSB_2X1) - -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) - #elif defined(CONFIG_SYS_33MHZ)
/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ @@ -459,9 +446,6 @@ HRCWL_DDR_TO_SCB_CLK_2X1 |\ HRCWL_CSB_TO_CLKIN_5X1 |\ HRCWL_CORE_TO_CSB_2X1) - -#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) - #endif
#define CONFIG_SYS_HRCW_HIGH_BASE (\ @@ -478,6 +462,7 @@ HRCWH_FROM_0XFFF00100 |\ HRCWH_ROM_LOC_NAND_SP_8BIT |\ HRCWH_RL_EXT_NAND) +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
/* System IO Config */ #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index afb0586c4b9..64b289adce4 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -30,16 +30,6 @@ #define CONFIG_VSC7385_ENET #define CONFIG_TSEC2
-#ifdef CONFIG_SYS_66MHZ -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ -#elif defined(CONFIG_SYS_33MHZ) -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#else -#error Unknown oscillator frequency. -#endif - -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - #define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_SYS_MEMTEST_START 0x00001000 @@ -420,8 +410,6 @@ HRCWL_CSB_TO_CLKIN_2X1 |\ HRCWL_CORE_TO_CSB_2X1)
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) - #elif defined(CONFIG_SYS_33MHZ)
/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ @@ -434,8 +422,6 @@ HRCWL_CSB_TO_CLKIN_5X1 |\ HRCWL_CORE_TO_CSB_2X1)
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) - #endif
#define CONFIG_SYS_HRCW_HIGH_BASE (\ @@ -452,6 +438,7 @@ HRCWH_FROM_0X00000100 |\ HRCWH_ROM_LOC_LOCAL_16BIT |\ HRCWH_RL_EXT_LEGACY) +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
/* System IO Config */ #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index adb2bb6c2d8..53a02f415fe 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -23,12 +23,6 @@ */ #define CONFIG_E300 1 /* E300 family */
-/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - /* * Hardware Reset Configuration Word * if CLKIN is 66.66MHz, then diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index bd1b1bb0a7c..ee4eeec8856 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -15,15 +15,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */
-/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN -#endif - /* * Hardware Reset Configuration Word */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 4cb595bb8e5..0ba64772542 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -12,19 +12,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */
-/* - * System Clock Setup - */ -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ -#else -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif - /* * Hardware Reset Configuration Word */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 40e5c1997da..4c9ee76815c 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -17,26 +17,11 @@ */ #define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_PCI_66M -#ifdef CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#endif - -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66666666 /* in Hz */ -#endif /* CONFIG_PCISLAVE */ - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef CONFIG_PCI_66M -#define CONFIG_SYS_CLK_FREQ 66000000 +#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#else -#define CONFIG_SYS_CLK_FREQ 33000000 +#elif CONFIG_SYS_CLK_FREQ == 33000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 #endif -#endif
#define CONFIG_SYS_IMMR 0xE0000000
diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 15f10492a58..b9710b65882 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -17,26 +17,11 @@ */ #define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_PCI_66M -#ifdef CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#endif - -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66666666 /* in Hz */ -#endif /* CONFIG_PCISLAVE */ - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef CONFIG_PCI_66M -#define CONFIG_SYS_CLK_FREQ 66000000 +#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#else -#define CONFIG_SYS_CLK_FREQ 33000000 +#elif CONFIG_SYS_CLK_FREQ == 33000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 #endif -#endif
#define CONFIG_SYS_IMMR 0xE0000000
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 5877279adaf..e170271c40d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -391,13 +391,6 @@ boards, we say we have two, but don't display a message if we find only one. */
#endif
-#define CONFIG_PCI_66M -#ifdef CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#endif - /* TSEC */
#ifdef CONFIG_TSEC_ENET diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 577f7ec0b2f..33c485aab78 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -12,19 +12,6 @@ */ #define CONFIG_E300 1 /* E300 family */
-/* - * System Clock Setup - */ -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ -#else -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif - /* * Hardware Reset Configuration Word * if CLKIN is 66MHz, then diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index a8f5b013b28..806b0f32e54 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -20,20 +20,6 @@ */ #define CONFIG_VSC7385_ENET
-/* - * System Clock Setup - */ -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66666667 /* in HZ */ -#else -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ -#define CONFIG_PCIE -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN -#endif - /* * Hardware Reset Configuration Word */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 949e370150f..58c301553e3 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -19,9 +19,6 @@ /* IMMR Base Address Register, use Freescale default: 0xff400000 */ #define CONFIG_SYS_IMMR 0xff400000
-/* System clock. Primary input clock when in PCI host mode */ -#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ - /* * Local Bus LCRR * LCRR: DLL bypass, Clock divider is 8 diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index a8f692d5ead..68fb989856c 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -25,22 +25,11 @@ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#define CONFIG_PCI_66M #ifdef CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef CONFIG_PCI_66M -#define CONFIG_SYS_CLK_FREQ 66000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 #else -#define CONFIG_SYS_CLK_FREQ 33000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 #endif -#endif
#define CONFIG_SYS_IMMR 0xE0000000
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index cd5e883b7a1..8eb12b76709 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -16,12 +16,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - /* * Hardware Reset Configuration Word * if CLKIN is 66.66MHz, then diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 4b0ec273fb7..eff0addd519 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -20,9 +20,6 @@ #define CONFIG_BOOT_RETRY_MIN 30 #define CONFIG_RESET_TO_RETRY
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - #define CONFIG_SYS_IMMR 0xF0000000
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 976255f5789..2280f007f2f 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -25,13 +25,6 @@ #include "km/keymile-common.h" #include "km/km-powerpc.h"
-/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - /* * IMMR new address */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index c007877276b..fd59471370d 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -21,12 +21,6 @@ #define CONFIG_TSEC1 #define CONFIG_TSEC2
-/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - /* * Hardware Reset Configuration Word * if CLKIN is 66.66MHz, then diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 60eb2cf8314..2520a77dd3c 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -22,27 +22,11 @@ /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-/* - * The default if PCI isn't enabled, or if no PCI clk setting is given - * is 66MHz; this is what the board defaults to when the PCI slot is - * physically empty. The board will automatically (i.e w/o jumpers) - * clock down to 33MHz if you insert a 33MHz PCI card. - */ #ifdef CONFIG_PCI_33M -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#else /* 66M */ -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef CONFIG_PCI_33M -#define CONFIG_SYS_CLK_FREQ 33000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 #else /* 66M */ -#define CONFIG_SYS_CLK_FREQ 66000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 #endif -#endif
#define CONFIG_SYS_IMMR 0xE0000000
diff --git a/include/configs/strider.h b/include/configs/strider.h index c42fe8c3ece..8c9acfba8d5 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -16,12 +16,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - /* * Hardware Reset Configuration Word * if CLKIN is 66.66MHz, then diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 87fbe36640b..2ef6f88bdf6 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -24,10 +24,6 @@ * On-board devices * */ -#define CONFIG_83XX_CLKIN 32000000 /* in Hz */ - -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - #define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_SYS_MEMTEST_START 0x00001000 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index ea080587522..c5086958ff3 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -26,21 +26,12 @@ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
#define CONFIG_PCI_66M -#ifdef CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#endif
-#ifndef CONFIG_SYS_CLK_FREQ #ifdef CONFIG_PCI_66M -#define CONFIG_SYS_CLK_FREQ 66000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 #else -#define CONFIG_SYS_CLK_FREQ 33000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 #endif -#endif
#define CONFIG_SYS_IMMR 0xE0000000
The HRCW (hardware reset configuration word) is a constant that must be hard-coded into the boot loader image. So, it must be available at compile time, and cannot be migrated to the DT mechanism, but has to be kept in Kconfig.
Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- arch/powerpc/cpu/mpc83xx/Kconfig | 69 ++ arch/powerpc/cpu/mpc83xx/hrcw/Kconfig | 816 ++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h | 37 ++ arch/powerpc/cpu/mpc83xx/start.S | 2 + board/freescale/mpc8315erdb/MAINTAINERS | 1 + board/freescale/mpc8349emds/MAINTAINERS | 1 + board/freescale/mpc8349itx/mpc8349itx.c | 2 + board/freescale/mpc837xemds/MAINTAINERS | 1 + configs/MPC8308RDB_defconfig | 7 + configs/MPC8313ERDB_33_defconfig | 8 + configs/MPC8313ERDB_66_defconfig | 7 + configs/MPC8313ERDB_NAND_33_defconfig | 7 + configs/MPC8313ERDB_NAND_66_defconfig | 6 + configs/MPC8315ERDB_defconfig | 8 + configs/MPC8323ERDB_defconfig | 6 + configs/MPC832XEMDS_ATM_defconfig | 6 + configs/MPC832XEMDS_HOST_33_defconfig | 6 + configs/MPC832XEMDS_HOST_66_defconfig | 6 + configs/MPC832XEMDS_SLAVE_defconfig | 3 + configs/MPC832XEMDS_defconfig | 6 + configs/MPC8349EMDS_PCI64_defconfig | 35 + configs/MPC8349EMDS_SDRAM_defconfig | 10 + configs/MPC8349EMDS_SLAVE_defconfig | 12 +- configs/MPC8349EMDS_defconfig | 10 + configs/MPC8349ITXGP_defconfig | 10 + configs/MPC8349ITX_LOWBOOT_defconfig | 10 + configs/MPC8349ITX_defconfig | 9 + configs/MPC837XEMDS_HOST_defconfig | 10 + configs/MPC837XEMDS_SLAVE_defconfig | 35 + configs/MPC837XEMDS_defconfig | 10 + configs/MPC837XERDB_SLAVE_defconfig | 7 + configs/MPC837XERDB_defconfig | 10 + configs/TQM834x_defconfig | 9 + configs/caddy2_defconfig | 10 + configs/hrcon_defconfig | 6 + configs/hrcon_dh_defconfig | 6 + configs/ids8313_defconfig | 3 + configs/kmcoge5ne_defconfig | 9 + configs/kmeter1_defconfig | 9 + configs/kmopti2_defconfig | 4 + configs/kmsupx5_defconfig | 4 + configs/kmtegr1_defconfig | 5 + configs/kmtepr2_defconfig | 4 + configs/kmvect1_defconfig | 5 + configs/mpc8308_p1m_defconfig | 5 + configs/sbc8349_PCI_33_defconfig | 10 + configs/sbc8349_PCI_66_defconfig | 10 + configs/sbc8349_defconfig | 10 + configs/strider_con_defconfig | 5 + configs/strider_con_dp_defconfig | 5 + configs/strider_cpu_defconfig | 5 + configs/strider_cpu_dp_defconfig | 5 + configs/suvd3_defconfig | 4 + configs/tuge1_defconfig | 4 + configs/tuxx1_defconfig | 4 + configs/ve8313_defconfig | 7 + configs/vme8349_defconfig | 10 + include/configs/MPC8308RDB.h | 32 - include/configs/MPC8313ERDB_NAND.h | 38 -- include/configs/MPC8313ERDB_NOR.h | 40 -- include/configs/MPC8315ERDB.h | 34 - include/configs/MPC8323ERDB.h | 24 - include/configs/MPC832XEMDS.h | 37 -- include/configs/MPC8349EMDS.h | 86 --- include/configs/MPC8349EMDS_SDRAM.h | 86 --- include/configs/MPC8349ITX.h | 39 -- include/configs/MPC837XEMDS.h | 42 -- include/configs/MPC837XERDB.h | 40 -- include/configs/TQM834x.h | 35 - include/configs/caddy2.h | 41 -- include/configs/hrcon.h | 32 - include/configs/ids8313.h | 21 - include/configs/kmcoge5ne.h | 19 - include/configs/kmeter1.h | 19 - include/configs/kmopti2.h | 22 - include/configs/kmsupx5.h | 22 - include/configs/kmtegr1.h | 22 - include/configs/kmtepr2.h | 22 - include/configs/kmvect1.h | 22 - include/configs/mpc8308_p1m.h | 32 - include/configs/sbc8349.h | 71 --- include/configs/strider.h | 32 - include/configs/suvd3.h | 22 - include/configs/tuge1.h | 22 - include/configs/tuxx1.h | 22 - include/configs/ve8313.h | 19 - include/configs/vme8349.h | 43 -- 87 files changed, 1330 insertions(+), 1039 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/hrcw/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h create mode 100644 configs/MPC8349EMDS_PCI64_defconfig create mode 100644 configs/MPC837XEMDS_SLAVE_defconfig
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index bd4e5c14a9a..1206c687cc7 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -177,30 +177,79 @@ config TARGET_STRIDER
endchoice
+config MPC83XX_QUICC_ENGINE + bool + +# TODO: Imply MPC83xx PCI driver +config MPC83XX_PCI_SUPPORT + bool + +# TODO: Imply TSEC driver +config MPC83XX_TSEC1_SUPPORT + bool + +config MPC83XX_TSEC2_SUPPORT + bool + +config MPC83XX_PCIE1_SUPPORT + bool + +config MPC83XX_PCIE2_SUPPORT + bool + +config MPC83XX_SDHC_SUPPORT + bool + +config MPC83XX_SATA_SUPPORT + bool + +config MPC83XX_SECOND_I2C_SUPPORT + bool + +config MPC83XX_LDP_PIN + bool + config ARCH_MPC830X bool + select MPC83XX_SDHC_SUPPORT
config ARCH_MPC8308 bool select ARCH_MPC830X + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT + select MPC83XX_PCIE1_SUPPORT + select MPC83XX_SECOND_I2C_SUPPORT
config ARCH_MPC8309 bool select ARCH_MPC830X + select MPC83XX_QUICC_ENGINE + select MPC83XX_PCI_SUPPORT + select MPC83XX_SECOND_I2C_SUPPORT
config ARCH_MPC831X bool + select MPC83XX_PCI_SUPPORT + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT
config ARCH_MPC8313 bool select ARCH_MPC831X + select MPC83XX_SECOND_I2C_SUPPORT
config ARCH_MPC8315 bool select ARCH_MPC831X + select MPC83XX_PCIE1_SUPPORT + select MPC83XX_PCIE2_SUPPORT + select MPC83XX_SATA_SUPPORT
config ARCH_MPC832X bool + select MPC83XX_QUICC_ENGINE + select MPC83XX_PCI_SUPPORT
config ARCH_MPC834X bool @@ -208,12 +257,32 @@ config ARCH_MPC834X config ARCH_MPC8349 bool select ARCH_MPC834X + select MPC83XX_PCI_SUPPORT + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT + select MPC83XX_LDP_PIN + select MPC83XX_SECOND_I2C_SUPPORT
config ARCH_MPC8360 bool + select MPC83XX_QUICC_ENGINE + select MPC83XX_PCI_SUPPORT + select MPC83XX_LDP_PIN + select MPC83XX_SECOND_I2C_SUPPORT
config ARCH_MPC837X bool + select MPC83XX_PCI_SUPPORT + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT + select MPC83XX_PCIE1_SUPPORT + select MPC83XX_PCIE2_SUPPORT + select MPC83XX_SDHC_SUPPORT + select MPC83XX_SATA_SUPPORT + select MPC83XX_LDP_PIN + select MPC83XX_SECOND_I2C_SUPPORT + +source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
menu "Legacy options"
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig new file mode 100644 index 00000000000..c657a47b114 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig @@ -0,0 +1,816 @@ +menu "Reset Configuration Word" + +choice + prompt "Local bus memory controller clock mode" + +config LBMC_CLOCK_MODE_1_1 + bool "1 : 1" + +config LBMC_CLOCK_MODE_1_2 + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + bool "1 : 2" + +endchoice + +choice + prompt "DDR SDRAM memory controller clock mode" + +config DDR_MC_CLOCK_MODE_1_2 + bool "1 : 2" + +config DDR_MC_CLOCK_MODE_1_1 + depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + bool "1 : 1" + +endchoice + +if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349 + +choice + prompt "System PLL VCO division" + +config SYSTEM_PLL_VCO_DIV_1 + depends on !ARCH_MPC837X + bool "1" + +config SYSTEM_PLL_VCO_DIV_2 + bool "2" + +config SYSTEM_PLL_VCO_DIV_4 + depends on !ARCH_MPC831X + bool "4" + +config SYSTEM_PLL_VCO_DIV_8 + depends on !ARCH_MPC831X + bool "8" + +endchoice + +endif + +choice + prompt "System PLL multiplication factor" + +config SYSTEM_PLL_FACTOR_2_1 + bool "2 : 1" + +config SYSTEM_PLL_FACTOR_3_1 + bool "3 : 1" + +config SYSTEM_PLL_FACTOR_4_1 + bool "4 : 1" + +config SYSTEM_PLL_FACTOR_5_1 + bool "5 : 1" + +config SYSTEM_PLL_FACTOR_6_1 + bool "6 : 1" + +config SYSTEM_PLL_FACTOR_7_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "7 : 1" + +config SYSTEM_PLL_FACTOR_8_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "8 : 1" + +config SYSTEM_PLL_FACTOR_9_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "9 : 1" + +config SYSTEM_PLL_FACTOR_10_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "10 : 1" + +config SYSTEM_PLL_FACTOR_11_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "11 : 1" + +config SYSTEM_PLL_FACTOR_12_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "12 : 1" + +config SYSTEM_PLL_FACTOR_13_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "13 : 1" + +config SYSTEM_PLL_FACTOR_14_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "14 : 1" + +config SYSTEM_PLL_FACTOR_15_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "15 : 1" + +config SYSTEM_PLL_FACTOR_16_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 + bool "16 : 1" + +endchoice + +config CORE_PLL_BYPASS + bool "Core PLL bypassed" + +if !CORE_PLL_BYPASS + +choice + prompt "Core PLL Ratio" + +config CORE_PLL_RATIO_1_1 + bool "1 : 1" + +config CORE_PLL_RATIO_15_1 + bool "1.5 : 1" + +config CORE_PLL_RATIO_2_1 + bool "2 : 1" + +config CORE_PLL_RATIO_25_1 + bool "2.5 : 1" + +config CORE_PLL_RATIO_3_1 + bool "3 : 1" + +endchoice + +choice + prompt "Core PLL VCO Divider" + +config CORE_PLL_VCO_DIVIDER_2 + bool "2" + +config CORE_PLL_VCO_DIVIDER_4 + bool "4" + +config CORE_PLL_VCO_DIVIDER_8 + depends on !ARCH_MPC8315 + bool "8" + +endchoice + +endif + +if MPC83XX_QUICC_ENGINE + +choice + prompt "QUICC Engine PLL VCO Divider" + +config QUICC_VCO_DIVIDER_2 + bool "2" + +config QUICC_VCO_DIVIDER_4 + bool "4" + +config QUICC_VCO_DIVIDER_8 + depends on ARCH_MPC8309 + bool "8" + +endchoice + +choice + prompt "QUICC Engine PLL division factor" + +config QUICC_DIV_FACTOR_1 + bool "1" + +config QUICC_DIV_FACTOR_2 + bool "2" + +endchoice + +choice + prompt "QUICC Engine PLL multiplication factor" + +config QUICC_MULT_FACTOR_2 + bool "2" + +config QUICC_MULT_FACTOR_3 + bool "3" + +config QUICC_MULT_FACTOR_4 + bool "4" + +config QUICC_MULT_FACTOR_5 + bool "5" + +config QUICC_MULT_FACTOR_6 + bool "6" + +config QUICC_MULT_FACTOR_7 + bool "7" + +config QUICC_MULT_FACTOR_8 + bool "8" + +config QUICC_MULT_FACTOR_9 + depends on ARCH_MPC8360 + bool "9" + +config QUICC_MULT_FACTOR_10 + depends on ARCH_MPC8360 + bool "10" + +config QUICC_MULT_FACTOR_11 + depends on ARCH_MPC8360 + bool "11" + +config QUICC_MULT_FACTOR_12 + depends on ARCH_MPC8360 + bool "12" + +config QUICC_MULT_FACTOR_13 + depends on ARCH_MPC8360 + bool "13" + +config QUICC_MULT_FACTOR_14 + depends on ARCH_MPC8360 + bool "14" + +config QUICC_MULT_FACTOR_15 + depends on ARCH_MPC8360 + bool "15" + +config QUICC_MULT_FACTOR_16 + depends on ARCH_MPC8360 + bool "16" + +config QUICC_MULT_FACTOR_17 + depends on ARCH_MPC8360 + bool "17" + +config QUICC_MULT_FACTOR_18 + depends on ARCH_MPC8360 + bool "18" + +config QUICC_MULT_FACTOR_19 + depends on ARCH_MPC8360 + bool "19" + +config QUICC_MULT_FACTOR_20 + depends on ARCH_MPC8360 + bool "20" + +config QUICC_MULT_FACTOR_21 + depends on ARCH_MPC8360 + bool "21" + +config QUICC_MULT_FACTOR_22 + depends on ARCH_MPC8360 + bool "22" + +config QUICC_MULT_FACTOR_23 + depends on ARCH_MPC8360 + bool "23" + +config QUICC_MULT_FACTOR_24 + depends on ARCH_MPC8360 + bool "24" + +config QUICC_MULT_FACTOR_25 + depends on ARCH_MPC8360 + bool "25" + +config QUICC_MULT_FACTOR_26 + depends on ARCH_MPC8360 + bool "26" + +config QUICC_MULT_FACTOR_27 + depends on ARCH_MPC8360 + bool "27" + +config QUICC_MULT_FACTOR_28 + depends on ARCH_MPC8360 + bool "28" + +config QUICC_MULT_FACTOR_29 + depends on ARCH_MPC8360 + bool "29" + +config QUICC_MULT_FACTOR_30 + depends on ARCH_MPC8360 + bool "30" + +config QUICC_MULT_FACTOR_31 + depends on ARCH_MPC8360 + bool "31" + +endchoice + +endif + +if MPC83XX_PCI_SUPPORT + +choice + prompt "PCI host mode" + +config PCI_HOST_MODE_DISABLE + bool "Disabled" + +config PCI_HOST_MODE_ENABLE + bool "Enabled" + +endchoice + +if ARCH_MPC8349 + +choice + prompt "PCI 64-bit mode" + +config PCI_64BIT_MODE_DISABLE + bool "Disabled" + +config PCI_64BIT_MODE_ENABLE + bool "Enabled" + +endchoice + +endif + +choice + prompt "PCI internal arbiter 1 mode" + +config PCI_INT_ARBITER1_DISABLE + bool "Disabled" + +config PCI_INT_ARBITER1_ENABLE + bool "Enabled" + +endchoice + +if ARCH_MPC8349 + +choice + prompt "PCI internal arbiter 2 mode" + +config PCI_INT_ARBITER2_DISABLE + bool "Disabled" + +config PCI_INT_ARBITER2_ENABLE + bool "Enabled" + +endchoice + +endif + +if ARCH_MPC8360 + +choice + prompt "PCI clock output drive" + +config PCI_CLOCK_OUTPUT_DRIVE_DISABLE + bool "Disabled" + +config PCI_CLOCK_OUTPUT_DRIVE_ENABLE + bool "Enabled" + +endchoice + +endif + +endif + +choice + prompt "Core disable mode" + +config CORE_DISABLE_MODE_OFF + bool "Off" + +config CORE_DISABLE_MODE_ON + bool "On" + +endchoice + +choice + prompt "Boot Memory Space" + +config BOOT_MEMORY_SPACE_HIGH + bool "High" + +config BOOT_MEMORY_SPACE_LOW + bool "Low" + +endchoice + +choice + prompt "Boot Sequencer Configuration" + +config BOOT_SEQUENCER_DISABLED + bool "Disabled" + +config BOOT_SEQUENCER_NORMAL_I2C + bool "Normal I2C" + +config BOOT_SEQUENCER_EXTENDED_I2C + bool "Extended I2C" + +endchoice + +choice + prompt "Software Watchdog" + +config SOFTWARE_WATCHDOG_DISABLED + bool "Disabled" + +config SOFTWARE_WATCHDOG_ENABLED + bool "Enabled" + +endchoice + +choice + prompt "Boot ROM interface location" + +config BOOT_ROM_INTERFACE_DDR_SDRAM + bool "DDR_SDRAM" + +config BOOT_ROM_INTERFACE_PCI1 + depends on MPC83XX_PCI_SUPPORT + bool "PCI1" + +config BOOT_ROM_INTERFACE_PCI2 + depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349 + bool "PCI2" + +config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM + depends on ARCH_MPC837X + bool "PCI2" + +config BOOT_ROM_INTERFACE_ESDHC + depends on ARCH_MPC8309 + bool "eSDHC" + +config BOOT_ROM_INTERFACE_SPI + depends on ARCH_MPC8309 + bool "SPI" + +config BOOT_ROM_INTERFACE_GPCM_8BIT + bool "Local bus GPCM - 8-bit ROM" + +config BOOT_ROM_INTERFACE_GPCM_16BIT + bool "Local bus GPCM - 16-bit ROM" + +config BOOT_ROM_INTERFACE_GPCM_32BIT + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + bool "Local bus GPCM - 32-bit ROM" + +config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "Local bus NAND Flash- 8-bit small page ROM" + +config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "Local bus NAND Flash- 8-bit large page ROM" + +endchoice + +if MPC83XX_TSEC1_SUPPORT + +choice + prompt "TSEC1 mode" + +config TSEC1_MODE_MII + depends on !ARCH_MPC8349 + bool "MII" + +config TSEC1_MODE_RMII + depends on ARCH_MPC831X && !ARCH_MPC8349 + bool "RMII" + +config TSEC1_MODE_RGMII + bool "RGMII" + +config TSEC1_MODE_RTBI + depends on ARCH_MPC831X || ARCH_MPC837X + bool "RTBI" + +config TSEC1_MODE_GMII + depends on ARCH_MPC8349 + bool "GMII" + +config TSEC1_MODE_TBI + depends on ARCH_MPC8349 + bool "TBI" + +config TSEC1_MODE_SGMII + depends on ARCH_MPC831X || ARCH_MPC837X + bool "SGMII" + +endchoice + +endif + +if MPC83XX_TSEC2_SUPPORT + +choice + prompt "TSEC2 mode" + +config TSEC2_MODE_MII + depends on !ARCH_MPC8349 + bool "MII" + +config TSEC2_MODE_RMII + depends on ARCH_MPC831X && !ARCH_MPC8349 + bool "RMII" + +config TSEC2_MODE_RGMII + bool "RGMII" + +config TSEC2_MODE_RTBI + depends on ARCH_MPC831X || ARCH_MPC837X + bool "RTBI" + +config TSEC2_MODE_GMII + depends on ARCH_MPC8349 + bool "GMII" + +config TSEC2_MODE_TBI + depends on ARCH_MPC8349 + bool "TBI" + +config TSEC2_MODE_SGMII + depends on ARCH_MPC831X || ARCH_MPC837X + bool "SGMII" + +endchoice + +endif + +choice + prompt "True litle-endian mode" + +config TRUE_LITTLE_ENDIAN_BIG_ENDIAN + bool "Big-endian" + +config TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN + bool "Little-endian" + +endchoice + +if ARCH_MPC8360 + +choice + prompt "Secondary DDR IO" + +config SECONDARY_DDR_IO_DISABLE + bool "Disable" + +config SECONDARY_DDR_IO_ENABLE + bool "Enable" + +endchoice + +endif + +if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360 + +choice + prompt "LALE timing" + +config LALE_TIMING_NORMAL + bool "Normal" + +config LALE_TIMING_EARLIER + bool "Earlier" + +endchoice + +endif + +if MPC83XX_LDP_PIN + +choice + prompt "LDP pin mux state" + +config LDP_PIN_MUX_STATE_1 + bool "Inital value 1" + +config LDP_PIN_MUX_STATE_0 + bool "Inital value 0" + +endchoice + +endif + +endmenu + +config LBMC_CLOCK_MODE + int + default 0 if LBMC_CLOCK_MODE_1_1 + default 1 if LBMC_CLOCK_MODE_1_2 + +config DDR_MC_CLOCK_MODE + int + default 1 if DDR_MC_CLOCK_MODE_1_2 + default 0 if DDR_MC_CLOCK_MODE_1_1 + +config SYSTEM_PLL_VCO_DIV + int + default 0 if ARCH_MPC8349 || ARCH_MPC832X + default 2 if ARCH_MPC8313 + default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X + default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X + default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X + default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X) + default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X) + default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X) + default 3 if SYSTEM_PLL_VCO_DIV_1 + +config SYSTEM_PLL_FACTOR + int + default 2 if SYSTEM_PLL_FACTOR_2_1 + default 3 if SYSTEM_PLL_FACTOR_3_1 + default 4 if SYSTEM_PLL_FACTOR_4_1 + default 5 if SYSTEM_PLL_FACTOR_5_1 + default 6 if SYSTEM_PLL_FACTOR_6_1 + default 7 if SYSTEM_PLL_FACTOR_7_1 + default 8 if SYSTEM_PLL_FACTOR_8_1 + default 9 if SYSTEM_PLL_FACTOR_9_1 + default 10 if SYSTEM_PLL_FACTOR_10_1 + default 11 if SYSTEM_PLL_FACTOR_11_1 + default 12 if SYSTEM_PLL_FACTOR_12_1 + default 13 if SYSTEM_PLL_FACTOR_13_1 + default 14 if SYSTEM_PLL_FACTOR_14_1 + default 15 if SYSTEM_PLL_FACTOR_15_1 + default 0 if SYSTEM_PLL_FACTOR_16_1 + +config CORE_PLL_RATIO + hex + default 0x0 if CORE_PLL_BYPASS + default 0x02 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x22 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x42 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_8 + default 0x03 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x23 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x43 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_8 + default 0x04 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x24 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x44 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_8 + default 0x05 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x25 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x45 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_8 + default 0x06 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x26 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x46 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_8 + +config CORE_DISABLE_MODE + int + default 0 if CORE_DISABLE_MODE_OFF + default 1 if CORE_DISABLE_MODE_ON + +config BOOT_MEMORY_SPACE + int + default 0 if BOOT_MEMORY_SPACE_LOW + default 1 if BOOT_MEMORY_SPACE_HIGH + +config BOOT_SEQUENCER + int + default 0 if BOOT_SEQUENCER_DISABLED + default 1 if BOOT_SEQUENCER_NORMAL_I2C + default 2 if BOOT_SEQUENCER_EXTENDED_I2C + +config SOFTWARE_WATCHDOG + int + default 0 if SOFTWARE_WATCHDOG_DISABLED + default 1 if SOFTWARE_WATCHDOG_ENABLED + +config BOOT_ROM_INTERFACE + hex + default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM + default 0x4 if BOOT_ROM_INTERFACE_PCI1 + default 0x8 if BOOT_ROM_INTERFACE_PCI2 + default 0x8 if BOOT_ROM_INTERFACE_ESDHC + default 0xc if BOOT_ROM_INTERFACE_SPI + default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM + default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT + default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT + default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT + default 0x5 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL + default 0x15 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE + +config TSEC1_MODE + hex + default 0x0 if !MPC83XX_TSEC1_SUPPORT + default 0x0 if TSEC1_MODE_MII + default 0x1 if TSEC1_MODE_RMII + default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349 + default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349 + default 0x6 if TSEC1_MODE_SGMII + default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349 + default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349 + default 0x2 if TSEC1_MODE_GMII + default 0x3 if TSEC1_MODE_TBI + +config TSEC2_MODE + hex + default 0x0 if !MPC83XX_TSEC2_SUPPORT + default 0x0 if TSEC2_MODE_MII + default 0x1 if TSEC2_MODE_RMII + default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349 + default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349 + default 0x6 if TSEC2_MODE_SGMII + default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349 + default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349 + default 0x2 if TSEC2_MODE_GMII + default 0x3 if TSEC2_MODE_TBI + +config SECONDARY_DDR_IO + int + default 0 if !ARCH_MPC8360 + default 0 if SECONDARY_DDR_IO_DISABLE + default 1 if SECONDARY_DDR_IO_ENABLE + +config TRUE_LITTLE_ENDIAN + int + default 0 if TRUE_LITTLE_ENDIAN_BIG_ENDIAN + default 1 if TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN + +config LALE_TIMING + int + default 0 if ARCH_MPC830X || ARCH_MPC837X + default 0 if LALE_TIMING_NORMAL + default 1 if LALE_TIMING_EARLIER + +config LDP_PIN_MUX_STATE + int + default 0 if !MPC83XX_LDP_PIN + default 0 if LDP_PIN_MUX_STATE_1 + default 1 if LDP_PIN_MUX_STATE_0 + +config QUICC_VCO_DIVIDER + int + default 0 if !MPC83XX_QUICC_ENGINE + default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309 + default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309 + default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309 + default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360) + default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360) + default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360 + +config QUICC_DIV_FACTOR + int + default 0 if !MPC83XX_QUICC_ENGINE + default 0 if QUICC_DIV_FACTOR_1 + default 1 if QUICC_DIV_FACTOR_2 + +config QUICC_MULT_FACTOR + int + default 0 if !MPC83XX_QUICC_ENGINE + default 2 if QUICC_MULT_FACTOR_2 + default 3 if QUICC_MULT_FACTOR_3 + default 4 if QUICC_MULT_FACTOR_4 + default 5 if QUICC_MULT_FACTOR_5 + default 6 if QUICC_MULT_FACTOR_6 + default 7 if QUICC_MULT_FACTOR_7 + default 8 if QUICC_MULT_FACTOR_8 + default 9 if QUICC_MULT_FACTOR_9 + default 10 if QUICC_MULT_FACTOR_10 + default 11 if QUICC_MULT_FACTOR_11 + default 12 if QUICC_MULT_FACTOR_12 + default 13 if QUICC_MULT_FACTOR_13 + default 14 if QUICC_MULT_FACTOR_14 + default 15 if QUICC_MULT_FACTOR_15 + default 16 if QUICC_MULT_FACTOR_16 + default 17 if QUICC_MULT_FACTOR_17 + default 18 if QUICC_MULT_FACTOR_18 + default 19 if QUICC_MULT_FACTOR_19 + default 20 if QUICC_MULT_FACTOR_20 + default 21 if QUICC_MULT_FACTOR_21 + default 22 if QUICC_MULT_FACTOR_22 + default 23 if QUICC_MULT_FACTOR_23 + default 24 if QUICC_MULT_FACTOR_24 + default 25 if QUICC_MULT_FACTOR_25 + default 26 if QUICC_MULT_FACTOR_26 + default 27 if QUICC_MULT_FACTOR_27 + default 28 if QUICC_MULT_FACTOR_28 + default 29 if QUICC_MULT_FACTOR_29 + default 30 if QUICC_MULT_FACTOR_30 + default 31 if QUICC_MULT_FACTOR_31 + +config PCI_HOST_MODE + int + default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308 + default 0 if PCI_HOST_MODE_DISABLE + default 1 if PCI_HOST_MODE_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless + +config PCI_64BIT_MODE + int + default 0 if !ARCH_MPC8349 + default 0 if PCI_64BIT_MODE_DISABLE + default 1 if PCI_64BIT_MODE_ENABLE + +config PCI_INT_ARBITER1 + int + default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308 + default 0 if PCI_INT_ARBITER1_DISABLE + default 1 if PCI_INT_ARBITER1_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless + +config PCI_INT_ARBITER2 + int + default 0 if !ARCH_MPC8349 + default 0 if PCI_INT_ARBITER2_DISABLE + default 1 if PCI_INT_ARBITER2_ENABLE + +config PCI_CLOCK_OUTPUT_DRIVE + int + default 0 if !ARCH_MPC8360 + default 0 if PCI_CLOCK_OUTPUT_DRIVE_DISABLE + default 1 if PCI_CLOCK_OUTPUT_DRIVE_ENABLE diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h new file mode 100644 index 00000000000..7d66ba726b9 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h @@ -0,0 +1,37 @@ +#ifdef CONFIG_ARCH_MPC8349 +#define TSEC1_MODE_SHIFT 17 +#define TSEC2_MODE_SHIFT 19 +#else +#define TSEC1_MODE_SHIFT 18 +#define TSEC2_MODE_SHIFT 21 +#endif + +#define CONFIG_SYS_HRCW_LOW (\ + (CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\ + (CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\ + (CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\ + (CONFIG_SYSTEM_PLL_FACTOR << (31 - 7)) |\ + (CONFIG_CORE_PLL_RATIO << (31 - 15)) |\ + (CONFIG_QUICC_VCO_DIVIDER << (31 - 25)) |\ + (CONFIG_QUICC_DIV_FACTOR << (31 - 26)) |\ + (CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \ + ) + +#define CONFIG_SYS_HRCW_HIGH (\ + (CONFIG_PCI_HOST_MODE << (31 - 0)) |\ + (CONFIG_PCI_64BIT_MODE << (31 - 1)) |\ + (CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\ + (CONFIG_PCI_INT_ARBITER2 << (31 - 3)) |\ + (CONFIG_PCI_CLOCK_OUTPUT_DRIVE << (31 - 3)) |\ + (CONFIG_CORE_DISABLE_MODE << (31 - 4)) |\ + (CONFIG_BOOT_MEMORY_SPACE << (31 - 5)) |\ + (CONFIG_BOOT_SEQUENCER << (31 - 7)) |\ + (CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\ + (CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\ + (CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\ + (CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\ + (CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\ + (CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\ + (CONFIG_LALE_TIMING << (31 - 29)) |\ + (CONFIG_LDP_PIN_MUX_STATE << (31 - 30)) \ + ) diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index a3bacf138c2..8784445e158 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -24,6 +24,8 @@ #include <asm/mmu.h> #include <asm/u-boot.h>
+#include "hrcw/hrcw.h" + /* We don't want the MMU yet. */ #undef MSR_KERNEL diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS index 5a67b409934..cdac1ac2eed 100644 --- a/board/freescale/mpc8315erdb/MAINTAINERS +++ b/board/freescale/mpc8315erdb/MAINTAINERS @@ -4,3 +4,4 @@ S: Orphan (since 2018-05) F: board/freescale/mpc8315erdb/ F: include/configs/MPC8315ERDB.h F: configs/MPC8315ERDB_defconfig +F: configs/MPC8315ERDB_NANDSPL_defconfig diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS index f236d543ccc..25c5f5f95cb 100644 --- a/board/freescale/mpc8349emds/MAINTAINERS +++ b/board/freescale/mpc8349emds/MAINTAINERS @@ -4,4 +4,5 @@ S: Orphan (since 2018-05) F: board/freescale/mpc8349emds/ F: include/configs/MPC8349EMDS.h F: configs/MPC8349EMDS_defconfig +F: configs/MPC8349EMDS_PCI64_defconfig F: configs/MPC8349EMDS_SLAVE_defconfig diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index d90553384f6..c4bec090be1 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -19,6 +19,8 @@ #include <linux/libfdt.h> #endif
+#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h" + DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPD_EEPROM diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS index 8386aa72977..ce9c446f2df 100644 --- a/board/freescale/mpc837xemds/MAINTAINERS +++ b/board/freescale/mpc837xemds/MAINTAINERS @@ -4,4 +4,5 @@ S: Orphan (since 2018-05) F: board/freescale/mpc837xemds/ F: include/configs/MPC837XEMDS.h F: configs/MPC837XEMDS_defconfig +F: configs/MPC837XEMDS_SLAVE_defconfig F: configs/MPC837XEMDS_HOST_defconfig diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 59dde136f2c..042f6aa010f 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308RDB=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 4851611cf53..c99d7399966 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -3,6 +3,14 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NOR=y +CONFIG_SYSTEM_PLL_FACTOR_5_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index fb4fddec469..c1eb49af7bc 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NOR=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 5fa8eba8537..df4716e26cc 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -5,6 +5,13 @@ CONFIG_SPL=y CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NAND=y +CONFIG_SYSTEM_PLL_FACTOR_5_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index f5dd21a943a..c69e3ff2ed9 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -5,6 +5,12 @@ CONFIG_SPL=y CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NAND=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index 15dbbe35dd1..cb3f206038b 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -3,6 +3,14 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8315ERDB=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index c43ae8c9929..cdc559a5812 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8323ERDB=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index a40f16d49b4..5f14da422dd 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 1031dd655ad..41245a3fc97 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 416e0e9aeab..ea90bea77d7 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index 29b8f1a988d..49446940481 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -3,6 +3,9 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index 2a15e5c18e9..d04292a3886 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig new file mode 100644 index 00000000000..db0698237be --- /dev/null +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -0,0 +1,35 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8349EMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +# CONFIG_MMC is not set +CONFIG_MTD_NOR_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index d4f6587bb38..8465cc6800f 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS_SDRAM=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 11e3b144b74..b0cb93bf7fa 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y +CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" @@ -19,7 +28,8 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y -CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 9a6eebf746c..ecded68c053 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index c7f465e4095..13312e04aa8 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 7dbde3222b2..221edf9116e 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index d3ab1eafeb1..46c9085852c 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xFEF00000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 15d60a2ccd3..1b88b599f42 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_6_1=y +CONFIG_CORE_PLL_RATIO_15_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig new file mode 100644 index 00000000000..8a50ff16d03 --- /dev/null +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -0,0 +1,35 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC837XEMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_6_1=y +CONFIG_CORE_PLL_RATIO_15_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" +CONFIG_BOOTDELAY=6 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index d5d42ab12fa..da908c762f6 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_6_1=y +CONFIG_CORE_PLL_RATIO_15_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 8c2389c6989..e145504ded2 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XERDB=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_5_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 090b9e51522..4b9a7deb945 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XERDB=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_5_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index 8f68804a482..1e873c3e019 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0x80000000 CONFIG_SYS_CLK_FREQ=66666000 CONFIG_MPC83xx=y CONFIG_TARGET_TQM834X=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 2d2d64d1038..29ec5e0afcf 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_CADDY2=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 2a7b932b1e0..97fe0e06fef 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -4,6 +4,12 @@ CONFIG_IDENT_STRING=" hrcon 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 3b1fbca2687..83dd6bf3a91 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -4,6 +4,12 @@ CONFIG_IDENT_STRING=" hrcon dh 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 7223af1f55f..482b51ef878 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -3,6 +3,9 @@ CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_IDS8313=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_IMAGE_FORMAT_LEGACY=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index beac453ce5c..7f22fa3b15a 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMCOGE5NE=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_VCO_DIV_4=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_6=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_LALE_TIMING_EARLIER=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 2bf2c40a637..600a1ad1dc8 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMETER1=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_VCO_DIV_4=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_6=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_LALE_TIMING_EARLIER=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 1b63b427f0f..6486c6a59cb 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMOPTI2=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index df1bfaef187..20df9f3fa46 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMSUPX5=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 7187af77863..c1d30cdde86 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -3,6 +3,11 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMTEGR1=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index bbd13b8bfaa..ed8bc32d653 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMTEPR2=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 98dd9e2b374..66b3cd39b59 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -3,6 +3,11 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMVECT1=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index 1e50782f7cf..cb24c97f045 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -3,6 +3,11 @@ CONFIG_SYS_TEXT_BASE=0xFC000000 CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308_P1M=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index eca22bec3ab..7fc0edde70a 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=33000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_8_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index fa1ec519c51..80cdd644f70 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index d70332c785c..1141b791e73 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 194cebdb67f..c2faf3855ee 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider con 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 4e72582d2f6..cff81f41f52 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider con dp 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index c633e030e34..f72bec439b2 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider cpu 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index e1d08e782d4..0e430496639 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider cpu dp 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 4744122e4ed..9b36aa0fa42 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SUVD3=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SUVD3" diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 349b1d00094..3467b7ebd93 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_TUGE1=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index a6654c90259..f67e3b8728d 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 084b1bdeaf5..f09c83d8561 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=32000000 CONFIG_MPC83xx=y CONFIG_TARGET_VE8313=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_LALE_TIMING_EARLIER=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index aae22141927..271e6905356 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_VME8349=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 77c30093bfd..db283578b9b 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -27,38 +27,6 @@ #define CONFIG_TSEC1 #define CONFIG_VSC7385_ENET
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - /* * System IO Config */ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 103ace2d3a9..e14652a6268 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -424,44 +424,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#ifdef CONFIG_SYS_66MHZ - -/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ -/* 0x62040000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif defined(CONFIG_SYS_33MHZ) - -/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ -/* 0x65040000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_5X1 |\ - HRCWL_CORE_TO_CSB_2X1) -#endif - -#define CONFIG_SYS_HRCW_HIGH_BASE (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_ROM_LOC_NAND_SP_8BIT |\ - HRCWH_RL_EXT_NAND) #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
/* System IO Config */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 64b289adce4..b550a8daf82 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -398,46 +398,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#ifdef CONFIG_SYS_66MHZ - -/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ -/* 0x62040000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#elif defined(CONFIG_SYS_33MHZ) - -/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ -/* 0x65040000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_5X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#endif - -#define CONFIG_SYS_HRCW_HIGH_BASE (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY) #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
/* System IO Config */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 53a02f415fe..446c98bad1a 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -23,40 +23,6 @@ */ #define CONFIG_E300 1 /* E300 family */
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_3X1) -#define CONFIG_SYS_HRCW_HIGH_BASE (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) - -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_ROM_LOC_NAND_SP_8BIT |\ - HRCWH_RL_EXT_NAND) -#else -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY) -#endif - /* * System IO Config */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index ee4eeec8856..7dbbb4e0fbd 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -15,30 +15,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2_5X1 |\ - HRCWL_CE_PLL_VCO_DIV_2 |\ - HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) - /* * System IO Config */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 0ba64772542..dad8407f679 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -12,43 +12,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1 |\ - HRCWL_CE_PLL_VCO_DIV_2 |\ - HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X3) - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) -#endif - /* * System IO Config */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 4c9ee76815c..21594540614 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -17,12 +17,6 @@ */ #define CONFIG_E300 1 /* E300 Family */
-#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#elif CONFIG_SYS_CLK_FREQ == 33000000 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -363,86 +357,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#if 1 /*528/264*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*396/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_3X1) -#elif 0 /*264/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*132/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#elif 0 /*264/264 */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#endif - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif /* CONFIG_PCI_64BIT */ -#endif /* CONFIG_PCISLAVE */ - /* * System performance */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index b9710b65882..a19e732d8a6 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -17,12 +17,6 @@ */ #define CONFIG_E300 1 /* E300 Family */
-#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#elif CONFIG_SYS_CLK_FREQ == 33000000 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -435,86 +429,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#if 1 /*528/264*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*396/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_3X1) -#elif 0 /*264/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*132/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#elif 0 /*264/264 */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#endif - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif /* CONFIG_PCI_64BIT */ -#endif /* CONFIG_PCISLAVE */ - /* * System performance */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index e170271c40d..6860c727946 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -39,10 +39,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) -#define CONFIG_SYS_LOWBOOT -#endif - /* * High Level Configuration Options */ @@ -461,41 +457,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#ifdef CONFIG_SYS_LOWBOOT -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* * System performance */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 33c485aab78..8c562fde2e5 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -12,48 +12,6 @@ */ #define CONFIG_E300 1 /* E300 family */
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66MHz, then - * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_6X1 |\ - HRCWL_CORE_TO_CSB_1_5X1) - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#endif - /* Arbiter Configuration Register */ #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 806b0f32e54..055a30e24fc 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -20,46 +20,6 @@ */ #define CONFIG_VSC7385_ENET
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_5X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#endif - /* System performance - define the value i.e. CONFIG_SYS_XXX */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 58c301553e3..be1c2893f16 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -260,41 +260,6 @@ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 68fb989856c..5e88bd7edab 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -25,12 +25,6 @@ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#ifdef CONFIG_PCI_66M -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#else -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -290,41 +284,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 8eb12b76709..c1fe6b45bd5 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -16,38 +16,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - /* * System IO Config */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index eff0addd519..4e5927ed700 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -25,27 +25,6 @@ #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66.000MHz, then - * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz - */ -#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_8BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_MII |\ - HRCWH_TSEC2M_IN_MII |\ - HRCWH_BIG_ENDIAN) - #define CONFIG_SYS_SICRH 0x00000000 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 1cff0a19f1b..32576fe3aa5 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -318,25 +318,6 @@ */ #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_CSB_TO_CLKIN_4X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X6) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_EARLY | \ - HRCWH_LDP_CLEAR) - /** * DDR RAM settings */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2280f007f2f..3a98f9497b4 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -304,25 +304,6 @@ */ #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_CSB_TO_CLKIN_4X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X6) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_EARLY | \ - HRCWH_LDP_CLEAR) - /** * DDR RAM settings */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index fa12d41080a..44944754867 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -323,28 +323,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 30898c0b75c..7c008f8516c 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -323,28 +323,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 329a5cfe0fe..95b16ca5852 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -374,28 +374,6 @@ #define CONFIG_SYS_GP2DIR 0xFF000000 #define CONFIG_SYS_GP2ODR 0x00000000
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 02b72c874e1..5191f2c4b01 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -323,28 +323,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index c21b9ba38f1..cc88f071ec6 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -366,28 +366,6 @@ #define CONFIG_SYS_GP2DIR 0xFF000000 #define CONFIG_SYS_GP2ODR 0x00000000
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index fd59471370d..2822aa3b9da 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -21,38 +21,6 @@ #define CONFIG_TSEC1 #define CONFIG_TSEC2
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_MII |\ - HRCWH_TSEC2M_IN_MII |\ - HRCWH_BIG_ENDIAN) - /* * System IO Config */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 2520a77dd3c..fd67aca2079 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -22,12 +22,6 @@ /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#ifdef CONFIG_PCI_33M -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#else /* 66M */ -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -374,71 +368,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#if 1 /*528/264*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*396/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_3X1) -#elif 0 /*264/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*132/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#elif 0 /*264/264 */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#endif - -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A diff --git a/include/configs/strider.h b/include/configs/strider.h index 8c9acfba8d5..ef33eaef9b0 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -16,38 +16,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_MII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - /* * System IO Config */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 87f7390bcc2..c84c7c0f6e2 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -320,28 +320,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 1cd0985dc29..8f60db30550 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -323,28 +323,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 0d7c571ee5f..9dddbae47b3 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -323,28 +323,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 2ef6f88bdf6..c4bdfe574a7 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -308,25 +308,6 @@ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-/* 0x64050000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_CSB_TO_CLKIN_4X1 | \ - HRCWL_CORE_TO_CSB_2_5X1) - -/* 0xa0600004 */ -#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ - HRCWH_PCI_ARBITER_ENABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_TSEC1M_IN_MII | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_EARLY) - /* System IO Config */ #define CONFIG_SYS_SICRH (0x01000000 | \ SICRH_ETSEC2_B | \ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index c5086958ff3..ca6233a26ec 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -25,14 +25,6 @@ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#define CONFIG_PCI_66M - -#ifdef CONFIG_PCI_66M -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#else -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -292,41 +284,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A
The MPC83xx DM timer driver disables arch.pciexp*_clk, and uses clk_get_rate instead. But the legacy MPC83xx PCIe driver still uses arch.pciexp*_clk for the clock.
Hence, read the PCIe clock from the registers in the legacy MPC83xx PCIe driver.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- arch/powerpc/cpu/mpc83xx/pcie.c | 39 ++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index c250150224d..2608447d80d 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -176,6 +176,41 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
+int get_pcie_clk(int index) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 pci_sync_in; + u8 spmf; + u8 clkin_div; + u32 sccr; + u32 csb_clk; + u32 testval; + + clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); + sccr = im->clk.sccr; + pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div); + spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; + csb_clk = pci_sync_in * (1 + clkin_div) * spmf; + + if (index) + testval = (sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT; + else + testval = (sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT; + + switch (testval) { + case 0: + return 0; + case 1: + return csb_clk; + case 2: + return csb_clk / 2; + case 3: + return csb_clk / 3; + } + + return 0; +} + static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) { immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; @@ -271,11 +306,9 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) /* Hose configure header is memory-mapped */ hose_cfg_base = (void *)pex;
- get_clocks(); /* Configure the PCIE controller core clock ratio */ out_le32(hose_cfg_base + PEX_GCLK_RATIO, - (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk) - / 1000000) * 16) / 333); + ((get_pcie_clk(bus) / 1000000) * 16) / 333); udelay(1000000);
/* Do Type 1 bridge configuration */
Migrate the CONFIG_HIGH_BATS variable to Kconfig.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: * Removed config option from whitelist
--- arch/powerpc/Kconfig | 6 ++++++ configs/MPC8313ERDB_33_defconfig | 1 + configs/MPC8313ERDB_66_defconfig | 1 + configs/MPC8313ERDB_NAND_33_defconfig | 1 + configs/MPC8313ERDB_NAND_66_defconfig | 1 + configs/MPC8315ERDB_defconfig | 1 + configs/MPC8323ERDB_defconfig | 1 + configs/MPC832XEMDS_ATM_defconfig | 1 + configs/MPC832XEMDS_HOST_33_defconfig | 1 + configs/MPC832XEMDS_HOST_66_defconfig | 1 + configs/MPC832XEMDS_SLAVE_defconfig | 1 + configs/MPC832XEMDS_defconfig | 1 + configs/MPC8349EMDS_PCI64_defconfig | 1 + configs/MPC8349EMDS_SDRAM_defconfig | 1 + configs/MPC8349EMDS_SLAVE_defconfig | 1 + configs/MPC8349EMDS_defconfig | 1 + configs/MPC8349ITXGP_defconfig | 1 + configs/MPC8349ITX_LOWBOOT_defconfig | 1 + configs/MPC8349ITX_defconfig | 1 + configs/MPC837XEMDS_HOST_defconfig | 1 + configs/MPC837XEMDS_defconfig | 1 + configs/MPC837XERDB_defconfig | 1 + configs/MPC8610HPCD_defconfig | 1 + configs/MPC8641HPCN_36BIT_defconfig | 1 + configs/MPC8641HPCN_defconfig | 1 + configs/TQM834x_defconfig | 1 + configs/caddy2_defconfig | 1 + configs/ids8313_defconfig | 1 + configs/kmcoge5ne_defconfig | 1 + configs/kmopti2_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmtegr1_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/kmvect1_defconfig | 1 + configs/sbc8349_PCI_33_defconfig | 1 + configs/sbc8349_PCI_66_defconfig | 1 + configs/sbc8349_defconfig | 1 + configs/sbc8641d_defconfig | 1 + configs/suvd3_defconfig | 1 + configs/tuge1_defconfig | 1 + configs/tuxx1_defconfig | 1 + configs/ve8313_defconfig | 1 + configs/vme8349_defconfig | 1 + configs/xpedite517x_defconfig | 1 + include/configs/MPC8313ERDB_NAND.h | 2 -- include/configs/MPC8313ERDB_NOR.h | 2 -- include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8323ERDB.h | 1 - include/configs/MPC832XEMDS.h | 2 -- include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349EMDS_SDRAM.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 2 -- include/configs/MPC8610HPCD.h | 1 - include/configs/MPC8641HPCN.h | 1 - include/configs/TQM834x.h | 2 -- include/configs/caddy2.h | 2 -- include/configs/ids8313.h | 1 - include/configs/kmcoge5ne.h | 2 -- include/configs/kmeter1.h | 2 -- include/configs/kmopti2.h | 2 -- include/configs/kmsupx5.h | 2 -- include/configs/kmtegr1.h | 2 -- include/configs/kmtepr2.h | 2 -- include/configs/kmvect1.h | 2 -- include/configs/sbc8349.h | 2 -- include/configs/sbc8641d.h | 1 - include/configs/suvd3.h | 2 -- include/configs/tuge1.h | 2 -- include/configs/tuxx1.h | 2 -- include/configs/ve8313.h | 2 -- include/configs/vme8349.h | 2 -- include/configs/xpedite517x.h | 1 - scripts/config_whitelist.txt | 1 - 75 files changed, 49 insertions(+), 50 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index c727d9162c4..ab9eefef153 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -39,6 +39,12 @@ config MPC8xx
endchoice
+config HIGH_BATS + bool "Enable high BAT registers" + help + Enable BATs (block address translation registers) 4-7 on machines + that support them. + source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc86xx/Kconfig" diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index c99d7399966..641c6c8545b 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8313ERDB_NOR=y CONFIG_SYSTEM_PLL_FACTOR_5_1=y CONFIG_CORE_PLL_RATIO_2_1=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index c1eb49af7bc..b1a4bcbc538 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8313ERDB_NOR=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_PCI_HOST_MODE_ENABLE=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index df4716e26cc..d3d26d319ff 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8313ERDB_NAND=y CONFIG_SYSTEM_PLL_FACTOR_5_1=y CONFIG_CORE_PLL_RATIO_2_1=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index c69e3ff2ed9..59d887e675b 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8313ERDB_NAND=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_PCI_HOST_MODE_ENABLE=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index cb3f206038b..149e71c310e 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8315ERDB=y CONFIG_SYSTEM_PLL_VCO_DIV_2=y CONFIG_CORE_PLL_RATIO_3_1=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index cdc559a5812..49e690e88ba 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8323ERDB=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 5f14da422dd..323b368f9ef 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 41245a3fc97..a13dcfb91da 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index ea90bea77d7..2a4ff9a3e11 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index 49446940481..e7ea39a2368 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index d04292a3886..bffc55b917b 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC832XEMDS=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index db0698237be..11bce06a093 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349EMDS=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index 8465cc6800f..6b571b03688 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349EMDS_SDRAM=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index b0cb93bf7fa..87892c3d672 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349EMDS=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index ecded68c053..40633d19be4 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349EMDS=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 13312e04aa8..9e466b1bd10 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349ITX=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 221edf9116e..3a612357361 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349ITX=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 46c9085852c..ed9bd83302a 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFEF00000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8349ITX=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 1b88b599f42..73ba7dc6328 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC837XEMDS=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_6_1=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index da908c762f6..cf0694f3b54 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC837XEMDS=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_6_1=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 4b9a7deb945..03fd7b70bae 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC837XERDB=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_5_1=y diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig index cfdfa9011fc..80ea441aa33 100644 --- a/configs/MPC8610HPCD_defconfig +++ b/configs/MPC8610HPCD_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xfff00000 CONFIG_MPC86xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8610HPCD=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig index 4b924c08b3c..81901f7a28b 100644 --- a/configs/MPC8641HPCN_36BIT_defconfig +++ b/configs/MPC8641HPCN_36BIT_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xeff00000 CONFIG_MPC86xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8641HPCN=y CONFIG_PHYS_64BIT=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig index 52fba9750da..497d398c834 100644 --- a/configs/MPC8641HPCN_defconfig +++ b/configs/MPC8641HPCN_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xeff00000 CONFIG_MPC86xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_MPC8641HPCN=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index 1e873c3e019..c746afd1fd7 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x80000000 CONFIG_SYS_CLK_FREQ=66666000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_TQM834X=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 29ec5e0afcf..b52ea881ce6 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_CADDY2=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 482b51ef878..a8619ef621b 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_IDS8313=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_PCI_HOST_MODE_ENABLE=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 7f22fa3b15a..03437f7cb83 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMCOGE5NE=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_VCO_DIV_4=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 6486c6a59cb..ba489eeb6ac 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMOPTI2=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 20df9f3fa46..f39bca4fbd0 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMSUPX5=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index c1d30cdde86..3e7b2f73fd9 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMTEGR1=y CONFIG_SYSTEM_PLL_VCO_DIV_2=y CONFIG_CORE_PLL_RATIO_2_1=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index ed8bc32d653..0f32283e9db 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMTEPR2=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 66b3cd39b59..ec3ff28793b 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMVECT1=y CONFIG_SYSTEM_PLL_VCO_DIV_2=y CONFIG_CORE_PLL_RATIO_2_1=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 7fc0edde70a..47feb5ae36d 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=33000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_SBC8349=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_8_1=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 80cdd644f70..019341691f2 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_SBC8349=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 1141b791e73..f7c3de8e9eb 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_SBC8349=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig index d1ffea5afbf..47cec18a95e 100644 --- a/configs/sbc8641d_defconfig +++ b/configs/sbc8641d_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xfff00000 CONFIG_MPC86xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_SBC8641D=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 9b36aa0fa42..b6f17d2f292 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_SUVD3=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 3467b7ebd93..445b89d483f 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_TUGE1=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index f67e3b8728d..d7b0a94ada7 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_TUXX1=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index f09c83d8561..52a51cc5bb5 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=32000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_VE8313=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_25_1=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 271e6905356..3f1f5c069b6 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_VME8349=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig index d2d8313da66..cad95d338ed 100644 --- a/configs/xpedite517x_defconfig +++ b/configs/xpedite517x_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xfff00000 CONFIG_MPC86xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_XPEDITE517X=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index e14652a6268..e3bcc63e130 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -438,8 +438,6 @@
#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index b550a8daf82..af2432b12d2 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -412,8 +412,6 @@
#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 446c98bad1a..d2f9309cd61 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -404,7 +404,6 @@ /* * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 7dbbb4e0fbd..37f173ef747 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -300,7 +300,6 @@ /* * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index dad8407f679..d8cadde0e0e 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -364,8 +364,6 @@ * MMU Setup */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ | BATL_PP_RW \ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 21594540614..d70e477f80e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -381,7 +381,6 @@ HID0_ENABLE_ADDRESS_BROADCAST) */
#define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index a19e732d8a6..286654066cf 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -453,7 +453,6 @@ HID0_ENABLE_ADDRESS_BROADCAST) */
#define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 6860c727946..e7031e94fd9 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -481,7 +481,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
#define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 8c562fde2e5..3473ca61024 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -423,7 +423,6 @@ extern int board_pci_host_broken(void); /* * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */ #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 055a30e24fc..9ddd2af0d9c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -439,8 +439,6 @@ * MMU Setup */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index a3f29c5f9ea..beadbab1916 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -43,7 +43,6 @@ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ #define CONFIG_ALTIVEC 1
/* diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index bb6dd95d598..5f2a0117ce4 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -45,7 +45,6 @@ #define CONFIG_ENV_OVERWRITE
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
#define CONFIG_ALTIVEC 1 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index be1c2893f16..c27a04ace99 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -270,8 +270,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR 0 - 512M */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ | BATL_PP_RW \ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 5e88bd7edab..007ded02990 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -302,8 +302,6 @@ #define CONFIG_SYS_GPIO2_DIR 0x78900000 #define CONFIG_SYS_GPIO2_DAT 0x70100000
-#define CONFIG_HIGH_BATS /* High BATs supported */ - /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 4e5927ed700..ac151dccbad 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -285,7 +285,6 @@ /* * BAT's */ -#define CONFIG_HIGH_BATS
/* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 32576fe3aa5..e44c5a883fe 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -238,8 +238,6 @@ * MMU Setup */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 3a98f9497b4..2d7b3106dd0 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -224,8 +224,6 @@ * MMU Setup */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 44944754867..2f19b2e9efa 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -243,8 +243,6 @@ * MMU Setup */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 7c008f8516c..ae997a71f6a 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -243,8 +243,6 @@ * MMU Setup */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 95b16ca5852..2e4e2a3b5fd 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -247,8 +247,6 @@ * MMU Setup */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 5191f2c4b01..f998b95f933 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -243,8 +243,6 @@ * MMU Setup */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index cc88f071ec6..f4da14a6161 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -239,8 +239,6 @@ * MMU Setup */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index fd67aca2079..d6f2813e50b 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -383,8 +383,6 @@
#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ | BATL_PP_RW \ diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index e9e264b40b0..d1535b6facc 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -45,7 +45,6 @@ #define CONFIG_ENV_OVERWRITE
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index c84c7c0f6e2..4cc9f13d379 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -240,8 +240,6 @@ * MMU Setup */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 8f60db30550..8d254689cfe 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -243,8 +243,6 @@ * MMU Setup */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 9dddbae47b3..630eb19f13a 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -243,8 +243,6 @@ * MMU Setup */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index c4bdfe574a7..b15cd218f29 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -333,8 +333,6 @@
#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index ca6233a26ec..d73265e064b 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -302,8 +302,6 @@ #define CONFIG_SYS_GPIO2_DIR 0x78900000 #define CONFIG_SYS_GPIO2_DAT 0x70100000
-#define CONFIG_HIGH_BATS /* High BATs supported */ - /* DDR @ 0x00000000 */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 2d2a87a7190..1ef803b0204 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -17,7 +17,6 @@ #define CONFIG_SYS_FORM_3U_VPX 1 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #define CONFIG_ALTIVEC 1
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 3483c2598ea..e2467997a80 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -760,7 +760,6 @@ CONFIG_HDBOOT CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_HETROGENOUS_CLUSTERS CONFIG_HIDE_LOGO_VERSION -CONFIG_HIGH_BATS CONFIG_HIKEY_GPIO CONFIG_HITACHI_SX14 CONFIG_HOSTNAME
The BATs (block address translation registers) determine the initial memory window mappings. Hence, they must be known at compile time and cannot be implemented in the DT mechanism.
Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/bats/Kconfig | 1311 +++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/bats/bats.h | 223 +++++ arch/powerpc/cpu/mpc83xx/start.S | 1 + configs/MPC8308RDB_defconfig | 36 + configs/MPC8313ERDB_33_defconfig | 45 + configs/MPC8313ERDB_66_defconfig | 45 + configs/MPC8313ERDB_NAND_33_defconfig | 45 + configs/MPC8313ERDB_NAND_66_defconfig | 45 + configs/MPC8315ERDB_defconfig | 56 ++ configs/MPC8323ERDB_defconfig | 56 ++ configs/MPC832XEMDS_ATM_defconfig | 46 + configs/MPC832XEMDS_HOST_33_defconfig | 66 ++ configs/MPC832XEMDS_HOST_66_defconfig | 66 ++ configs/MPC832XEMDS_SLAVE_defconfig | 66 ++ configs/MPC832XEMDS_defconfig | 46 + configs/MPC8349EMDS_PCI64_defconfig | 31 + configs/MPC8349EMDS_SDRAM_defconfig | 31 + configs/MPC8349EMDS_SLAVE_defconfig | 31 + configs/MPC8349EMDS_defconfig | 31 + configs/MPC8349ITXGP_defconfig | 71 ++ configs/MPC8349ITX_LOWBOOT_defconfig | 71 ++ configs/MPC8349ITX_defconfig | 71 ++ configs/MPC837XEMDS_HOST_defconfig | 75 ++ configs/MPC837XEMDS_SLAVE_defconfig | 39 + configs/MPC837XEMDS_defconfig | 55 ++ configs/MPC837XERDB_SLAVE_defconfig | 39 + configs/MPC837XERDB_defconfig | 75 ++ configs/TQM834x_defconfig | 79 ++ configs/caddy2_defconfig | 49 + configs/hrcon_defconfig | 36 + configs/hrcon_dh_defconfig | 36 + configs/ids8313_defconfig | 46 + configs/kmcoge5ne_defconfig | 79 ++ configs/kmeter1_defconfig | 53 + configs/kmopti2_defconfig | 68 ++ configs/kmsupx5_defconfig | 58 ++ configs/kmtegr1_defconfig | 58 ++ configs/kmtepr2_defconfig | 68 ++ configs/kmvect1_defconfig | 68 ++ configs/mpc8308_p1m_defconfig | 36 + configs/sbc8349_PCI_33_defconfig | 51 + configs/sbc8349_PCI_66_defconfig | 51 + configs/sbc8349_defconfig | 31 + configs/strider_con_defconfig | 36 + configs/strider_con_dp_defconfig | 36 + configs/strider_cpu_defconfig | 36 + configs/strider_cpu_dp_defconfig | 36 + configs/suvd3_defconfig | 68 ++ configs/tuge1_defconfig | 58 ++ configs/tuxx1_defconfig | 68 ++ configs/ve8313_defconfig | 54 + configs/vme8349_defconfig | 49 + include/configs/MPC8308RDB.h | 37 - include/configs/MPC8313ERDB_NAND.h | 62 -- include/configs/MPC8313ERDB_NOR.h | 62 -- include/configs/MPC8315ERDB.h | 79 -- include/configs/MPC8323ERDB.h | 94 -- include/configs/MPC832XEMDS.h | 100 -- include/configs/MPC8349EMDS.h | 93 -- include/configs/MPC8349EMDS_SDRAM.h | 93 -- include/configs/MPC8349ITX.h | 96 -- include/configs/MPC837XEMDS.h | 108 -- include/configs/MPC837XERDB.h | 108 -- include/configs/TQM834x.h | 92 -- include/configs/caddy2.h | 72 -- include/configs/hrcon.h | 37 - include/configs/ids8313.h | 77 -- include/configs/kmcoge5ne.h | 104 -- include/configs/kmeter1.h | 77 -- include/configs/kmopti2.h | 89 -- include/configs/kmsupx5.h | 81 -- include/configs/kmtegr1.h | 68 -- include/configs/kmtepr2.h | 90 -- include/configs/kmvect1.h | 72 -- include/configs/mpc8308_p1m.h | 37 - include/configs/sbc8349.h | 93 -- include/configs/strider.h | 37 - include/configs/suvd3.h | 72 -- include/configs/tuge1.h | 81 -- include/configs/tuxx1.h | 90 -- include/configs/ve8313.h | 70 -- include/configs/vme8349.h | 72 -- 83 files changed, 4082 insertions(+), 2343 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/bats/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/bats/bats.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 1206c687cc7..f7f625aea1f 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -283,6 +283,7 @@ config ARCH_MPC837X select MPC83XX_SECOND_I2C_SUPPORT
source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" +source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
menu "Legacy options"
diff --git a/arch/powerpc/cpu/mpc83xx/bats/Kconfig b/arch/powerpc/cpu/mpc83xx/bats/Kconfig new file mode 100644 index 00000000000..218920cfc9a --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/bats/Kconfig @@ -0,0 +1,1311 @@ +menu "BATS setup" + +menuconfig BAT0 + bool "BAT0" + +if BAT0 + +config BAT0_NAME + string "Identifier" + +config BAT0_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT0_LENGTH_128_KBYTES + bool "128 kb" + +config BAT0_LENGTH_256_KBYTES + bool "256 kb" + +config BAT0_LENGTH_512_KBYTES + bool "512 kb" + +config BAT0_LENGTH_1_MBYTES + bool "1 mb" + +config BAT0_LENGTH_2_MBYTES + bool "2 mb" + +config BAT0_LENGTH_4_MBYTES + bool "4 mb" + +config BAT0_LENGTH_8_MBYTES + bool "8 mb" + +config BAT0_LENGTH_16_MBYTES + bool "16 mb" + +config BAT0_LENGTH_32_MBYTES + bool "32 mb" + +config BAT0_LENGTH_64_MBYTES + bool "64 mb" + +config BAT0_LENGTH_128_MBYTES + bool "128 mb" + +config BAT0_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT0_ACCESS_NONE + bool "No access" + +config BAT0_ACCESS_RO + bool "Read-only" + +config BAT0_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT0_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT0_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT0_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT0_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT0_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT0_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT0_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT0_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT0_USER_MODE_VALID + bool "User mode valid" + +config BAT0_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT0_LENGTH + hex + default 0x00000000 if BAT0_LENGTH_128_KBYTES + default 0x00000004 if BAT0_LENGTH_256_KBYTES + default 0x0000000c if BAT0_LENGTH_512_KBYTES + default 0x0000001c if BAT0_LENGTH_1_MBYTES + default 0x0000003c if BAT0_LENGTH_2_MBYTES + default 0x0000007c if BAT0_LENGTH_4_MBYTES + default 0x000000fc if BAT0_LENGTH_8_MBYTES + default 0x000001fc if BAT0_LENGTH_16_MBYTES + default 0x000003fc if BAT0_LENGTH_32_MBYTES + default 0x000007fc if BAT0_LENGTH_64_MBYTES + default 0x00000ffc if BAT0_LENGTH_128_MBYTES + default 0x00001ffc if BAT0_LENGTH_256_MBYTES + +config BAT0_PAGE_PROTECTION + hex + default 0x0 if BAT0_ACCESS_NONE + default 0x1 if BAT0_ACCESS_RO + default 0x2 if BAT0_ACCESS_RW + +config BAT0_WIMG_ICACHE + hex + default 0x0 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x8 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x10 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x18 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x20 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x28 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x30 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x38 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x40 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x48 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x50 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x58 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x60 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x68 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x70 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED + default 0x78 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + +config BAT0_WIMG_DCACHE + hex + default 0x0 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x8 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x10 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x18 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x20 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x28 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x30 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x38 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x40 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x48 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x50 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x58 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x60 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x68 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + default 0x70 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED + default 0x78 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED + +config BAT0_VALID_BITS + hex + default 0x0 if !BAT0_SUPERVISOR_MODE_VALID && !BAT0_USER_MODE_VALID + default 0x1 if !BAT0_SUPERVISOR_MODE_VALID && BAT0_USER_MODE_VALID + default 0x2 if BAT0_SUPERVISOR_MODE_VALID && !BAT0_USER_MODE_VALID + default 0x3 if BAT0_SUPERVISOR_MODE_VALID && BAT0_USER_MODE_VALID + +menuconfig BAT1 + bool "BAT1" + +if BAT1 + +config BAT1_NAME + string "Identifier" + +config BAT1_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT1_LENGTH_128_KBYTES + bool "128 kb" + +config BAT1_LENGTH_256_KBYTES + bool "256 kb" + +config BAT1_LENGTH_512_KBYTES + bool "512 kb" + +config BAT1_LENGTH_1_MBYTES + bool "1 mb" + +config BAT1_LENGTH_2_MBYTES + bool "2 mb" + +config BAT1_LENGTH_4_MBYTES + bool "4 mb" + +config BAT1_LENGTH_8_MBYTES + bool "8 mb" + +config BAT1_LENGTH_16_MBYTES + bool "16 mb" + +config BAT1_LENGTH_32_MBYTES + bool "32 mb" + +config BAT1_LENGTH_64_MBYTES + bool "64 mb" + +config BAT1_LENGTH_128_MBYTES + bool "128 mb" + +config BAT1_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT1_ACCESS_NONE + bool "No access" + +config BAT1_ACCESS_RO + bool "Read-only" + +config BAT1_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT1_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT1_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT1_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT1_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT1_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT1_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT1_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT1_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT1_USER_MODE_VALID + bool "User mode valid" + +config BAT1_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT1_LENGTH + hex + default 0x00000000 if BAT1_LENGTH_128_KBYTES + default 0x00000004 if BAT1_LENGTH_256_KBYTES + default 0x0000000c if BAT1_LENGTH_512_KBYTES + default 0x0000001c if BAT1_LENGTH_1_MBYTES + default 0x0000003c if BAT1_LENGTH_2_MBYTES + default 0x0000007c if BAT1_LENGTH_4_MBYTES + default 0x000000fc if BAT1_LENGTH_8_MBYTES + default 0x000001fc if BAT1_LENGTH_16_MBYTES + default 0x000003fc if BAT1_LENGTH_32_MBYTES + default 0x000007fc if BAT1_LENGTH_64_MBYTES + default 0x00000ffc if BAT1_LENGTH_128_MBYTES + default 0x00001ffc if BAT1_LENGTH_256_MBYTES + +config BAT1_PAGE_PROTECTION + hex + default 0x0 if BAT1_ACCESS_NONE + default 0x1 if BAT1_ACCESS_RO + default 0x2 if BAT1_ACCESS_RW + +config BAT1_WIMG_ICACHE + hex + default 0x0 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x8 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x10 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x18 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x20 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x28 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x30 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x38 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x40 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x48 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x50 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x58 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x60 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x68 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x70 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED + default 0x78 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + +config BAT1_WIMG_DCACHE + hex + default 0x0 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x8 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x10 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x18 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x20 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x28 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x30 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x38 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x40 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x48 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x50 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x58 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x60 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x68 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + default 0x70 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED + default 0x78 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED + +config BAT1_VALID_BITS + hex + default 0x0 if !BAT1_SUPERVISOR_MODE_VALID && !BAT1_USER_MODE_VALID + default 0x1 if !BAT1_SUPERVISOR_MODE_VALID && BAT1_USER_MODE_VALID + default 0x2 if BAT1_SUPERVISOR_MODE_VALID && !BAT1_USER_MODE_VALID + default 0x3 if BAT1_SUPERVISOR_MODE_VALID && BAT1_USER_MODE_VALID + +menuconfig BAT2 + bool "BAT2" + +if BAT2 + +config BAT2_NAME + string "Identifier" + +config BAT2_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT2_LENGTH_128_KBYTES + bool "128 kb" + +config BAT2_LENGTH_256_KBYTES + bool "256 kb" + +config BAT2_LENGTH_512_KBYTES + bool "512 kb" + +config BAT2_LENGTH_1_MBYTES + bool "1 mb" + +config BAT2_LENGTH_2_MBYTES + bool "2 mb" + +config BAT2_LENGTH_4_MBYTES + bool "4 mb" + +config BAT2_LENGTH_8_MBYTES + bool "8 mb" + +config BAT2_LENGTH_16_MBYTES + bool "16 mb" + +config BAT2_LENGTH_32_MBYTES + bool "32 mb" + +config BAT2_LENGTH_64_MBYTES + bool "64 mb" + +config BAT2_LENGTH_128_MBYTES + bool "128 mb" + +config BAT2_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT2_ACCESS_NONE + bool "No access" + +config BAT2_ACCESS_RO + bool "Read-only" + +config BAT2_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT2_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT2_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT2_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT2_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT2_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT2_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT2_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT2_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT2_USER_MODE_VALID + bool "User mode valid" + +config BAT2_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT2_LENGTH + hex + default 0x00000000 if BAT2_LENGTH_128_KBYTES + default 0x00000004 if BAT2_LENGTH_256_KBYTES + default 0x0000000c if BAT2_LENGTH_512_KBYTES + default 0x0000001c if BAT2_LENGTH_1_MBYTES + default 0x0000003c if BAT2_LENGTH_2_MBYTES + default 0x0000007c if BAT2_LENGTH_4_MBYTES + default 0x000000fc if BAT2_LENGTH_8_MBYTES + default 0x000001fc if BAT2_LENGTH_16_MBYTES + default 0x000003fc if BAT2_LENGTH_32_MBYTES + default 0x000007fc if BAT2_LENGTH_64_MBYTES + default 0x00000ffc if BAT2_LENGTH_128_MBYTES + default 0x00001ffc if BAT2_LENGTH_256_MBYTES + +config BAT2_PAGE_PROTECTION + hex + default 0x0 if BAT2_ACCESS_NONE + default 0x1 if BAT2_ACCESS_RO + default 0x2 if BAT2_ACCESS_RW + +config BAT2_WIMG_ICACHE + hex + default 0x0 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x8 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x10 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x18 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x20 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x28 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x30 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x38 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x40 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x48 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x50 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x58 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x60 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x68 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x70 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED + default 0x78 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + +config BAT2_WIMG_DCACHE + hex + default 0x0 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x8 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x10 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x18 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x20 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x28 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x30 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x38 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x40 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x48 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x50 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x58 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x60 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x68 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + default 0x70 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED + default 0x78 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED + +config BAT2_VALID_BITS + hex + default 0x0 if !BAT2_SUPERVISOR_MODE_VALID && !BAT2_USER_MODE_VALID + default 0x1 if !BAT2_SUPERVISOR_MODE_VALID && BAT2_USER_MODE_VALID + default 0x2 if BAT2_SUPERVISOR_MODE_VALID && !BAT2_USER_MODE_VALID + default 0x3 if BAT2_SUPERVISOR_MODE_VALID && BAT2_USER_MODE_VALID + +menuconfig BAT3 + bool "BAT3" + +if BAT3 + +config BAT3_NAME + string "Identifier" + +config BAT3_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT3_LENGTH_128_KBYTES + bool "128 kb" + +config BAT3_LENGTH_256_KBYTES + bool "256 kb" + +config BAT3_LENGTH_512_KBYTES + bool "512 kb" + +config BAT3_LENGTH_1_MBYTES + bool "1 mb" + +config BAT3_LENGTH_2_MBYTES + bool "2 mb" + +config BAT3_LENGTH_4_MBYTES + bool "4 mb" + +config BAT3_LENGTH_8_MBYTES + bool "8 mb" + +config BAT3_LENGTH_16_MBYTES + bool "16 mb" + +config BAT3_LENGTH_32_MBYTES + bool "32 mb" + +config BAT3_LENGTH_64_MBYTES + bool "64 mb" + +config BAT3_LENGTH_128_MBYTES + bool "128 mb" + +config BAT3_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT3_ACCESS_NONE + bool "No access" + +config BAT3_ACCESS_RO + bool "Read-only" + +config BAT3_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT3_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT3_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT3_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT3_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT3_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT3_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT3_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT3_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT3_USER_MODE_VALID + bool "User mode valid" + +config BAT3_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT3_LENGTH + hex + default 0x00000000 if BAT3_LENGTH_128_KBYTES + default 0x00000004 if BAT3_LENGTH_256_KBYTES + default 0x0000000c if BAT3_LENGTH_512_KBYTES + default 0x0000001c if BAT3_LENGTH_1_MBYTES + default 0x0000003c if BAT3_LENGTH_2_MBYTES + default 0x0000007c if BAT3_LENGTH_4_MBYTES + default 0x000000fc if BAT3_LENGTH_8_MBYTES + default 0x000001fc if BAT3_LENGTH_16_MBYTES + default 0x000003fc if BAT3_LENGTH_32_MBYTES + default 0x000007fc if BAT3_LENGTH_64_MBYTES + default 0x00000ffc if BAT3_LENGTH_128_MBYTES + default 0x00001ffc if BAT3_LENGTH_256_MBYTES + +config BAT3_PAGE_PROTECTION + hex + default 0x0 if BAT3_ACCESS_NONE + default 0x1 if BAT3_ACCESS_RO + default 0x2 if BAT3_ACCESS_RW + +config BAT3_WIMG_ICACHE + hex + default 0x0 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x8 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x10 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x18 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x20 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x28 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x30 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x38 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x40 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x48 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x50 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x58 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x60 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x68 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x70 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED + default 0x78 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + +config BAT3_WIMG_DCACHE + hex + default 0x0 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x8 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x10 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x18 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x20 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x28 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x30 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x38 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x40 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x48 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x50 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x58 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x60 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x68 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + default 0x70 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED + default 0x78 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED + +config BAT3_VALID_BITS + hex + default 0x0 if !BAT3_SUPERVISOR_MODE_VALID && !BAT3_USER_MODE_VALID + default 0x1 if !BAT3_SUPERVISOR_MODE_VALID && BAT3_USER_MODE_VALID + default 0x2 if BAT3_SUPERVISOR_MODE_VALID && !BAT3_USER_MODE_VALID + default 0x3 if BAT3_SUPERVISOR_MODE_VALID && BAT3_USER_MODE_VALID + +if HIGH_BATS + +menuconfig BAT4 + bool "BAT4" + +if BAT4 + +config BAT4_NAME + string "Identifier" + +config BAT4_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT4_LENGTH_128_KBYTES + bool "128 kb" + +config BAT4_LENGTH_256_KBYTES + bool "256 kb" + +config BAT4_LENGTH_512_KBYTES + bool "512 kb" + +config BAT4_LENGTH_1_MBYTES + bool "1 mb" + +config BAT4_LENGTH_2_MBYTES + bool "2 mb" + +config BAT4_LENGTH_4_MBYTES + bool "4 mb" + +config BAT4_LENGTH_8_MBYTES + bool "8 mb" + +config BAT4_LENGTH_16_MBYTES + bool "16 mb" + +config BAT4_LENGTH_32_MBYTES + bool "32 mb" + +config BAT4_LENGTH_64_MBYTES + bool "64 mb" + +config BAT4_LENGTH_128_MBYTES + bool "128 mb" + +config BAT4_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT4_ACCESS_NONE + bool "No access" + +config BAT4_ACCESS_RO + bool "Read-only" + +config BAT4_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT4_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT4_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT4_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT4_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT4_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT4_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT4_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT4_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT4_USER_MODE_VALID + bool "User mode valid" + +config BAT4_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT4_LENGTH + hex + default 0x00000000 if BAT4_LENGTH_128_KBYTES + default 0x00000004 if BAT4_LENGTH_256_KBYTES + default 0x0000000c if BAT4_LENGTH_512_KBYTES + default 0x0000001c if BAT4_LENGTH_1_MBYTES + default 0x0000003c if BAT4_LENGTH_2_MBYTES + default 0x0000007c if BAT4_LENGTH_4_MBYTES + default 0x000000fc if BAT4_LENGTH_8_MBYTES + default 0x000001fc if BAT4_LENGTH_16_MBYTES + default 0x000003fc if BAT4_LENGTH_32_MBYTES + default 0x000007fc if BAT4_LENGTH_64_MBYTES + default 0x00000ffc if BAT4_LENGTH_128_MBYTES + default 0x00001ffc if BAT4_LENGTH_256_MBYTES + +config BAT4_PAGE_PROTECTION + hex + default 0x0 if BAT4_ACCESS_NONE + default 0x1 if BAT4_ACCESS_RO + default 0x2 if BAT4_ACCESS_RW + +config BAT4_WIMG_ICACHE + hex + default 0x0 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x8 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x10 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x18 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x20 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x28 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x30 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x38 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x40 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x48 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x50 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x58 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x60 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x68 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x70 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED + default 0x78 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + +config BAT4_WIMG_DCACHE + hex + default 0x0 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x8 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x10 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x18 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x20 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x28 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x30 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x38 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x40 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x48 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x50 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x58 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x60 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x68 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + default 0x70 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED + default 0x78 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED + +config BAT4_VALID_BITS + hex + default 0x0 if !BAT4_SUPERVISOR_MODE_VALID && !BAT4_USER_MODE_VALID + default 0x1 if !BAT4_SUPERVISOR_MODE_VALID && BAT4_USER_MODE_VALID + default 0x2 if BAT4_SUPERVISOR_MODE_VALID && !BAT4_USER_MODE_VALID + default 0x3 if BAT4_SUPERVISOR_MODE_VALID && BAT4_USER_MODE_VALID + +menuconfig BAT5 + bool "BAT5" + +if BAT5 + +config BAT5_NAME + string "Identifier" + +config BAT5_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT5_LENGTH_128_KBYTES + bool "128 kb" + +config BAT5_LENGTH_256_KBYTES + bool "256 kb" + +config BAT5_LENGTH_512_KBYTES + bool "512 kb" + +config BAT5_LENGTH_1_MBYTES + bool "1 mb" + +config BAT5_LENGTH_2_MBYTES + bool "2 mb" + +config BAT5_LENGTH_4_MBYTES + bool "4 mb" + +config BAT5_LENGTH_8_MBYTES + bool "8 mb" + +config BAT5_LENGTH_16_MBYTES + bool "16 mb" + +config BAT5_LENGTH_32_MBYTES + bool "32 mb" + +config BAT5_LENGTH_64_MBYTES + bool "64 mb" + +config BAT5_LENGTH_128_MBYTES + bool "128 mb" + +config BAT5_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT5_ACCESS_NONE + bool "No access" + +config BAT5_ACCESS_RO + bool "Read-only" + +config BAT5_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT5_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT5_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT5_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT5_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT5_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT5_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT5_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT5_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT5_USER_MODE_VALID + bool "User mode valid" + +config BAT5_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT5_LENGTH + hex + default 0x00000000 if BAT5_LENGTH_128_KBYTES + default 0x00000004 if BAT5_LENGTH_256_KBYTES + default 0x0000000c if BAT5_LENGTH_512_KBYTES + default 0x0000001c if BAT5_LENGTH_1_MBYTES + default 0x0000003c if BAT5_LENGTH_2_MBYTES + default 0x0000007c if BAT5_LENGTH_4_MBYTES + default 0x000000fc if BAT5_LENGTH_8_MBYTES + default 0x000001fc if BAT5_LENGTH_16_MBYTES + default 0x000003fc if BAT5_LENGTH_32_MBYTES + default 0x000007fc if BAT5_LENGTH_64_MBYTES + default 0x00000ffc if BAT5_LENGTH_128_MBYTES + default 0x00001ffc if BAT5_LENGTH_256_MBYTES + +config BAT5_PAGE_PROTECTION + hex + default 0x0 if BAT5_ACCESS_NONE + default 0x1 if BAT5_ACCESS_RO + default 0x2 if BAT5_ACCESS_RW + +config BAT5_WIMG_ICACHE + hex + default 0x0 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x8 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x10 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x18 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x20 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x28 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x30 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x38 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x40 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x48 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x50 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x58 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x60 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x68 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x70 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED + default 0x78 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + +config BAT5_WIMG_DCACHE + hex + default 0x0 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x8 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x10 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x18 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x20 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x28 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x30 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x38 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x40 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x48 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x50 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x58 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x60 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x68 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + default 0x70 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED + default 0x78 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED + +config BAT5_VALID_BITS + hex + default 0x0 if !BAT5_SUPERVISOR_MODE_VALID && !BAT5_USER_MODE_VALID + default 0x1 if !BAT5_SUPERVISOR_MODE_VALID && BAT5_USER_MODE_VALID + default 0x2 if BAT5_SUPERVISOR_MODE_VALID && !BAT5_USER_MODE_VALID + default 0x3 if BAT5_SUPERVISOR_MODE_VALID && BAT5_USER_MODE_VALID + +menuconfig BAT6 + bool "BAT6" + +if BAT6 + +config BAT6_NAME + string "Identifier" + +config BAT6_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT6_LENGTH_128_KBYTES + bool "128 kb" + +config BAT6_LENGTH_256_KBYTES + bool "256 kb" + +config BAT6_LENGTH_512_KBYTES + bool "512 kb" + +config BAT6_LENGTH_1_MBYTES + bool "1 mb" + +config BAT6_LENGTH_2_MBYTES + bool "2 mb" + +config BAT6_LENGTH_4_MBYTES + bool "4 mb" + +config BAT6_LENGTH_8_MBYTES + bool "8 mb" + +config BAT6_LENGTH_16_MBYTES + bool "16 mb" + +config BAT6_LENGTH_32_MBYTES + bool "32 mb" + +config BAT6_LENGTH_64_MBYTES + bool "64 mb" + +config BAT6_LENGTH_128_MBYTES + bool "128 mb" + +config BAT6_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT6_ACCESS_NONE + bool "No access" + +config BAT6_ACCESS_RO + bool "Read-only" + +config BAT6_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT6_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT6_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT6_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT6_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT6_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT6_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT6_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT6_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT6_USER_MODE_VALID + bool "User mode valid" + +config BAT6_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT6_LENGTH + hex + default 0x00000000 if BAT6_LENGTH_128_KBYTES + default 0x00000004 if BAT6_LENGTH_256_KBYTES + default 0x0000000c if BAT6_LENGTH_512_KBYTES + default 0x0000001c if BAT6_LENGTH_1_MBYTES + default 0x0000003c if BAT6_LENGTH_2_MBYTES + default 0x0000007c if BAT6_LENGTH_4_MBYTES + default 0x000000fc if BAT6_LENGTH_8_MBYTES + default 0x000001fc if BAT6_LENGTH_16_MBYTES + default 0x000003fc if BAT6_LENGTH_32_MBYTES + default 0x000007fc if BAT6_LENGTH_64_MBYTES + default 0x00000ffc if BAT6_LENGTH_128_MBYTES + default 0x00001ffc if BAT6_LENGTH_256_MBYTES + +config BAT6_PAGE_PROTECTION + hex + default 0x0 if BAT6_ACCESS_NONE + default 0x1 if BAT6_ACCESS_RO + default 0x2 if BAT6_ACCESS_RW + +config BAT6_WIMG_ICACHE + hex + default 0x0 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x8 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x10 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x18 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x20 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x28 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x30 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x38 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x40 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x48 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x50 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x58 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x60 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x68 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x70 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED + default 0x78 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + +config BAT6_WIMG_DCACHE + hex + default 0x0 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x8 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x10 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x18 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x20 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x28 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x30 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x38 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x40 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x48 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x50 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x58 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x60 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x68 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + default 0x70 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED + default 0x78 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED + +config BAT6_VALID_BITS + hex + default 0x0 if !BAT6_SUPERVISOR_MODE_VALID && !BAT6_USER_MODE_VALID + default 0x1 if !BAT6_SUPERVISOR_MODE_VALID && BAT6_USER_MODE_VALID + default 0x2 if BAT6_SUPERVISOR_MODE_VALID && !BAT6_USER_MODE_VALID + default 0x3 if BAT6_SUPERVISOR_MODE_VALID && BAT6_USER_MODE_VALID + +menuconfig BAT7 + bool "BAT7" + +if BAT7 + +config BAT7_NAME + string "Identifier" + +config BAT7_BASE + hex "Base" + +choice + prompt "Block length" + +config BAT7_LENGTH_128_KBYTES + bool "128 kb" + +config BAT7_LENGTH_256_KBYTES + bool "256 kb" + +config BAT7_LENGTH_512_KBYTES + bool "512 kb" + +config BAT7_LENGTH_1_MBYTES + bool "1 mb" + +config BAT7_LENGTH_2_MBYTES + bool "2 mb" + +config BAT7_LENGTH_4_MBYTES + bool "4 mb" + +config BAT7_LENGTH_8_MBYTES + bool "8 mb" + +config BAT7_LENGTH_16_MBYTES + bool "16 mb" + +config BAT7_LENGTH_32_MBYTES + bool "32 mb" + +config BAT7_LENGTH_64_MBYTES + bool "64 mb" + +config BAT7_LENGTH_128_MBYTES + bool "128 mb" + +config BAT7_LENGTH_256_MBYTES + bool "256 mb" +endchoice + +choice + prompt "Protection mode" + +config BAT7_ACCESS_NONE + bool "No access" + +config BAT7_ACCESS_RO + bool "Read-only" + +config BAT7_ACCESS_RW + bool "Read-write" + +endchoice + +config BAT7_ICACHE_WRITETHROUGH + bool "I-cache Write-through" + +config BAT7_ICACHE_INHIBITED + bool "I-cache Inhibited" + +config BAT7_ICACHE_MEMORYCOHERENCE + bool "I-cache Memory coherence" + +config BAT7_ICACHE_GUARDED + bool "I-cache Guarded" + +config BAT7_DCACHE_WRITETHROUGH + bool "D-cache Write-through" + +config BAT7_DCACHE_INHIBITED + bool "D-cache Inhibited" + +config BAT7_DCACHE_MEMORYCOHERENCE + bool "D-cache Memory coherence" + +config BAT7_DCACHE_GUARDED + bool "D-cache Guarded" + +config BAT7_USER_MODE_VALID + bool "User mode valid" + +config BAT7_SUPERVISOR_MODE_VALID + bool "Supervisor mode valid" + +endif + +config BAT7_LENGTH + hex + default 0x00000000 if BAT7_LENGTH_128_KBYTES + default 0x00000004 if BAT7_LENGTH_256_KBYTES + default 0x0000000c if BAT7_LENGTH_512_KBYTES + default 0x0000001c if BAT7_LENGTH_1_MBYTES + default 0x0000003c if BAT7_LENGTH_2_MBYTES + default 0x0000007c if BAT7_LENGTH_4_MBYTES + default 0x000000fc if BAT7_LENGTH_8_MBYTES + default 0x000001fc if BAT7_LENGTH_16_MBYTES + default 0x000003fc if BAT7_LENGTH_32_MBYTES + default 0x000007fc if BAT7_LENGTH_64_MBYTES + default 0x00000ffc if BAT7_LENGTH_128_MBYTES + default 0x00001ffc if BAT7_LENGTH_256_MBYTES + +config BAT7_PAGE_PROTECTION + hex + default 0x0 if BAT7_ACCESS_NONE + default 0x1 if BAT7_ACCESS_RO + default 0x2 if BAT7_ACCESS_RW + +config BAT7_WIMG_ICACHE + hex + default 0x0 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x8 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x10 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x18 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x20 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x28 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x30 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x38 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x40 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x48 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x50 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x58 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x60 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x68 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x70 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED + default 0x78 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + +config BAT7_WIMG_DCACHE + hex + default 0x0 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x8 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x10 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x18 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x20 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x28 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x30 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x38 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x40 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x48 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x50 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x58 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x60 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x68 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + default 0x70 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED + default 0x78 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED + +config BAT7_VALID_BITS + hex + default 0x0 if !BAT7_SUPERVISOR_MODE_VALID && !BAT7_USER_MODE_VALID + default 0x1 if !BAT7_SUPERVISOR_MODE_VALID && BAT7_USER_MODE_VALID + default 0x2 if BAT7_SUPERVISOR_MODE_VALID && !BAT7_USER_MODE_VALID + default 0x3 if BAT7_SUPERVISOR_MODE_VALID && BAT7_USER_MODE_VALID + +endif + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/bats/bats.h b/arch/powerpc/cpu/mpc83xx/bats/bats.h new file mode 100644 index 00000000000..f0754c2351e --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/bats/bats.h @@ -0,0 +1,223 @@ +#ifdef CONFIG_BAT0 +#define CONFIG_SYS_IBAT0L (\ + (CONFIG_BAT0_BASE) |\ + (CONFIG_BAT0_PAGE_PROTECTION) |\ + (CONFIG_BAT0_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT0U (\ + (CONFIG_BAT0_BASE) |\ + (CONFIG_BAT0_LENGTH) |\ + (CONFIG_BAT0_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT0L (\ + (CONFIG_BAT0_BASE) |\ + (CONFIG_BAT0_PAGE_PROTECTION) |\ + (CONFIG_BAT0_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT0U (\ + (CONFIG_BAT0_BASE) |\ + (CONFIG_BAT0_LENGTH) |\ + (CONFIG_BAT0_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT0L (0) +#define CONFIG_SYS_IBAT0U (0) +#define CONFIG_SYS_DBAT0L (0) +#define CONFIG_SYS_DBAT0U (0) +#endif /* CONFIG_BAT0 */ + +#ifdef CONFIG_BAT1 +#define CONFIG_SYS_IBAT1L (\ + (CONFIG_BAT1_BASE) |\ + (CONFIG_BAT1_PAGE_PROTECTION) |\ + (CONFIG_BAT1_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT1U (\ + (CONFIG_BAT1_BASE) |\ + (CONFIG_BAT1_LENGTH) |\ + (CONFIG_BAT1_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT1L (\ + (CONFIG_BAT1_BASE) |\ + (CONFIG_BAT1_PAGE_PROTECTION) |\ + (CONFIG_BAT1_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT1U (\ + (CONFIG_BAT1_BASE) |\ + (CONFIG_BAT1_LENGTH) |\ + (CONFIG_BAT1_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT1L (0) +#define CONFIG_SYS_IBAT1U (0) +#define CONFIG_SYS_DBAT1L (0) +#define CONFIG_SYS_DBAT1U (0) +#endif /* CONFIG_BAT1 */ + +#ifdef CONFIG_BAT2 +#define CONFIG_SYS_IBAT2L (\ + (CONFIG_BAT2_BASE) |\ + (CONFIG_BAT2_PAGE_PROTECTION) |\ + (CONFIG_BAT2_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT2U (\ + (CONFIG_BAT2_BASE) |\ + (CONFIG_BAT2_LENGTH) |\ + (CONFIG_BAT2_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT2L (\ + (CONFIG_BAT2_BASE) |\ + (CONFIG_BAT2_PAGE_PROTECTION) |\ + (CONFIG_BAT2_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT2U (\ + (CONFIG_BAT2_BASE) |\ + (CONFIG_BAT2_LENGTH) |\ + (CONFIG_BAT2_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT2L (0) +#define CONFIG_SYS_IBAT2U (0) +#define CONFIG_SYS_DBAT2L (0) +#define CONFIG_SYS_DBAT2U (0) +#endif /* CONFIG_BAT2 */ + +#ifdef CONFIG_BAT3 +#define CONFIG_SYS_IBAT3L (\ + (CONFIG_BAT3_BASE) |\ + (CONFIG_BAT3_PAGE_PROTECTION) |\ + (CONFIG_BAT3_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT3U (\ + (CONFIG_BAT3_BASE) |\ + (CONFIG_BAT3_LENGTH) |\ + (CONFIG_BAT3_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT3L (\ + (CONFIG_BAT3_BASE) |\ + (CONFIG_BAT3_PAGE_PROTECTION) |\ + (CONFIG_BAT3_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT3U (\ + (CONFIG_BAT3_BASE) |\ + (CONFIG_BAT3_LENGTH) |\ + (CONFIG_BAT3_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT3L (0) +#define CONFIG_SYS_IBAT3U (0) +#define CONFIG_SYS_DBAT3L (0) +#define CONFIG_SYS_DBAT3U (0) +#endif /* CONFIG_BAT3 */ + +#ifdef CONFIG_BAT4 +#define CONFIG_SYS_IBAT4L (\ + (CONFIG_BAT4_BASE) |\ + (CONFIG_BAT4_PAGE_PROTECTION) |\ + (CONFIG_BAT4_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT4U (\ + (CONFIG_BAT4_BASE) |\ + (CONFIG_BAT4_LENGTH) |\ + (CONFIG_BAT4_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT4L (\ + (CONFIG_BAT4_BASE) |\ + (CONFIG_BAT4_PAGE_PROTECTION) |\ + (CONFIG_BAT4_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT4U (\ + (CONFIG_BAT4_BASE) |\ + (CONFIG_BAT4_LENGTH) |\ + (CONFIG_BAT4_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) +#define CONFIG_SYS_DBAT4L (0) +#define CONFIG_SYS_DBAT4U (0) +#endif /* CONFIG_BAT4 */ + +#ifdef CONFIG_BAT5 +#define CONFIG_SYS_IBAT5L (\ + (CONFIG_BAT5_BASE) |\ + (CONFIG_BAT5_PAGE_PROTECTION) |\ + (CONFIG_BAT5_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT5U (\ + (CONFIG_BAT5_BASE) |\ + (CONFIG_BAT5_LENGTH) |\ + (CONFIG_BAT5_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT5L (\ + (CONFIG_BAT5_BASE) |\ + (CONFIG_BAT5_PAGE_PROTECTION) |\ + (CONFIG_BAT5_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT5U (\ + (CONFIG_BAT5_BASE) |\ + (CONFIG_BAT5_LENGTH) |\ + (CONFIG_BAT5_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT5L (0) +#define CONFIG_SYS_IBAT5U (0) +#define CONFIG_SYS_DBAT5L (0) +#define CONFIG_SYS_DBAT5U (0) +#endif /* CONFIG_BAT5 */ + +#ifdef CONFIG_BAT6 +#define CONFIG_SYS_IBAT6L (\ + (CONFIG_BAT6_BASE) |\ + (CONFIG_BAT6_PAGE_PROTECTION) |\ + (CONFIG_BAT6_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT6U (\ + (CONFIG_BAT6_BASE) |\ + (CONFIG_BAT6_LENGTH) |\ + (CONFIG_BAT6_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT6L (\ + (CONFIG_BAT6_BASE) |\ + (CONFIG_BAT6_PAGE_PROTECTION) |\ + (CONFIG_BAT6_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT6U (\ + (CONFIG_BAT6_BASE) |\ + (CONFIG_BAT6_LENGTH) |\ + (CONFIG_BAT6_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_DBAT6L (0) +#define CONFIG_SYS_DBAT6U (0) +#endif /* CONFIG_BAT6 */ + +#ifdef CONFIG_BAT7 +#define CONFIG_SYS_IBAT7L (\ + (CONFIG_BAT7_BASE) |\ + (CONFIG_BAT7_PAGE_PROTECTION) |\ + (CONFIG_BAT7_WIMG_ICACHE) \ + ) +#define CONFIG_SYS_IBAT7U (\ + (CONFIG_BAT7_BASE) |\ + (CONFIG_BAT7_LENGTH) |\ + (CONFIG_BAT7_VALID_BITS) \ + ) +#define CONFIG_SYS_DBAT7L (\ + (CONFIG_BAT7_BASE) |\ + (CONFIG_BAT7_PAGE_PROTECTION) |\ + (CONFIG_BAT7_WIMG_DCACHE) \ + ) +#define CONFIG_SYS_DBAT7U (\ + (CONFIG_BAT7_BASE) |\ + (CONFIG_BAT7_LENGTH) |\ + (CONFIG_BAT7_VALID_BITS) \ + ) +#else +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L (0) +#define CONFIG_SYS_DBAT7U (0) +#endif /* CONFIG_BAT7 */ diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 8784445e158..95e4b906a76 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -25,6 +25,7 @@ #include <asm/u-boot.h>
#include "hrcw/hrcw.h" +#include "bats/bats.h"
/* We don't want the MMU yet. */ diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 042f6aa010f..14136f6b673 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -10,6 +10,42 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 641c6c8545b..8e34ee2c2ba 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -12,6 +12,51 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO_BASE" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index b1a4bcbc538..a2f7eb5837e 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -11,6 +11,51 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO_BASE" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index d3d26d319ff..c3ad8fa5640 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -13,6 +13,51 @@ CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO_BASE" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index 59d887e675b..2491de4134a 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -12,6 +12,51 @@ CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO_BASE" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index 149e71c310e..43daee1f19f 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -12,6 +12,62 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_32_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="PCI_MEM_PHYS" +CONFIG_BAT4_BASE=0x80000000 +CONFIG_BAT4_LENGTH_256_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="PCI_MMIO_PHYS" +CONFIG_BAT5_BASE=0x90000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 49e690e88ba..9039652d4b6 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -10,6 +10,62 @@ CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_32_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="PCI_MEM_PHYS" +CONFIG_BAT5_BASE=0x80000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="PCI1_MMIO_PHYS" +CONFIG_BAT6_BASE=0x90000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_INHIBITED=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 323b368f9ef..aefb01f150e 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -10,6 +10,52 @@ CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="BCSR" +CONFIG_BAT2_BASE=0xF8000000 +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xFE000000 +CONFIG_BAT3_LENGTH_32_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index a13dcfb91da..f410f8dac00 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -10,6 +10,72 @@ CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="BCSR" +CONFIG_BAT2_BASE=0xF8000000 +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xFE000000 +CONFIG_BAT3_LENGTH_32_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="PCI_MEM_PHYS" +CONFIG_BAT6_BASE=0x80000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="PCI1_MMIO_PHYS" +CONFIG_BAT7_BASE=0x90000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 2a4ff9a3e11..dac8f28a4d3 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -10,6 +10,72 @@ CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="BCSR" +CONFIG_BAT2_BASE=0xF8000000 +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xFE000000 +CONFIG_BAT3_LENGTH_32_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="PCI_MEM_PHYS" +CONFIG_BAT6_BASE=0x80000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="PCI1_MMIO_PHYS" +CONFIG_BAT7_BASE=0x90000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index e7ea39a2368..c1cb69ad934 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -7,6 +7,72 @@ CONFIG_TARGET_MPC832XEMDS=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="BCSR" +CONFIG_BAT2_BASE=0xF8000000 +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xFE000000 +CONFIG_BAT3_LENGTH_32_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="PCI_MEM_PHYS" +CONFIG_BAT6_BASE=0x80000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="PCI1_MMIO_PHYS" +CONFIG_BAT7_BASE=0x90000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index bffc55b917b..38e0b7f6deb 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -10,6 +10,52 @@ CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="BCSR" +CONFIG_BAT2_BASE=0xF8000000 +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xFE000000 +CONFIG_BAT3_LENGTH_32_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index 11bce06a093..6daab44b620 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -14,6 +14,37 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index 6b571b03688..d3f42f99e02 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -14,6 +14,37 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 87892c3d672..c264f7b53d6 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -12,6 +12,37 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 40633d19be4..4018d818256 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -14,6 +14,37 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 9e466b1bd10..0434118419f 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -14,6 +14,77 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="PCI2_MEM" +CONFIG_BAT3_BASE=0xA0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="PCI2_MMIO" +CONFIG_BAT4_BASE=0xB0000000 +CONFIG_BAT4_LENGTH_256_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_INHIBITED=y +CONFIG_BAT4_ICACHE_GUARDED=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 3a612357361..de97bb15b2b 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -14,6 +14,77 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="PCI2_MEM" +CONFIG_BAT3_BASE=0xA0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="PCI2_MMIO" +CONFIG_BAT4_BASE=0xB0000000 +CONFIG_BAT4_LENGTH_256_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_INHIBITED=y +CONFIG_BAT4_ICACHE_GUARDED=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index ed9bd83302a..b1e687ceab1 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -13,6 +13,77 @@ CONFIG_PCI_INT_ARBITER2_ENABLE=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="PCI2_MEM" +CONFIG_BAT3_BASE=0xA0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="PCI2_MMIO" +CONFIG_BAT4_BASE=0xB0000000 +CONFIG_BAT4_LENGTH_256_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_INHIBITED=y +CONFIG_BAT4_ICACHE_GUARDED=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="STACK_IN_DCACHE" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 73ba7dc6328..86b9f6071a0 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -14,6 +14,81 @@ CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="SDRAM_UPPER" +CONFIG_BAT1_BASE=0x10000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="IMMR" +CONFIG_BAT2_BASE=0xE0000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="BCSR" +CONFIG_BAT3_BASE=0xF8000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_INHIBITED=y +CONFIG_BAT3_ICACHE_GUARDED=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="FLASH" +CONFIG_BAT4_BASE=0xFE000000 +CONFIG_BAT4_LENGTH_32_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="PCI_MEM" +CONFIG_BAT6_BASE=0x80000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="PCI_MMIO" +CONFIG_BAT7_BASE=0x90000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index 8a50ff16d03..44c23eade50 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -10,6 +10,45 @@ CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="SDRAM_UPPER" +CONFIG_BAT1_BASE=0x10000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="IMMR" +CONFIG_BAT2_BASE=0xE0000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="BCSR" +CONFIG_BAT3_BASE=0xF8000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_INHIBITED=y +CONFIG_BAT3_ICACHE_GUARDED=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index cf0694f3b54..f21cdbd1793 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -14,6 +14,61 @@ CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="SDRAM_UPPER" +CONFIG_BAT1_BASE=0x10000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="IMMR" +CONFIG_BAT2_BASE=0xE0000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="BCSR" +CONFIG_BAT3_BASE=0xF8000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_INHIBITED=y +CONFIG_BAT3_ICACHE_GUARDED=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="FLASH" +CONFIG_BAT4_BASE=0xFE000000 +CONFIG_BAT4_LENGTH_32_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACK_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index e145504ded2..d1455b0e9dd 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -10,6 +10,45 @@ CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="SDRAM_UPPER" +CONFIG_BAT1_BASE=0x10000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="IMMR" +CONFIG_BAT2_BASE=0xE0000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="L2_SWITCH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_INHIBITED=y +CONFIG_BAT3_ICACHE_GUARDED=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 03fd7b70bae..e6138c06fc3 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -14,6 +14,81 @@ CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="SDRAM_UPPER" +CONFIG_BAT1_BASE=0x10000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="IMMR" +CONFIG_BAT2_BASE=0xE0000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="L2_SWITCH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_INHIBITED=y +CONFIG_BAT3_ICACHE_GUARDED=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="FLASH" +CONFIG_BAT4_BASE=0xFE000000 +CONFIG_BAT4_LENGTH_32_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_DCACHE_INHIBITED=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="STACH_IN_DCACHE" +CONFIG_BAT5_BASE=0xE6000000 +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="PCI_MEM" +CONFIG_BAT6_BASE=0x80000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="PCI_MMIO" +CONFIG_BAT7_BASE=0x90000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index c746afd1fd7..677f0513a35 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -13,6 +13,85 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="SDRAM_UPPER" +CONFIG_BAT1_BASE=0x10000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="STACK_IN_DCACHE" +CONFIG_BAT2_BASE=0x20000000 +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="PCI_MEM_BASE" +CONFIG_BAT3_BASE=0x90000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="PCI_MMIO" +CONFIG_BAT4_BASE=0xA0000000 +CONFIG_BAT4_LENGTH_256_MBYTES=y +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_ICACHE_GUARDED=y +CONFIG_BAT4_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT4_DCACHE_GUARDED=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="PCI_IO" +CONFIG_BAT5_BASE=0xE2000000 +CONFIG_BAT5_LENGTH_16_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="IMMR" +CONFIG_BAT6_BASE=0xFF400000 +CONFIG_BAT6_LENGTH_1_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_INHIBITED=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="FLASH" +CONFIG_BAT7_BASE=0x80000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index b52ea881ce6..2665e725730 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -14,6 +14,55 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR_PCIIO" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="UNKNOWN" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 97fe0e06fef..deed831c11a 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -10,6 +10,42 @@ CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 83dd6bf3a91..c1135434724 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -10,6 +10,42 @@ CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_RGMII=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index a8619ef621b..4afed470331 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -7,6 +7,52 @@ CONFIG_TARGET_IDS8313=y CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="INITRAM" +CONFIG_BAT1_BASE=0xFD000000 +CONFIG_BAT1_LENGTH_256_KBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFF800000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR" +CONFIG_BAT5_BASE=0xF0000000 +CONFIG_BAT5_LENGTH_128_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="NAND_MRAM_CPLD" +CONFIG_BAT6_BASE=0xE0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_IMAGE_FORMAT_LEGACY=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 03437f7cb83..a358e28886c 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -13,6 +13,85 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_LALE_TIMING_EARLIER=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM_LOWER" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="PAXE" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="BFTIC3" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="SDRAM_UPPER" +CONFIG_BAT7_BASE=0x10000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_INHIBITED=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_INHIBITED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 600a1ad1dc8..10f7fdf1109 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y +CONFIG_HIGH_BATS=y CONFIG_TARGET_KMETER1=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_VCO_DIV_4=y @@ -12,6 +13,58 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_LALE_TIMING_EARLIER=y CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="PAXE" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index ba489eeb6ac..b32b39113fa 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -8,6 +8,74 @@ CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="APP2" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index f39bca4fbd0..cc94d174f03 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -8,6 +8,64 @@ CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 3e7b2f73fd9..994e1525f79 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -9,6 +9,64 @@ CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="APP2" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 0f32283e9db..bb237860578 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -8,6 +8,74 @@ CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="APP2" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index ec3ff28793b..666dbf32cc9 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -9,6 +9,74 @@ CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="APP2" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index cb24c97f045..f583fa922e3 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -8,6 +8,42 @@ CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFC000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACKINDCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 47feb5ae36d..f8ce3093761 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -14,6 +14,57 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR_PCIIO" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="LBC_INITRAM_FLASH" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 019341691f2..bc9e2288941 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -14,6 +14,57 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR_PCIIO" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="LBC_INITRAM_FLASH" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index f7c3de8e9eb..d8e60da7be1 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -14,6 +14,37 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR_PCIIO" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="LBC_INITRAM_FLASH" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index c2faf3855ee..508ffe201ab 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -9,6 +9,42 @@ CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index cff81f41f52..514db1c2133 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -9,6 +9,42 @@ CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index f72bec439b2..a998585f3a8 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -9,6 +9,42 @@ CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 0e430496639..48579c75633 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -9,6 +9,42 @@ CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_3_1=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="DDR" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMRBAR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="STACK_IN_DCACHE" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index b6f17d2f292..4dd36cac919 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -8,6 +8,74 @@ CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="APP2" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SUVD3" diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 445b89d483f..7db157bf210 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -8,6 +8,64 @@ CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index d7b0a94ada7..e0c1366291c 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -8,6 +8,74 @@ CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_INHIBITED=y +CONFIG_BAT0_ICACHE_GUARDED=y +CONFIG_BAT0_DCACHE_INHIBITED=y +CONFIG_BAT0_DCACHE_GUARDED=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_4_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="KMBEC_FPGA" +CONFIG_BAT2_BASE=0xE8000000 +CONFIG_BAT2_LENGTH_128_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="FLASH" +CONFIG_BAT3_BASE=0xF0000000 +CONFIG_BAT3_LENGTH_256_MBYTES=y +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT3_DCACHE_INHIBITED=y +CONFIG_BAT3_DCACHE_GUARDED=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_BAT4=y +CONFIG_BAT4_NAME="STACK_IN_DCACHE" +CONFIG_BAT4_BASE=0xE6000000 +CONFIG_BAT4_ACCESS_RW=y +CONFIG_BAT4_USER_MODE_VALID=y +CONFIG_BAT4_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="APP1" +CONFIG_BAT5_BASE=0xA0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="APP2" +CONFIG_BAT6_BASE=0xB0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_INHIBITED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 52a51cc5bb5..517c4aa854e 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -11,6 +11,60 @@ CONFIG_PCI_INT_ARBITER1_ENABLE=y CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_LALE_TIMING_EARLIER=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR_PCIIO_BCSR" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="INITRAM_FLASH" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_GUARDED=y +CONFIG_BAT6_DCACHE_GUARDED=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_BAT7=y +CONFIG_BAT7_NAME="FPGA_SRAM_NAND" +CONFIG_BAT7_BASE=0x60000000 +CONFIG_BAT7_LENGTH_256_MBYTES=y +CONFIG_BAT7_ACCESS_RW=y +CONFIG_BAT7_ICACHE_GUARDED=y +CONFIG_BAT7_DCACHE_GUARDED=y +CONFIG_BAT7_USER_MODE_VALID=y +CONFIG_BAT7_SUPERVISOR_MODE_VALID=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 3f1f5c069b6..b7cf6a44bc8 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -14,6 +14,55 @@ CONFIG_BOOT_MEMORY_SPACE_LOW=y CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_TSEC1_MODE_GMII=y CONFIG_TSEC2_MODE_GMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_256_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="PCI1_MEM" +CONFIG_BAT1_BASE=0x80000000 +CONFIG_BAT1_LENGTH_256_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="PCI1_MMIO" +CONFIG_BAT2_BASE=0x90000000 +CONFIG_BAT2_LENGTH_256_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_INHIBITED=y +CONFIG_BAT2_ICACHE_GUARDED=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT5=y +CONFIG_BAT5_NAME="IMMR_PCIIO" +CONFIG_BAT5_BASE=0xE0000000 +CONFIG_BAT5_LENGTH_256_MBYTES=y +CONFIG_BAT5_ACCESS_RW=y +CONFIG_BAT5_ICACHE_INHIBITED=y +CONFIG_BAT5_ICACHE_GUARDED=y +CONFIG_BAT5_DCACHE_INHIBITED=y +CONFIG_BAT5_DCACHE_GUARDED=y +CONFIG_BAT5_USER_MODE_VALID=y +CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_BAT6=y +CONFIG_BAT6_NAME="UNKNOWN" +CONFIG_BAT6_BASE=0xF0000000 +CONFIG_BAT6_LENGTH_256_MBYTES=y +CONFIG_BAT6_ACCESS_RW=y +CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT6_USER_MODE_VALID=y +CONFIG_BAT6_SUPERVISOR_MODE_VALID=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index db283578b9b..dc7a8b8aa85 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -387,43 +387,6 @@ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - /* * Environment Configuration */ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index e3bcc63e130..596d39ee5e9 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -438,68 +438,6 @@
#define CONFIG_SYS_HID2 HID2_HBE
-/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI2 not supported on 8313 */ -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - /* * Environment Configuration */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index af2432b12d2..9d1ce200ec5 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -412,68 +412,6 @@
#define CONFIG_SYS_HID2 HID2_HBE
-/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI2 not supported on 8313 */ -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - /* * Environment Configuration */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index d2f9309cd61..fb568efe2d4 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -405,85 +405,6 @@ * MMU Setup */
-/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_128M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ - | BATU_BL_8M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#define CONFIG_SYS_IBAT6L 0 -#define CONFIG_SYS_IBAT6U 0 -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L 0 -#define CONFIG_SYS_IBAT7U 0 -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 37f173ef747..489e7c3368c 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -297,100 +297,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ - | BATU_BL_4M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#else -#define CONFIG_SYS_IBAT5L (0) -#define CONFIG_SYS_IBAT5U (0) -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#endif - -/* Nothing in BAT7 */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if (CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index d8cadde0e0e..15fca456cc7 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -360,106 +360,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ - | BATU_BL_4M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* BCSR: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#else -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index d70e477f80e..e4d90589e9a 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -382,103 +382,10 @@
#define CONFIG_SYS_HID2 HID2_HBE
-/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) #endif
-#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 286654066cf..a24a2011d2f 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -454,103 +454,10 @@
#define CONFIG_SYS_HID2 HID2_HBE
-/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) #endif
-#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index e7031e94fd9..aeee6e0408f 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -482,102 +482,6 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_HID2 HID2_HBE
-/* DDR */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI */ -#ifdef CONFIG_PCI -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L 0 -#define CONFIG_SYS_IBAT1U 0 -#define CONFIG_SYS_IBAT2L 0 -#define CONFIG_SYS_IBAT2U 0 -#endif - -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L 0 -#define CONFIG_SYS_IBAT3U 0 -#define CONFIG_SYS_IBAT4L 0 -#define CONFIG_SYS_IBAT4U 0 -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_IBAT7L 0 -#define CONFIG_SYS_IBAT7U 0 - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 3473ca61024..01a3a77e997 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -420,114 +420,6 @@ extern int board_pci_host_broken(void); HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ - | BATU_BL_8M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* BCSR: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#else -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 9ddd2af0d9c..9a4eeb63903 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -435,114 +435,6 @@ | HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ - | BATU_BL_8M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* L2 Switch: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#else -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c27a04ace99..c5a6203001b 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -270,103 +270,11 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* DDR 0 - 512M */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* stack in DCACHE @ 512M (no backing mem) */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) - /* PCI */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ - | BATU_BL_16M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#define CONFIG_SYS_IBAT5L (0) -#define CONFIG_SYS_IBAT5U (0) #endif
-/* IMMRBAR */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ - | BATU_BL_1M \ - | BATU_VS \ - | BATU_VP) - -/* FLASH */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 007ded02990..f4ee2228084 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -302,82 +302,10 @@ #define CONFIG_SYS_GPIO2_DIR 0x78900000 #define CONFIG_SYS_GPIO2_DAT 0x70100000
-/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) - -/* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) -#endif - -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) #endif
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ - BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#if (CONFIG_SYS_DDR_SIZE == 512) -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ - BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ - BATU_BL_256M | BATU_VS | BATU_VP) -#else -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#endif - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index c1fe6b45bd5..c8fabf9da54 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -482,43 +482,6 @@ void fpga_control_clear(unsigned int bus, int pin); HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - /* * Environment Configuration */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index ac151dccbad..120eb0a6b71 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -282,83 +282,6 @@ #define CONFIG_HAS_FSL_DR_USB #define CONFIG_SYS_SCCR_USBDRCM 3
-/* - * BAT's - */ - -/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\ - BATL_PP_10) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\ - BATU_BL_256M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* Initial RAM @ 0xFD000000 */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\ - BATL_PP_10 |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\ - BATU_BL_256K |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH @ 0xFF800000 */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\ - BATL_PP_10 |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\ - BATU_BL_8M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\ - BATL_PP_10 |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* IMMRBAR @ 0xF0000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\ - BATL_PP_10 |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\ - BATU_BL_128M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */ -#define CONFIG_SYS_IBAT6L (0xE0000000 |\ - BATL_PP_10 |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xE0000000 |\ - BATU_BL_256M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - /* * U-Boot environment setup */ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index e44c5a883fe..8e5626da4c0 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -234,51 +234,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -434,62 +389,6 @@ OR_GPCM_TRLX |\ OR_GPCM_EAD)
-/* - * MMU Setup - */ - -/* PAXE: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (\ - CONFIG_SYS_PAXE_BASE | \ - BATL_PP_10 | \ - BATL_MEMCOHERENCE) - -#define CONFIG_SYS_IBAT5U (\ - CONFIG_SYS_PAXE_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) - -#define CONFIG_SYS_DBAT5L (\ - CONFIG_SYS_PAXE_BASE | \ - BATL_PP_10 | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) - -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* BFTIC3: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (\ - CONFIG_SYS_BFTIC3_BASE | \ - BATL_PP_10 | \ - BATL_MEMCOHERENCE) - -#define CONFIG_SYS_IBAT6U (\ - CONFIG_SYS_BFTIC3_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) - -#define CONFIG_SYS_DBAT6L (\ - CONFIG_SYS_BFTIC3_BASE | \ - BATL_PP_10 | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) - -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -/* DDR/LBC SDRAM next 256M: cacheable */ -#define CONFIG_SYS_IBAT7L (\ - CONFIG_SYS_SDRAM_BASE2 |\ - BATL_PP_10 |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) - -#define CONFIG_SYS_IBAT7U (\ - CONFIG_SYS_SDRAM_BASE2 |\ - BATU_BL_256M |\ - BATU_VS |\ - BATU_VP) /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ @@ -497,7 +396,4 @@ #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #endif /* CONFIG */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2d7b3106dd0..f6c7cfce438 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -220,51 +220,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -395,36 +350,4 @@ OR_GPCM_TRLX | \ OR_GPCM_EAD)
-/* - * MMU Setup - */ - -/* PAXE: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (\ - CONFIG_SYS_PAXE_BASE | \ - BATL_PP_10 | \ - BATL_MEMCOHERENCE) - -#define CONFIG_SYS_IBAT5U (\ - CONFIG_SYS_PAXE_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) - -#define CONFIG_SYS_DBAT5L (\ - CONFIG_SYS_PAXE_BASE | \ - BATL_PP_10 | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) - -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #endif /* CONFIG */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 2f19b2e9efa..6ac36c0f921 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -239,51 +239,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -389,14 +344,6 @@
#define CONFIG_SYS_LBC_LBCR 0x00000000
-/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ @@ -451,41 +398,5 @@ OR_GPCM_SCY_4 | \ OR_GPCM_TRLX_CLEAR | \ OR_GPCM_EHTR_CLEAR) -/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -/* 512M should also include APP2... */ -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* APP2: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index ae997a71f6a..7ee9a914a46 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -239,51 +239,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -389,14 +344,6 @@
#define CONFIG_SYS_LBC_LBCR 0x00000000
-/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
@@ -436,32 +383,4 @@ OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD)
-/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -/* 512M should also include APP2... */ -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #endif /* __CONFIG_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 2e4e2a3b5fd..53017faa1cf 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -243,51 +243,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -441,14 +396,6 @@
#define CONFIG_SYS_LBC_LBCR 0x00000000
-/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - /* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
@@ -483,21 +430,6 @@ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT5L (0) -#define CONFIG_SYS_IBAT5U (0) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - /* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 #define CONFIG_UEC_ETH2 diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index f998b95f933..8f2be980a04 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -239,51 +239,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -389,14 +344,6 @@
#define CONFIG_SYS_LBC_LBCR 0x00000000
-/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ @@ -452,41 +399,4 @@ OR_GPCM_TRLX_CLEAR | \ OR_GPCM_EHTR_CLEAR)
-/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -/* 512M should also include APP2... */ -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* APP2: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index f4da14a6161..172a28e8504 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -235,51 +235,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -433,14 +388,6 @@
#define CONFIG_SYS_LBC_LBCR 0x00000000
-/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 @@ -488,25 +435,6 @@ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - /* * QE UEC ethernet configuration */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 2822aa3b9da..1bca11bd6e7 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -354,43 +354,6 @@ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - /* * Environment Configuration */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index d6f2813e50b..8179147bc22 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -383,103 +383,10 @@
#define CONFIG_SYS_HID2 HID2_HBE
-/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) #endif
-#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/strider.h b/include/configs/strider.h index ef33eaef9b0..a716096bed8 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -514,43 +514,6 @@ void fpga_control_clear(unsigned int bus, int pin); HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - /* * Environment Configuration */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 4cc9f13d379..6a4006ef6ad 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -236,51 +236,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -386,14 +341,6 @@
#define CONFIG_SYS_LBC_LBCR 0x00000000
-/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 @@ -441,23 +388,4 @@ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - #endif /* __CONFIG_H */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 8d254689cfe..5bb74fd9aeb 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -239,51 +239,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -389,14 +344,6 @@
#define CONFIG_SYS_LBC_LBCR 0x00000000
-/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
@@ -436,32 +383,4 @@ OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD)
-/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -/* 512M should also include APP2... */ -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 630eb19f13a..a85039bf3c1 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -239,51 +239,6 @@ HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE
-/* - * MMU Setup - */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - /* * Internal Definitions */ @@ -389,14 +344,6 @@
#define CONFIG_SYS_LBC_LBCR 0x00000000
-/* - * MMU Setup - */ -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ @@ -462,41 +409,4 @@ 0x0000c000 | \ MxMR_WLFx_2X)
-/* - * MMU Setup - */ -/* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -/* 512M should also include APP2... */ -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* APP2: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ - BATU_BL_256M | \ - BATU_VS | \ - BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_RW | \ - BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #endif /* __CONFIG_H */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index b15cd218f29..84d2c897d76 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -333,76 +333,6 @@
#define CONFIG_SYS_HID2 HID2_HBE
-/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#if defined(CONFIG_PCI) -/* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) -#endif - -/* PCI2 not supported on 8313 */ -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* FPGA, SRAM, NAND @ 0x60000000 */ -#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #define CONFIG_NETDEV eth0
#define CONFIG_HOSTNAME "ve8313" diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index d73265e064b..249783720c4 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -302,82 +302,10 @@ #define CONFIG_SYS_GPIO2_DIR 0x78900000 #define CONFIG_SYS_GPIO2_DAT 0x70100000
-/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) - -/* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) -#endif - -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) #endif
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ - BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#if (CONFIG_SYS_DDR_SIZE == 512) -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ - BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ - BATU_BL_256M | BATU_VS | BATU_VP) -#else -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#endif - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif
The LBLAW_* values determine the window configuration of the memory controller. Hence, they must be known at compile time, and cannot be implemented in the DT mechanism.
Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 + arch/powerpc/cpu/mpc83xx/lblaw/Kconfig | 519 +++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h | 55 +++ arch/powerpc/cpu/mpc83xx/spl_minimal.c | 2 + configs/MPC8308RDB_defconfig | 12 + configs/MPC8313ERDB_33_defconfig | 16 + configs/MPC8313ERDB_66_defconfig | 16 + configs/MPC8313ERDB_NAND_33_defconfig | 17 + configs/MPC8313ERDB_NAND_66_defconfig | 17 + configs/MPC8315ERDB_defconfig | 8 + configs/MPC8323ERDB_defconfig | 4 + configs/MPC832XEMDS_ATM_defconfig | 12 + configs/MPC832XEMDS_HOST_33_defconfig | 12 + configs/MPC832XEMDS_HOST_66_defconfig | 12 + configs/MPC832XEMDS_SLAVE_defconfig | 12 + configs/MPC832XEMDS_defconfig | 12 + configs/MPC8349EMDS_PCI64_defconfig | 8 + configs/MPC8349EMDS_SDRAM_defconfig | 12 + configs/MPC8349EMDS_SLAVE_defconfig | 8 + configs/MPC8349EMDS_defconfig | 8 + configs/MPC8349ITXGP_defconfig | 12 + configs/MPC8349ITX_LOWBOOT_defconfig | 12 + configs/MPC8349ITX_defconfig | 12 + configs/MPC837XEMDS_HOST_defconfig | 12 + configs/MPC837XEMDS_SLAVE_defconfig | 12 + configs/MPC837XEMDS_defconfig | 12 + configs/MPC837XERDB_SLAVE_defconfig | 12 + configs/MPC837XERDB_defconfig | 12 + configs/TQM834x_defconfig | 10 + configs/caddy2_defconfig | 8 + configs/hrcon_defconfig | 8 + configs/hrcon_dh_defconfig | 8 + configs/ids8313_defconfig | 17 + configs/kmcoge5ne_defconfig | 12 + configs/kmeter1_defconfig | 12 + configs/kmopti2_defconfig | 16 + configs/kmsupx5_defconfig | 12 + configs/kmtegr1_defconfig | 12 + configs/kmtepr2_defconfig | 16 + configs/kmvect1_defconfig | 16 + configs/mpc8308_p1m_defconfig | 12 + configs/sbc8349_PCI_33_defconfig | 4 + configs/sbc8349_PCI_66_defconfig | 4 + configs/sbc8349_defconfig | 4 + configs/strider_con_defconfig | 8 + configs/strider_con_dp_defconfig | 8 + configs/strider_cpu_defconfig | 8 + configs/strider_cpu_dp_defconfig | 8 + configs/suvd3_defconfig | 16 + configs/tuge1_defconfig | 12 + configs/tuxx1_defconfig | 16 + configs/ve8313_defconfig | 9 + configs/vme8349_defconfig | 8 + include/configs/MPC8308RDB.h | 10 - include/configs/MPC8313ERDB_NAND.h | 18 - include/configs/MPC8313ERDB_NOR.h | 18 - include/configs/MPC8315ERDB.h | 10 - include/configs/MPC8323ERDB.h | 3 - include/configs/MPC832XEMDS.h | 8 - include/configs/MPC8349EMDS.h | 6 - include/configs/MPC8349EMDS_SDRAM.h | 8 - include/configs/MPC8349ITX.h | 10 - include/configs/MPC837XEMDS.h | 10 - include/configs/MPC837XERDB.h | 12 - include/configs/TQM834x.h | 11 - include/configs/caddy2.h | 4 - include/configs/hrcon.h | 6 - include/configs/ids8313.h | 12 - include/configs/kmcoge5ne.h | 10 - include/configs/kmeter1.h | 10 - include/configs/kmopti2.h | 13 - include/configs/kmsupx5.h | 11 - include/configs/kmtegr1.h | 9 - include/configs/kmtepr2.h | 13 - include/configs/kmvect1.h | 13 - include/configs/mpc8308_p1m.h | 9 - include/configs/sbc8349.h | 7 - include/configs/strider.h | 6 - include/configs/suvd3.h | 13 - include/configs/tuge1.h | 11 - include/configs/tuxx1.h | 16 - include/configs/ve8313.h | 9 - include/configs/vme8349.h | 4 - scripts/config_whitelist.txt | 16 - 85 files changed, 1125 insertions(+), 316 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/lblaw/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index f7f625aea1f..8c84196b978 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -284,6 +284,7 @@ config ARCH_MPC837X
source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" +source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
menu "Legacy options"
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 7c378671feb..91451e7b304 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -12,6 +12,8 @@ #include <usb/ehci-ci.h> #endif
+#include "lblaw/lblaw.h" + DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_QE diff --git a/arch/powerpc/cpu/mpc83xx/lblaw/Kconfig b/arch/powerpc/cpu/mpc83xx/lblaw/Kconfig new file mode 100644 index 00000000000..b20f68b77a0 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/lblaw/Kconfig @@ -0,0 +1,519 @@ +menu "LBLAW setup" + +choice + prompt "NAND LAWBAR for NAND SPL" + +config NAND_LBLAWBAR_PRELIM_NONE + bool "None" + +config NAND_LBLAWBAR_PRELIM_0 + bool "0" + depends on LBLAW0 + +config NAND_LBLAWBAR_PRELIM_1 + bool "1" + depends on LBLAW1 + +config NAND_LBLAWBAR_PRELIM_2 + bool "2" + depends on LBLAW2 + +config NAND_LBLAWBAR_PRELIM_3 + bool "3" + depends on LBLAW3 + +endchoice + +menuconfig LBLAW0 + bool "LBLAW0" + +if LBLAW0 + +config LBLAW0_ENABLE + bool "Window enable" + default "y" + +if !LBLAW0_ENABLE + +config LBLAW0_BASE + hex + default 0x0 + +endif + +if LBLAW0_ENABLE + +config LBLAW0_NAME + string "Identifier" + +config LBLAW0_BASE + hex "Window base" + +choice + prompt "Window size" + +config LBLAW0_LENGTH_4_KBYTES + bool "4 kb" + +config LBLAW0_LENGTH_8_KBYTES + bool "8 kb" + +config LBLAW0_LENGTH_16_KBYTES + bool "16 kb" + +config LBLAW0_LENGTH_32_KBYTES + bool "32 kb" + +config LBLAW0_LENGTH_64_KBYTES + bool "64 kb" + +config LBLAW0_LENGTH_128_KBYTES + bool "128 kb" + +config LBLAW0_LENGTH_256_KBYTES + bool "256 kb" + +config LBLAW0_LENGTH_512_KBYTES + bool "512 kb" + +config LBLAW0_LENGTH_1_MBYTES + bool "1 mb" + +config LBLAW0_LENGTH_2_MBYTES + bool "2 mb" + +config LBLAW0_LENGTH_4_MBYTES + bool "4 mb" + +config LBLAW0_LENGTH_8_MBYTES + bool "8 mb" + +config LBLAW0_LENGTH_16_MBYTES + bool "16 mb" + +config LBLAW0_LENGTH_32_MBYTES + bool "32 mb" + +config LBLAW0_LENGTH_64_MBYTES + bool "64 mb" + +config LBLAW0_LENGTH_128_MBYTES + bool "128 mb" + +config LBLAW0_LENGTH_256_MBYTES + bool "256 mb" + +config LBLAW0_LENGTH_512_MBYTES + bool "512 mb" + +config LBLAW0_LENGTH_1_GBYTES + bool "1 gb" + +config LBLAW0_LENGTH_2_GBYTES + bool "2 gb" + +endchoice + +endif # LBLAW0_ENABLE + +endif # LBLAW0 + +config LBLAW0_ENABLE_BIT + hex + default 0x0 if !LBLAW0_ENABLE + default 0x80000000 if LBLAW0_ENABLE + +config LBLAW0_LENGTH + hex + default 0x0 if !LBLAW0_ENABLE + default 0x0000000B if LBLAW0_LENGTH_4_KBYTES + default 0x0000000C if LBLAW0_LENGTH_8_KBYTES + default 0x0000000D if LBLAW0_LENGTH_16_KBYTES + default 0x0000000E if LBLAW0_LENGTH_32_KBYTES + default 0x0000000F if LBLAW0_LENGTH_64_KBYTES + default 0x00000010 if LBLAW0_LENGTH_128_KBYTES + default 0x00000011 if LBLAW0_LENGTH_256_KBYTES + default 0x00000012 if LBLAW0_LENGTH_512_KBYTES + default 0x00000013 if LBLAW0_LENGTH_1_MBYTES + default 0x00000014 if LBLAW0_LENGTH_2_MBYTES + default 0x00000015 if LBLAW0_LENGTH_4_MBYTES + default 0x00000016 if LBLAW0_LENGTH_8_MBYTES + default 0x00000017 if LBLAW0_LENGTH_16_MBYTES + default 0x00000018 if LBLAW0_LENGTH_32_MBYTES + default 0x00000019 if LBLAW0_LENGTH_64_MBYTES + default 0x0000001A if LBLAW0_LENGTH_128_MBYTES + default 0x0000001B if LBLAW0_LENGTH_256_MBYTES + default 0x0000001C if LBLAW0_LENGTH_512_MBYTES + default 0x0000001D if LBLAW0_LENGTH_1_GBYTES + default 0x0000001E if LBLAW0_LENGTH_2_GBYTES + +menuconfig LBLAW1 + bool "LBLAW1" + +if LBLAW1 + +config LBLAW1_ENABLE + bool "Window enable" + default "y" + +if !LBLAW1_ENABLE + +config LBLAW1_BASE + hex + default 0x0 + +endif + +if LBLAW1_ENABLE + +config LBLAW1_NAME + string "Identifier" + +config LBLAW1_BASE + hex "Window base" + +choice + prompt "Window size" + +config LBLAW1_LENGTH_4_KBYTES + bool "4 kb" + +config LBLAW1_LENGTH_8_KBYTES + bool "8 kb" + +config LBLAW1_LENGTH_16_KBYTES + bool "16 kb" + +config LBLAW1_LENGTH_32_KBYTES + bool "32 kb" + +config LBLAW1_LENGTH_64_KBYTES + bool "64 kb" + +config LBLAW1_LENGTH_128_KBYTES + bool "128 kb" + +config LBLAW1_LENGTH_256_KBYTES + bool "256 kb" + +config LBLAW1_LENGTH_512_KBYTES + bool "512 kb" + +config LBLAW1_LENGTH_1_MBYTES + bool "1 mb" + +config LBLAW1_LENGTH_2_MBYTES + bool "2 mb" + +config LBLAW1_LENGTH_4_MBYTES + bool "4 mb" + +config LBLAW1_LENGTH_8_MBYTES + bool "8 mb" + +config LBLAW1_LENGTH_16_MBYTES + bool "16 mb" + +config LBLAW1_LENGTH_32_MBYTES + bool "32 mb" + +config LBLAW1_LENGTH_64_MBYTES + bool "64 mb" + +config LBLAW1_LENGTH_128_MBYTES + bool "128 mb" + +config LBLAW1_LENGTH_256_MBYTES + bool "256 mb" + +config LBLAW1_LENGTH_512_MBYTES + bool "512 mb" + +config LBLAW1_LENGTH_1_GBYTES + bool "1 gb" + +config LBLAW1_LENGTH_2_GBYTES + bool "2 gb" + +endchoice + +endif # LBLAW1_ENABLE + +endif # LBLAW1 + +config LBLAW1_ENABLE_BIT + hex + default 0x0 if !LBLAW1_ENABLE + default 0x80000000 if LBLAW1_ENABLE + +config LBLAW1_LENGTH + hex + default 0x0 if !LBLAW1_ENABLE + default 0x0000000B if LBLAW1_LENGTH_4_KBYTES + default 0x0000000C if LBLAW1_LENGTH_8_KBYTES + default 0x0000000D if LBLAW1_LENGTH_16_KBYTES + default 0x0000000E if LBLAW1_LENGTH_32_KBYTES + default 0x0000000F if LBLAW1_LENGTH_64_KBYTES + default 0x00000010 if LBLAW1_LENGTH_128_KBYTES + default 0x00000011 if LBLAW1_LENGTH_256_KBYTES + default 0x00000012 if LBLAW1_LENGTH_512_KBYTES + default 0x00000013 if LBLAW1_LENGTH_1_MBYTES + default 0x00000014 if LBLAW1_LENGTH_2_MBYTES + default 0x00000015 if LBLAW1_LENGTH_4_MBYTES + default 0x00000016 if LBLAW1_LENGTH_8_MBYTES + default 0x00000017 if LBLAW1_LENGTH_16_MBYTES + default 0x00000018 if LBLAW1_LENGTH_32_MBYTES + default 0x00000019 if LBLAW1_LENGTH_64_MBYTES + default 0x0000001A if LBLAW1_LENGTH_128_MBYTES + default 0x0000001B if LBLAW1_LENGTH_256_MBYTES + default 0x0000001C if LBLAW1_LENGTH_512_MBYTES + default 0x0000001D if LBLAW1_LENGTH_1_GBYTES + default 0x0000001E if LBLAW1_LENGTH_2_GBYTES + +menuconfig LBLAW2 + bool "LBLAW2" + +if LBLAW2 + +config LBLAW2_ENABLE + bool "Window enable" + default "y" + +if !LBLAW2_ENABLE + +config LBLAW2_BASE + hex + default 0x0 + +endif + +if LBLAW2_ENABLE + +config LBLAW2_NAME + string "Identifier" + +config LBLAW2_BASE + hex "Window base" + +choice + prompt "Window size" + +config LBLAW2_LENGTH_4_KBYTES + bool "4 kb" + +config LBLAW2_LENGTH_8_KBYTES + bool "8 kb" + +config LBLAW2_LENGTH_16_KBYTES + bool "16 kb" + +config LBLAW2_LENGTH_32_KBYTES + bool "32 kb" + +config LBLAW2_LENGTH_64_KBYTES + bool "64 kb" + +config LBLAW2_LENGTH_128_KBYTES + bool "128 kb" + +config LBLAW2_LENGTH_256_KBYTES + bool "256 kb" + +config LBLAW2_LENGTH_512_KBYTES + bool "512 kb" + +config LBLAW2_LENGTH_1_MBYTES + bool "1 mb" + +config LBLAW2_LENGTH_2_MBYTES + bool "2 mb" + +config LBLAW2_LENGTH_4_MBYTES + bool "4 mb" + +config LBLAW2_LENGTH_8_MBYTES + bool "8 mb" + +config LBLAW2_LENGTH_16_MBYTES + bool "16 mb" + +config LBLAW2_LENGTH_32_MBYTES + bool "32 mb" + +config LBLAW2_LENGTH_64_MBYTES + bool "64 mb" + +config LBLAW2_LENGTH_128_MBYTES + bool "128 mb" + +config LBLAW2_LENGTH_256_MBYTES + bool "256 mb" + +config LBLAW2_LENGTH_512_MBYTES + bool "512 mb" + +config LBLAW2_LENGTH_1_GBYTES + bool "1 gb" + +config LBLAW2_LENGTH_2_GBYTES + bool "2 gb" + +endchoice + +endif # LBLAW2_ENABLE + +endif # LBLAW2 + +config LBLAW2_ENABLE_BIT + hex + default 0x0 if !LBLAW2_ENABLE + default 0x80000000 if LBLAW2_ENABLE + +config LBLAW2_LENGTH + hex + default 0x0 if !LBLAW2_ENABLE + default 0x0000000B if LBLAW2_LENGTH_4_KBYTES + default 0x0000000C if LBLAW2_LENGTH_8_KBYTES + default 0x0000000D if LBLAW2_LENGTH_16_KBYTES + default 0x0000000E if LBLAW2_LENGTH_32_KBYTES + default 0x0000000F if LBLAW2_LENGTH_64_KBYTES + default 0x00000010 if LBLAW2_LENGTH_128_KBYTES + default 0x00000011 if LBLAW2_LENGTH_256_KBYTES + default 0x00000012 if LBLAW2_LENGTH_512_KBYTES + default 0x00000013 if LBLAW2_LENGTH_1_MBYTES + default 0x00000014 if LBLAW2_LENGTH_2_MBYTES + default 0x00000015 if LBLAW2_LENGTH_4_MBYTES + default 0x00000016 if LBLAW2_LENGTH_8_MBYTES + default 0x00000017 if LBLAW2_LENGTH_16_MBYTES + default 0x00000018 if LBLAW2_LENGTH_32_MBYTES + default 0x00000019 if LBLAW2_LENGTH_64_MBYTES + default 0x0000001A if LBLAW2_LENGTH_128_MBYTES + default 0x0000001B if LBLAW2_LENGTH_256_MBYTES + default 0x0000001C if LBLAW2_LENGTH_512_MBYTES + default 0x0000001D if LBLAW2_LENGTH_1_GBYTES + default 0x0000001E if LBLAW2_LENGTH_2_GBYTES + +menuconfig LBLAW3 + bool "LBLAW3" + +if LBLAW3 + +config LBLAW3_ENABLE + bool "Window enable" + default "y" + +if !LBLAW3_ENABLE + +config LBLAW3_BASE + hex + default 0x0 + +endif + +if LBLAW3_ENABLE + +config LBLAW3_NAME + string "Identifier" + +config LBLAW3_BASE + hex "Window base" + +choice + prompt "Window size" + +config LBLAW3_LENGTH_4_KBYTES + bool "4 kb" + +config LBLAW3_LENGTH_8_KBYTES + bool "8 kb" + +config LBLAW3_LENGTH_16_KBYTES + bool "16 kb" + +config LBLAW3_LENGTH_32_KBYTES + bool "32 kb" + +config LBLAW3_LENGTH_64_KBYTES + bool "64 kb" + +config LBLAW3_LENGTH_128_KBYTES + bool "128 kb" + +config LBLAW3_LENGTH_256_KBYTES + bool "256 kb" + +config LBLAW3_LENGTH_512_KBYTES + bool "512 kb" + +config LBLAW3_LENGTH_1_MBYTES + bool "1 mb" + +config LBLAW3_LENGTH_2_MBYTES + bool "2 mb" + +config LBLAW3_LENGTH_4_MBYTES + bool "4 mb" + +config LBLAW3_LENGTH_8_MBYTES + bool "8 mb" + +config LBLAW3_LENGTH_16_MBYTES + bool "16 mb" + +config LBLAW3_LENGTH_32_MBYTES + bool "32 mb" + +config LBLAW3_LENGTH_64_MBYTES + bool "64 mb" + +config LBLAW3_LENGTH_128_MBYTES + bool "128 mb" + +config LBLAW3_LENGTH_256_MBYTES + bool "256 mb" + +config LBLAW3_LENGTH_512_MBYTES + bool "512 mb" + +config LBLAW3_LENGTH_1_GBYTES + bool "1 gb" + +config LBLAW3_LENGTH_2_GBYTES + bool "2 gb" + +endchoice + +endif # LBLAW3_ENABLE + +endif # LBLAW3 + +config LBLAW3_ENABLE_BIT + hex + default 0x0 if !LBLAW3_ENABLE + default 0x80000000 if LBLAW3_ENABLE + +config LBLAW3_LENGTH + hex + default 0x0 if !LBLAW3_ENABLE + default 0x0000000B if LBLAW3_LENGTH_4_KBYTES + default 0x0000000C if LBLAW3_LENGTH_8_KBYTES + default 0x0000000D if LBLAW3_LENGTH_16_KBYTES + default 0x0000000E if LBLAW3_LENGTH_32_KBYTES + default 0x0000000F if LBLAW3_LENGTH_64_KBYTES + default 0x00000010 if LBLAW3_LENGTH_128_KBYTES + default 0x00000011 if LBLAW3_LENGTH_256_KBYTES + default 0x00000012 if LBLAW3_LENGTH_512_KBYTES + default 0x00000013 if LBLAW3_LENGTH_1_MBYTES + default 0x00000014 if LBLAW3_LENGTH_2_MBYTES + default 0x00000015 if LBLAW3_LENGTH_4_MBYTES + default 0x00000016 if LBLAW3_LENGTH_8_MBYTES + default 0x00000017 if LBLAW3_LENGTH_16_MBYTES + default 0x00000018 if LBLAW3_LENGTH_32_MBYTES + default 0x00000019 if LBLAW3_LENGTH_64_MBYTES + default 0x0000001A if LBLAW3_LENGTH_128_MBYTES + default 0x0000001B if LBLAW3_LENGTH_256_MBYTES + default 0x0000001C if LBLAW3_LENGTH_512_MBYTES + default 0x0000001D if LBLAW3_LENGTH_1_GBYTES + default 0x0000001E if LBLAW3_LENGTH_2_GBYTES + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h b/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h new file mode 100644 index 00000000000..6972afcc2c7 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h @@ -0,0 +1,55 @@ +#if defined(CONFIG_LBLAW0) +#define CONFIG_SYS_LBLAWBAR0_PRELIM \ + CONFIG_LBLAW0_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (\ + CONFIG_LBLAW0_ENABLE_BIT |\ + CONFIG_LBLAW0_LENGTH \ +) +#endif + +#if defined(CONFIG_LBLAW1) +#define CONFIG_SYS_LBLAWBAR1_PRELIM \ + CONFIG_LBLAW1_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (\ + CONFIG_LBLAW1_ENABLE_BIT |\ + CONFIG_LBLAW1_LENGTH \ +) +#endif + +#if defined(CONFIG_LBLAW2) +#define CONFIG_SYS_LBLAWBAR2_PRELIM \ + CONFIG_LBLAW2_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (\ + CONFIG_LBLAW2_ENABLE_BIT |\ + CONFIG_LBLAW2_LENGTH \ +) +#endif + +#if defined(CONFIG_LBLAW3) +#define CONFIG_SYS_LBLAWBAR3_PRELIM \ + CONFIG_LBLAW3_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (\ + CONFIG_LBLAW3_ENABLE_BIT |\ + CONFIG_LBLAW3_LENGTH \ +) +#endif + +#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_0 +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM +#endif + +#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_1 +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM +#endif + +#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_2 +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR2_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR2_PRELIM +#endif + +#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_3 +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR3_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR3_PRELIM +#endif diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 2d6ba12e2d9..75eb65010ec 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -6,6 +6,8 @@ #include <common.h> #include <mpc83xx.h>
+#include "lblaw/lblaw.h" + DECLARE_GLOBAL_DATA_PTR;
/* diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 14136f6b673..38c5d8d5327 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -46,6 +46,18 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 8e34ee2c2ba..5783165e5d1 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -57,6 +57,22 @@ CONFIG_BAT6_ICACHE_GUARDED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2800000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xFA000000 +CONFIG_LBLAW3_NAME="BCSR" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index a2f7eb5837e..2395b8e3978 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -56,6 +56,22 @@ CONFIG_BAT6_ICACHE_GUARDED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2800000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xFA000000 +CONFIG_LBLAW3_NAME="BCSR" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index c3ad8fa5640..4c2d3400fdf 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -58,6 +58,23 @@ CONFIG_BAT6_ICACHE_GUARDED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_NAND_LBLAWBAR_PRELIM_1=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2800000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xFA000000 +CONFIG_LBLAW3_NAME="BCSR" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index 2491de4134a..b241091e489 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -57,6 +57,23 @@ CONFIG_BAT6_ICACHE_GUARDED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_NAND_LBLAWBAR_PRELIM_1=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2800000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xFA000000 +CONFIG_LBLAW3_NAME="BCSR" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index 43daee1f19f..b6e43b66aac 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -68,6 +68,14 @@ CONFIG_BAT5_DCACHE_INHIBITED=y CONFIG_BAT5_DCACHE_GUARDED=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 9039652d4b6..7243cf67f96 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -66,6 +66,10 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index aefb01f150e..8cbc14022b6 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -56,6 +56,18 @@ CONFIG_BAT5_BASE=0xE6000000 CONFIG_BAT5_ACCESS_RW=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF8008000 +CONFIG_LBLAW3_NAME="PIB" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index f410f8dac00..487d1d85442 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -76,6 +76,18 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF8008000 +CONFIG_LBLAW3_NAME="PIB" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index dac8f28a4d3..10ea03422c7 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -76,6 +76,18 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF8008000 +CONFIG_LBLAW3_NAME="PIB" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index c1cb69ad934..b1afa2fa474 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -73,6 +73,18 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF8008000 +CONFIG_LBLAW3_NAME="PIB" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index 38e0b7f6deb..a9bb8a77139 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -56,6 +56,18 @@ CONFIG_BAT5_BASE=0xE6000000 CONFIG_BAT5_ACCESS_RW=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF8008000 +CONFIG_LBLAW3_NAME="PIB" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index 6daab44b620..28779bbeb74 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -45,6 +45,14 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2400000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index d3f42f99e02..a157066968d 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -45,6 +45,18 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2400000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="SDRAM" +CONFIG_LBLAW2_LENGTH_64_MBYTES=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index c264f7b53d6..588d9420f16 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -43,6 +43,14 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2400000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 4018d818256..a38edb52939 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -45,6 +45,14 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE2400000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 0434118419f..844b8973295 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -85,6 +85,18 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="VSC7385" +CONFIG_LBLAW1_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF0000000 +CONFIG_LBLAW3_NAME="CF" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index de97bb15b2b..91ed6686f81 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -85,6 +85,18 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="VSC7385" +CONFIG_LBLAW1_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF0000000 +CONFIG_LBLAW3_NAME="CF" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index b1e687ceab1..cfa31c72307 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -84,6 +84,18 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_16_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="VSC7385" +CONFIG_LBLAW1_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xF0000000 +CONFIG_LBLAW3_NAME="CF" +CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 86b9f6071a0..4cc36a5c7fb 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -89,6 +89,18 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xE0600000 +CONFIG_LBLAW3_NAME="NAND" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index 44c23eade50..ba58e49ba24 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -49,6 +49,18 @@ CONFIG_BAT3_DCACHE_INHIBITED=y CONFIG_BAT3_DCACHE_GUARDED=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xE0600000 +CONFIG_LBLAW3_NAME="NAND" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index f21cdbd1793..b3c1c87824a 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -69,6 +69,18 @@ CONFIG_BAT5_BASE=0xE6000000 CONFIG_BAT5_ACCESS_RW=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF8000000 +CONFIG_LBLAW1_NAME="BCSR" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xE0600000 +CONFIG_LBLAW3_NAME="NAND" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index d1455b0e9dd..07016936d62 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -49,6 +49,18 @@ CONFIG_BAT3_DCACHE_INHIBITED=y CONFIG_BAT3_DCACHE_GUARDED=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index e6138c06fc3..59d591fa05b 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -89,6 +89,18 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xF0000000 +CONFIG_LBLAW2_NAME="VSC7385" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index 677f0513a35..fdaded29704 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -92,6 +92,16 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0x80000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_1_GBYTES=y +CONFIG_LBLAW1=y +# CONFIG_LBLAW1_ENABLE is not set +CONFIG_LBLAW2=y +# CONFIG_LBLAW2_ENABLE is not set +CONFIG_LBLAW3=y +# CONFIG_LBLAW3_ENABLE is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 2665e725730..12721f8db42 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -63,6 +63,14 @@ CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFFC00000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_4_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF0000000 +CONFIG_LBLAW1_NAME="WINDOW1" +CONFIG_LBLAW1_LENGTH_256_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index deed831c11a..f1aa24683c0 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -46,6 +46,14 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index c1135434724..22689ef0aca 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -46,6 +46,14 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 4afed470331..168564606c0 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -53,6 +53,23 @@ CONFIG_BAT6_ICACHE_GUARDED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_NAND_LBLAWBAR_PRELIM_1=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFF800000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE1000000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xE2000000 +CONFIG_LBLAW2_NAME="MRAM" +CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xE3000000 +CONFIG_LBLAW3_NAME="CPLD" +CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_IMAGE_FORMAT_LEGACY=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index a358e28886c..088dee63ba0 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -92,6 +92,18 @@ CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xA0000000 +CONFIG_LBLAW3_NAME="PAXE" +CONFIG_LBLAW3_LENGTH_512_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 10f7fdf1109..64ea83fd128 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -65,6 +65,18 @@ CONFIG_BAT5_DCACHE_INHIBITED=y CONFIG_BAT5_DCACHE_GUARDED=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xA0000000 +CONFIG_LBLAW3_NAME="PAXE" +CONFIG_LBLAW3_LENGTH_512_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index b32b39113fa..3a88b6a0276 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -76,6 +76,22 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xB0000000 +CONFIG_LBLAW3_NAME="APP2" +CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index cc94d174f03..c818d7e4a12 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -66,6 +66,18 @@ CONFIG_BAT5_DCACHE_INHIBITED=y CONFIG_BAT5_DCACHE_GUARDED=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 994e1525f79..640e0c7c3c3 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -67,6 +67,18 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xB0000000 +CONFIG_LBLAW3_NAME="APP2" +CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index bb237860578..81579c6b02f 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -76,6 +76,22 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xB0000000 +CONFIG_LBLAW3_NAME="APP2" +CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 666dbf32cc9..709947b5391 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -77,6 +77,22 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xB0000000 +CONFIG_LBLAW3_NAME="APP2" +CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index f583fa922e3..b44e04e1ae2 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -44,6 +44,18 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFC000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_64_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xFBFF0000 +CONFIG_LBLAW1_NAME="SJA1000" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xFBFF8000 +CONFIG_LBLAW2_NAME="CPLD" +CONFIG_LBLAW2_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index f8ce3093761..6f407d56d56 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -65,6 +65,10 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFF800000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index bc9e2288941..9c0b30f446c 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -65,6 +65,10 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFF800000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index d8e60da7be1..05361f76fcb 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -45,6 +45,10 @@ CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFF800000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 508ffe201ab..196c44470a2 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -45,6 +45,14 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 514db1c2133..c407bed189d 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -45,6 +45,14 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index a998585f3a8..1128950ace2 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -45,6 +45,14 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 48579c75633..f0b2c44efb1 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -45,6 +45,14 @@ CONFIG_BAT3_BASE=0xE6000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_USER_MODE_VALID=y CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 4dd36cac919..10a32178f13 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -76,6 +76,22 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xB0000000 +CONFIG_LBLAW3_NAME="APP2" +CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SUVD3" diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 7db157bf210..6fada9bdf70 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -66,6 +66,18 @@ CONFIG_BAT5_DCACHE_INHIBITED=y CONFIG_BAT5_DCACHE_GUARDED=y CONFIG_BAT5_USER_MODE_VALID=y CONFIG_BAT5_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index e0c1366291c..1eb21e0e5af 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -76,6 +76,22 @@ CONFIG_BAT6_DCACHE_INHIBITED=y CONFIG_BAT6_DCACHE_GUARDED=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF0000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_256_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE8000000 +CONFIG_LBLAW1_NAME="KMBEC_FPGA" +CONFIG_LBLAW1_LENGTH_128_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xA0000000 +CONFIG_LBLAW2_NAME="APP1" +CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_LBLAW3=y +CONFIG_LBLAW3_BASE=0xB0000000 +CONFIG_LBLAW3_NAME="APP2" +CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 517c4aa854e..1df5195e977 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -65,6 +65,15 @@ CONFIG_BAT7_ICACHE_GUARDED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y CONFIG_BAT7_SUPERVISOR_MODE_VALID=y +CONFIG_NAND_LBLAWBAR_PRELIM_1=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0x61000000 +CONFIG_LBLAW1_NAME="NAND" +CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index b7cf6a44bc8..9336dfac5cb 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -63,6 +63,14 @@ CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y CONFIG_BAT6_USER_MODE_VALID=y CONFIG_BAT6_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xF8000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_128_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xF0000000 +CONFIG_LBLAW1_NAME="WINDOW1" +CONFIG_LBLAW1_LENGTH_256_KBYTES=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index dc7a8b8aa85..1953d18e878 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -176,9 +176,6 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -218,9 +215,6 @@ | OR_FCM_EHTR) /* 0xFFFF8396 */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - #ifdef CONFIG_VSC7385_ENET #define CONFIG_TSEC2 /* VSC7385 Base address on CS2 */ @@ -239,10 +233,6 @@ | OR_GPCM_TRLX_SET \ | OR_GPCM_EHTR_SET) /* 0xFFFE09FF */ -/* Access window base at VSC7385 base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -/* Access window size 128K */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 #define CONFIG_VSC7385_IMAGE_SIZE 8192 diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 596d39ee5e9..79c7f12baee 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -180,10 +180,6 @@ | OR_GPCM_EHTR \ | OR_GPCM_EAD) /* 0xFF006FF7 TODO SLOW 16 MB flash size */ - /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE - /* 16 MB window size */ -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ @@ -253,12 +249,6 @@ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - /* local bus write LED / read status buffer (BCSR) mapping */ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ @@ -277,9 +267,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFFFF8FF7 */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET @@ -301,11 +288,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFFFE09FF */ - - /* Access window base at VSC7385 base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - #endif
#define CONFIG_MPC83XX_GPIO 1 diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 9d1ce200ec5..1b2bba96d33 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -153,10 +153,6 @@ | OR_GPCM_EHTR \ | OR_GPCM_EAD) /* 0xFF006FF7 TODO SLOW 16 MB flash size */ - /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE - /* 16 MB window size */ -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ @@ -222,12 +218,6 @@ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - /* local bus write LED / read status buffer (BCSR) mapping */ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ @@ -246,9 +236,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFFFF8FF7 */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET @@ -270,11 +257,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xFFFE09FF */ - - /* Access window base at VSC7385 base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - #endif
#define CONFIG_MPC83XX_GPIO 1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index fb568efe2d4..86491b41d66 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -146,10 +146,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
- /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -213,12 +209,6 @@ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ !defined(CONFIG_NAND_SPL) #define CONFIG_SYS_RAMBOOT diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 489e7c3368c..cb17c7644de 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -141,9 +141,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
- /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 15fca456cc7..d51d5ce06d5 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -133,10 +133,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
- /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -162,8 +158,6 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | BR_PS_8 \ @@ -185,8 +179,6 @@ /* PIB window base 0xF8008000 */ #define CONFIG_SYS_PIB_BASE 0xF8008000 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
/* * CS2 on Local Bus, to PIB diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index e4d90589e9a..06017a81bc8 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -137,10 +137,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD)
- /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
@@ -161,8 +157,6 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | BR_PS_8 \ | BR_MS_GPCM \ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index a24a2011d2f..708a21f1649 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -137,10 +137,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD)
- /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
@@ -161,8 +157,6 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | BR_PS_8 \ | BR_MS_GPCM \ @@ -222,8 +216,6 @@ | BR_MS_SDRAM /* MSEL = SDRAM */ \ | BR_V) /* Valid */ /* 0xF0001861 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
/* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index aeee6e0408f..16d615dcc65 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -226,9 +226,6 @@ boards, we say we have two, but don't display a message if we find only one. */ | OR_GPCM_TRLX_SET \ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) - /* Vitesse 7385 */
#define CONFIG_SYS_VSC7385_BASE 0xF8000000 @@ -247,10 +244,6 @@ boards, we say we have two, but don't display a message if we find only one. */ | OR_GPCM_TRLX_SET \ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) - -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - #endif
/* LED */ @@ -281,9 +274,6 @@ boards, we say we have two, but don't display a message if we find only one. */ | BR_V) #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) - #endif
/* diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 01a3a77e997..9d6dc767ef3 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -162,10 +162,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
- /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -193,9 +189,6 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | BR_PS_8 \ | BR_MS_GPCM \ @@ -233,9 +226,6 @@ | OR_FCM_EHTR) /* 0xFFFF919E */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* * Serial Port */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 9a4eeb63903..a1de8acc5c7 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -188,10 +188,6 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
- /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -226,9 +222,6 @@ | OR_FCM_SCY_1 \ | OR_FCM_TRLX \ | OR_FCM_EHTR) -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* Vitesse 7385 */
#define CONFIG_SYS_VSC7385_BASE 0xF0000000 @@ -249,11 +242,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xfffe09ff */ - - /* Access Base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - #endif
/* diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c5a6203001b..4479000d25a 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -93,26 +93,15 @@ #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) - - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE - /* disable remaining mappings */ #define CONFIG_SYS_BR1_PRELIM 0x00000000 #define CONFIG_SYS_OR1_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
#define CONFIG_SYS_BR2_PRELIM 0x00000000 #define CONFIG_SYS_OR2_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
#define CONFIG_SYS_BR3_PRELIM 0x00000000 #define CONFIG_SYS_OR3_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
/* * Monitor config diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index f4ee2228084..b355e56355f 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -84,8 +84,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xffc06ff7 */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ @@ -96,8 +94,6 @@ #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ | OR_GPCM_SETA) /* 0xfffc0208 */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index c8fabf9da54..d86de800db7 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -170,9 +170,6 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -199,9 +196,6 @@ #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
/* Window base at FPGA base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 120eb0a6b71..e930c65637b 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ BR_PS_8 |\ BR_MS_GPCM |\ @@ -173,11 +170,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ (2<<BR_DECC_SHIFT) |\ BR_PS_8 |\ @@ -199,8 +191,6 @@ */ #define CONFIG_SYS_MRAM_BASE 0xE2000000 #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
#define CONFIG_SYS_OR_TIMING_MRAM
@@ -216,8 +206,6 @@ */ #define CONFIG_SYS_CPLD_BASE 0xE3000000 #define CONFIG_SYS_CPLD_SIZE 0x8000 -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
#define CONFIG_SYS_OR_TIMING_MRAM
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 8e5626da4c0..f286d9b4749 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -108,9 +108,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -129,9 +126,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -353,10 +347,6 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE - -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ - #define CONFIG_SYS_BR3_PRELIM (\ CONFIG_SYS_PAXE_BASE | \ (1 << BR_PS_SHIFT) | \ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index f6c7cfce438..1da8df39312 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -93,9 +93,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -114,9 +111,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -333,10 +327,6 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE - -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ - #define CONFIG_SYS_BR3_PRELIM (\ CONFIG_SYS_PAXE_BASE | \ (1 << BR_PS_SHIFT) | \ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 6ac36c0f921..e732c2ad022 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -134,9 +131,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -367,11 +361,6 @@ /* * Configuration for C2 on the local bus */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ @@ -388,8 +377,6 @@ /* * Configuration for C3 on the local bus */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ BR_PS_16 | \ BR_MS_GPCM | \ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 7ee9a914a46..42fbdbf947f 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -134,9 +131,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -365,11 +359,6 @@ /* * Configuration for C2 on the local bus */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 53017faa1cf..222eb72f8eb 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -120,9 +120,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -141,9 +138,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -427,9 +421,6 @@ OR_GPCM_TRLX_CLEAR | \ OR_GPCM_EHTR_CLEAR)
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - /* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 #define CONFIG_UEC_ETH2 diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 8f2be980a04..e542158022a 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -134,9 +131,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -367,11 +361,6 @@ /* * Configuration for C2 on the local bus */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ @@ -388,8 +377,6 @@ /* * Configuration for C3 on the local bus */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ BR_PS_16 | \ BR_MS_GPCM | \ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 172a28e8504..3e2cc60f3ed 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -112,9 +112,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -133,9 +130,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -409,9 +403,6 @@ /* * APP1 on the local bus CS2 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_16 | \ BR_MS_UPMA | \ @@ -431,10 +422,6 @@ #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ MxMR_WLFx_2X) - -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - /* * QE UEC ethernet configuration */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 1bca11bd6e7..aa9710f9c21 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -180,9 +180,6 @@ #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -217,9 +214,6 @@ | OR_GPCM_EHTR_SET) /* 0xFFFF8052 */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* * CPLD on Local Bus */ @@ -233,9 +227,6 @@ | OR_GPCM_EHTR_SET) /* 0xFFFF8042 */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - /* * Serial Port */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 8179147bc22..edf76e58519 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -114,10 +114,6 @@ | OR_GPCM_EAD) /* 0xFF806FF7 */
- /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
@@ -180,9 +176,6 @@ | BR_MS_SDRAM \ | BR_V) /* 0xF0001861 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) - /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * diff --git a/include/configs/strider.h b/include/configs/strider.h index a716096bed8..3b0207488f4 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -168,9 +168,6 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ @@ -197,9 +194,6 @@ #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
/* Window base at FPGA base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 6a4006ef6ad..987b2d77cc1 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -110,9 +110,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -131,9 +128,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -362,9 +356,6 @@ /* * APP1 on the local bus CS2 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_16 | \ BR_MS_UPMA | \ @@ -384,8 +375,4 @@ #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ MxMR_WLFx_2X) - -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #endif /* __CONFIG_H */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 5bb74fd9aeb..5fceac7ae16 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -134,9 +131,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -365,11 +359,6 @@ /* * Configuration for C2 on the local bus */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index a85039bf3c1..2906c2995be 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ BR_PS_16 | /* 16 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -134,9 +131,6 @@ * PRIO1/PIGGY on the local bus CS1 */ /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) - #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ @@ -367,11 +361,6 @@ /* * Configuration for C2 on the local bus */ -/* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ @@ -388,11 +377,6 @@ /* * Configuration for C3 on the local bus */ -/* Access window base at PINC3 base */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE -/* Window size: 256 MB */ -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 84d2c897d76..7dcc150f195 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -111,9 +111,6 @@ #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
@@ -186,12 +183,6 @@ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM - /* CS2 NvRAM */ #define CONFIG_SYS_BR2_PRELIM (0x60000000 \ | BR_PS_8 \ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 249783720c4..ed02661f82a 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -84,8 +84,6 @@ | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xf8006ff7 */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ @@ -96,8 +94,6 @@ #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ | OR_GPCM_SETA) /* 0xfffc0208 */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e2467997a80..6e1f8390a07 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3250,22 +3250,6 @@ CONFIG_SYS_LBC_NONCACHE_BASE CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_SIZE -CONFIG_SYS_LBLAWAR0_PRELIM -CONFIG_SYS_LBLAWAR1_PRELIM -CONFIG_SYS_LBLAWAR2_PRELIM -CONFIG_SYS_LBLAWAR3_PRELIM -CONFIG_SYS_LBLAWAR4_PRELIM -CONFIG_SYS_LBLAWAR5_PRELIM -CONFIG_SYS_LBLAWAR6_PRELIM -CONFIG_SYS_LBLAWAR7_PRELIM -CONFIG_SYS_LBLAWBAR0_PRELIM -CONFIG_SYS_LBLAWBAR1_PRELIM -CONFIG_SYS_LBLAWBAR2_PRELIM -CONFIG_SYS_LBLAWBAR3_PRELIM -CONFIG_SYS_LBLAWBAR4_PRELIM -CONFIG_SYS_LBLAWBAR5_PRELIM -CONFIG_SYS_LBLAWBAR6_PRELIM -CONFIG_SYS_LBLAWBAR7_PRELIM CONFIG_SYS_LB_SDRAM CONFIG_SYS_LCD_BASE CONFIG_SYS_LCRR_CLKDIV
All BR/OR option lines should have the same layout to make them easier to migrate to Kconfig. This includes using the same option macros everywhere.
The normalize the lines, * replace function macros with their results, and * replace hardcoded hex values with standard macros
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- include/configs/MPC8308RDB.h | 6 +++--- include/configs/MPC8313ERDB_NAND.h | 4 ++-- include/configs/MPC8313ERDB_NOR.h | 4 ++-- include/configs/MPC8323ERDB.h | 2 +- include/configs/MPC832XEMDS.h | 6 +++--- include/configs/MPC8349EMDS.h | 2 +- include/configs/MPC8349EMDS_SDRAM.h | 2 +- include/configs/MPC8349ITX.h | 2 +- include/configs/MPC837XEMDS.h | 2 +- include/configs/MPC837XERDB.h | 2 +- include/configs/caddy2.h | 2 +- include/configs/hrcon.h | 4 ++-- include/configs/ids8313.h | 10 +++++----- include/configs/kmcoge5ne.h | 12 ++++++------ include/configs/kmeter1.h | 8 ++++---- include/configs/kmopti2.h | 8 ++++---- include/configs/kmsupx5.h | 6 +++--- include/configs/kmtegr1.h | 6 +++--- include/configs/kmtepr2.h | 8 ++++---- include/configs/kmvect1.h | 8 ++++---- include/configs/mpc8308_p1m.h | 2 +- include/configs/sbc8349.h | 4 ++-- include/configs/strider.h | 4 ++-- include/configs/suvd3.h | 8 ++++---- include/configs/tuge1.h | 6 +++--- include/configs/tuxx1.h | 8 ++++---- include/configs/vme8349.h | 2 +- 27 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 1953d18e878..e19bcafd5ce 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -180,7 +180,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -206,7 +206,7 @@ | BR_PS_8 /* 8 bit Port */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -225,7 +225,7 @@ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ /* 0xF0000801 */ -#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ | OR_GPCM_CSNT \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 79c7f12baee..bbb9d4b936c 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -258,7 +258,7 @@ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ /* 0xFA000801 */ -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ @@ -279,7 +279,7 @@ | BR_PS_8 /* 8 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ | OR_GPCM_CSNT \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 1b2bba96d33..1cb001864a4 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -227,7 +227,7 @@ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ /* 0xFA000801 */ -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ @@ -248,7 +248,7 @@ | BR_PS_8 /* 8 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ | OR_GPCM_CSNT \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index cb17c7644de..30f1e4453d1 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -146,7 +146,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \ | OR_GPCM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index d51d5ce06d5..3a8a3e4fb89 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -137,7 +137,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \ | OR_GPCM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -188,7 +188,7 @@ | BR_MS_GPCM \ | BR_V) /* 0xF8008801 */ -#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \ | OR_GPCM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_XACS \ @@ -207,7 +207,7 @@ | BR_MS_GPCM \ | BR_V) /* 0xF8010801 */ -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ | OR_GPCM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_XACS \ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 06017a81bc8..fa73b81c3a0 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -127,7 +127,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 708a21f1649..218c4b1fc98 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -127,7 +127,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 16d615dcc65..0bf179a70b1 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -217,7 +217,7 @@ boards, we say we have two, but don't display a message if we find only one. */ | BR_PS_16 \ | BR_MS_GPCM \ | BR_V) -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 9d6dc767ef3..e10c58d7eda 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -166,7 +166,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index a1de8acc5c7..1e45b5ee3f1 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -192,7 +192,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ | OR_GPCM_XACS \ | OR_GPCM_SCY_9 \ | OR_GPCM_EHTR_SET \ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index b355e56355f..ffd52a200a3 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -74,7 +74,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_4MB \ | OR_GPCM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index d86de800db7..4193ceb3793 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -174,7 +174,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -200,7 +200,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index e930c65637b..871b91f2183 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -147,7 +147,7 @@ BR_MS_GPCM |\ BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB |\ OR_GPCM_SCY_10 |\ OR_GPCM_EHTR |\ OR_GPCM_TRLX |\ @@ -171,12 +171,12 @@ #define NAND_CACHE_PAGES 64
#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ - (2<<BR_DECC_SHIFT) |\ + BR_DECC_CHK_GEN |\ BR_PS_8 |\ BR_MS_FCM |\ BR_V)
-#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB |\ OR_FCM_PGS |\ OR_FCM_CSCT |\ OR_FCM_CST |\ @@ -199,7 +199,7 @@ BR_MS_GPCM |\ BR_V)
-#define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74 +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET)
/* * CPLD setup @@ -214,7 +214,7 @@ BR_MS_GPCM |\ BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xFFFF8814 +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET)
/* * HW-Watchdog diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index f286d9b4749..1c5dcc52601 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -113,7 +113,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -130,7 +130,7 @@ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -349,11 +349,11 @@
#define CONFIG_SYS_BR3_PRELIM (\ CONFIG_SYS_PAXE_BASE | \ - (1 << BR_PS_SHIFT) | \ + BR_PS_8 | \ BR_V)
#define CONFIG_SYS_OR3_PRELIM (\ - MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ + OR_AM_256MB | \ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ @@ -368,11 +368,11 @@
#define CONFIG_SYS_BR4_PRELIM (\ CONFIG_SYS_BFTIC3_BASE |\ - (1 << BR_PS_SHIFT) | \ + BR_PS_8 | \ BR_V)
#define CONFIG_SYS_OR4_PRELIM (\ - MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\ + OR_AM_256MB|\ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV2 |\ OR_GPCM_SCY_2 |\ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 1da8df39312..2650544305c 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -98,7 +98,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -115,7 +115,7 @@ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -329,11 +329,11 @@
#define CONFIG_SYS_BR3_PRELIM (\ CONFIG_SYS_PAXE_BASE | \ - (1 << BR_PS_SHIFT) | \ + BR_PS_8 | \ BR_V)
#define CONFIG_SYS_OR3_PRELIM (\ - MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ + OR_AM_256MB | \ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index e732c2ad022..6e59fde6bd0 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -118,7 +118,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -135,7 +135,7 @@ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -366,7 +366,7 @@ BR_MS_GPCM | \ BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_2 | \ @@ -381,7 +381,7 @@ BR_PS_16 | \ BR_MS_GPCM | \ BR_V) -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ OR_GPCM_SCY_4 | \ OR_GPCM_TRLX_CLEAR | \ OR_GPCM_EHTR_CLEAR) diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 42fbdbf947f..af39e8bb857 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -118,7 +118,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -135,7 +135,7 @@ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -364,7 +364,7 @@ BR_MS_GPCM | \ BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_2 | \ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 222eb72f8eb..1312aa2fa99 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -125,7 +125,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -142,7 +142,7 @@ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -416,7 +416,7 @@ BR_MS_GPCM | \ BR_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX_CLEAR | \ OR_GPCM_EHTR_CLEAR) diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index e542158022a..fd00ea86a98 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -118,7 +118,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -135,7 +135,7 @@ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -366,7 +366,7 @@ BR_MS_GPCM | \ BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_2 | \ @@ -381,7 +381,7 @@ BR_PS_16 | \ BR_MS_GPCM | \ BR_V) -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ OR_GPCM_SCY_4 | \ OR_GPCM_TRLX_CLEAR | \ OR_GPCM_EHTR_CLEAR) diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 3e2cc60f3ed..3d9164714c7 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -117,7 +117,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -134,7 +134,7 @@ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -407,13 +407,13 @@ BR_PS_16 | \ BR_MS_UPMA | \ BR_V) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB)
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ BR_PS_16 | \ BR_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_3 | \ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index aa9710f9c21..046355f6454 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -184,7 +184,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index edf76e58519..dffb7c61086 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -103,7 +103,7 @@ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ | OR_GPCM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -190,7 +190,7 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 */
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ | OR_SDRAM_XAM \ | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ diff --git a/include/configs/strider.h b/include/configs/strider.h index 3b0207488f4..184396e0379 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -172,7 +172,7 @@ | BR_PS_16 /* 16 bit port */ \ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -199,7 +199,7 @@ | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_SCY_5 \ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 987b2d77cc1..ad270de87d7 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -115,7 +115,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -132,7 +132,7 @@ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -360,13 +360,13 @@ BR_PS_16 | \ BR_MS_UPMA | \ BR_V) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB)
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ BR_PS_16 | \ BR_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_3 | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 5fceac7ae16..af6a348ba57 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -118,7 +118,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -135,7 +135,7 @@ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -364,7 +364,7 @@ BR_MS_GPCM | \ BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_2 | \ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 2906c2995be..89af940ba6f 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -118,7 +118,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -135,7 +135,7 @@ BR_PS_8 | /* 8 bit port size */ \ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX_SET | OR_GPCM_EAD) @@ -366,7 +366,7 @@ BR_MS_GPCM | \ BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_2 | \ @@ -382,7 +382,7 @@ BR_MS_GPCM | \ BR_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index ed02661f82a..76821e7a407 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -74,7 +74,7 @@ BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB \ | OR_GPCM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \
We want to normalize all BR/OR config lines as much as possible.
The TQM834x board uses CONFIG_SYS_OR_TIMING_FLASH in a OR definition, which we want to remove. But CONFIG_SYS_OR_TIMING_FLASH is also used outside of the config file.
Replace these usages with the definition of the variable, so we can remove the variable in the next patch.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- board/tqc/tqm834x/tqm834x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index 7c92f4f54c1..c75251e132c 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -235,8 +235,8 @@ static int detect_num_flash_banks(void) debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);
/* set OR0 and BR0 */ - set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH | - (-(total_size) & OR_GPCM_AM)); + set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | + OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM)); set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) | (BR_MS_GPCM | BR_PS_32 | BR_V));
Re-format all BR,OR #define lines into single lines. This makes them harder to read, but accessible to semi-automatic replacement.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- include/configs/MPC8308RDB.h | 46 ++++--------------- include/configs/MPC8313ERDB_NAND.h | 67 +++++++-------------------- include/configs/MPC8313ERDB_NOR.h | 66 ++++++--------------------- include/configs/MPC8315ERDB.h | 34 +++----------- include/configs/MPC8323ERDB.h | 17 ++----- include/configs/MPC832XEMDS.h | 70 ++++++----------------------- include/configs/MPC8349EMDS.h | 32 +++---------- include/configs/MPC8349EMDS_SDRAM.h | 45 ++++--------------- include/configs/MPC8349ITX.h | 60 +++++++------------------ include/configs/MPC837XEMDS.h | 52 +++++---------------- include/configs/MPC837XERDB.h | 48 +++++--------------- include/configs/TQM834x.h | 19 ++------ include/configs/caddy2.h | 31 ++++--------- include/configs/hrcon.h | 32 +++---------- include/configs/ids8313.h | 47 +++++-------------- include/configs/kmcoge5ne.h | 55 ++++++----------------- include/configs/kmeter1.h | 40 +++++------------ include/configs/kmopti2.h | 53 +++++++--------------- include/configs/kmsupx5.h | 43 +++++------------- include/configs/kmtegr1.h | 37 +++++---------- include/configs/kmtepr2.h | 57 ++++++----------------- include/configs/kmvect1.h | 46 +++++-------------- include/configs/mpc8308_p1m.h | 40 +++++------------ include/configs/sbc8349.h | 18 ++------ include/configs/strider.h | 31 +++---------- include/configs/suvd3.h | 46 +++++-------------- include/configs/tuge1.h | 43 +++++------------- include/configs/tuxx1.h | 60 ++++++------------------- include/configs/ve8313.h | 64 ++++++-------------------- include/configs/vme8349.h | 31 ++++--------- 30 files changed, 302 insertions(+), 1028 deletions(-)
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index e19bcafd5ce..185f6490d7c 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -175,19 +175,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
-/* Window base at flash base */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ @@ -201,18 +191,9 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit Port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* 0xFFFF8396 */
#ifdef CONFIG_VSC7385_ENET @@ -220,18 +201,9 @@ /* VSC7385 Base address on CS2 */ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ - | BR_PS_8 /* 8-bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - /* 0xF0000801 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_SETA \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET) +/* VSC7385_BASE */ +#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) /* 0xFFFE09FF */ /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index bbb9d4b936c..40b0264dbe4 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -170,17 +170,6 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_9 \ - | OR_GPCM_EHTR \ - | OR_GPCM_EAD) - /* 0xFF006FF7 TODO SLOW 16 MB flash size */ - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
@@ -230,20 +219,13 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM \ - (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) - /* 0xFFFF8396 */ +/* NAND */ +#define CONFIG_SYS_BR0_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) + +/* FLASH */ +#define CONFIG_SYS_BR1_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM @@ -253,20 +235,10 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - /* 0xFA000801 */ -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFF8FF7 */ +/* BCSR */ +#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + /* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET @@ -275,19 +247,10 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_SETA \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFE09FF */ +/* VSC7385 */ +#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + #endif
#define CONFIG_MPC83XX_GPIO 1 diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 1cb001864a4..390ee4eb265 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -143,17 +143,6 @@ #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_9 \ - | OR_GPCM_EHTR \ - | OR_GPCM_EAD) - /* 0xFF006FF7 TODO SLOW 16 MB flash size */ - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
@@ -199,20 +188,13 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM \ - (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) - /* 0xFFFF8396 */ +/* FLASH*/ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
/* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM @@ -222,20 +204,9 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - /* 0xFA000801 */ -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFF8FF7 */ +/* BCSR */ +#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET @@ -244,19 +215,10 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_SETA \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFE09FF */ +/* VSC7385 */ +#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + #endif
#define CONFIG_MPC83XX_GPIO 1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 86491b41d66..97b66415c9b 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -177,33 +177,13 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM \ - (OR_AM_32KB \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) - /* 0xFFFF8396 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
/* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 30f1e4453d1..fd884a1e654 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -142,20 +142,9 @@ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFE006FF7 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 3a8a3e4fb89..41b02231352 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -133,20 +133,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xfe006ff7 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ @@ -159,19 +148,9 @@ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFFE9F7 */ +/* BCSR */ +#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* * Windows to access PIB via local bus @@ -183,39 +162,18 @@ /* * CS2 on Local Bus, to PIB */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF8008801 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffffe9f7 */ + +/* PIB1 */ +#define CONFIG_SYS_BR2_PRELIM (0xF8008000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* * CS3 on Local Bus, to PIB */ -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \ - CONFIG_SYS_PIB_WINDOW_SIZE) \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF8010801 */ -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffffe9f7 */ + +/* PIB2 */ +#define CONFIG_SYS_BR3_PRELIM (0xF8010000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* * Serial Port diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index fa73b81c3a0..4cda1589b67 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -123,19 +123,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -157,18 +147,10 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0x00000801 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_CLEAR \ - | OR_GPCM_EHTR_CLEAR) - /* 0xFFFFE8F0 */ + +/* BCSR */ +#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 218c4b1fc98..7f906c38d89 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -123,19 +123,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -157,18 +147,9 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0x00000801 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_CLEAR \ - | OR_GPCM_EHTR_CLEAR) - /* 0xFFFFE8F0 */ +/* BCSR */ +#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ @@ -211,11 +192,9 @@ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ - | BR_PS_32 /* 32-bit port */ \ - | BR_MS_SDRAM /* MSEL = SDRAM */ \ - | BR_V) /* Valid */ - /* 0xF0001861 */ +/* SDRAM */ +#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_SDRAM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_SDRAM_XAM | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) | OR_SDRAM_EAD)
/* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. @@ -231,12 +210,6 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ - | OR_SDRAM_XAM \ - | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ - | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ - | OR_SDRAM_EAD) - /* 0xFC006901 */
/* LB sdram refresh timer, about 6us */ #define CONFIG_SYS_LBC_LSRT 0x32000000 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 0bf179a70b1..e90d497f5ef 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -211,56 +211,28 @@ boards, we say we have two, but don't display a message if we find only one. */ * BRx, ORx, LBLAWBARx, and LBLAWARx */
-/* Flash */ - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + /* Vitesse 7385 */
#define CONFIG_SYS_VSC7385_BASE 0xF8000000
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_SETA \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) +/* VSC7385 */ +#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + #endif
-/* LED */
#define CONFIG_SYS_LED_BASE 0xF9000000 -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_9 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) + +/* LED */ +#define CONFIG_SYS_BR2_PRELIM (0xF9000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* Compact Flash */
@@ -268,11 +240,9 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_CF_BASE 0xF0000000
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ - | BR_PS_16 \ - | BR_MS_UPMA \ - | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) +/* CF */ +#define CONFIG_SYS_BR3_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_UPM_BI)
#endif
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e10c58d7eda..e569e63741f 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -162,20 +162,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFE000FF7 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -189,20 +178,9 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF8000801 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFFE9F7 */ +/* BCSR */ +#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* * NAND Flash on the Local Bus @@ -211,20 +189,10 @@ #define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BASE 0xE0600000 -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ - | OR_FCM_BCTLD \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_RST \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) - /* 0xFFFF919E */ + +/* NAND */ +#define CONFIG_SYS_BR3_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST | OR_FCM_TRLX | OR_FCM_EHTR)
/* * Serial Port diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 1e45b5ee3f1..c1898a53a6c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -188,16 +188,9 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_9 \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFF800191 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -210,38 +203,21 @@ * NAND Flash on the Local Bus */ #define CONFIG_SYS_NAND_BASE 0xE0600000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) + +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) + /* Vitesse 7385 */
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF0000801 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_SETA \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xfffe09ff */ +/* VSC7385 */ +#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + #endif
/* diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 4479000d25a..c76df2847d2 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -76,22 +76,9 @@
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
-/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ - | BR_MS_GPCM \ - | BR_PS_32 \ - | BR_V) - -/* FLASH timing (0x0000_0c54) */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV4 \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_TRLX) - -#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ - | CONFIG_SYS_OR_TIMING_FLASH) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0x80000000 | BR_MS_GPCM | BR_PS_32 | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_1GB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET)
/* disable remaining mappings */ #define CONFIG_SYS_BR1_PRELIM 0x00000000 diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index ffd52a200a3..a7eb5f52953 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -69,31 +69,16 @@ */ #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16bit */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) /* valid */ - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_4MB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffc06ff7 */ + +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFFC00000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_4MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ - | BR_PS_32 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF0001801 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ - | OR_GPCM_SETA) - /* 0xfffc0208 */ + +/* WINDOW1 */ +#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 4193ceb3793..3fe72db188c 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -169,19 +169,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
-/* Window base at flash base */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -195,19 +185,9 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
-/* Window base at FPGA base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET) +/* FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 871b91f2183..61f64ebbbc0 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -142,17 +142,10 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ - BR_PS_8 |\ - BR_MS_GPCM |\ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB |\ - OR_GPCM_SCY_10 |\ - OR_GPCM_EHTR |\ - OR_GPCM_TRLX |\ - OR_GPCM_CSNT |\ - OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_SCY_10 | OR_GPCM_EHTR_SET | OR_GPCM_TRLX_SET | OR_GPCM_CSNT | OR_GPCM_EAD) + #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128
@@ -170,21 +163,9 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ - BR_DECC_CHK_GEN |\ - BR_PS_8 |\ - BR_MS_FCM |\ - BR_V) - -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB |\ - OR_FCM_PGS |\ - OR_FCM_CSCT |\ - OR_FCM_CST |\ - OR_FCM_CHT |\ - OR_FCM_SCY_4 |\ - OR_FCM_TRLX |\ - OR_FCM_EHTR |\ - OR_FCM_RST) +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0xE1000000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_4 | OR_FCM_TRLX | OR_FCM_EHTR | OR_FCM_RST)
/* * MRAM setup @@ -194,11 +175,8 @@
#define CONFIG_SYS_OR_TIMING_MRAM
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\ - BR_PS_8 |\ - BR_MS_GPCM |\ - BR_V) - +/* MRAM */ +#define CONFIG_SYS_BR2_PRELIM (0xE2000000 | BR_PS_8 | BR_MS_GPCM | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET)
/* @@ -209,11 +187,8 @@
#define CONFIG_SYS_OR_TIMING_MRAM
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\ - BR_PS_8 |\ - BR_MS_GPCM |\ - BR_V) - +/* CPLD */ +#define CONFIG_SYS_BR3_PRELIM (0xE3000000 | BR_PS_8 | BR_MS_GPCM | BR_V) #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET)
/* diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 1c5dcc52601..01f432548f4 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -108,15 +108,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,15 +119,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -347,18 +336,9 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256
-#define CONFIG_SYS_BR3_PRELIM (\ - CONFIG_SYS_PAXE_BASE | \ - BR_PS_8 | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (\ - OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX | \ - OR_GPCM_EAD) +/* PAXE */ +#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * BFTIC3 on the local bus CS4 @@ -366,18 +346,9 @@ #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 #define CONFIG_SYS_BFTIC3_SIZE 256
-#define CONFIG_SYS_BR4_PRELIM (\ - CONFIG_SYS_BFTIC3_BASE |\ - BR_PS_8 | \ - BR_V) - -#define CONFIG_SYS_OR4_PRELIM (\ - OR_AM_256MB|\ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 |\ - OR_GPCM_SCY_2 |\ - OR_GPCM_TRLX |\ - OR_GPCM_EAD) +/* BFTIC3 */ +#define CONFIG_SYS_BR4_PRELIM (0xB0000000 | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR4_PRELIM (OR_AM_256MB| OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2650544305c..84516bb9bb7 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -93,15 +93,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -110,15 +104,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -327,17 +316,8 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256
-#define CONFIG_SYS_BR3_PRELIM (\ - CONFIG_SYS_PAXE_BASE | \ - BR_PS_8 | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (\ - OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX | \ - OR_GPCM_EAD) +/* PAXE */ +#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#endif /* CONFIG */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 6e59fde6bd0..678cb6a7cc7 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -113,15 +113,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -130,15 +124,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -361,29 +350,17 @@ /* * Configuration for C2 on the local bus */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) + +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
/* * Configuration for C3 on the local bus */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ - OR_GPCM_SCY_4 | \ - OR_GPCM_TRLX_CLEAR | \ - OR_GPCM_EHTR_CLEAR) + +/* APP2 */ +#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
#endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index af39e8bb857..3e2e425c34b 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -113,15 +113,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -130,15 +124,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -356,20 +345,8 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */
-/* - * Configuration for C2 on the local bus - */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
#endif /* __CONFIG_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 1312aa2fa99..ed221e23019 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -120,15 +120,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -137,15 +131,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -411,15 +400,9 @@ * */
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_CLEAR | \ - OR_GPCM_EHTR_CLEAR) +/* APP2 */ +#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
/* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index fd00ea86a98..c1ed71e2afe 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -113,15 +113,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -130,15 +124,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -358,32 +347,12 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */
-/* - * Configuration for C2 on the local bus - */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
-/* - * Configuration for C3 on the local bus - */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ - OR_GPCM_SCY_4 | \ - OR_GPCM_TRLX_CLEAR | \ - OR_GPCM_EHTR_CLEAR) +/* APP2 */ +#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
#endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 3d9164714c7..406b6e78244 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -112,15 +112,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -129,15 +123,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -400,24 +389,13 @@ * */
-/* - * APP1 on the local bus CS2 - */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_16 | \ - BR_MS_UPMA | \ - BR_V) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB)
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_3 | \ - OR_GPCM_TRLX_SET) +/* APP2 */ +#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET)
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 046355f6454..31bf9971ab2 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -179,19 +179,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
-/* Window base at flash base */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_4 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFC000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_4 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 @@ -205,27 +195,19 @@ * SJA1000 CAN controller on Local Bus */ #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \ - | BR_PS_8 /* 8 bit port size */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_EHTR_SET) - /* 0xFFFF8052 */ + +/* SJA1000 */ +#define CONFIG_SYS_BR1_PRELIM (0xFBFF0000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_SCY_5 | OR_GPCM_EHTR_SET)
/* * CPLD on Local Bus */ #define CONFIG_SYS_CPLD_BASE 0xFBFF8000 -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \ - | OR_GPCM_SCY_4 \ - | OR_GPCM_EHTR_SET) - /* 0xFFFF8042 */ + +/* CPLD */ +#define CONFIG_SYS_BR2_PRELIM (0xFBFF8000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_SCY_4 | OR_GPCM_EHTR_SET)
/* * Serial Port diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index dffb7c61086..09cdb7c1a8a 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -98,21 +98,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFF806FF7 */ +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ diff --git a/include/configs/strider.h b/include/configs/strider.h index 184396e0379..1519dad3217 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -167,19 +167,9 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
-/* Window base at flash base */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -193,18 +183,9 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
-/* Window base at FPGA base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_TRLX_CLEAR \ - | OR_GPCM_EHTR_CLEAR) +/* FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index ad270de87d7..6aacbc2077e 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -110,15 +110,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -127,15 +121,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -353,24 +342,13 @@ * */
-/* - * APP1 on the local bus CS2 - */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_16 | \ - BR_MS_UPMA | \ - BR_V) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB)
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_16 | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_3 | \ - OR_GPCM_TRLX_SET) +/* APP2 */ +#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET)
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index af6a348ba57..b11d49629ac 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -113,15 +113,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -130,15 +124,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -356,20 +345,8 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */
-/* - * Configuration for C2 on the local bus - */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
#endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 89af940ba6f..5c8f682d23a 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -113,15 +113,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -130,15 +124,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -358,36 +347,13 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */
-/* - * Configuration for C2 on the local bus - */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) +/* APP1 */ +#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
-/* - * Configuration for C3 on the local bus - */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR) +/* APP2 */ +#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 7dcc150f195..3a5bcf9c62f 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -153,63 +153,25 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV4 \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EAD) - /* 0xfe000c55 */ - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_PS_8 \ - | BR_DECC_CHK_GEN \ - | BR_MS_FCM \ - | BR_V) /* valid */ - /* 0x61000c21 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_FCM_BCTLD \ - | OR_FCM_CHT \ - | OR_FCM_SCY_2 \ - | OR_FCM_RST \ - | OR_FCM_TRLX) /* 0xffff90ac */ +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0x61000000 | BR_PS_8 | BR_DECC_CHK_GEN | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CHT | OR_FCM_SCY_2 | OR_FCM_RST | OR_FCM_TRLX)
/* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
-/* CS2 NvRAM */ -#define CONFIG_SYS_BR2_PRELIM (0x60000000 \ - | BR_PS_8 \ - | BR_V) - /* 0x60000801 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_3 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xfffe0937 */ -/* local bus read write buffer mapping SRAM@0x64000000 */ -#define CONFIG_SYS_BR3_PRELIM (0x62000000 \ - | BR_PS_16 \ - | BR_V) - /* 0x62001001 */ - -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xfe0009f7 */ +/* NVRAM */ +#define CONFIG_SYS_BR2_PRELIM (0x60000000 | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) + +/* SRAM */ +#define CONFIG_SYS_BR3_PRELIM (0x62000000 | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* * Serial Port diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 76821e7a407..dd8aae51173 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -69,31 +69,16 @@ */ #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16bit */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) /* valid */ - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xf8006ff7 */ + +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF8000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ - | BR_PS_32 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF0001801 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ - | OR_GPCM_SETA) - /* 0xfffc0208 */ + +/* WINDOW1 */ +#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
The MPC8349EMDS configuration was the basis for the sbc8349, so it also contains its SDRAM option.
Since * the SDRAM has to be soldered onto the board, * the sbc8349 never used the support, and * the support never worked (see previous patch fixing it),
we can assume that the support on the sbc8349 is an artifact created by copying the MPC8349EMDS config wholesome.
Hence, instead of creating a separate sbc8349 config that supports SDRAM, we can remove the SDRAM option for this board.
Should it be needed in the future, it can be copied from the new MPC8349EMDS_SDRAM board.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- include/configs/sbc8349.h | 67 --------------------------------------- 1 file changed, 67 deletions(-)
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 09cdb7c1a8a..42a1e1682d2 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -142,73 +142,6 @@
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
-#ifdef CONFIG_SYS_LB_SDRAM -/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ - | BR_PS_32 \ - | BR_MS_SDRAM \ - | BR_V) - /* 0xF0001861 */ -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 - */ - -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ - | OR_SDRAM_XAM \ - | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ - | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ - | OR_SDRAM_EAD) - /* 0xFC006901 */ - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ - | LSDMR_BSMA1516 \ - | LSDMR_RFCR8 \ - | LSDMR_PRETOACT6 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC3 \ - | LSDMR_CL3) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) -#endif - /* * Serial Port */
Migrate the BR/OR settings to Kconfig. These must be known at compile time, so cannot be configured via DT.
Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: No changes
--- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 1 + arch/powerpc/cpu/mpc83xx/elbc/Kconfig | 32 + arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 | 733 ++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 | 733 ++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 | 733 ++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 | 733 ++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 | 733 ++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/elbc/elbc.h | 186 +++++ arch/powerpc/cpu/mpc83xx/spl_minimal.c | 1 + arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 4 + board/freescale/mpc8349itx/mpc8349itx.c | 1 + configs/MPC8308RDB_defconfig | 38 + configs/MPC8313ERDB_33_defconfig | 50 ++ configs/MPC8313ERDB_66_defconfig | 50 ++ configs/MPC8313ERDB_NAND_33_defconfig | 50 ++ configs/MPC8313ERDB_NAND_66_defconfig | 50 ++ configs/MPC8315ERDB_defconfig | 27 + configs/MPC8323ERDB_defconfig | 14 + configs/MPC832XEMDS_ATM_defconfig | 53 ++ configs/MPC832XEMDS_HOST_33_defconfig | 53 ++ configs/MPC832XEMDS_HOST_66_defconfig | 53 ++ configs/MPC832XEMDS_SLAVE_defconfig | 53 ++ configs/MPC832XEMDS_defconfig | 53 ++ configs/MPC8349EMDS_PCI64_defconfig | 24 + configs/MPC8349EMDS_SDRAM_defconfig | 27 + configs/MPC8349EMDS_SLAVE_defconfig | 24 + configs/MPC8349EMDS_defconfig | 24 + configs/MPC8349ITXGP_defconfig | 47 ++ configs/MPC8349ITX_LOWBOOT_defconfig | 47 ++ configs/MPC8349ITX_defconfig | 47 ++ configs/MPC837XEMDS_HOST_defconfig | 41 ++ configs/MPC837XEMDS_SLAVE_defconfig | 41 ++ configs/MPC837XEMDS_defconfig | 41 ++ configs/MPC837XERDB_SLAVE_defconfig | 36 + configs/MPC837XERDB_defconfig | 36 + configs/TQM834x_defconfig | 10 + configs/caddy2_defconfig | 21 + configs/hrcon_defconfig | 26 + configs/hrcon_dh_defconfig | 26 + configs/ids8313_defconfig | 45 ++ configs/kmcoge5ne_defconfig | 42 ++ configs/kmeter1_defconfig | 32 + configs/kmopti2_defconfig | 42 ++ configs/kmsupx5_defconfig | 34 + configs/kmtegr1_defconfig | 30 + configs/kmtepr2_defconfig | 42 ++ configs/kmvect1_defconfig | 37 + configs/mpc8308_p1m_defconfig | 29 + configs/sbc8349_PCI_33_defconfig | 14 + configs/sbc8349_PCI_66_defconfig | 14 + configs/sbc8349_defconfig | 14 + configs/strider_con_defconfig | 23 + configs/strider_con_dp_defconfig | 23 + configs/strider_cpu_defconfig | 23 + configs/strider_cpu_dp_defconfig | 23 + configs/suvd3_defconfig | 37 + configs/tuge1_defconfig | 34 + configs/tuxx1_defconfig | 45 ++ configs/ve8313_defconfig | 45 ++ configs/vme8349_defconfig | 21 + drivers/mtd/nand/raw/fsl_elbc_spl.c | 4 + include/configs/MPC8308RDB.h | 9 - include/configs/MPC8313ERDB_NAND.h | 14 - include/configs/MPC8313ERDB_NOR.h | 14 - include/configs/MPC8315ERDB.h | 6 - include/configs/MPC8323ERDB.h | 3 - include/configs/MPC832XEMDS.h | 12 - include/configs/MPC8349EMDS.h | 6 - include/configs/MPC8349EMDS_SDRAM.h | 12 - include/configs/MPC8349ITX.h | 12 - include/configs/MPC837XEMDS.h | 9 - include/configs/MPC837XERDB.h | 9 - include/configs/TQM834x.h | 3 - include/configs/caddy2.h | 6 - include/configs/hrcon.h | 6 - include/configs/ids8313.h | 12 - include/configs/kmcoge5ne.h | 12 - include/configs/kmeter1.h | 9 - include/configs/kmopti2.h | 12 - include/configs/kmsupx5.h | 9 - include/configs/kmtegr1.h | 9 - include/configs/kmtepr2.h | 12 - include/configs/kmvect1.h | 12 - include/configs/mpc8308_p1m.h | 9 - include/configs/sbc8349.h | 3 - include/configs/strider.h | 6 - include/configs/suvd3.h | 12 - include/configs/tuge1.h | 9 - include/configs/tuxx1.h | 12 - include/configs/ve8313.h | 12 - include/configs/vme8349.h | 6 - 92 files changed, 5606 insertions(+), 277 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 create mode 100644 arch/powerpc/cpu/mpc83xx/elbc/elbc.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 8c84196b978..474572f245e 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -285,6 +285,7 @@ config ARCH_MPC837X source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig"
menu "Legacy options"
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 91451e7b304..5ce7b794b26 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -13,6 +13,7 @@ #endif
#include "lblaw/lblaw.h" +#include "elbc/elbc.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig new file mode 100644 index 00000000000..74c4ff3ed43 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig @@ -0,0 +1,32 @@ +menu "ELBC register setup" + +choice + prompt "OR/BR for NAND SPL" + +config ELBC_BR_OR_NAND_PRELIM_NONE + bool "None" + +config ELBC_BR_OR_NAND_PRELIM_0 + bool "0" + +config ELBC_BR_OR_NAND_PRELIM_1 + bool "1" + +config ELBC_BR_OR_NAND_PRELIM_2 + bool "2" + +config ELBC_BR_OR_NAND_PRELIM_3 + bool "3" + +config ELBC_BR_OR_NAND_PRELIM_4 + bool "4" + +endchoice + +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3" +source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4" + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 new file mode 100644 index 00000000000..23e81ab0bf9 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR0_OR0 + bool "ELBC BR0/OR0" + +if ELBC_BR0_OR0 + +config BR0_OR0_NAME + string "Identifier" + +config BR0_OR0_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR0_PORTSIZE_8BIT + bool "8-bit" + +config BR0_PORTSIZE_16BIT + depends on !BR0_MACHINE_FCM + bool "16-bit" + + +config BR0_PORTSIZE_32BIT + depends on !BR0_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR0_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR0_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR0_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR0_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR0_WRITE_PROTECT + bool "Write-protect" + +config BR0_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR0_MACHINE_GPCM + bool "GPCM" + +config BR0_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR0_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR0_MACHINE_UPMA + select BR0_MACHINE_UPM + bool "UPM (A)" + +config BR0_MACHINE_UPMB + select BR0_MACHINE_UPM + bool "UPM (B)" + +config BR0_MACHINE_UPMC + select BR0_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR0_ATOMIC_NONE + bool "No atomic operations" + +config BR0_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR0_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR0_MACHINE_GPCM || BR0_MACHINE_FCM || BR0_MACHINE_UPM || BR0_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR0_AM_32_KBYTES + depends on !BR0_MACHINE_SDRAM + bool "32 kb" + +config OR0_AM_64_KBYTES + bool "64 kb" + +config OR0_AM_128_KBYTES + bool "128 kb" + +config OR0_AM_256_KBYTES + bool "256 kb" + +config OR0_AM_512_KBYTES + bool "512 kb" + +config OR0_AM_1_MBYTES + bool "1 mb" + +config OR0_AM_2_MBYTES + bool "2 mb" + +config OR0_AM_4_MBYTES + bool "4 mb" + +config OR0_AM_8_MBYTES + bool "8 mb" + +config OR0_AM_16_MBYTES + bool "16 mb" + +config OR0_AM_32_MBYTES + bool "32 mb" + +config OR0_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR0_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR0_AM_256_MBYTES + bool "256 mb" + +config OR0_AM_512_MBYTES + depends on BR0_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR0_AM_1_GBYTES + bool "1 gb" + +config OR0_AM_2_GBYTES + depends on BR0_MACHINE_FCM + bool "2 gb" + +config OR0_AM_4_GBYTES + depends on BR0_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR0_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR0_BCTLD_ASSERTED + bool "Asserted" + +config OR0_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR0_MACHINE_GPCM || BR0_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR0_SCY_0 + bool "No wait states" + +config OR0_SCY_1 + bool "1 wait state" + +config OR0_SCY_2 + bool "2 wait states" + +config OR0_SCY_3 + bool "3 wait states" + +config OR0_SCY_4 + bool "4 wait states" + +config OR0_SCY_5 + bool "5 wait states" + +config OR0_SCY_6 + bool "6 wait states" + +config OR0_SCY_7 + bool "7 wait states" + +config OR0_SCY_8 + depends on BR0_MACHINE_GPCM + bool "8 wait states" + +config OR0_SCY_9 + depends on BR0_MACHINE_GPCM + bool "9 wait states" + +config OR0_SCY_10 + depends on BR0_MACHINE_GPCM + bool "10 wait states" + +config OR0_SCY_11 + depends on BR0_MACHINE_GPCM + bool "11 wait states" + +config OR0_SCY_12 + depends on BR0_MACHINE_GPCM + bool "12 wait states" + +config OR0_SCY_13 + depends on BR0_MACHINE_GPCM + bool "13 wait states" + +config OR0_SCY_14 + depends on BR0_MACHINE_GPCM + bool "14 wait states" + +config OR0_SCY_15 + depends on BR0_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR0_MACHINE_GPCM || BR0_MACHINE_FCM + +if BR0_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR0_CSNT_NORMAL + bool "Normal" + +config OR0_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR0_ACS_SAME_TIME + bool "At the same time" + +config OR0_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR0_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR0_XACS_NORMAL + bool "Normal" + +config OR0_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR0_SETA_INTERNAL + bool "Access is terminated internally" + +config OR0_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR0_MACHINE_GPCM + +if BR0_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR0_PGS_SMALL + bool "Small page device" + +config OR0_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR0_CSCT_1_CYCLE + depends on OR0_TRLX_NORMAL + bool "1 cycle" + +config OR0_CSCT_2_CYCLE + depends on OR0_TRLX_RELAXED + bool "2 cycles" + +config OR0_CSCT_4_CYCLE + depends on OR0_TRLX_NORMAL + bool "4 cycles" + +config OR0_CSCT_8_CYCLE + depends on OR0_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR0_CST_COINCIDENT + depends on OR0_TRLX_NORMAL + bool "Coincident with any command" + +config OR0_CST_QUARTER_CLOCK + depends on OR0_TRLX_NORMAL + bool "0.25 clocks after" + +config OR0_CST_HALF_CLOCK + depends on OR0_TRLX_RELAXED + bool "0.5 clocks after" + +config OR0_CST_ONE_CLOCK + depends on OR0_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR0_CHT_HALF_CLOCK + depends on OR0_TRLX_NORMAL + bool "0.5 clocks before" + +config OR0_CHT_ONE_CLOCK + depends on OR0_TRLX_NORMAL + bool "1 clock before" + +config OR0_CHT_ONE_HALF_CLOCK + depends on OR0_TRLX_RELAXED + bool "1.5 clocks before" + +config OR0_CHT_TWO_CLOCK + depends on OR0_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR0_RST_THREE_QUARTER_CLOCK + depends on OR0_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR0_RST_ONE_HALF_CLOCK + depends on OR0_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR0_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR0_MACHINE_FCM + +if BR0_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR0_BI_BURSTSUPPORT + bool "Support burst access" + +config OR0_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR0_MACHINE_UPM + +if BR0_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR0_COLS_7 + bool "7" + +config OR0_COLS_8 + bool "8" + +config OR0_COLS_9 + bool "9" + +config OR0_COLS_10 + bool "10" + +config OR0_COLS_11 + bool "11" + +config OR0_COLS_12 + bool "12" + +config OR0_COLS_13 + bool "13" + +config OR0_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR0_ROWS_9 + bool "9" + +config OR0_ROWS_10 + bool "10" + +config OR0_ROWS_11 + bool "11" + +config OR0_ROWS_12 + bool "12" + +config OR0_ROWS_13 + bool "13" + +config OR0_ROWS_14 + bool "14" + +config OR0_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR0_PMSEL_BTB + bool "Back-to-back" + +config OR0_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR0_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR0_TRLX_NORMAL + bool "Normal" + +config OR0_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR0_EHTR_NORMAL + depends on OR0_TRLX_NORMAL + bool "Normal" + +config OR0_EHTR_1_CYCLE + depends on OR0_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR0_EHTR_4_CYCLE + depends on OR0_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR0_EHTR_8_CYCLE + depends on OR0_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR0_EAD_NONE + bool "None" + +config OR0_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR0_OR0 + +config BR0_PORTSIZE + hex + default 0x800 if BR0_PORTSIZE_8BIT + default 0x1000 if BR0_PORTSIZE_16BIT + default 0x1800 if BR0_PORTSIZE_32BIT + +config BR0_ERRORCHECKING + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if BR0_ERRORCHECKING_DISABLED + default 0x200 if BR0_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR0_ERRORCHECKING_BOTH + +config BR0_WRITE_PROTECT_BIT + hex + default 0x0 if !BR0_WRITE_PROTECT + default 0x100 if BR0_WRITE_PROTECT + +config BR0_MACHINE + hex + default 0x0 if BR0_MACHINE_GPCM + default 0x20 if BR0_MACHINE_FCM + default 0x60 if BR0_MACHINE_SDRAM + default 0x80 if BR0_MACHINE_UPMA + default 0xa0 if BR0_MACHINE_UPMB + default 0xc0 if BR0_MACHINE_UPMC + +config BR0_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR0_ATOMIC_NONE + default 0x4 if BR0_ATOMIC_RAWA + default 0x8 if BR0_ATOMIC_WARA + +config BR0_VALID_BIT + hex + default 0x0 if !ELBC_BR0_OR0 + default 0x1 if ELBC_BR0_OR0 + +config OR0_AM + hex + default 0xffff8000 if OR0_AM_32_KBYTES && !BR0_MACHINE_SDRAM + default 0xffff0000 if OR0_AM_64_KBYTES + default 0xfffe0000 if OR0_AM_128_KBYTES + default 0xfffc0000 if OR0_AM_256_KBYTES + default 0xfff80000 if OR0_AM_512_KBYTES + default 0xfff00000 if OR0_AM_1_MBYTES + default 0xffe00000 if OR0_AM_2_MBYTES + default 0xffc00000 if OR0_AM_4_MBYTES + default 0xff800000 if OR0_AM_8_MBYTES + default 0xff000000 if OR0_AM_16_MBYTES + default 0xfe000000 if OR0_AM_32_MBYTES + default 0xfc000000 if OR0_AM_64_MBYTES + default 0xf8000000 if OR0_AM_128_MBYTES + default 0xf0000000 if OR0_AM_256_MBYTES + default 0xe0000000 if OR0_AM_512_MBYTES + default 0xc0000000 if OR0_AM_1_GBYTES + default 0x80000000 if OR0_AM_2_GBYTES + default 0x00000000 if OR0_AM_4_GBYTES + +config OR0_XAM + hex + default 0x0 if !OR0_XAM_SET + default 0x6000 if OR0_XAM_SET + +config OR0_BCTLD + hex + default 0x0 if OR0_BCTLD_ASSERTED + default 0x1000 if OR0_BCTLD_NOT_ASSERTED + +config OR0_BI + hex + default 0x0 if !BR0_MACHINE_UPM + default 0x0 if OR0_BI_BURSTSUPPORT + default 0x100 if OR0_BI_BURSTINHIBIT + +config OR0_COLS + hex + default 0x0 if !BR0_MACHINE_SDRAM + default 0x0 if OR0_COLS_7 + default 0x400 if OR0_COLS_8 + default 0x800 if OR0_COLS_9 + default 0xc00 if OR0_COLS_10 + default 0x1000 if OR0_COLS_11 + default 0x1400 if OR0_COLS_12 + default 0x1800 if OR0_COLS_13 + default 0x1c00 if OR0_COLS_14 + +config OR0_ROWS + hex + default 0x0 if !BR0_MACHINE_SDRAM + default 0x0 if OR0_ROWS_9 + default 0x40 if OR0_ROWS_10 + default 0x80 if OR0_ROWS_11 + default 0xc0 if OR0_ROWS_12 + default 0x100 if OR0_ROWS_13 + default 0x140 if OR0_ROWS_14 + default 0x180 if OR0_ROWS_15 + +config OR0_PMSEL + hex + default 0x0 if !BR0_MACHINE_SDRAM + default 0x0 if OR0_PMSEL_BTB + default 0x20 if OR0_PMSEL_KEPT_OPEN + +config OR0_SCY + hex + default 0x0 if !BR0_MACHINE_GPCM && !BR0_MACHINE_FCM + default 0x0 if OR0_SCY_0 + default 0x10 if OR0_SCY_1 + default 0x20 if OR0_SCY_2 + default 0x30 if OR0_SCY_3 + default 0x40 if OR0_SCY_4 + default 0x50 if OR0_SCY_5 + default 0x60 if OR0_SCY_6 + default 0x70 if OR0_SCY_7 + default 0x80 if OR0_SCY_8 + default 0x90 if OR0_SCY_9 + default 0xa0 if OR0_SCY_10 + default 0xb0 if OR0_SCY_11 + default 0xc0 if OR0_SCY_12 + default 0xd0 if OR0_SCY_13 + default 0xe0 if OR0_SCY_14 + default 0xf0 if OR0_SCY_15 + +config OR0_PGS + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_PGS_SMALL + default 0x400 if OR0_PGS_LARGE + +config OR0_CSCT + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_CSCT_1_CYCLE + default 0x0 if OR0_CSCT_2_CYCLE + default 0x200 if OR0_CSCT_4_CYCLE + default 0x200 if OR0_CSCT_8_CYCLE + +config OR0_CST + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_CST_COINCIDENT + default 0x100 if OR0_CST_QUARTER_CLOCK + default 0x0 if OR0_CST_HALF_CLOCK + default 0x100 if OR0_CST_ONE_CLOCK + +config OR0_CHT + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_CHT_HALF_CLOCK + default 0x80 if OR0_CHT_ONE_CLOCK + default 0x0 if OR0_CHT_ONE_HALF_CLOCK + default 0x80 if OR0_CHT_TWO_CLOCK + +config OR0_RST + hex + default 0x0 if !BR0_MACHINE_FCM + default 0x0 if OR0_RST_THREE_QUARTER_CLOCK + default 0x8 if OR0_RST_ONE_CLOCK + default 0x0 if OR0_RST_ONE_HALF_CLOCK + +config OR0_CSNT + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_CSNT_NORMAL + default 0x800 if OR0_CSNT_EARLIER + +config OR0_ACS + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_ACS_SAME_TIME + default 0x400 if OR0_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR0_ACS_HALF_CYCLE_EARLIER + +config OR0_XACS + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_XACS_NORMAL + default 0x100 if OR0_XACS_EXTENDED + +config OR0_SETA + hex + default 0x0 if !BR0_MACHINE_GPCM + default 0x0 if OR0_SETA_INTERNAL + default 0x8 if OR0_SETA_EXTERNAL + +config OR0_TRLX + hex + default 0x0 if OR0_TRLX_NORMAL + default 0x4 if OR0_TRLX_RELAXED + +config OR0_EHTR + hex + default 0x0 if OR0_EHTR_NORMAL + default 0x2 if OR0_EHTR_1_CYCLE + default 0x0 if OR0_EHTR_4_CYCLE + default 0x2 if OR0_EHTR_8_CYCLE + +config OR0_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR0_EAD_NONE + default 0x1 if OR0_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 new file mode 100644 index 00000000000..08dcc7dd2ba --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR1_OR1 + bool "ELBC BR1/OR1" + +if ELBC_BR1_OR1 + +config BR1_OR1_NAME + string "Identifier" + +config BR1_OR1_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR1_PORTSIZE_8BIT + bool "8-bit" + +config BR1_PORTSIZE_16BIT + depends on !BR1_MACHINE_FCM + bool "16-bit" + + +config BR1_PORTSIZE_32BIT + depends on !BR1_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR1_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR1_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR1_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR1_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR1_WRITE_PROTECT + bool "Write-protect" + +config BR1_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR1_MACHINE_GPCM + bool "GPCM" + +config BR1_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR1_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR1_MACHINE_UPMA + select BR1_MACHINE_UPM + bool "UPM (A)" + +config BR1_MACHINE_UPMB + select BR1_MACHINE_UPM + bool "UPM (B)" + +config BR1_MACHINE_UPMC + select BR1_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR1_ATOMIC_NONE + bool "No atomic operations" + +config BR1_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR1_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR1_MACHINE_GPCM || BR1_MACHINE_FCM || BR1_MACHINE_UPM || BR1_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR1_AM_32_KBYTES + depends on !BR1_MACHINE_SDRAM + bool "32 kb" + +config OR1_AM_64_KBYTES + bool "64 kb" + +config OR1_AM_128_KBYTES + bool "128 kb" + +config OR1_AM_256_KBYTES + bool "256 kb" + +config OR1_AM_512_KBYTES + bool "512 kb" + +config OR1_AM_1_MBYTES + bool "1 mb" + +config OR1_AM_2_MBYTES + bool "2 mb" + +config OR1_AM_4_MBYTES + bool "4 mb" + +config OR1_AM_8_MBYTES + bool "8 mb" + +config OR1_AM_16_MBYTES + bool "16 mb" + +config OR1_AM_32_MBYTES + bool "32 mb" + +config OR1_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR1_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR1_AM_256_MBYTES + bool "256 mb" + +config OR1_AM_512_MBYTES + depends on BR1_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR1_AM_1_GBYTES + bool "1 gb" + +config OR1_AM_2_GBYTES + depends on BR1_MACHINE_FCM + bool "2 gb" + +config OR1_AM_4_GBYTES + depends on BR1_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR1_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR1_BCTLD_ASSERTED + bool "Asserted" + +config OR1_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR1_MACHINE_GPCM || BR1_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR1_SCY_0 + bool "No wait states" + +config OR1_SCY_1 + bool "1 wait state" + +config OR1_SCY_2 + bool "2 wait states" + +config OR1_SCY_3 + bool "3 wait states" + +config OR1_SCY_4 + bool "4 wait states" + +config OR1_SCY_5 + bool "5 wait states" + +config OR1_SCY_6 + bool "6 wait states" + +config OR1_SCY_7 + bool "7 wait states" + +config OR1_SCY_8 + depends on BR1_MACHINE_GPCM + bool "8 wait states" + +config OR1_SCY_9 + depends on BR1_MACHINE_GPCM + bool "9 wait states" + +config OR1_SCY_10 + depends on BR1_MACHINE_GPCM + bool "10 wait states" + +config OR1_SCY_11 + depends on BR1_MACHINE_GPCM + bool "11 wait states" + +config OR1_SCY_12 + depends on BR1_MACHINE_GPCM + bool "12 wait states" + +config OR1_SCY_13 + depends on BR1_MACHINE_GPCM + bool "13 wait states" + +config OR1_SCY_14 + depends on BR1_MACHINE_GPCM + bool "14 wait states" + +config OR1_SCY_15 + depends on BR1_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR1_MACHINE_GPCM || BR1_MACHINE_FCM + +if BR1_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR1_CSNT_NORMAL + bool "Normal" + +config OR1_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR1_ACS_SAME_TIME + bool "At the same time" + +config OR1_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR1_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR1_XACS_NORMAL + bool "Normal" + +config OR1_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR1_SETA_INTERNAL + bool "Access is terminated internally" + +config OR1_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR1_MACHINE_GPCM + +if BR1_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR1_PGS_SMALL + bool "Small page device" + +config OR1_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR1_CSCT_1_CYCLE + depends on OR1_TRLX_NORMAL + bool "1 cycle" + +config OR1_CSCT_2_CYCLE + depends on OR1_TRLX_RELAXED + bool "2 cycles" + +config OR1_CSCT_4_CYCLE + depends on OR1_TRLX_NORMAL + bool "4 cycles" + +config OR1_CSCT_8_CYCLE + depends on OR1_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR1_CST_COINCIDENT + depends on OR1_TRLX_NORMAL + bool "Coincident with any command" + +config OR1_CST_QUARTER_CLOCK + depends on OR1_TRLX_NORMAL + bool "0.25 clocks after" + +config OR1_CST_HALF_CLOCK + depends on OR1_TRLX_RELAXED + bool "0.5 clocks after" + +config OR1_CST_ONE_CLOCK + depends on OR1_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR1_CHT_HALF_CLOCK + depends on OR1_TRLX_NORMAL + bool "0.5 clocks before" + +config OR1_CHT_ONE_CLOCK + depends on OR1_TRLX_NORMAL + bool "1 clock before" + +config OR1_CHT_ONE_HALF_CLOCK + depends on OR1_TRLX_RELAXED + bool "1.5 clocks before" + +config OR1_CHT_TWO_CLOCK + depends on OR1_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR1_RST_THREE_QUARTER_CLOCK + depends on OR1_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR1_RST_ONE_HALF_CLOCK + depends on OR1_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR1_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR1_MACHINE_FCM + +if BR1_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR1_BI_BURSTSUPPORT + bool "Support burst access" + +config OR1_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR1_MACHINE_UPM + +if BR1_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR1_COLS_7 + bool "7" + +config OR1_COLS_8 + bool "8" + +config OR1_COLS_9 + bool "9" + +config OR1_COLS_10 + bool "10" + +config OR1_COLS_11 + bool "11" + +config OR1_COLS_12 + bool "12" + +config OR1_COLS_13 + bool "13" + +config OR1_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR1_ROWS_9 + bool "9" + +config OR1_ROWS_10 + bool "10" + +config OR1_ROWS_11 + bool "11" + +config OR1_ROWS_12 + bool "12" + +config OR1_ROWS_13 + bool "13" + +config OR1_ROWS_14 + bool "14" + +config OR1_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR1_PMSEL_BTB + bool "Back-to-back" + +config OR1_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR1_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR1_TRLX_NORMAL + bool "Normal" + +config OR1_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR1_EHTR_NORMAL + depends on OR1_TRLX_NORMAL + bool "Normal" + +config OR1_EHTR_1_CYCLE + depends on OR1_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR1_EHTR_4_CYCLE + depends on OR1_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR1_EHTR_8_CYCLE + depends on OR1_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR1_EAD_NONE + bool "None" + +config OR1_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR1_OR1 + +config BR1_PORTSIZE + hex + default 0x800 if BR1_PORTSIZE_8BIT + default 0x1000 if BR1_PORTSIZE_16BIT + default 0x1800 if BR1_PORTSIZE_32BIT + +config BR1_ERRORCHECKING + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if BR1_ERRORCHECKING_DISABLED + default 0x200 if BR1_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR1_ERRORCHECKING_BOTH + +config BR1_WRITE_PROTECT_BIT + hex + default 0x0 if !BR1_WRITE_PROTECT + default 0x100 if BR1_WRITE_PROTECT + +config BR1_MACHINE + hex + default 0x0 if BR1_MACHINE_GPCM + default 0x20 if BR1_MACHINE_FCM + default 0x60 if BR1_MACHINE_SDRAM + default 0x80 if BR1_MACHINE_UPMA + default 0xa0 if BR1_MACHINE_UPMB + default 0xc0 if BR1_MACHINE_UPMC + +config BR1_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR1_ATOMIC_NONE + default 0x4 if BR1_ATOMIC_RAWA + default 0x8 if BR1_ATOMIC_WARA + +config BR1_VALID_BIT + hex + default 0x0 if !ELBC_BR1_OR1 + default 0x1 if ELBC_BR1_OR1 + +config OR1_AM + hex + default 0xffff8000 if OR1_AM_32_KBYTES && !BR1_MACHINE_SDRAM + default 0xffff0000 if OR1_AM_64_KBYTES + default 0xfffe0000 if OR1_AM_128_KBYTES + default 0xfffc0000 if OR1_AM_256_KBYTES + default 0xfff80000 if OR1_AM_512_KBYTES + default 0xfff00000 if OR1_AM_1_MBYTES + default 0xffe00000 if OR1_AM_2_MBYTES + default 0xffc00000 if OR1_AM_4_MBYTES + default 0xff800000 if OR1_AM_8_MBYTES + default 0xff000000 if OR1_AM_16_MBYTES + default 0xfe000000 if OR1_AM_32_MBYTES + default 0xfc000000 if OR1_AM_64_MBYTES + default 0xf8000000 if OR1_AM_128_MBYTES + default 0xf0000000 if OR1_AM_256_MBYTES + default 0xe0000000 if OR1_AM_512_MBYTES + default 0xc0000000 if OR1_AM_1_GBYTES + default 0x80000000 if OR1_AM_2_GBYTES + default 0x00000000 if OR1_AM_4_GBYTES + +config OR1_XAM + hex + default 0x0 if !OR1_XAM_SET + default 0x6000 if OR1_XAM_SET + +config OR1_BCTLD + hex + default 0x0 if OR1_BCTLD_ASSERTED + default 0x1000 if OR1_BCTLD_NOT_ASSERTED + +config OR1_BI + hex + default 0x0 if !BR1_MACHINE_UPM + default 0x0 if OR1_BI_BURSTSUPPORT + default 0x100 if OR1_BI_BURSTINHIBIT + +config OR1_COLS + hex + default 0x0 if !BR1_MACHINE_SDRAM + default 0x0 if OR1_COLS_7 + default 0x400 if OR1_COLS_8 + default 0x800 if OR1_COLS_9 + default 0xc00 if OR1_COLS_10 + default 0x1000 if OR1_COLS_11 + default 0x1400 if OR1_COLS_12 + default 0x1800 if OR1_COLS_13 + default 0x1c00 if OR1_COLS_14 + +config OR1_ROWS + hex + default 0x0 if !BR1_MACHINE_SDRAM + default 0x0 if OR1_ROWS_9 + default 0x40 if OR1_ROWS_10 + default 0x80 if OR1_ROWS_11 + default 0xc0 if OR1_ROWS_12 + default 0x100 if OR1_ROWS_13 + default 0x140 if OR1_ROWS_14 + default 0x180 if OR1_ROWS_15 + +config OR1_PMSEL + hex + default 0x0 if !BR1_MACHINE_SDRAM + default 0x0 if OR1_PMSEL_BTB + default 0x20 if OR1_PMSEL_KEPT_OPEN + +config OR1_SCY + hex + default 0x0 if !BR1_MACHINE_GPCM && !BR1_MACHINE_FCM + default 0x0 if OR1_SCY_0 + default 0x10 if OR1_SCY_1 + default 0x20 if OR1_SCY_2 + default 0x30 if OR1_SCY_3 + default 0x40 if OR1_SCY_4 + default 0x50 if OR1_SCY_5 + default 0x60 if OR1_SCY_6 + default 0x70 if OR1_SCY_7 + default 0x80 if OR1_SCY_8 + default 0x90 if OR1_SCY_9 + default 0xa0 if OR1_SCY_10 + default 0xb0 if OR1_SCY_11 + default 0xc0 if OR1_SCY_12 + default 0xd0 if OR1_SCY_13 + default 0xe0 if OR1_SCY_14 + default 0xf0 if OR1_SCY_15 + +config OR1_PGS + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_PGS_SMALL + default 0x400 if OR1_PGS_LARGE + +config OR1_CSCT + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_CSCT_1_CYCLE + default 0x0 if OR1_CSCT_2_CYCLE + default 0x200 if OR1_CSCT_4_CYCLE + default 0x200 if OR1_CSCT_8_CYCLE + +config OR1_CST + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_CST_COINCIDENT + default 0x100 if OR1_CST_QUARTER_CLOCK + default 0x0 if OR1_CST_HALF_CLOCK + default 0x100 if OR1_CST_ONE_CLOCK + +config OR1_CHT + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_CHT_HALF_CLOCK + default 0x80 if OR1_CHT_ONE_CLOCK + default 0x0 if OR1_CHT_ONE_HALF_CLOCK + default 0x80 if OR1_CHT_TWO_CLOCK + +config OR1_RST + hex + default 0x0 if !BR1_MACHINE_FCM + default 0x0 if OR1_RST_THREE_QUARTER_CLOCK + default 0x8 if OR1_RST_ONE_CLOCK + default 0x0 if OR1_RST_ONE_HALF_CLOCK + +config OR1_CSNT + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_CSNT_NORMAL + default 0x800 if OR1_CSNT_EARLIER + +config OR1_ACS + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_ACS_SAME_TIME + default 0x400 if OR1_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR1_ACS_HALF_CYCLE_EARLIER + +config OR1_XACS + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_XACS_NORMAL + default 0x100 if OR1_XACS_EXTENDED + +config OR1_SETA + hex + default 0x0 if !BR1_MACHINE_GPCM + default 0x0 if OR1_SETA_INTERNAL + default 0x8 if OR1_SETA_EXTERNAL + +config OR1_TRLX + hex + default 0x0 if OR1_TRLX_NORMAL + default 0x4 if OR1_TRLX_RELAXED + +config OR1_EHTR + hex + default 0x0 if OR1_EHTR_NORMAL + default 0x2 if OR1_EHTR_1_CYCLE + default 0x0 if OR1_EHTR_4_CYCLE + default 0x2 if OR1_EHTR_8_CYCLE + +config OR1_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR1_EAD_NONE + default 0x1 if OR1_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 new file mode 100644 index 00000000000..298d87f5e0f --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR2_OR2 + bool "ELBC BR2/OR2" + +if ELBC_BR2_OR2 + +config BR2_OR2_NAME + string "Identifier" + +config BR2_OR2_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR2_PORTSIZE_8BIT + bool "8-bit" + +config BR2_PORTSIZE_16BIT + depends on !BR2_MACHINE_FCM + bool "16-bit" + + +config BR2_PORTSIZE_32BIT + depends on !BR2_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR2_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR2_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR2_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR2_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR2_WRITE_PROTECT + bool "Write-protect" + +config BR2_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR2_MACHINE_GPCM + bool "GPCM" + +config BR2_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR2_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR2_MACHINE_UPMA + select BR2_MACHINE_UPM + bool "UPM (A)" + +config BR2_MACHINE_UPMB + select BR2_MACHINE_UPM + bool "UPM (B)" + +config BR2_MACHINE_UPMC + select BR2_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR2_ATOMIC_NONE + bool "No atomic operations" + +config BR2_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR2_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR2_MACHINE_GPCM || BR2_MACHINE_FCM || BR2_MACHINE_UPM || BR2_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR2_AM_32_KBYTES + depends on !BR2_MACHINE_SDRAM + bool "32 kb" + +config OR2_AM_64_KBYTES + bool "64 kb" + +config OR2_AM_128_KBYTES + bool "128 kb" + +config OR2_AM_256_KBYTES + bool "256 kb" + +config OR2_AM_512_KBYTES + bool "512 kb" + +config OR2_AM_1_MBYTES + bool "1 mb" + +config OR2_AM_2_MBYTES + bool "2 mb" + +config OR2_AM_4_MBYTES + bool "4 mb" + +config OR2_AM_8_MBYTES + bool "8 mb" + +config OR2_AM_16_MBYTES + bool "16 mb" + +config OR2_AM_32_MBYTES + bool "32 mb" + +config OR2_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR2_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR2_AM_256_MBYTES + bool "256 mb" + +config OR2_AM_512_MBYTES + depends on BR2_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR2_AM_1_GBYTES + bool "1 gb" + +config OR2_AM_2_GBYTES + depends on BR2_MACHINE_FCM + bool "2 gb" + +config OR2_AM_4_GBYTES + depends on BR2_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR2_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR2_BCTLD_ASSERTED + bool "Asserted" + +config OR2_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR2_MACHINE_GPCM || BR2_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR2_SCY_0 + bool "No wait states" + +config OR2_SCY_1 + bool "1 wait state" + +config OR2_SCY_2 + bool "2 wait states" + +config OR2_SCY_3 + bool "3 wait states" + +config OR2_SCY_4 + bool "4 wait states" + +config OR2_SCY_5 + bool "5 wait states" + +config OR2_SCY_6 + bool "6 wait states" + +config OR2_SCY_7 + bool "7 wait states" + +config OR2_SCY_8 + depends on BR2_MACHINE_GPCM + bool "8 wait states" + +config OR2_SCY_9 + depends on BR2_MACHINE_GPCM + bool "9 wait states" + +config OR2_SCY_10 + depends on BR2_MACHINE_GPCM + bool "10 wait states" + +config OR2_SCY_11 + depends on BR2_MACHINE_GPCM + bool "11 wait states" + +config OR2_SCY_12 + depends on BR2_MACHINE_GPCM + bool "12 wait states" + +config OR2_SCY_13 + depends on BR2_MACHINE_GPCM + bool "13 wait states" + +config OR2_SCY_14 + depends on BR2_MACHINE_GPCM + bool "14 wait states" + +config OR2_SCY_15 + depends on BR2_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR2_MACHINE_GPCM || BR2_MACHINE_FCM + +if BR2_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR2_CSNT_NORMAL + bool "Normal" + +config OR2_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR2_ACS_SAME_TIME + bool "At the same time" + +config OR2_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR2_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR2_XACS_NORMAL + bool "Normal" + +config OR2_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR2_SETA_INTERNAL + bool "Access is terminated internally" + +config OR2_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR2_MACHINE_GPCM + +if BR2_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR2_PGS_SMALL + bool "Small page device" + +config OR2_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR2_CSCT_1_CYCLE + depends on OR2_TRLX_NORMAL + bool "1 cycle" + +config OR2_CSCT_2_CYCLE + depends on OR2_TRLX_RELAXED + bool "2 cycles" + +config OR2_CSCT_4_CYCLE + depends on OR2_TRLX_NORMAL + bool "4 cycles" + +config OR2_CSCT_8_CYCLE + depends on OR2_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR2_CST_COINCIDENT + depends on OR2_TRLX_NORMAL + bool "Coincident with any command" + +config OR2_CST_QUARTER_CLOCK + depends on OR2_TRLX_NORMAL + bool "0.25 clocks after" + +config OR2_CST_HALF_CLOCK + depends on OR2_TRLX_RELAXED + bool "0.5 clocks after" + +config OR2_CST_ONE_CLOCK + depends on OR2_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR2_CHT_HALF_CLOCK + depends on OR2_TRLX_NORMAL + bool "0.5 clocks before" + +config OR2_CHT_ONE_CLOCK + depends on OR2_TRLX_NORMAL + bool "1 clock before" + +config OR2_CHT_ONE_HALF_CLOCK + depends on OR2_TRLX_RELAXED + bool "1.5 clocks before" + +config OR2_CHT_TWO_CLOCK + depends on OR2_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR2_RST_THREE_QUARTER_CLOCK + depends on OR2_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR2_RST_ONE_HALF_CLOCK + depends on OR2_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR2_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR2_MACHINE_FCM + +if BR2_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR2_BI_BURSTSUPPORT + bool "Support burst access" + +config OR2_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR2_MACHINE_UPM + +if BR2_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR2_COLS_7 + bool "7" + +config OR2_COLS_8 + bool "8" + +config OR2_COLS_9 + bool "9" + +config OR2_COLS_10 + bool "10" + +config OR2_COLS_11 + bool "11" + +config OR2_COLS_12 + bool "12" + +config OR2_COLS_13 + bool "13" + +config OR2_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR2_ROWS_9 + bool "9" + +config OR2_ROWS_10 + bool "10" + +config OR2_ROWS_11 + bool "11" + +config OR2_ROWS_12 + bool "12" + +config OR2_ROWS_13 + bool "13" + +config OR2_ROWS_14 + bool "14" + +config OR2_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR2_PMSEL_BTB + bool "Back-to-back" + +config OR2_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR2_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR2_TRLX_NORMAL + bool "Normal" + +config OR2_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR2_EHTR_NORMAL + depends on OR2_TRLX_NORMAL + bool "Normal" + +config OR2_EHTR_1_CYCLE + depends on OR2_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR2_EHTR_4_CYCLE + depends on OR2_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR2_EHTR_8_CYCLE + depends on OR2_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR2_EAD_NONE + bool "None" + +config OR2_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR2_OR2 + +config BR2_PORTSIZE + hex + default 0x800 if BR2_PORTSIZE_8BIT + default 0x1000 if BR2_PORTSIZE_16BIT + default 0x1800 if BR2_PORTSIZE_32BIT + +config BR2_ERRORCHECKING + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if BR2_ERRORCHECKING_DISABLED + default 0x200 if BR2_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR2_ERRORCHECKING_BOTH + +config BR2_WRITE_PROTECT_BIT + hex + default 0x0 if !BR2_WRITE_PROTECT + default 0x100 if BR2_WRITE_PROTECT + +config BR2_MACHINE + hex + default 0x0 if BR2_MACHINE_GPCM + default 0x20 if BR2_MACHINE_FCM + default 0x60 if BR2_MACHINE_SDRAM + default 0x80 if BR2_MACHINE_UPMA + default 0xa0 if BR2_MACHINE_UPMB + default 0xc0 if BR2_MACHINE_UPMC + +config BR2_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR2_ATOMIC_NONE + default 0x4 if BR2_ATOMIC_RAWA + default 0x8 if BR2_ATOMIC_WARA + +config BR2_VALID_BIT + hex + default 0x0 if !ELBC_BR2_OR2 + default 0x1 if ELBC_BR2_OR2 + +config OR2_AM + hex + default 0xffff8000 if OR2_AM_32_KBYTES && !BR2_MACHINE_SDRAM + default 0xffff0000 if OR2_AM_64_KBYTES + default 0xfffe0000 if OR2_AM_128_KBYTES + default 0xfffc0000 if OR2_AM_256_KBYTES + default 0xfff80000 if OR2_AM_512_KBYTES + default 0xfff00000 if OR2_AM_1_MBYTES + default 0xffe00000 if OR2_AM_2_MBYTES + default 0xffc00000 if OR2_AM_4_MBYTES + default 0xff800000 if OR2_AM_8_MBYTES + default 0xff000000 if OR2_AM_16_MBYTES + default 0xfe000000 if OR2_AM_32_MBYTES + default 0xfc000000 if OR2_AM_64_MBYTES + default 0xf8000000 if OR2_AM_128_MBYTES + default 0xf0000000 if OR2_AM_256_MBYTES + default 0xe0000000 if OR2_AM_512_MBYTES + default 0xc0000000 if OR2_AM_1_GBYTES + default 0x80000000 if OR2_AM_2_GBYTES + default 0x00000000 if OR2_AM_4_GBYTES + +config OR2_XAM + hex + default 0x0 if !OR2_XAM_SET + default 0x6000 if OR2_XAM_SET + +config OR2_BCTLD + hex + default 0x0 if OR2_BCTLD_ASSERTED + default 0x1000 if OR2_BCTLD_NOT_ASSERTED + +config OR2_BI + hex + default 0x0 if !BR2_MACHINE_UPM + default 0x0 if OR2_BI_BURSTSUPPORT + default 0x100 if OR2_BI_BURSTINHIBIT + +config OR2_COLS + hex + default 0x0 if !BR2_MACHINE_SDRAM + default 0x0 if OR2_COLS_7 + default 0x400 if OR2_COLS_8 + default 0x800 if OR2_COLS_9 + default 0xc00 if OR2_COLS_10 + default 0x1000 if OR2_COLS_11 + default 0x1400 if OR2_COLS_12 + default 0x1800 if OR2_COLS_13 + default 0x1c00 if OR2_COLS_14 + +config OR2_ROWS + hex + default 0x0 if !BR2_MACHINE_SDRAM + default 0x0 if OR2_ROWS_9 + default 0x40 if OR2_ROWS_10 + default 0x80 if OR2_ROWS_11 + default 0xc0 if OR2_ROWS_12 + default 0x100 if OR2_ROWS_13 + default 0x140 if OR2_ROWS_14 + default 0x180 if OR2_ROWS_15 + +config OR2_PMSEL + hex + default 0x0 if !BR2_MACHINE_SDRAM + default 0x0 if OR2_PMSEL_BTB + default 0x20 if OR2_PMSEL_KEPT_OPEN + +config OR2_SCY + hex + default 0x0 if !BR2_MACHINE_GPCM && !BR2_MACHINE_FCM + default 0x0 if OR2_SCY_0 + default 0x10 if OR2_SCY_1 + default 0x20 if OR2_SCY_2 + default 0x30 if OR2_SCY_3 + default 0x40 if OR2_SCY_4 + default 0x50 if OR2_SCY_5 + default 0x60 if OR2_SCY_6 + default 0x70 if OR2_SCY_7 + default 0x80 if OR2_SCY_8 + default 0x90 if OR2_SCY_9 + default 0xa0 if OR2_SCY_10 + default 0xb0 if OR2_SCY_11 + default 0xc0 if OR2_SCY_12 + default 0xd0 if OR2_SCY_13 + default 0xe0 if OR2_SCY_14 + default 0xf0 if OR2_SCY_15 + +config OR2_PGS + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_PGS_SMALL + default 0x400 if OR2_PGS_LARGE + +config OR2_CSCT + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_CSCT_1_CYCLE + default 0x0 if OR2_CSCT_2_CYCLE + default 0x200 if OR2_CSCT_4_CYCLE + default 0x200 if OR2_CSCT_8_CYCLE + +config OR2_CST + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_CST_COINCIDENT + default 0x100 if OR2_CST_QUARTER_CLOCK + default 0x0 if OR2_CST_HALF_CLOCK + default 0x100 if OR2_CST_ONE_CLOCK + +config OR2_CHT + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_CHT_HALF_CLOCK + default 0x80 if OR2_CHT_ONE_CLOCK + default 0x0 if OR2_CHT_ONE_HALF_CLOCK + default 0x80 if OR2_CHT_TWO_CLOCK + +config OR2_RST + hex + default 0x0 if !BR2_MACHINE_FCM + default 0x0 if OR2_RST_THREE_QUARTER_CLOCK + default 0x8 if OR2_RST_ONE_CLOCK + default 0x0 if OR2_RST_ONE_HALF_CLOCK + +config OR2_CSNT + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_CSNT_NORMAL + default 0x800 if OR2_CSNT_EARLIER + +config OR2_ACS + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_ACS_SAME_TIME + default 0x400 if OR2_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR2_ACS_HALF_CYCLE_EARLIER + +config OR2_XACS + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_XACS_NORMAL + default 0x100 if OR2_XACS_EXTENDED + +config OR2_SETA + hex + default 0x0 if !BR2_MACHINE_GPCM + default 0x0 if OR2_SETA_INTERNAL + default 0x8 if OR2_SETA_EXTERNAL + +config OR2_TRLX + hex + default 0x0 if OR2_TRLX_NORMAL + default 0x4 if OR2_TRLX_RELAXED + +config OR2_EHTR + hex + default 0x0 if OR2_EHTR_NORMAL + default 0x2 if OR2_EHTR_1_CYCLE + default 0x0 if OR2_EHTR_4_CYCLE + default 0x2 if OR2_EHTR_8_CYCLE + +config OR2_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR2_EAD_NONE + default 0x1 if OR2_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 new file mode 100644 index 00000000000..963831bfcbd --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR3_OR3 + bool "ELBC BR3/OR3" + +if ELBC_BR3_OR3 + +config BR3_OR3_NAME + string "Identifier" + +config BR3_OR3_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR3_PORTSIZE_8BIT + bool "8-bit" + +config BR3_PORTSIZE_16BIT + depends on !BR3_MACHINE_FCM + bool "16-bit" + + +config BR3_PORTSIZE_32BIT + depends on !BR3_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR3_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR3_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR3_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR3_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR3_WRITE_PROTECT + bool "Write-protect" + +config BR3_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR3_MACHINE_GPCM + bool "GPCM" + +config BR3_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR3_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR3_MACHINE_UPMA + select BR3_MACHINE_UPM + bool "UPM (A)" + +config BR3_MACHINE_UPMB + select BR3_MACHINE_UPM + bool "UPM (B)" + +config BR3_MACHINE_UPMC + select BR3_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR3_ATOMIC_NONE + bool "No atomic operations" + +config BR3_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR3_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR3_MACHINE_GPCM || BR3_MACHINE_FCM || BR3_MACHINE_UPM || BR3_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR3_AM_32_KBYTES + depends on !BR3_MACHINE_SDRAM + bool "32 kb" + +config OR3_AM_64_KBYTES + bool "64 kb" + +config OR3_AM_128_KBYTES + bool "128 kb" + +config OR3_AM_256_KBYTES + bool "256 kb" + +config OR3_AM_512_KBYTES + bool "512 kb" + +config OR3_AM_1_MBYTES + bool "1 mb" + +config OR3_AM_2_MBYTES + bool "2 mb" + +config OR3_AM_4_MBYTES + bool "4 mb" + +config OR3_AM_8_MBYTES + bool "8 mb" + +config OR3_AM_16_MBYTES + bool "16 mb" + +config OR3_AM_32_MBYTES + bool "32 mb" + +config OR3_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR3_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR3_AM_256_MBYTES + bool "256 mb" + +config OR3_AM_512_MBYTES + depends on BR3_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR3_AM_1_GBYTES + bool "1 gb" + +config OR3_AM_2_GBYTES + depends on BR3_MACHINE_FCM + bool "2 gb" + +config OR3_AM_4_GBYTES + depends on BR3_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR3_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR3_BCTLD_ASSERTED + bool "Asserted" + +config OR3_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR3_MACHINE_GPCM || BR3_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR3_SCY_0 + bool "No wait states" + +config OR3_SCY_1 + bool "1 wait state" + +config OR3_SCY_2 + bool "2 wait states" + +config OR3_SCY_3 + bool "3 wait states" + +config OR3_SCY_4 + bool "4 wait states" + +config OR3_SCY_5 + bool "5 wait states" + +config OR3_SCY_6 + bool "6 wait states" + +config OR3_SCY_7 + bool "7 wait states" + +config OR3_SCY_8 + depends on BR3_MACHINE_GPCM + bool "8 wait states" + +config OR3_SCY_9 + depends on BR3_MACHINE_GPCM + bool "9 wait states" + +config OR3_SCY_10 + depends on BR3_MACHINE_GPCM + bool "10 wait states" + +config OR3_SCY_11 + depends on BR3_MACHINE_GPCM + bool "11 wait states" + +config OR3_SCY_12 + depends on BR3_MACHINE_GPCM + bool "12 wait states" + +config OR3_SCY_13 + depends on BR3_MACHINE_GPCM + bool "13 wait states" + +config OR3_SCY_14 + depends on BR3_MACHINE_GPCM + bool "14 wait states" + +config OR3_SCY_15 + depends on BR3_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR3_MACHINE_GPCM || BR3_MACHINE_FCM + +if BR3_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR3_CSNT_NORMAL + bool "Normal" + +config OR3_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR3_ACS_SAME_TIME + bool "At the same time" + +config OR3_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR3_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR3_XACS_NORMAL + bool "Normal" + +config OR3_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR3_SETA_INTERNAL + bool "Access is terminated internally" + +config OR3_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR3_MACHINE_GPCM + +if BR3_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR3_PGS_SMALL + bool "Small page device" + +config OR3_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR3_CSCT_1_CYCLE + depends on OR3_TRLX_NORMAL + bool "1 cycle" + +config OR3_CSCT_2_CYCLE + depends on OR3_TRLX_RELAXED + bool "2 cycles" + +config OR3_CSCT_4_CYCLE + depends on OR3_TRLX_NORMAL + bool "4 cycles" + +config OR3_CSCT_8_CYCLE + depends on OR3_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR3_CST_COINCIDENT + depends on OR3_TRLX_NORMAL + bool "Coincident with any command" + +config OR3_CST_QUARTER_CLOCK + depends on OR3_TRLX_NORMAL + bool "0.25 clocks after" + +config OR3_CST_HALF_CLOCK + depends on OR3_TRLX_RELAXED + bool "0.5 clocks after" + +config OR3_CST_ONE_CLOCK + depends on OR3_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR3_CHT_HALF_CLOCK + depends on OR3_TRLX_NORMAL + bool "0.5 clocks before" + +config OR3_CHT_ONE_CLOCK + depends on OR3_TRLX_NORMAL + bool "1 clock before" + +config OR3_CHT_ONE_HALF_CLOCK + depends on OR3_TRLX_RELAXED + bool "1.5 clocks before" + +config OR3_CHT_TWO_CLOCK + depends on OR3_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR3_RST_THREE_QUARTER_CLOCK + depends on OR3_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR3_RST_ONE_HALF_CLOCK + depends on OR3_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR3_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR3_MACHINE_FCM + +if BR3_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR3_BI_BURSTSUPPORT + bool "Support burst access" + +config OR3_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR3_MACHINE_UPM + +if BR3_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR3_COLS_7 + bool "7" + +config OR3_COLS_8 + bool "8" + +config OR3_COLS_9 + bool "9" + +config OR3_COLS_10 + bool "10" + +config OR3_COLS_11 + bool "11" + +config OR3_COLS_12 + bool "12" + +config OR3_COLS_13 + bool "13" + +config OR3_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR3_ROWS_9 + bool "9" + +config OR3_ROWS_10 + bool "10" + +config OR3_ROWS_11 + bool "11" + +config OR3_ROWS_12 + bool "12" + +config OR3_ROWS_13 + bool "13" + +config OR3_ROWS_14 + bool "14" + +config OR3_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR3_PMSEL_BTB + bool "Back-to-back" + +config OR3_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR3_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR3_TRLX_NORMAL + bool "Normal" + +config OR3_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR3_EHTR_NORMAL + depends on OR3_TRLX_NORMAL + bool "Normal" + +config OR3_EHTR_1_CYCLE + depends on OR3_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR3_EHTR_4_CYCLE + depends on OR3_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR3_EHTR_8_CYCLE + depends on OR3_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR3_EAD_NONE + bool "None" + +config OR3_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR3_OR3 + +config BR3_PORTSIZE + hex + default 0x800 if BR3_PORTSIZE_8BIT + default 0x1000 if BR3_PORTSIZE_16BIT + default 0x1800 if BR3_PORTSIZE_32BIT + +config BR3_ERRORCHECKING + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if BR3_ERRORCHECKING_DISABLED + default 0x200 if BR3_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR3_ERRORCHECKING_BOTH + +config BR3_WRITE_PROTECT_BIT + hex + default 0x0 if !BR3_WRITE_PROTECT + default 0x100 if BR3_WRITE_PROTECT + +config BR3_MACHINE + hex + default 0x0 if BR3_MACHINE_GPCM + default 0x20 if BR3_MACHINE_FCM + default 0x60 if BR3_MACHINE_SDRAM + default 0x80 if BR3_MACHINE_UPMA + default 0xa0 if BR3_MACHINE_UPMB + default 0xc0 if BR3_MACHINE_UPMC + +config BR3_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR3_ATOMIC_NONE + default 0x4 if BR3_ATOMIC_RAWA + default 0x8 if BR3_ATOMIC_WARA + +config BR3_VALID_BIT + hex + default 0x0 if !ELBC_BR3_OR3 + default 0x1 if ELBC_BR3_OR3 + +config OR3_AM + hex + default 0xffff8000 if OR3_AM_32_KBYTES && !BR3_MACHINE_SDRAM + default 0xffff0000 if OR3_AM_64_KBYTES + default 0xfffe0000 if OR3_AM_128_KBYTES + default 0xfffc0000 if OR3_AM_256_KBYTES + default 0xfff80000 if OR3_AM_512_KBYTES + default 0xfff00000 if OR3_AM_1_MBYTES + default 0xffe00000 if OR3_AM_2_MBYTES + default 0xffc00000 if OR3_AM_4_MBYTES + default 0xff800000 if OR3_AM_8_MBYTES + default 0xff000000 if OR3_AM_16_MBYTES + default 0xfe000000 if OR3_AM_32_MBYTES + default 0xfc000000 if OR3_AM_64_MBYTES + default 0xf8000000 if OR3_AM_128_MBYTES + default 0xf0000000 if OR3_AM_256_MBYTES + default 0xe0000000 if OR3_AM_512_MBYTES + default 0xc0000000 if OR3_AM_1_GBYTES + default 0x80000000 if OR3_AM_2_GBYTES + default 0x00000000 if OR3_AM_4_GBYTES + +config OR3_XAM + hex + default 0x0 if !OR3_XAM_SET + default 0x6000 if OR3_XAM_SET + +config OR3_BCTLD + hex + default 0x0 if OR3_BCTLD_ASSERTED + default 0x1000 if OR3_BCTLD_NOT_ASSERTED + +config OR3_BI + hex + default 0x0 if !BR3_MACHINE_UPM + default 0x0 if OR3_BI_BURSTSUPPORT + default 0x100 if OR3_BI_BURSTINHIBIT + +config OR3_COLS + hex + default 0x0 if !BR3_MACHINE_SDRAM + default 0x0 if OR3_COLS_7 + default 0x400 if OR3_COLS_8 + default 0x800 if OR3_COLS_9 + default 0xc00 if OR3_COLS_10 + default 0x1000 if OR3_COLS_11 + default 0x1400 if OR3_COLS_12 + default 0x1800 if OR3_COLS_13 + default 0x1c00 if OR3_COLS_14 + +config OR3_ROWS + hex + default 0x0 if !BR3_MACHINE_SDRAM + default 0x0 if OR3_ROWS_9 + default 0x40 if OR3_ROWS_10 + default 0x80 if OR3_ROWS_11 + default 0xc0 if OR3_ROWS_12 + default 0x100 if OR3_ROWS_13 + default 0x140 if OR3_ROWS_14 + default 0x180 if OR3_ROWS_15 + +config OR3_PMSEL + hex + default 0x0 if !BR3_MACHINE_SDRAM + default 0x0 if OR3_PMSEL_BTB + default 0x20 if OR3_PMSEL_KEPT_OPEN + +config OR3_SCY + hex + default 0x0 if !BR3_MACHINE_GPCM && !BR3_MACHINE_FCM + default 0x0 if OR3_SCY_0 + default 0x10 if OR3_SCY_1 + default 0x20 if OR3_SCY_2 + default 0x30 if OR3_SCY_3 + default 0x40 if OR3_SCY_4 + default 0x50 if OR3_SCY_5 + default 0x60 if OR3_SCY_6 + default 0x70 if OR3_SCY_7 + default 0x80 if OR3_SCY_8 + default 0x90 if OR3_SCY_9 + default 0xa0 if OR3_SCY_10 + default 0xb0 if OR3_SCY_11 + default 0xc0 if OR3_SCY_12 + default 0xd0 if OR3_SCY_13 + default 0xe0 if OR3_SCY_14 + default 0xf0 if OR3_SCY_15 + +config OR3_PGS + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_PGS_SMALL + default 0x400 if OR3_PGS_LARGE + +config OR3_CSCT + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_CSCT_1_CYCLE + default 0x0 if OR3_CSCT_2_CYCLE + default 0x200 if OR3_CSCT_4_CYCLE + default 0x200 if OR3_CSCT_8_CYCLE + +config OR3_CST + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_CST_COINCIDENT + default 0x100 if OR3_CST_QUARTER_CLOCK + default 0x0 if OR3_CST_HALF_CLOCK + default 0x100 if OR3_CST_ONE_CLOCK + +config OR3_CHT + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_CHT_HALF_CLOCK + default 0x80 if OR3_CHT_ONE_CLOCK + default 0x0 if OR3_CHT_ONE_HALF_CLOCK + default 0x80 if OR3_CHT_TWO_CLOCK + +config OR3_RST + hex + default 0x0 if !BR3_MACHINE_FCM + default 0x0 if OR3_RST_THREE_QUARTER_CLOCK + default 0x8 if OR3_RST_ONE_CLOCK + default 0x0 if OR3_RST_ONE_HALF_CLOCK + +config OR3_CSNT + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_CSNT_NORMAL + default 0x800 if OR3_CSNT_EARLIER + +config OR3_ACS + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_ACS_SAME_TIME + default 0x400 if OR3_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR3_ACS_HALF_CYCLE_EARLIER + +config OR3_XACS + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_XACS_NORMAL + default 0x100 if OR3_XACS_EXTENDED + +config OR3_SETA + hex + default 0x0 if !BR3_MACHINE_GPCM + default 0x0 if OR3_SETA_INTERNAL + default 0x8 if OR3_SETA_EXTERNAL + +config OR3_TRLX + hex + default 0x0 if OR3_TRLX_NORMAL + default 0x4 if OR3_TRLX_RELAXED + +config OR3_EHTR + hex + default 0x0 if OR3_EHTR_NORMAL + default 0x2 if OR3_EHTR_1_CYCLE + default 0x0 if OR3_EHTR_4_CYCLE + default 0x2 if OR3_EHTR_8_CYCLE + +config OR3_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR3_EAD_NONE + default 0x1 if OR3_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 new file mode 100644 index 00000000000..0063dab9622 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 @@ -0,0 +1,733 @@ +menuconfig ELBC_BR4_OR4 + bool "ELBC BR4/OR4" + +if ELBC_BR4_OR4 + +config BR4_OR4_NAME + string "Identifier" + +config BR4_OR4_BASE + hex "Port base" + +choice + prompt "Port size" + +config BR4_PORTSIZE_8BIT + bool "8-bit" + +config BR4_PORTSIZE_16BIT + depends on !BR4_MACHINE_FCM + bool "16-bit" + + +config BR4_PORTSIZE_32BIT + depends on !BR4_MACHINE_FCM + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + bool "32-bit" + +endchoice + +if BR4_MACHINE_FCM + +choice + prompt "Data Error Checking" + +config BR4_ERRORCHECKING_DISABLED + bool "Disabled" + +config BR4_ERRORCHECKING_ECC_CHECKING + bool "ECC checking / No ECC generation" + +config BR4_ERRORCHECKING_BOTH + bool "ECC checking and generation" + +endchoice + +endif + +config BR4_WRITE_PROTECT + bool "Write-protect" + +config BR4_MACHINE_UPM + bool + +choice + prompt "Machine select" + +config BR4_MACHINE_GPCM + bool "GPCM" + +config BR4_MACHINE_FCM + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "FCM" + +config BR4_MACHINE_SDRAM + depends on ARCH_MPC8349 || ARCH_MPC8360 + bool "SDRAM" + +config BR4_MACHINE_UPMA + select BR4_MACHINE_UPM + bool "UPM (A)" + +config BR4_MACHINE_UPMB + select BR4_MACHINE_UPM + bool "UPM (B)" + +config BR4_MACHINE_UPMC + select BR4_MACHINE_UPM + bool "UPM (C)" + +endchoice + +if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360 + +choice + prompt "Atomic operations" + +config BR4_ATOMIC_NONE + bool "No atomic operations" + +config BR4_ATOMIC_RAWA + bool "Read-after-write-atomic" + +config BR4_ATOMIC_WARA + bool "Write-after-read-atomic" + +endchoice + +endif + +if BR4_MACHINE_GPCM || BR4_MACHINE_FCM || BR4_MACHINE_UPM || BR4_MACHINE_SDRAM + +choice + prompt "Address mask" + +config OR4_AM_32_KBYTES + depends on !BR4_MACHINE_SDRAM + bool "32 kb" + +config OR4_AM_64_KBYTES + bool "64 kb" + +config OR4_AM_128_KBYTES + bool "128 kb" + +config OR4_AM_256_KBYTES + bool "256 kb" + +config OR4_AM_512_KBYTES + bool "512 kb" + +config OR4_AM_1_MBYTES + bool "1 mb" + +config OR4_AM_2_MBYTES + bool "2 mb" + +config OR4_AM_4_MBYTES + bool "4 mb" + +config OR4_AM_8_MBYTES + bool "8 mb" + +config OR4_AM_16_MBYTES + bool "16 mb" + +config OR4_AM_32_MBYTES + bool "32 mb" + +config OR4_AM_64_MBYTES + bool "64 mb" + +# XXX: Some boards define 128MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR4_AM_128_MBYTES + bool "128 mb" + +# XXX: Some boards define 256MB AM with GPCM, even though it should not be +# possible according to the manuals +config OR4_AM_256_MBYTES + bool "256 mb" + +config OR4_AM_512_MBYTES + depends on BR4_MACHINE_FCM + bool "512 mb" + +# XXX: Some boards define 1GB AM with GPCM, even though it should not be +# possible according to the manuals +config OR4_AM_1_GBYTES + bool "1 gb" + +config OR4_AM_2_GBYTES + depends on BR4_MACHINE_FCM + bool "2 gb" + +config OR4_AM_4_GBYTES + depends on BR4_MACHINE_FCM + bool "4 gb" + +endchoice + +config OR4_XAM_SET + bool "Set unused bytes after address mask" +choice + prompt "Buffer control disable" + +config OR4_BCTLD_ASSERTED + bool "Asserted" + +config OR4_BCTLD_NOT_ASSERTED + bool "Not asserted" + +endchoice + +endif + +if BR4_MACHINE_GPCM || BR4_MACHINE_FCM + +choice + prompt "Cycle length in bus clocks" + +config OR4_SCY_0 + bool "No wait states" + +config OR4_SCY_1 + bool "1 wait state" + +config OR4_SCY_2 + bool "2 wait states" + +config OR4_SCY_3 + bool "3 wait states" + +config OR4_SCY_4 + bool "4 wait states" + +config OR4_SCY_5 + bool "5 wait states" + +config OR4_SCY_6 + bool "6 wait states" + +config OR4_SCY_7 + bool "7 wait states" + +config OR4_SCY_8 + depends on BR4_MACHINE_GPCM + bool "8 wait states" + +config OR4_SCY_9 + depends on BR4_MACHINE_GPCM + bool "9 wait states" + +config OR4_SCY_10 + depends on BR4_MACHINE_GPCM + bool "10 wait states" + +config OR4_SCY_11 + depends on BR4_MACHINE_GPCM + bool "11 wait states" + +config OR4_SCY_12 + depends on BR4_MACHINE_GPCM + bool "12 wait states" + +config OR4_SCY_13 + depends on BR4_MACHINE_GPCM + bool "13 wait states" + +config OR4_SCY_14 + depends on BR4_MACHINE_GPCM + bool "14 wait states" + +config OR4_SCY_15 + depends on BR4_MACHINE_GPCM + bool "15 wait states" + +endchoice + +endif # BR4_MACHINE_GPCM || BR4_MACHINE_FCM + +if BR4_MACHINE_GPCM + +choice + prompt "Chip select negotiation time" + +config OR4_CSNT_NORMAL + bool "Normal" + +config OR4_CSNT_EARLIER + bool "Earlier" + +endchoice + +choice + prompt "Address to chip-select setup" + +config OR4_ACS_SAME_TIME + bool "At the same time" + +config OR4_ACS_HALF_CYCLE_EARLIER + bool "Half of a bus clock cycle earlier" + +config OR4_ACS_QUARTER_CYCLE_EARLIER + bool "Half/Quarter of a bus clock cycle earlier" + +endchoice + +choice + prompt "Extra address to check-select setup" + +config OR4_XACS_NORMAL + bool "Normal" + +config OR4_XACS_EXTENDED + bool "Extended" + +endchoice + +choice + prompt "External address termination" + +config OR4_SETA_INTERNAL + bool "Access is terminated internally" + +config OR4_SETA_EXTERNAL + bool "Access is terminated externally" + +endchoice + +endif # BR4_MACHINE_GPCM + +if BR4_MACHINE_FCM + +choice + prompt "NAND Flash EEPROM page size" + +config OR4_PGS_SMALL + bool "Small page device" + +config OR4_PGS_LARGE + bool "Large page device" + +endchoice + +choice + prompt "Chip select to command time" + +config OR4_CSCT_1_CYCLE + depends on OR4_TRLX_NORMAL + bool "1 cycle" + +config OR4_CSCT_2_CYCLE + depends on OR4_TRLX_RELAXED + bool "2 cycles" + +config OR4_CSCT_4_CYCLE + depends on OR4_TRLX_NORMAL + bool "4 cycles" + +config OR4_CSCT_8_CYCLE + depends on OR4_TRLX_RELAXED + bool "8 cycles" + +endchoice + +choice + prompt "Command setup time" + +config OR4_CST_COINCIDENT + depends on OR4_TRLX_NORMAL + bool "Coincident with any command" + +config OR4_CST_QUARTER_CLOCK + depends on OR4_TRLX_NORMAL + bool "0.25 clocks after" + +config OR4_CST_HALF_CLOCK + depends on OR4_TRLX_RELAXED + bool "0.5 clocks after" + +config OR4_CST_ONE_CLOCK + depends on OR4_TRLX_RELAXED + bool "1 clock after" + +endchoice + +choice + prompt "Command hold time" + +config OR4_CHT_HALF_CLOCK + depends on OR4_TRLX_NORMAL + bool "0.5 clocks before" + +config OR4_CHT_ONE_CLOCK + depends on OR4_TRLX_NORMAL + bool "1 clock before" + +config OR4_CHT_ONE_HALF_CLOCK + depends on OR4_TRLX_RELAXED + bool "1.5 clocks before" + +config OR4_CHT_TWO_CLOCK + depends on OR4_TRLX_RELAXED + bool "2 clocks before" + +endchoice + +choice + prompt "Reset setup time" + +config OR4_RST_THREE_QUARTER_CLOCK + depends on OR4_TRLX_NORMAL + bool "0.75 clocks prior" + +config OR4_RST_ONE_HALF_CLOCK + depends on OR4_TRLX_RELAXED + bool "0.5 clocks prior" + +config OR4_RST_ONE_CLOCK + bool "1 clock prior" + +endchoice + +endif # BR4_MACHINE_FCM + +if BR4_MACHINE_UPM + +choice + prompt "Burst inhibit" + +config OR4_BI_BURSTSUPPORT + bool "Support burst access" + +config OR4_BI_BURSTINHIBIT + bool "Inhibit burst access" + +endchoice + +endif # BR4_MACHINE_UPM + +if BR4_MACHINE_SDRAM + +choice + prompt "Number of column address lines" + +config OR4_COLS_7 + bool "7" + +config OR4_COLS_8 + bool "8" + +config OR4_COLS_9 + bool "9" + +config OR4_COLS_10 + bool "10" + +config OR4_COLS_11 + bool "11" + +config OR4_COLS_12 + bool "12" + +config OR4_COLS_13 + bool "13" + +config OR4_COLS_14 + bool "14" + +endchoice + +choice + prompt "Number of rows address lines" + +config OR4_ROWS_9 + bool "9" + +config OR4_ROWS_10 + bool "10" + +config OR4_ROWS_11 + bool "11" + +config OR4_ROWS_12 + bool "12" + +config OR4_ROWS_13 + bool "13" + +config OR4_ROWS_14 + bool "14" + +config OR4_ROWS_15 + bool "15" + +endchoice + +choice + prompt "Page mode select" + +config OR4_PMSEL_BTB + bool "Back-to-back" + +config OR4_PMSEL_KEPT_OPEN + bool "Page kept open until page miss or refresh" + +endchoice + +endif # BR4_MACHINE_SDRAM + +choice + prompt "Relaxed timing" + +config OR4_TRLX_NORMAL + bool "Normal" + +config OR4_TRLX_RELAXED + bool "Relaxed" + +endchoice + +choice + prompt "Extended hold time" + +config OR4_EHTR_NORMAL + depends on OR4_TRLX_NORMAL + bool "Normal" + +config OR4_EHTR_1_CYCLE + depends on OR4_TRLX_NORMAL + bool "1 idle clock cycle inserted" + +config OR4_EHTR_4_CYCLE + depends on OR4_TRLX_RELAXED + bool "4 idle clock cycles inserted" + +config OR4_EHTR_8_CYCLE + depends on OR4_TRLX_RELAXED + bool "8 idle clock cycles inserted" + +endchoice + +if !ARCH_MPC8308 + +choice + prompt "External address latch delay" + +config OR4_EAD_NONE + bool "None" + +config OR4_EAD_EXTRA + bool "Extra" + +endchoice + +endif # !ARCH_MPC8308 + +endif # ELBC_BR4_OR4 + +config BR4_PORTSIZE + hex + default 0x800 if BR4_PORTSIZE_8BIT + default 0x1000 if BR4_PORTSIZE_16BIT + default 0x1800 if BR4_PORTSIZE_32BIT + +config BR4_ERRORCHECKING + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if BR4_ERRORCHECKING_DISABLED + default 0x200 if BR4_ERRORCHECKING_ECC_CHECKING + default 0x400 if BR4_ERRORCHECKING_BOTH + +config BR4_WRITE_PROTECT_BIT + hex + default 0x0 if !BR4_WRITE_PROTECT + default 0x100 if BR4_WRITE_PROTECT + +config BR4_MACHINE + hex + default 0x0 if BR4_MACHINE_GPCM + default 0x20 if BR4_MACHINE_FCM + default 0x60 if BR4_MACHINE_SDRAM + default 0x80 if BR4_MACHINE_UPMA + default 0xa0 if BR4_MACHINE_UPMB + default 0xc0 if BR4_MACHINE_UPMC + +config BR4_ATOMIC + hex + default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360 + default 0x0 if BR4_ATOMIC_NONE + default 0x4 if BR4_ATOMIC_RAWA + default 0x8 if BR4_ATOMIC_WARA + +config BR4_VALID_BIT + hex + default 0x0 if !ELBC_BR4_OR4 + default 0x1 if ELBC_BR4_OR4 + +config OR4_AM + hex + default 0xffff8000 if OR4_AM_32_KBYTES && !BR4_MACHINE_SDRAM + default 0xffff0000 if OR4_AM_64_KBYTES + default 0xfffe0000 if OR4_AM_128_KBYTES + default 0xfffc0000 if OR4_AM_256_KBYTES + default 0xfff80000 if OR4_AM_512_KBYTES + default 0xfff00000 if OR4_AM_1_MBYTES + default 0xffe00000 if OR4_AM_2_MBYTES + default 0xffc00000 if OR4_AM_4_MBYTES + default 0xff800000 if OR4_AM_8_MBYTES + default 0xff000000 if OR4_AM_16_MBYTES + default 0xfe000000 if OR4_AM_32_MBYTES + default 0xfc000000 if OR4_AM_64_MBYTES + default 0xf8000000 if OR4_AM_128_MBYTES + default 0xf0000000 if OR4_AM_256_MBYTES + default 0xe0000000 if OR4_AM_512_MBYTES + default 0xc0000000 if OR4_AM_1_GBYTES + default 0x80000000 if OR4_AM_2_GBYTES + default 0x00000000 if OR4_AM_4_GBYTES + +config OR4_XAM + hex + default 0x0 if !OR4_XAM_SET + default 0x6000 if OR4_XAM_SET + +config OR4_BCTLD + hex + default 0x0 if OR4_BCTLD_ASSERTED + default 0x1000 if OR4_BCTLD_NOT_ASSERTED + +config OR4_BI + hex + default 0x0 if !BR4_MACHINE_UPM + default 0x0 if OR4_BI_BURSTSUPPORT + default 0x100 if OR4_BI_BURSTINHIBIT + +config OR4_COLS + hex + default 0x0 if !BR4_MACHINE_SDRAM + default 0x0 if OR4_COLS_7 + default 0x400 if OR4_COLS_8 + default 0x800 if OR4_COLS_9 + default 0xc00 if OR4_COLS_10 + default 0x1000 if OR4_COLS_11 + default 0x1400 if OR4_COLS_12 + default 0x1800 if OR4_COLS_13 + default 0x1c00 if OR4_COLS_14 + +config OR4_ROWS + hex + default 0x0 if !BR4_MACHINE_SDRAM + default 0x0 if OR4_ROWS_9 + default 0x40 if OR4_ROWS_10 + default 0x80 if OR4_ROWS_11 + default 0xc0 if OR4_ROWS_12 + default 0x100 if OR4_ROWS_13 + default 0x140 if OR4_ROWS_14 + default 0x180 if OR4_ROWS_15 + +config OR4_PMSEL + hex + default 0x0 if !BR4_MACHINE_SDRAM + default 0x0 if OR4_PMSEL_BTB + default 0x20 if OR4_PMSEL_KEPT_OPEN + +config OR4_SCY + hex + default 0x0 if !BR4_MACHINE_GPCM && !BR4_MACHINE_FCM + default 0x0 if OR4_SCY_0 + default 0x10 if OR4_SCY_1 + default 0x20 if OR4_SCY_2 + default 0x30 if OR4_SCY_3 + default 0x40 if OR4_SCY_4 + default 0x50 if OR4_SCY_5 + default 0x60 if OR4_SCY_6 + default 0x70 if OR4_SCY_7 + default 0x80 if OR4_SCY_8 + default 0x90 if OR4_SCY_9 + default 0xa0 if OR4_SCY_10 + default 0xb0 if OR4_SCY_11 + default 0xc0 if OR4_SCY_12 + default 0xd0 if OR4_SCY_13 + default 0xe0 if OR4_SCY_14 + default 0xf0 if OR4_SCY_15 + +config OR4_PGS + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_PGS_SMALL + default 0x400 if OR4_PGS_LARGE + +config OR4_CSCT + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_CSCT_1_CYCLE + default 0x0 if OR4_CSCT_2_CYCLE + default 0x200 if OR4_CSCT_4_CYCLE + default 0x200 if OR4_CSCT_8_CYCLE + +config OR4_CST + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_CST_COINCIDENT + default 0x100 if OR4_CST_QUARTER_CLOCK + default 0x0 if OR4_CST_HALF_CLOCK + default 0x100 if OR4_CST_ONE_CLOCK + +config OR4_CHT + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_CHT_HALF_CLOCK + default 0x80 if OR4_CHT_ONE_CLOCK + default 0x0 if OR4_CHT_ONE_HALF_CLOCK + default 0x80 if OR4_CHT_TWO_CLOCK + +config OR4_RST + hex + default 0x0 if !BR4_MACHINE_FCM + default 0x0 if OR4_RST_THREE_QUARTER_CLOCK + default 0x8 if OR4_RST_ONE_CLOCK + default 0x0 if OR4_RST_ONE_HALF_CLOCK + +config OR4_CSNT + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_CSNT_NORMAL + default 0x800 if OR4_CSNT_EARLIER + +config OR4_ACS + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_ACS_SAME_TIME + default 0x400 if OR4_ACS_QUARTER_CYCLE_EARLIER + default 0x600 if OR4_ACS_HALF_CYCLE_EARLIER + +config OR4_XACS + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_XACS_NORMAL + default 0x100 if OR4_XACS_EXTENDED + +config OR4_SETA + hex + default 0x0 if !BR4_MACHINE_GPCM + default 0x0 if OR4_SETA_INTERNAL + default 0x8 if OR4_SETA_EXTERNAL + +config OR4_TRLX + hex + default 0x0 if OR4_TRLX_NORMAL + default 0x4 if OR4_TRLX_RELAXED + +config OR4_EHTR + hex + default 0x0 if OR4_EHTR_NORMAL + default 0x2 if OR4_EHTR_1_CYCLE + default 0x0 if OR4_EHTR_4_CYCLE + default 0x2 if OR4_EHTR_8_CYCLE + +config OR4_EAD + hex + default 0x0 if ARCH_MPC8308 + default 0x0 if OR4_EAD_NONE + default 0x1 if OR4_EAD_EXTRA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h new file mode 100644 index 00000000000..245fe7c6fb7 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h @@ -0,0 +1,186 @@ +#ifdef CONFIG_ELBC_BR0_OR0 +#define CONFIG_SYS_BR0_PRELIM (\ + CONFIG_BR0_OR0_BASE |\ + CONFIG_BR0_PORTSIZE |\ + CONFIG_BR0_ERRORCHECKING |\ + CONFIG_BR0_WRITE_PROTECT_BIT |\ + CONFIG_BR0_MACHINE |\ + CONFIG_BR0_ATOMIC |\ + CONFIG_BR0_VALID_BIT \ +) +#define CONFIG_SYS_OR0_PRELIM (\ + CONFIG_OR0_AM |\ + CONFIG_OR0_XAM |\ + CONFIG_OR0_BCTLD |\ + CONFIG_OR0_BI |\ + CONFIG_OR0_COLS |\ + CONFIG_OR0_ROWS |\ + CONFIG_OR0_PMSEL |\ + CONFIG_OR0_SCY |\ + CONFIG_OR0_PGS |\ + CONFIG_OR0_CSCT |\ + CONFIG_OR0_CST |\ + CONFIG_OR0_CHT |\ + CONFIG_OR0_RST |\ + CONFIG_OR0_CSNT |\ + CONFIG_OR0_ACS |\ + CONFIG_OR0_XACS |\ + CONFIG_OR0_SETA |\ + CONFIG_OR0_TRLX |\ + CONFIG_OR0_EHTR |\ + CONFIG_OR0_EAD \ +) +#endif /* CONFIG_ELBC_BR0_OR0 */ + +#ifdef CONFIG_ELBC_BR1_OR1 +#define CONFIG_SYS_BR1_PRELIM (\ + CONFIG_BR1_OR1_BASE |\ + CONFIG_BR1_PORTSIZE |\ + CONFIG_BR1_ERRORCHECKING |\ + CONFIG_BR1_WRITE_PROTECT_BIT |\ + CONFIG_BR1_MACHINE |\ + CONFIG_BR1_ATOMIC |\ + CONFIG_BR1_VALID_BIT \ +) +#define CONFIG_SYS_OR1_PRELIM (\ + CONFIG_OR1_AM |\ + CONFIG_OR1_XAM |\ + CONFIG_OR1_BCTLD |\ + CONFIG_OR1_BI |\ + CONFIG_OR1_COLS |\ + CONFIG_OR1_ROWS |\ + CONFIG_OR1_PMSEL |\ + CONFIG_OR1_SCY |\ + CONFIG_OR1_PGS |\ + CONFIG_OR1_CSCT |\ + CONFIG_OR1_CST |\ + CONFIG_OR1_CHT |\ + CONFIG_OR1_RST |\ + CONFIG_OR1_CSNT |\ + CONFIG_OR1_ACS |\ + CONFIG_OR1_XACS |\ + CONFIG_OR1_SETA |\ + CONFIG_OR1_TRLX |\ + CONFIG_OR1_EHTR |\ + CONFIG_OR1_EAD \ +) +#endif /* CONFIG_ELBC_BR1_OR1 */ + +#ifdef CONFIG_ELBC_BR2_OR2 +#define CONFIG_SYS_BR2_PRELIM (\ + CONFIG_BR2_OR2_BASE |\ + CONFIG_BR2_PORTSIZE |\ + CONFIG_BR2_ERRORCHECKING |\ + CONFIG_BR2_WRITE_PROTECT_BIT |\ + CONFIG_BR2_MACHINE |\ + CONFIG_BR2_ATOMIC |\ + CONFIG_BR2_VALID_BIT \ +) +#define CONFIG_SYS_OR2_PRELIM (\ + CONFIG_OR2_AM |\ + CONFIG_OR2_XAM |\ + CONFIG_OR2_BCTLD |\ + CONFIG_OR2_BI |\ + CONFIG_OR2_COLS |\ + CONFIG_OR2_ROWS |\ + CONFIG_OR2_PMSEL |\ + CONFIG_OR2_SCY |\ + CONFIG_OR2_PGS |\ + CONFIG_OR2_CSCT |\ + CONFIG_OR2_CST |\ + CONFIG_OR2_CHT |\ + CONFIG_OR2_RST |\ + CONFIG_OR2_CSNT |\ + CONFIG_OR2_ACS |\ + CONFIG_OR2_XACS |\ + CONFIG_OR2_SETA |\ + CONFIG_OR2_TRLX |\ + CONFIG_OR2_EHTR |\ + CONFIG_OR2_EAD \ +) +#endif /* CONFIG_ELBC_BR2_OR2 */ + +#ifdef CONFIG_ELBC_BR3_OR3 +#define CONFIG_SYS_BR3_PRELIM (\ + CONFIG_BR3_OR3_BASE |\ + CONFIG_BR3_PORTSIZE |\ + CONFIG_BR3_ERRORCHECKING |\ + CONFIG_BR3_WRITE_PROTECT_BIT |\ + CONFIG_BR3_MACHINE |\ + CONFIG_BR3_ATOMIC |\ + CONFIG_BR3_VALID_BIT \ +) +#define CONFIG_SYS_OR3_PRELIM (\ + CONFIG_OR3_AM |\ + CONFIG_OR3_XAM |\ + CONFIG_OR3_BCTLD |\ + CONFIG_OR3_BI |\ + CONFIG_OR3_COLS |\ + CONFIG_OR3_ROWS |\ + CONFIG_OR3_PMSEL |\ + CONFIG_OR3_SCY |\ + CONFIG_OR3_PGS |\ + CONFIG_OR3_CSCT |\ + CONFIG_OR3_CST |\ + CONFIG_OR3_CHT |\ + CONFIG_OR3_RST |\ + CONFIG_OR3_CSNT |\ + CONFIG_OR3_ACS |\ + CONFIG_OR3_XACS |\ + CONFIG_OR3_SETA |\ + CONFIG_OR3_TRLX |\ + CONFIG_OR3_EHTR |\ + CONFIG_OR3_EAD \ +) +#endif /* CONFIG_ELBC_BR3_OR3 */ + +#ifdef CONFIG_ELBC_BR4_OR4 +#define CONFIG_SYS_BR4_PRELIM (\ + CONFIG_BR4_OR4_BASE |\ + CONFIG_BR4_PORTSIZE |\ + CONFIG_BR4_ERRORCHECKING |\ + CONFIG_BR4_WRITE_PROTECT_BIT |\ + CONFIG_BR4_MACHINE |\ + CONFIG_BR4_ATOMIC |\ + CONFIG_BR4_VALID_BIT \ +) +#define CONFIG_SYS_OR4_PRELIM (\ + CONFIG_OR4_AM |\ + CONFIG_OR4_XAM |\ + CONFIG_OR4_BCTLD |\ + CONFIG_OR4_BI |\ + CONFIG_OR4_COLS |\ + CONFIG_OR4_ROWS |\ + CONFIG_OR4_PMSEL |\ + CONFIG_OR4_SCY |\ + CONFIG_OR4_PGS |\ + CONFIG_OR4_CSCT |\ + CONFIG_OR4_CST |\ + CONFIG_OR4_CHT |\ + CONFIG_OR4_RST |\ + CONFIG_OR4_CSNT |\ + CONFIG_OR4_ACS |\ + CONFIG_OR4_XACS |\ + CONFIG_OR4_SETA |\ + CONFIG_OR4_TRLX |\ + CONFIG_OR4_EHTR |\ + CONFIG_OR4_EAD \ +) +#endif /* CONFIG_ELBC_BR4_OR4 */ + +#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM +#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4) +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM +#endif diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 75eb65010ec..b4e2fb1119d 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -7,6 +7,7 @@ #include <mpc83xx.h>
#include "lblaw/lblaw.h" +#include "elbc/elbc.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 13545fc6ad6..c43732f7c5c 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -6,6 +6,10 @@ #include <common.h> #include <asm/fsl_lbc.h>
+#ifdef CONFIG_MPC83xx +#include "../mpc83xx/elbc/elbc.h" +#endif + #ifdef CONFIG_MPC85xx /* Boards should provide their own version of this if they use lbc sdram */ static void __lbc_sdram_init(void) diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index c4bec090be1..62bcf235711 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -20,6 +20,7 @@ #endif
#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h" +#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 38c5d8d5327..c38ac328d2a 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -86,3 +86,41 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385_BASE" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 5783165e5d1..1588adf3d66 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -103,3 +103,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE2800000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index 2395b8e3978..2425256ee30 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -102,3 +102,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE2800000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 4c2d3400fdf..c874f6188f7 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -110,3 +110,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="NAND" +CONFIG_BR0_OR0_BASE=0xE2800000 +CONFIG_BR0_ERRORCHECKING_BOTH=y +CONFIG_BR0_MACHINE_FCM=y +CONFIG_BR0_PORTSIZE_8BIT=y +CONFIG_OR0_AM_32_KBYTES=y +CONFIG_OR0_SCY_1=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_CHT_TWO_CLOCK=y +CONFIG_OR0_CSCT_8_CYCLE=y +CONFIG_OR0_CST_ONE_CLOCK=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FLASH" +CONFIG_BR1_OR1_BASE=0xFE000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_8_MBYTES=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_9=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index b241091e489..198b373c3e5 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -109,3 +109,53 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="NAND" +CONFIG_BR0_OR0_BASE=0xE2800000 +CONFIG_BR0_ERRORCHECKING_BOTH=y +CONFIG_BR0_MACHINE_FCM=y +CONFIG_BR0_PORTSIZE_8BIT=y +CONFIG_OR0_AM_32_KBYTES=y +CONFIG_OR0_SCY_1=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_CHT_TWO_CLOCK=y +CONFIG_OR0_CSCT_8_CYCLE=y +CONFIG_OR0_CST_ONE_CLOCK=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FLASH" +CONFIG_BR1_OR1_BASE=0xFE000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_8_MBYTES=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_9=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="BCSR" +CONFIG_BR3_OR3_BASE=0xFA000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index b6e43b66aac..b9539893ff7 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -109,3 +109,30 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 7243cf67f96..64e6f58f38c 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -88,3 +88,17 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 8cbc14022b6..ffc82260ec3 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -87,3 +87,56 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 487d1d85442..911f62de653 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -107,3 +107,56 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 10ea03422c7..7dd02a95c92 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -107,3 +107,56 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index b1afa2fa474..3e3c82b2ef5 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -104,3 +104,56 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index a9bb8a77139..4cfa01074d1 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -86,3 +86,56 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="PIB1" +CONFIG_BR2_OR2_BASE=0xF8008000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_XAM_SET=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PIB2" +CONFIG_BR3_OR3_BASE=0xF8010000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_XAM_SET=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index 28779bbeb74..a29d3268f79 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -73,3 +73,27 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index a157066968d..e3058f0b5e8 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -57,6 +57,33 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xF0000000 CONFIG_LBLAW2_NAME="SDRAM" CONFIG_LBLAW2_LENGTH_64_MBYTES=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="SDRAM" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_PORTSIZE_32BIT=y +CONFIG_BR2_MACHINE_SDRAM=y +CONFIG_OR2_COLS_9=y +CONFIG_OR2_ROWS_13=y +CONFIG_OR2_EAD_EXTRA=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 588d9420f16..d45b6489b47 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -73,3 +73,27 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index a38edb52939..e3ca6811ccf 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -76,3 +76,27 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xE2400000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 844b8973295..cf4ce83307a 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -125,3 +125,50 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="VSC7385" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="LED" +CONFIG_BR2_OR2_BASE=0xF9000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_2_MBYTES=y +CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_9=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CF" +CONFIG_BR3_OR3_BASE=0xF0000000 +CONFIG_BR3_MACHINE_UPMA=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BI_BURSTINHIBIT=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 91ed6686f81..e0185191bc7 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -133,3 +133,50 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="VSC7385" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="LED" +CONFIG_BR2_OR2_BASE=0xF9000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_2_MBYTES=y +CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_9=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CF" +CONFIG_BR3_OR3_BASE=0xF0000000 +CONFIG_BR3_MACHINE_UPMA=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BI_BURSTINHIBIT=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index cfa31c72307..0187f4f1280 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -132,3 +132,50 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_16_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="VSC7385" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="LED" +CONFIG_BR2_OR2_BASE=0xF9000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_2_MBYTES=y +CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_9=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CF" +CONFIG_BR3_OR3_BASE=0xF0000000 +CONFIG_BR3_MACHINE_UPMA=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BI_BURSTINHIBIT=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 4cc36a5c7fb..b048d5b5d00 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -131,3 +131,44 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="NAND" +CONFIG_BR3_OR3_BASE=0xE0600000 +CONFIG_BR3_ERRORCHECKING_BOTH=y +CONFIG_BR3_MACHINE_FCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BCTLD_NOT_ASSERTED=y +CONFIG_OR3_RST_ONE_CLOCK=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_CHT_TWO_CLOCK=y +CONFIG_OR3_CST_ONE_CLOCK=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index ba58e49ba24..9e2966b371f 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -84,3 +84,44 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="NAND" +CONFIG_BR3_OR3_BASE=0xE0600000 +CONFIG_BR3_ERRORCHECKING_BOTH=y +CONFIG_BR3_MACHINE_FCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BCTLD_NOT_ASSERTED=y +CONFIG_OR3_RST_ONE_CLOCK=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_CHT_TWO_CLOCK=y +CONFIG_OR3_CST_ONE_CLOCK=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index b3c1c87824a..9256aac17cd 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -107,3 +107,44 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="BCSR" +CONFIG_BR1_OR1_BASE=0xF8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="NAND" +CONFIG_BR3_OR3_BASE=0xE0600000 +CONFIG_BR3_ERRORCHECKING_BOTH=y +CONFIG_BR3_MACHINE_FCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_BCTLD_NOT_ASSERTED=y +CONFIG_OR3_RST_ONE_CLOCK=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_CHT_TWO_CLOCK=y +CONFIG_OR3_CST_ONE_CLOCK=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 07016936d62..95400114f2f 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -90,3 +90,39 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 59d591fa05b..a8c69eb6bcb 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -133,3 +133,39 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_9=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_EHTR_1_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_1=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="VSC7385" +CONFIG_BR2_OR2_BASE=0xF0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_15=y +CONFIG_OR2_SETA_EXTERNAL=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index fdaded29704..49f0916663d 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -134,3 +134,13 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0x80000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_32BIT=y +CONFIG_OR0_AM_1_GBYTES=y +CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 12721f8db42..e2ea71d11a7 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -92,3 +92,24 @@ CONFIG_E1000=y CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFFC00000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_4_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="WINDOW1" +CONFIG_BR1_OR1_BASE=0xF0000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_32BIT=y +CONFIG_OR1_AM_256_KBYTES=y +CONFIG_OR1_SETA_EXTERNAL=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index f1aa24683c0..7b17f602b6d 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -89,3 +89,29 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 22689ef0aca..9a20a0d0690 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -87,3 +87,29 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_15=y +CONFIG_OR1_XACS_EXTENDED=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_EHTR_8_CYCLE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 168564606c0..14104a441bf 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -119,3 +119,48 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_8BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_10=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0xE1000000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_PGS_LARGE=y +CONFIG_OR1_RST_ONE_CLOCK=y +CONFIG_OR1_SCY_4=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_OR1_CSCT_8_CYCLE=y +CONFIG_OR1_CST_ONE_CLOCK=y +CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="MRAM" +CONFIG_BR2_OR2_BASE=0xE2000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_SCY_7=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="CPLD" +CONFIG_BR3_OR3_BASE=0xE3000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_32_KBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_1=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 088dee63ba0..6740c4c8a97 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -143,3 +143,45 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_BCH=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_64_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PAXE" +CONFIG_BR3_OR3_BASE=0xA0000000 +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_ELBC_BR4_OR4=y +CONFIG_BR4_OR4_NAME="BFTIC3" +CONFIG_BR4_OR4_BASE=0xB0000000 +CONFIG_BR4_PORTSIZE_8BIT=y +CONFIG_OR4_AM_256_MBYTES=y +CONFIG_OR4_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR4_CSNT_EARLIER=y +CONFIG_OR4_EAD_EXTRA=y +CONFIG_OR4_SCY_2=y +CONFIG_OR4_TRLX_RELAXED=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 64ea83fd128..182fa477f88 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -115,3 +115,35 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_64_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="PAXE" +CONFIG_BR3_OR3_BASE=0xA0000000 +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 3a88b6a0276..678900d05ce 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -130,3 +130,45 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_SCY_4=y +CONFIG_OR3_EHTR_NORMAL=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index c818d7e4a12..49780b4b19b 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -116,3 +116,37 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 640e0c7c3c3..9a57e43d784 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -120,3 +120,33 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_NS16550=y CONFIG_BCH=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_SCY_5=y +CONFIG_OR3_EHTR_NORMAL=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 81579c6b02f..78f7de9899a 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -130,3 +130,45 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_SCY_4=y +CONFIG_OR3_EHTR_NORMAL=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 709947b5391..7256750ea0b 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -133,3 +133,40 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_UPMA=y +CONFIG_BR2_PORTSIZE_16BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_3=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index b44e04e1ae2..ec2e30709ca 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -78,3 +78,32 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFC000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_64_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_4=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="SJA1000" +CONFIG_BR1_OR1_BASE=0xFBFF0000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_EHTR_1_CYCLE=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="CPLD" +CONFIG_BR2_OR2_BASE=0xFBFF8000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_32_KBYTES=y +CONFIG_OR2_SCY_4=y +CONFIG_OR2_EHTR_1_CYCLE=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 6f407d56d56..453f85a0e33 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -89,3 +89,17 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 9c0b30f446c..b3046156302 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -89,3 +89,17 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 05361f76fcb..4ec51af9f2e 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -67,3 +67,17 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFF800000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 196c44470a2..a806e9957f7 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index c407bed189d..3687a28fc3a 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 1128950ace2..4231a431b88 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index f0b2c44efb1..afb991ce1e2 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -91,3 +91,26 @@ CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_XAM_SET=y +CONFIG_OR1_EHTR_NORMAL=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 10a32178f13..2b16ceb5242 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -131,3 +131,40 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_UPMA=y +CONFIG_BR2_PORTSIZE_16BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_3=y +CONFIG_OR3_TRLX_RELAXED=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 6fada9bdf70..07666c3b50b 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -116,3 +116,37 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 1eb21e0e5af..627bf2febf3 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -130,3 +130,48 @@ CONFIG_SYS_FLASH_CFI=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF0000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_256_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="KMBEC_FPGA" +CONFIG_BR1_OR1_BASE=0xE8000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_128_MBYTES=y +CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_OR1_EAD_EXTRA=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="APP1" +CONFIG_BR2_OR2_BASE=0xA0000000 +CONFIG_BR2_MACHINE_GPCM=y +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_256_MBYTES=y +CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_2=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="APP2" +CONFIG_BR3_OR3_BASE=0xB0000000 +CONFIG_BR3_MACHINE_GPCM=y +CONFIG_BR3_PORTSIZE_8BIT=y +CONFIG_OR3_AM_256_MBYTES=y +CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_SCY_2=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_4_CYCLE=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 1df5195e977..365c4ea8587 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -95,3 +95,48 @@ CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_32_MBYTES=y +CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_5=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="NAND" +CONFIG_BR1_OR1_BASE=0x61000000 +CONFIG_BR1_ERRORCHECKING_BOTH=y +CONFIG_BR1_MACHINE_FCM=y +CONFIG_BR1_PORTSIZE_8BIT=y +CONFIG_OR1_AM_32_KBYTES=y +CONFIG_OR1_BCTLD_NOT_ASSERTED=y +CONFIG_OR1_RST_ONE_CLOCK=y +CONFIG_OR1_SCY_2=y +CONFIG_OR1_TRLX_RELAXED=y +CONFIG_OR1_CHT_TWO_CLOCK=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="NVRAM" +CONFIG_BR2_OR2_BASE=0x60000000 +CONFIG_BR2_PORTSIZE_8BIT=y +CONFIG_OR2_AM_128_KBYTES=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_OR2_EAD_EXTRA=y +CONFIG_OR2_SCY_3=y +CONFIG_OR2_XACS_EXTENDED=y +CONFIG_OR2_TRLX_RELAXED=y +CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_ELBC_BR3_OR3=y +CONFIG_BR3_OR3_NAME="SRAM" +CONFIG_BR3_OR3_BASE=0x62000000 +CONFIG_BR3_PORTSIZE_16BIT=y +CONFIG_OR3_AM_32_MBYTES=y +CONFIG_OR3_CSNT_EARLIER=y +CONFIG_OR3_EAD_EXTRA=y +CONFIG_OR3_SCY_15=y +CONFIG_OR3_XACS_EXTENDED=y +CONFIG_OR3_TRLX_RELAXED=y +CONFIG_OR3_EHTR_8_CYCLE=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 9336dfac5cb..072674cbeb6 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -94,3 +94,24 @@ CONFIG_TSEC_ENET=y CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xF8000000 +CONFIG_BR0_MACHINE_GPCM=y +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_128_MBYTES=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_EAD_EXTRA=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_XAM_SET=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="WINDOW1" +CONFIG_BR1_OR1_BASE=0xF0000000 +CONFIG_BR1_MACHINE_GPCM=y +CONFIG_BR1_PORTSIZE_32BIT=y +CONFIG_OR1_AM_256_KBYTES=y +CONFIG_OR1_SETA_EXTERNAL=y diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c index 30c3308940e..099d86427c5 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_spl.c +++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c @@ -14,6 +14,10 @@ #include <asm/fsl_lbc.h> #include <nand.h>
+#ifdef CONFIG_MPC83xx +#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h" +#endif + #define WINDOW_SIZE 8192
static void nand_wait(void) diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 185f6490d7c..cd78836bcd5 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -175,9 +175,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ @@ -191,9 +188,6 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* 0xFFFF8396 */
#ifdef CONFIG_VSC7385_ENET @@ -201,9 +195,6 @@ /* VSC7385 Base address on CS2 */ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385_BASE */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) /* 0xFFFE09FF */ /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 40b0264dbe4..93b553c9050 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -219,14 +219,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-/* NAND */ -#define CONFIG_SYS_BR0_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) - -/* FLASH */ -#define CONFIG_SYS_BR1_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM @@ -235,9 +227,6 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -/* BCSR */ -#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* Vitesse 7385 */
@@ -247,9 +236,6 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#endif
diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 390ee4eb265..18e056e1b24 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -188,14 +188,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-/* FLASH*/ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) - /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM @@ -204,9 +196,6 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -/* BCSR */ -#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET @@ -215,9 +204,6 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#endif
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 97b66415c9b..708829dae80 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -177,13 +177,7 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
-/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
/* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index fd884a1e654..c66e33a247e 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 41b02231352..ed47bcd5b42 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -133,9 +133,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ @@ -148,9 +145,6 @@ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */
-/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* * Windows to access PIB via local bus @@ -163,17 +157,11 @@ * CS2 on Local Bus, to PIB */
-/* PIB1 */ -#define CONFIG_SYS_BR2_PRELIM (0xF8008000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* * CS3 on Local Bus, to PIB */
-/* PIB2 */ -#define CONFIG_SYS_BR3_PRELIM (0xF8010000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* * Serial Port diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 4cda1589b67..3e0907dae4e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -123,9 +123,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -148,9 +145,6 @@ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */
-/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 7f906c38d89..e401c29d6b7 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -123,10 +123,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
@@ -147,10 +143,6 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) - #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ @@ -192,10 +184,6 @@ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 */
-/* SDRAM */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_SDRAM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_SDRAM_XAM | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) | OR_SDRAM_EAD) - /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index e90d497f5ef..cc62fc32135 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -211,9 +211,6 @@ boards, we say we have two, but don't display a message if we find only one. */ * BRx, ORx, LBLAWBARx, and LBLAWARx */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* Vitesse 7385 */
@@ -221,18 +218,12 @@ boards, we say we have two, but don't display a message if we find only one. */
#ifdef CONFIG_VSC7385_ENET
-/* VSC7385 */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#endif
#define CONFIG_SYS_LED_BASE 0xF9000000
-/* LED */ -#define CONFIG_SYS_BR2_PRELIM (0xF9000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* Compact Flash */
@@ -240,9 +231,6 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_SYS_CF_BASE 0xF0000000
-/* CF */ -#define CONFIG_SYS_BR3_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_UPM_BI)
#endif
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e569e63741f..a244ae87a22 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -162,9 +162,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -178,9 +175,6 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* * NAND Flash on the Local Bus @@ -190,9 +184,6 @@
#define CONFIG_SYS_NAND_BASE 0xE0600000
-/* NAND */ -#define CONFIG_SYS_BR3_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST | OR_FCM_TRLX | OR_FCM_EHTR)
/* * Serial Port diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index c1898a53a6c..006279a58c3 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -188,9 +188,6 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -204,9 +201,6 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000
-/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
/* Vitesse 7385 */
@@ -214,9 +208,6 @@
#ifdef CONFIG_VSC7385_ENET
-/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#endif
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c76df2847d2..af03c037865 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -76,9 +76,6 @@
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0x80000000 | BR_MS_GPCM | BR_PS_32 | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_1GB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET)
/* disable remaining mappings */ #define CONFIG_SYS_BR1_PRELIM 0x00000000 diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index a7eb5f52953..e9cfeae64d8 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -70,15 +70,9 @@ #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFFC00000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_4MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
-/* WINDOW1 */ -#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 3fe72db188c..9318e6252ae 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -169,9 +169,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -185,9 +182,6 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
-/* FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 61f64ebbbc0..d86dda18fb1 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_SCY_10 | OR_GPCM_EHTR_SET | OR_GPCM_TRLX_SET | OR_GPCM_CSNT | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 @@ -163,9 +160,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64
-/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE1000000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_4 | OR_FCM_TRLX | OR_FCM_EHTR | OR_FCM_RST)
/* * MRAM setup @@ -175,9 +169,6 @@
#define CONFIG_SYS_OR_TIMING_MRAM
-/* MRAM */ -#define CONFIG_SYS_BR2_PRELIM (0xE2000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET)
/* * CPLD setup @@ -187,9 +178,6 @@
#define CONFIG_SYS_OR_TIMING_MRAM
-/* CPLD */ -#define CONFIG_SYS_BR3_PRELIM (0xE3000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET)
/* * HW-Watchdog diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 01f432548f4..5031a6c8bf4 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -108,9 +108,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -120,9 +117,6 @@ * PRIO1/PIGGY on the local bus CS1 */
-/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -336,9 +330,6 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256
-/* PAXE */ -#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * BFTIC3 on the local bus CS4 @@ -346,9 +337,6 @@ #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 #define CONFIG_SYS_BFTIC3_SIZE 256
-/* BFTIC3 */ -#define CONFIG_SYS_BR4_PRELIM (0xB0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR4_PRELIM (OR_AM_256MB| OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 84516bb9bb7..728c9b199f2 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -93,9 +93,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -105,9 +102,6 @@ * PRIO1/PIGGY on the local bus CS1 */
-/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -316,8 +310,5 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256
-/* PAXE */ -#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#endif /* CONFIG */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 678cb6a7cc7..f39dbe05b7e 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */
-/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -351,16 +345,10 @@ * Configuration for C2 on the local bus */
-/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
/* * Configuration for C3 on the local bus */
-/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
#endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 3e2e425c34b..19e415619a5 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */
-/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -345,8 +339,5 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */
-/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
#endif /* __CONFIG_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index ed221e23019..fe4763ce8ad 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -120,9 +120,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -132,9 +129,6 @@ * PRIO1/PIGGY on the local bus CS1 */
-/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -400,9 +394,6 @@ * */
-/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
/* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index c1ed71e2afe..9302d35949d 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */
-/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -347,12 +341,6 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */
-/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
-/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
#endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 406b6e78244..06c5923ae1d 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -112,9 +112,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -124,9 +121,6 @@ * PRIO1/PIGGY on the local bus CS1 */
-/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -389,13 +383,7 @@ * */
-/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB)
-/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET)
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 31bf9971ab2..cb7dabd9321 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -179,9 +179,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFC000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_4 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 @@ -196,18 +193,12 @@ */ #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
-/* SJA1000 */ -#define CONFIG_SYS_BR1_PRELIM (0xFBFF0000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_SCY_5 | OR_GPCM_EHTR_SET)
/* * CPLD on Local Bus */ #define CONFIG_SYS_CPLD_BASE 0xFBFF8000
-/* CPLD */ -#define CONFIG_SYS_BR2_PRELIM (0xFBFF8000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_SCY_4 | OR_GPCM_EHTR_SET)
/* * Serial Port diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 42a1e1682d2..98770ca0a64 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -98,9 +98,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ diff --git a/include/configs/strider.h b/include/configs/strider.h index 1519dad3217..dd89ee8c815 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -167,9 +167,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -183,9 +180,6 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
-/* FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 6aacbc2077e..a65b61bfbf8 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -110,9 +110,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -122,9 +119,6 @@ * PRIO1/PIGGY on the local bus CS1 */
-/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -342,13 +336,7 @@ * */
-/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB)
-/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET)
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index b11d49629ac..6084e8af605 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */
-/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -345,8 +339,5 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */
-/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
#endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 5c8f682d23a..b989f4eadea 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */
-/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* * Serial Port @@ -347,13 +341,7 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */
-/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
-/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 3a5bcf9c62f..4c5dad9dc26 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -153,25 +153,13 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
-/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0x61000000 | BR_PS_8 | BR_DECC_CHK_GEN | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CHT | OR_FCM_SCY_2 | OR_FCM_RST | OR_FCM_TRLX)
/* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
-/* NVRAM */ -#define CONFIG_SYS_BR2_PRELIM (0x60000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
-/* SRAM */ -#define CONFIG_SYS_BR3_PRELIM (0x62000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
/* * Serial Port diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index dd8aae51173..9b9c1ff54e2 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -70,15 +70,9 @@ #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
-/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF8000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
-/* WINDOW1 */ -#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
The MPC8308 has two I2C controllers, but no PCI controller.
Fix the register map layout for this SoC.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/Makefile | 2 ++ arch/powerpc/include/asm/immap_83xx.h | 42 +++++++++++++++++++++++++-- 2 files changed, 41 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index aa4affa911b..304029977e5 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -29,7 +29,9 @@ obj-y += interrupts.o obj-y += ecc.o obj-$(CONFIG_QE) += qe_io.o obj-$(CONFIG_FSL_SERDES) += serdes.o +ifndef CONFIG_ARCH_MPC8308 obj-$(CONFIG_PCI) += pci.o +endif obj-$(CONFIG_PCIE) += pcie.o obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 30bbd5671ba..d02da6495ce 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -714,7 +714,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t;
-#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) +#elif defined(CONFIG_ARCH_MPC8315) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ @@ -729,8 +729,8 @@ typedef struct immap { gpio83xx_t gpio[1]; /* General purpose I/O module */ u8 res0[0x1300]; ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res1[0x1300]; + fsl_i2c_t i2c[1]; /* I2C Controllers */ + u8 res1[0x1400]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ @@ -759,6 +759,42 @@ typedef struct immap { u8 res12[0x1CF00]; } immap_t;
+#elif defined(CONFIG_ARCH_MPC8308) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[1]; /* Global Timers Module */ + u8 res0[0x100]; + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + gpio83xx_t gpio[1]; /* General purpose I/O module */ + u8 res1[0x1300]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res2[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res3[0x900]; + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ + u8 res4[0x1000]; + spi8xxx_t spi; /* Serial Peripheral Interface */ + u8 res5[0x1000]; + pex83xx_t pciexp[1]; /* PCI Express Controller */ + u8 res6[0x19000]; + usb83xx_t usb[1]; /* USB DR Controller */ + tsec83xx_t tsec[2]; + u8 res7[0x6000]; + tdmdmac83xx_t tdmdmac; /* TDM DMAC */ + sdhc83xx_t sdhc; /* SDHC Controller */ + u8 res8[0xb4000]; + serdes83xx_t serdes[1]; /* SerDes Registers */ + u8 res9[0x1CF00]; +} immap_t; + #elif defined(CONFIG_ARCH_MPC837X) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */
DM serial drivers on PowerPC determine their clock frequency via the get_serial_clock function. This function is not Implemented yet for MPC83xx.
This patch Implements the function so that DM serial drivers work on MPC83xx.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/speed.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index e870a23103b..e118a10fa8b 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -516,6 +516,11 @@ ulong get_ddr_freq(ulong dummy) return gd->mem_clk; }
+int get_serial_clock(void) +{ + return get_bus_freq(0); +} + static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char buf[32];
Replace the hard-coded CONFIG_SYS_NS16550_CLK value for the FDT fixup with the previously introduced get_serial_clock function
This will make it possible to activate DM for serial devices on MPC83xx later on.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/fdt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index cfd391b78ab..b487e31cc0f 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -116,8 +116,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif
#ifdef CONFIG_SYS_NS16550 - do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + do_fixup_by_compat_u32(blob, "ns16550", + "clock-frequency", get_serial_clock(), 1); #endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
Remove the last instances of the CONFIG_MPC83xx symbol.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- include/configs/hrcon.h | 1 - include/configs/strider.h | 1 - 2 files changed, 2 deletions(-)
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 9318e6252ae..4001a0a16b0 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -12,7 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
diff --git a/include/configs/strider.h b/include/configs/strider.h index dd89ee8c815..94164de06c2 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -12,7 +12,6 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
The MPC85xx GPIO driver was converted to handle a broader range of SoCs.
Prepare the MPC83xx code for usage of this driver.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index b5ec50ba44c..385d651d200 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -17,7 +17,15 @@
#define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS)
+struct mpc8xxx_gpio_plat { + ulong addr; + unsigned long size; + uint ngpios; +}; + +#ifndef DM_GPIO void mpc83xx_gpio_init_f(void); void mpc83xx_gpio_init_r(void); +#endif /* DM_GPIO */
#endif /* MPC83XX_GPIO_H_ */
Mirate the HID configuration settings to Kconfig.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/hid/Kconfig | 565 ++++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/hid/hid.h | 72 ++++ arch/powerpc/cpu/mpc83xx/start.S | 1 + configs/MPC8308RDB_defconfig | 4 + configs/MPC8313ERDB_33_defconfig | 4 + configs/MPC8313ERDB_66_defconfig | 4 + configs/MPC8313ERDB_NAND_33_defconfig | 4 + configs/MPC8313ERDB_NAND_66_defconfig | 4 + configs/MPC8315ERDB_defconfig | 4 + configs/MPC8323ERDB_defconfig | 3 + configs/MPC832XEMDS_ATM_defconfig | 3 + configs/MPC832XEMDS_HOST_33_defconfig | 3 + configs/MPC832XEMDS_HOST_66_defconfig | 3 + configs/MPC832XEMDS_SLAVE_defconfig | 3 + configs/MPC832XEMDS_defconfig | 3 + configs/MPC8349EMDS_PCI64_defconfig | 3 + configs/MPC8349EMDS_SDRAM_defconfig | 3 + configs/MPC8349EMDS_SLAVE_defconfig | 3 + configs/MPC8349EMDS_defconfig | 3 + configs/MPC8349ITXGP_defconfig | 2 + configs/MPC8349ITX_LOWBOOT_defconfig | 2 + configs/MPC8349ITX_defconfig | 2 + configs/MPC837XEMDS_HOST_defconfig | 3 + configs/MPC837XEMDS_SLAVE_defconfig | 3 + configs/MPC837XEMDS_defconfig | 3 + configs/MPC837XERDB_SLAVE_defconfig | 3 + configs/MPC837XERDB_defconfig | 3 + configs/TQM834x_defconfig | 2 + configs/caddy2_defconfig | 3 + configs/hrcon_defconfig | 4 + configs/hrcon_dh_defconfig | 4 + configs/ids8313_defconfig | 3 + configs/kmcoge5ne_defconfig | 3 + configs/kmeter1_defconfig | 3 + configs/kmopti2_defconfig | 3 + configs/kmsupx5_defconfig | 3 + configs/kmtegr1_defconfig | 3 + configs/kmtepr2_defconfig | 3 + configs/kmvect1_defconfig | 3 + configs/mpc8308_p1m_defconfig | 4 + configs/sbc8349_PCI_33_defconfig | 3 + configs/sbc8349_PCI_66_defconfig | 3 + configs/sbc8349_defconfig | 3 + configs/strider_con_defconfig | 4 + configs/strider_con_dp_defconfig | 4 + configs/strider_cpu_defconfig | 4 + configs/strider_cpu_dp_defconfig | 4 + configs/suvd3_defconfig | 3 + configs/tuge1_defconfig | 3 + configs/tuxx1_defconfig | 3 + configs/ve8313_defconfig | 3 + configs/vme8349_defconfig | 3 + include/configs/MPC8308RDB.h | 9 - include/configs/MPC8313ERDB_NAND.h | 7 - include/configs/MPC8313ERDB_NOR.h | 7 - include/configs/MPC8315ERDB.h | 9 - include/configs/MPC8323ERDB.h | 8 - include/configs/MPC832XEMDS.h | 8 - include/configs/MPC8349EMDS.h | 11 - include/configs/MPC8349EMDS_SDRAM.h | 11 - include/configs/MPC8349ITX.h | 5 - include/configs/MPC837XEMDS.h | 8 - include/configs/MPC837XERDB.h | 8 - include/configs/TQM834x.h | 6 - include/configs/caddy2.h | 6 - include/configs/hrcon.h | 9 - include/configs/ids8313.h | 7 - include/configs/kmcoge5ne.h | 8 - include/configs/kmeter1.h | 8 - include/configs/kmopti2.h | 8 - include/configs/kmsupx5.h | 8 - include/configs/kmtegr1.h | 8 - include/configs/kmtepr2.h | 8 - include/configs/kmvect1.h | 8 - include/configs/mpc8308_p1m.h | 9 - include/configs/sbc8349.h | 11 - include/configs/strider.h | 9 - include/configs/suvd3.h | 8 - include/configs/tuge1.h | 8 - include/configs/tuxx1.h | 8 - include/configs/ve8313.h | 6 - include/configs/vme8349.h | 6 - scripts/config_whitelist.txt | 3 - 84 files changed, 795 insertions(+), 243 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/hid/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/hid/hid.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 474572f245e..5fb4228076e 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -286,6 +286,7 @@ source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig" +source "arch/powerpc/cpu/mpc83xx/hid/Kconfig"
menu "Legacy options"
diff --git a/arch/powerpc/cpu/mpc83xx/hid/Kconfig b/arch/powerpc/cpu/mpc83xx/hid/Kconfig new file mode 100644 index 00000000000..c367ad2ce15 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/hid/Kconfig @@ -0,0 +1,565 @@ +menu "HID setup" + +menu "HID0 initial" + +config HID0_INIT_EMCP + bool "Enable machine check int on mcp" + +config HID0_INIT_ECPE + bool "Enable cache parity errors" + +config HID0_INIT_EBA + bool "Enable address parity checking" + +config HID0_INIT_EBD + bool "Enable data parity checking" + +choice + prompt "HID0 clock configuration" + +config HID0_INIT_CLKOUT_OFF + bool "Clock output off" + +config HID0_INIT_CLKOUT_CORE_HALF + bool "Core clock / 2" + +config HID0_INIT_CLKOUT_CORE + bool "Core clock" + +config HID0_INIT_CLKOUT_BUS + bool "Bus clock" + +endchoice + +config HID0_INIT_PAR + bool "Disable precharge of artry_out" + +config HID0_INIT_DOZE + bool "Enable doze mode" + +config HID0_INIT_NAP + bool "Enable nap mode" + +config HID0_INIT_SLEEP + bool "Enable sleep mode" + +config HID0_INIT_DPM + bool "Enable dynamic power management" + +config HID0_INIT_ICE + bool "Enable instruction cache" + +config HID0_INIT_DCE + bool "Enable data cache" + +config HID0_INIT_ILOCK + bool "Lock instruction cache" + +config HID0_INIT_DLOCK + bool "Lock data cache" + +config HID0_INIT_ICFI + bool "Flash invalidate instruction cache" + +config HID0_INIT_DCFI + bool "Flash invalidate data cache" + +config HID0_INIT_IFEM + bool "Enable m bit on bus for instruction fetches" + +config HID0_INIT_DECAREN + bool "Decrementer auto reload" + +config HID0_INIT_FBIOB + bool "Force indirect branch on the bus" + +config HID0_INIT_ABE + bool "Enable address broadcast" + +config HID0_INIT_NOOPTI + bool "No-op data cache touch intructions" + +endmenu + +menu "HID0 final" + +config HID0_FINAL_EMCP + bool "Enable machine check int on mcp" + +config HID0_FINAL_ECPE + bool "Enable cache parity errors" + +config HID0_FINAL_EBA + bool "Enable address parity checking" + +config HID0_FINAL_EBD + bool "Enable data parity checking" + +choice + prompt "HID0 clock configuration" + +config HID0_FINAL_CLKOUT_OFF + bool "Clock output off" + +config HID0_FINAL_CLKOUT_CORE_HALF + bool "Core clock / 2" + +config HID0_FINAL_CLKOUT_CORE + bool "Core clock" + +config HID0_FINAL_CLKOUT_BUS + bool "Bus clock" + +endchoice + +config HID0_FINAL_PAR + bool "Disable precharge of artry_out" + +config HID0_FINAL_DOZE + bool "Enable doze mode" + +config HID0_FINAL_NAP + bool "Enable nap mode" + +config HID0_FINAL_SLEEP + bool "Enable sleep mode" + +config HID0_FINAL_DPM + bool "Enable dynamic power management" + +config HID0_FINAL_ICE + bool "Enable instruction cache" + +config HID0_FINAL_DCE + bool "Enable data cache" + +config HID0_FINAL_ILOCK + bool "Lock instruction cache" + +config HID0_FINAL_DLOCK + bool "Lock data cache" + +config HID0_FINAL_ICFI + bool "Flash invalidate instruction cache" + +config HID0_FINAL_DCFI + bool "Flash invalidate data cache" + +config HID0_FINAL_IFEM + bool "Enable m bit on bus for instruction fetches" + +config HID0_FINAL_DECAREN + bool "Decrementer auto reload" + +config HID0_FINAL_FBIOB + bool "Force indirect branch on the bus" + +config HID0_FINAL_ABE + bool "Enable address broadcast" + +config HID0_FINAL_NOOPTI + bool "No-op data cache touch intructions" + +endmenu + +config HID0_INIT_EMCP_BIT + hex + default 0x0 if !HID0_INIT_EMCP + default 0x80000000 if HID0_INIT_EMCP + +config HID0_INIT_ECPE_BIT + hex + default 0x0 if !HID0_INIT_ECPE + default 0x40000000 if HID0_INIT_ECPE + +config HID0_INIT_EBA_BIT + hex + default 0x0 if !HID0_INIT_EBA + default 0x20000000 if HID0_INIT_EBA + +config HID0_INIT_EBD_BIT + hex + default 0x0 if !HID0_INIT_EBD + default 0x10000000 if HID0_INIT_EBD + +config HID0_INIT_CLKOUT + hex + default 0x0 if HID0_INIT_CLKOUT_OFF + default 0x8000000 if HID0_INIT_CLKOUT_CORE_HALF + default 0x2000000 if HID0_INIT_CLKOUT_CORE + default 0xa000000 if HID0_INIT_CLKOUT_BUS + +config HID0_INIT_PAR_BIT + hex + default 0x0 if !HID0_INIT_PAR + default 0x1000000 if HID0_INIT_PAR + +config HID0_INIT_DOZE_BIT + hex + default 0x0 if !HID0_INIT_DOZE + default 0x800000 if HID0_INIT_DOZE + +config HID0_INIT_NAP_BIT + hex + default 0x0 if !HID0_INIT_NAP + default 0x400000 if HID0_INIT_NAP + +config HID0_INIT_SLEEP_BIT + hex + default 0x0 if !HID0_INIT_SLEEP + default 0x200000 if HID0_INIT_SLEEP + +config HID0_INIT_DPM_BIT + hex + default 0x0 if !HID0_INIT_DPM + default 0x100000 if HID0_INIT_DPM + +config HID0_INIT_ICE_BIT + hex + default 0x0 if !HID0_INIT_ICE + default 0x8000 if HID0_INIT_ICE + +config HID0_INIT_DCE_BIT + hex + default 0x0 if !HID0_INIT_DCE + default 0x4000 if HID0_INIT_DCE + +config HID0_INIT_ILOCK_BIT + hex + default 0x0 if !HID0_INIT_ILOCK + default 0x2000 if HID0_INIT_ILOCK + +config HID0_INIT_DLOCK_BIT + hex + default 0x0 if !HID0_INIT_DLOCK + default 0x1000 if HID0_INIT_DLOCK + +config HID0_INIT_ICFI_BIT + hex + default 0x0 if !HID0_INIT_ICFI + default 0x800 if HID0_INIT_ICFI + +config HID0_INIT_DCFI_BIT + hex + default 0x0 if !HID0_INIT_DCFI + default 0x400 if HID0_INIT_DCFI + +config HID0_INIT_IFEM_BIT + hex + default 0x0 if !HID0_INIT_IFEM + default 0x80 if HID0_INIT_IFEM + +config HID0_INIT_DECAREN_BIT + hex + default 0x0 if !HID0_INIT_DECAREN + default 0x40 if HID0_INIT_DECAREN + +config HID0_INIT_FBIOB_BIT + hex + default 0x0 if !HID0_INIT_FBIOB + default 0x10 if HID0_INIT_FBIOB + +config HID0_INIT_ABE_BIT + hex + default 0x0 if !HID0_INIT_ABE + default 0x8 if HID0_INIT_ABE + +config HID0_INIT_NOOPTI_BIT + hex + default 0x0 if !HID0_INIT_NOOPTI + default 0x1 if HID0_INIT_NOOPTI + +config HID0_FINAL_EMCP_BIT + hex + default 0x0 if !HID0_FINAL_EMCP + default 0x80000000 if HID0_FINAL_EMCP + +config HID0_FINAL_ECPE_BIT + hex + default 0x0 if !HID0_FINAL_ECPE + default 0x40000000 if HID0_FINAL_ECPE + +config HID0_FINAL_EBA_BIT + hex + default 0x0 if !HID0_FINAL_EBA + default 0x20000000 if HID0_FINAL_EBA + +config HID0_FINAL_EBD_BIT + hex + default 0x0 if !HID0_FINAL_EBD + default 0x10000000 if HID0_FINAL_EBD + +config HID0_FINAL_CLKOUT + hex + default 0x0 if HID0_FINAL_CLKOUT_OFF + default 0x8000000 if HID0_FINAL_CLKOUT_CORE_HALF + default 0x2000000 if HID0_FINAL_CLKOUT_CORE + default 0xa000000 if HID0_FINAL_CLKOUT_BUS + +config HID0_FINAL_SBCLK_BIT + hex + default 0x0 if !HID0_FINAL_SBCLK + default 0x8000000 if HID0_FINAL_SBCLK + +config HID0_FINAL_ECLK_BIT + hex + default 0x0 if !HID0_FINAL_ECLK + default 0x2000000 if HID0_FINAL_ECLK + +config HID0_FINAL_PAR_BIT + hex + default 0x0 if !HID0_FINAL_PAR + default 0x1000000 if HID0_FINAL_PAR + +config HID0_FINAL_DOZE_BIT + hex + default 0x0 if !HID0_FINAL_DOZE + default 0x800000 if HID0_FINAL_DOZE + +config HID0_FINAL_NAP_BIT + hex + default 0x0 if !HID0_FINAL_NAP + default 0x400000 if HID0_FINAL_NAP + +config HID0_FINAL_SLEEP_BIT + hex + default 0x0 if !HID0_FINAL_SLEEP + default 0x200000 if HID0_FINAL_SLEEP + +config HID0_FINAL_DPM_BIT + hex + default 0x0 if !HID0_FINAL_DPM + default 0x100000 if HID0_FINAL_DPM + +config HID0_FINAL_ICE_BIT + hex + default 0x0 if !HID0_FINAL_ICE + default 0x8000 if HID0_FINAL_ICE + +config HID0_FINAL_DCE_BIT + hex + default 0x0 if !HID0_FINAL_DCE + default 0x4000 if HID0_FINAL_DCE + +config HID0_FINAL_ILOCK_BIT + hex + default 0x0 if !HID0_FINAL_ILOCK + default 0x2000 if HID0_FINAL_ILOCK + +config HID0_FINAL_DLOCK_BIT + hex + default 0x0 if !HID0_FINAL_DLOCK + default 0x1000 if HID0_FINAL_DLOCK + +config HID0_FINAL_ICFI_BIT + hex + default 0x0 if !HID0_FINAL_ICFI + default 0x800 if HID0_FINAL_ICFI + +config HID0_FINAL_DCFI_BIT + hex + default 0x0 if !HID0_FINAL_DCFI + default 0x400 if HID0_FINAL_DCFI + +config HID0_FINAL_IFEM_BIT + hex + default 0x0 if !HID0_FINAL_IFEM + default 0x80 if HID0_FINAL_IFEM + +config HID0_FINAL_DECAREN_BIT + hex + default 0x0 if !HID0_FINAL_DECAREN + default 0x40 if HID0_FINAL_DECAREN + +config HID0_FINAL_FBIOB_BIT + hex + default 0x0 if !HID0_FINAL_FBIOB + default 0x10 if HID0_FINAL_FBIOB + +config HID0_FINAL_ABE_BIT + hex + default 0x0 if !HID0_FINAL_ABE + default 0x8 if HID0_FINAL_ABE + +config HID0_FINAL_NOOPTI_BIT + hex + default 0x0 if !HID0_FINAL_NOOPTI + default 0x1 if HID0_FINAL_NOOPTI + +menu "HID2" + +config HID2_LET + bool "True little-endian mode" + +config HID2_IFEB + bool "Instruction fetch burst extension" + +config HID2_MESISTATE + bool "MESI state enable" + +config HID2_IFEC + bool "Instruction fetch cancel extension" + +config HID2_EBQS + bool "BIU queue sharing" + +config HID2_EBPX + bool "BIU pipeline extension" + +if !ARCH_MPC8360 + +config HID2_ELRW + bool "Weighted LRU" + +config HID2_NOKS + bool "No kill for snoop" + +endif + +config HID2_HBE + bool "High bat enable" + +choice + prompt "Instruction cache way-lock" + +config HID2_IWLCK_NONE + bool "No ways locked" + +config HID2_IWLCK_0 + bool "Way 0 locked" + +config HID2_IWLCK_1 + bool "Way 0 through 1 locked" + +config HID2_IWLCK_2 + bool "Way 0 through 2 locked" + +if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + +config HID2_IWLCK_3 + bool "Way 0 through 3 locked" + +config HID2_IWLCK_4 + bool "Way 0 through 4 locked" + +config HID2_IWLCK_5 + bool "Way 0 through 5 locked" + +config HID2_IWLCK_6 + bool "Way 0 through 6 locked" + +endif + +endchoice + +config HID2_ICWP + bool "Instruction cache way protection" + +choice + prompt "Data cache way-lock" + +config HID2_DWLCK_NONE + bool "No ways locked" + +config HID2_DWLCK_0 + bool "Way 0 locked" + +config HID2_DWLCK_1 + bool "Way 0 through 1 locked" + +config HID2_DWLCK_2 + bool "Way 0 through 2 locked" + +if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + +config HID2_DWLCK_3 + bool "Way 0 through 3 locked" + +config HID2_DWLCK_4 + bool "Way 0 through 4 locked" + +config HID2_DWLCK_5 + bool "Way 0 through 5 locked" + +config HID2_DWLCK_6 + bool "Way 0 through 6 locked" + +endif + +endchoice + +config HID2_LET_BIT + hex + default 0x0 if !HID2_LET + default 0x8000000 if HID2_LET + +config HID2_IFEB_BIT + hex + default 0x0 if !HID2_IFEB + default 0x4000000 if HID2_IFEB + +config HID2_MESISTATE_BIT + hex + default 0x0 if !HID2_MESISTATE + default 0x1000000 if HID2_MESISTATE + +config HID2_IFEC_BIT + hex + default 0x0 if !HID2_IFEC + default 0x800000 if HID2_IFEC + +config HID2_EBQS_BIT + hex + default 0x0 if !HID2_EBQS + default 0x400000 if HID2_EBQS + +config HID2_EBPX_BIT + hex + default 0x0 if !HID2_EBPX + default 0x200000 if HID2_EBPX + +config HID2_ELRW_BIT + hex + default 0x0 if !HID2_ELRW + default 0x100000 if HID2_ELRW + +config HID2_NOKS_BIT + hex + default 0x0 if !HID2_NOKS + default 0x80000 if HID2_NOKS + +config HID2_HBE_BIT + hex + default 0x0 if !HID2_HBE + default 0x40000 if HID2_HBE + +config HID2_IWLCK + hex + default 0x0 if HID2_IWLCK_NONE + default 0x2000 if HID2_IWLCK_0 + default 0x4000 if HID2_IWLCK_1 + default 0x6000 if HID2_IWLCK_2 + default 0x8000 if HID2_IWLCK_3 + default 0xA000 if HID2_IWLCK_4 + default 0xC000 if HID2_IWLCK_5 + default 0xE000 if HID2_IWLCK_6 + +config HID2_ICWP_BIT + hex + default 0x0 if !HID2_ICWP + default 0x1000 if HID2_ICWP + +config HID2_DWLCK + hex + default 0x0 if HID2_DWLCK_NONE + default 0x20 if HID2_DWLCK_0 + default 0x40 if HID2_DWLCK_1 + default 0x60 if HID2_DWLCK_2 + default 0x80 if HID2_DWLCK_3 + default 0xA0 if HID2_DWLCK_4 + default 0xC0 if HID2_DWLCK_5 + default 0xE0 if HID2_DWLCK_6 + +endmenu + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/hid/hid.h b/arch/powerpc/cpu/mpc83xx/hid/hid.h new file mode 100644 index 00000000000..9f5260c012c --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/hid/hid.h @@ -0,0 +1,72 @@ +#define CONFIG_SYS_HID0_FINAL ( \ + CONFIG_HID0_FINAL_ABE_BIT |\ + CONFIG_HID0_FINAL_CLKOUT |\ + CONFIG_HID0_FINAL_DCE_BIT |\ + CONFIG_HID0_FINAL_DCFI_BIT |\ + CONFIG_HID0_FINAL_DECAREN_BIT |\ + CONFIG_HID0_FINAL_DLOCK_BIT |\ + CONFIG_HID0_FINAL_DOZE_BIT |\ + CONFIG_HID0_FINAL_DPM_BIT |\ + CONFIG_HID0_FINAL_EBA_BIT |\ + CONFIG_HID0_FINAL_EBD_BIT |\ + CONFIG_HID0_FINAL_ECLK_BIT |\ + CONFIG_HID0_FINAL_ECPE_BIT |\ + CONFIG_HID0_FINAL_EMCP_BIT |\ + CONFIG_HID0_FINAL_FBIOB_BIT |\ + CONFIG_HID0_FINAL_ICE_BIT |\ + CONFIG_HID0_FINAL_ICFI_BIT |\ + CONFIG_HID0_FINAL_IFEM_BIT |\ + CONFIG_HID0_FINAL_ILOCK_BIT |\ + CONFIG_HID0_FINAL_NAP_BIT |\ + CONFIG_HID0_FINAL_NOOPTI_BIT |\ + CONFIG_HID0_FINAL_PAR_BIT |\ + CONFIG_HID0_FINAL_SBCLK_BIT |\ + CONFIG_HID0_FINAL_SLEEP_BIT \ +) + +#define CONFIG_SYS_HID0_INIT ( \ + CONFIG_HID0_INIT_ABE_BIT |\ + CONFIG_HID0_INIT_CLKOUT |\ + CONFIG_HID0_INIT_DCE_BIT |\ + CONFIG_HID0_INIT_DCFI_BIT |\ + CONFIG_HID0_INIT_DECAREN_BIT |\ + CONFIG_HID0_INIT_DLOCK_BIT |\ + CONFIG_HID0_INIT_DOZE_BIT |\ + CONFIG_HID0_INIT_DPM_BIT |\ + CONFIG_HID0_INIT_EBA_BIT |\ + CONFIG_HID0_INIT_EBD_BIT |\ + CONFIG_HID0_INIT_ECPE_BIT |\ + CONFIG_HID0_INIT_EMCP_BIT |\ + CONFIG_HID0_INIT_FBIOB_BIT |\ + CONFIG_HID0_INIT_ICE_BIT |\ + CONFIG_HID0_INIT_ICFI_BIT |\ + CONFIG_HID0_INIT_IFEM_BIT |\ + CONFIG_HID0_INIT_ILOCK_BIT |\ + CONFIG_HID0_INIT_NAP_BIT |\ + CONFIG_HID0_INIT_NOOPTI_BIT |\ + CONFIG_HID0_INIT_PAR_BIT |\ + CONFIG_HID0_INIT_SLEEP_BIT \ +) + +#ifdef CONFIG_TARGET_IDS8313 +/* IDS8313 defines a reserved bit; keep to not break compatibility */ +#define CONFIG_HID2_SPECIAL 0x00020000 +#else +#define CONFIG_HID2_SPECIAL 0x0 +#endif + +#define CONFIG_SYS_HID2 ( \ + CONFIG_HID2_LET_BIT |\ + CONFIG_HID2_IFEB_BIT |\ + CONFIG_HID2_MESISTATE_BIT |\ + CONFIG_HID2_IFEC_BIT |\ + CONFIG_HID2_EBQS_BIT |\ + CONFIG_HID2_EBPX_BIT |\ + CONFIG_HID2_ELRW_BIT |\ + CONFIG_HID2_NOKS_BIT |\ + CONFIG_HID2_HBE_BIT |\ + CONFIG_HID2_IWLCK |\ + CONFIG_HID2_ICWP_BIT |\ + CONFIG_HID2_DWLCK |\ + CONFIG_HID2_SPECIAL \ +) diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 95e4b906a76..4df22f64fec 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -26,6 +26,7 @@
#include "hrcw/hrcw.h" #include "bats/bats.h" +#include "hid/hid.h"
/* We don't want the MMU yet. */ diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index c38ac328d2a..e674848a6c4 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -58,6 +58,10 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xF0000000 CONFIG_LBLAW2_NAME="VSC7385" CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 1588adf3d66..732beab2e1c 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -73,6 +73,10 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xFA000000 CONFIG_LBLAW3_NAME="BCSR" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index 2425256ee30..f2ec6cc7db0 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -72,6 +72,10 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xFA000000 CONFIG_LBLAW3_NAME="BCSR" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index c874f6188f7..7a308f144fe 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -75,6 +75,10 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xFA000000 CONFIG_LBLAW3_NAME="BCSR" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index 198b373c3e5..e4de72dbdf1 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -74,6 +74,10 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xFA000000 CONFIG_LBLAW3_NAME="BCSR" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index b9539893ff7..d19e7977311 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -76,6 +76,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="NAND" CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 64e6f58f38c..19425abb1d5 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -70,6 +70,9 @@ CONFIG_LBLAW0=y CONFIG_LBLAW0_BASE=0xFE000000 CONFIG_LBLAW0_NAME="FLASH" CONFIG_LBLAW0_LENGTH_32_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index ffc82260ec3..807d3e391a3 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -68,6 +68,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF8008000 CONFIG_LBLAW3_NAME="PIB" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 911f62de653..e328deb9fe4 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -88,6 +88,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF8008000 CONFIG_LBLAW3_NAME="PIB" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 7dd02a95c92..d5bf354eeca 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -88,6 +88,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF8008000 CONFIG_LBLAW3_NAME="PIB" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index 3e3c82b2ef5..9d9d9051189 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -85,6 +85,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF8008000 CONFIG_LBLAW3_NAME="PIB" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index 4cfa01074d1..518f7114d79 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -68,6 +68,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF8008000 CONFIG_LBLAW3_NAME="PIB" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index a29d3268f79..fef4f343579 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -53,6 +53,9 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE2400000 CONFIG_LBLAW1_NAME="BCSR" CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index e3058f0b5e8..d0774431a39 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -57,6 +57,9 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xF0000000 CONFIG_LBLAW2_NAME="SDRAM" CONFIG_LBLAW2_LENGTH_64_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_ELBC_BR0_OR0=y CONFIG_BR0_OR0_NAME="FLASH" CONFIG_BR0_OR0_BASE=0xFE000000 diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index d45b6489b47..429d273e4e9 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -51,6 +51,9 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE2400000 CONFIG_LBLAW1_NAME="BCSR" CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index e3ca6811ccf..8c09cd90eec 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -53,6 +53,9 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE2400000 CONFIG_LBLAW1_NAME="BCSR" CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index cf4ce83307a..c32c8f0d74c 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -97,6 +97,8 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF0000000 CONFIG_LBLAW3_NAME="CF" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index e0185191bc7..4d55fd00882 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -97,6 +97,8 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF0000000 CONFIG_LBLAW3_NAME="CF" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 0187f4f1280..697567f53ed 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -96,6 +96,8 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xF0000000 CONFIG_LBLAW3_NAME="CF" CONFIG_LBLAW3_LENGTH_64_KBYTES=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index b048d5b5d00..45b2ee74f4c 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -101,6 +101,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xE0600000 CONFIG_LBLAW3_NAME="NAND" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index 9e2966b371f..5d5811b85a2 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -61,6 +61,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xE0600000 CONFIG_LBLAW3_NAME="NAND" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index 9256aac17cd..70f9df7e76f 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -81,6 +81,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xE0600000 CONFIG_LBLAW3_NAME="NAND" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 95400114f2f..1b8f33ab011 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -61,6 +61,9 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xF0000000 CONFIG_LBLAW2_NAME="VSC7385" CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index a8c69eb6bcb..40eaf93ac54 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -101,6 +101,9 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xF0000000 CONFIG_LBLAW2_NAME="VSC7385" CONFIG_LBLAW2_LENGTH_128_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index 49f0916663d..e85bfaea315 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -102,6 +102,8 @@ CONFIG_LBLAW2=y # CONFIG_LBLAW2_ENABLE is not set CONFIG_LBLAW3=y # CONFIG_LBLAW3_ENABLE is not set +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index e2ea71d11a7..192c3442cee 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -71,6 +71,9 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xF0000000 CONFIG_LBLAW1_NAME="WINDOW1" CONFIG_LBLAW1_LENGTH_256_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 7b17f602b6d..2046b6067dd 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -54,6 +54,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="FPGA0" CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 9a20a0d0690..e9d427be366 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -54,6 +54,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="FPGA0" CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 14104a441bf..24590d1448b 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -70,6 +70,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xE3000000 CONFIG_LBLAW3_NAME="CPLD" CONFIG_LBLAW3_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_IMAGE_FORMAT_LEGACY=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 6740c4c8a97..30af114c8c6 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -104,6 +104,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xA0000000 CONFIG_LBLAW3_NAME="PAXE" CONFIG_LBLAW3_LENGTH_512_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 182fa477f88..e673d6c4dbb 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -77,6 +77,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xA0000000 CONFIG_LBLAW3_NAME="PAXE" CONFIG_LBLAW3_LENGTH_512_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 678900d05ce..fb4bd417481 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -92,6 +92,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xB0000000 CONFIG_LBLAW3_NAME="APP2" CONFIG_LBLAW3_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 49780b4b19b..8f5e8aececa 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -78,6 +78,9 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xA0000000 CONFIG_LBLAW2_NAME="APP1" CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 9a57e43d784..e3d721e093e 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -79,6 +79,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xB0000000 CONFIG_LBLAW3_NAME="APP2" CONFIG_LBLAW3_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 78f7de9899a..749b38586f2 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -92,6 +92,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xB0000000 CONFIG_LBLAW3_NAME="APP2" CONFIG_LBLAW3_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 7256750ea0b..e8bb547b6f4 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -93,6 +93,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xB0000000 CONFIG_LBLAW3_NAME="APP2" CONFIG_LBLAW3_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index ec2e30709ca..b0da1c07047 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -56,6 +56,10 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xFBFF8000 CONFIG_LBLAW2_NAME="CPLD" CONFIG_LBLAW2_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 453f85a0e33..a213f038ee4 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -69,6 +69,9 @@ CONFIG_LBLAW0=y CONFIG_LBLAW0_BASE=0xFF800000 CONFIG_LBLAW0_NAME="FLASH" CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index b3046156302..321c3d40735 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -69,6 +69,9 @@ CONFIG_LBLAW0=y CONFIG_LBLAW0_BASE=0xFF800000 CONFIG_LBLAW0_NAME="FLASH" CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 4ec51af9f2e..865a3ef74a5 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -49,6 +49,9 @@ CONFIG_LBLAW0=y CONFIG_LBLAW0_BASE=0xFF800000 CONFIG_LBLAW0_NAME="FLASH" CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index a806e9957f7..82db1696735 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -53,6 +53,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="FPGA0" CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 3687a28fc3a..b9f43273b0e 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -53,6 +53,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="FPGA0" CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 4231a431b88..5dc1ddf9230 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -53,6 +53,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="FPGA0" CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index afb991ce1e2..093f3e6b8bd 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -53,6 +53,10 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xE0600000 CONFIG_LBLAW1_NAME="FPGA0" CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 2b16ceb5242..fcd57410927 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -92,6 +92,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xB0000000 CONFIG_LBLAW3_NAME="APP2" CONFIG_LBLAW3_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SUVD3" diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 07666c3b50b..5f7f2289f13 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -78,6 +78,9 @@ CONFIG_LBLAW2=y CONFIG_LBLAW2_BASE=0xA0000000 CONFIG_LBLAW2_NAME="APP1" CONFIG_LBLAW2_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 627bf2febf3..600c6f36e05 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -92,6 +92,9 @@ CONFIG_LBLAW3=y CONFIG_LBLAW3_BASE=0xB0000000 CONFIG_LBLAW3_NAME="APP2" CONFIG_LBLAW3_LENGTH_256_MBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 365c4ea8587..42e0098a1c7 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -74,6 +74,9 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0x61000000 CONFIG_LBLAW1_NAME="NAND" CONFIG_LBLAW1_LENGTH_32_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 072674cbeb6..9ac88c0a4ba 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -71,6 +71,9 @@ CONFIG_LBLAW1=y CONFIG_LBLAW1_BASE=0xF0000000 CONFIG_LBLAW1_NAME="WINDOW1" CONFIG_LBLAW1_LENGTH_256_KBYTES=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index cd78836bcd5..9c4de054403 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -331,15 +331,6 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Environment Configuration */ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 93b553c9050..2f48b135c46 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -362,13 +362,6 @@ /* Enable Internal USB Phy and GPIO on LCD Connector */ #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
-#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) - -#define CONFIG_SYS_HID2 HID2_HBE - /* * Environment Configuration */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 18e056e1b24..bd1e54feec3 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -335,13 +335,6 @@ /* Enable Internal USB Phy and GPIO on LCD Connector */ #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
-#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) - -#define CONFIG_SYS_HID2 HID2_HBE - /* * Environment Configuration */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 708829dae80..5ce213f5949 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -356,15 +356,6 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) -#define CONFIG_SYS_HID2 HID2_HBE - /* * MMU Setup */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index c66e33a247e..abc62f7e699 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -272,14 +272,6 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - #if (CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index ed47bcd5b42..a138bd6724f 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -290,14 +290,6 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 3e0907dae4e..d0d6eaf6c21 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -341,17 +341,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A
-#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_INSTRUCTION_CACHE) - -/* #define CONFIG_SYS_HID0_FINAL (\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_ENABLE_M_BIT |\ - HID0_ENABLE_ADDRESS_BROADCAST) */ - -#define CONFIG_SYS_HID2 HID2_HBE - #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #endif diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index e401c29d6b7..976c1e80638 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -396,17 +396,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A
-#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_INSTRUCTION_CACHE) - -/* #define CONFIG_SYS_HID0_FINAL (\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_ENABLE_M_BIT |\ - HID0_ENABLE_ADDRESS_BROADCAST) */ - -#define CONFIG_SYS_HID2 HID2_HBE - #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #endif diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index cc62fc32135..f37b086b1f1 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -425,11 +425,6 @@ boards, we say we have two, but don't display a message if we find only one. */ /* USB DR as device + USB MPH as host */ #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
-#define CONFIG_SYS_HID0_INIT 0x00000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE - -#define CONFIG_SYS_HID2 HID2_HBE - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index a244ae87a22..7361f0e2f67 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -361,14 +361,6 @@ extern int board_pci_host_broken(void); #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 006279a58c3..3f17574cee9 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -382,14 +382,6 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index af03c037865..dc2bba828c3 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -237,12 +237,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A
-/* i-cache and d-cache disabled */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* PCI */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index e9cfeae64d8..016477c04fb 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -263,12 +263,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A
-#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) - -#define CONFIG_SYS_HID2 HID2_HBE - #define CONFIG_SYS_GPIO1_PRELIM #define CONFIG_SYS_GPIO1_DIR 0x00100000 #define CONFIG_SYS_GPIO1_DAT 0x00100000 diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 4001a0a16b0..b28f3c1d45a 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -440,15 +440,6 @@ void fpga_control_clear(unsigned int bus, int pin); */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Environment Configuration */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index d86dda18fb1..1637ed9646b 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -30,13 +30,6 @@
#define CONFIG_HWCONFIG
-#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_DISABLE_DYNAMIC_POWER_MANAGMENT) - -#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000) - /* * Definitions for initial stack pointer and data area (in DCACHE ) */ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 5031a6c8bf4..c359d7314de 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -203,14 +203,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 728c9b199f2..aaa0607ed5e 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -189,14 +189,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index f39dbe05b7e..e9bb3f79835 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -208,14 +208,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 19e415619a5..182357b0c0d 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -208,14 +208,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index fe4763ce8ad..0855dd152ce 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -212,14 +212,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 9302d35949d..7edb573747f 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -208,14 +208,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 06c5923ae1d..b88f1582656 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -204,14 +204,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index cb7dabd9321..8ea3ea11dc8 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -309,15 +309,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Environment Configuration */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 98770ca0a64..b58628262d3 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -283,17 +283,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A
-#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_INSTRUCTION_CACHE) - -/* #define CONFIG_SYS_HID0_FINAL (\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_ENABLE_M_BIT |\ - HID0_ENABLE_ADDRESS_BROADCAST) */ - -#define CONFIG_SYS_HID2 HID2_HBE - #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #endif diff --git a/include/configs/strider.h b/include/configs/strider.h index 94164de06c2..96b31741fd2 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -473,15 +473,6 @@ void fpga_control_clear(unsigned int bus, int pin); */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Environment Configuration */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index a65b61bfbf8..5d7d48dd391 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -205,14 +205,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 6084e8af605..d95147d1edb 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -208,14 +208,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index b989f4eadea..ce6d44e6dd5 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -208,14 +208,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - /* * Internal Definitions */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 4c5dad9dc26..87160f2c341 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -268,12 +268,6 @@ SICRL_ETSEC2_A) /* 0x33fc0003) */
-#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) - -#define CONFIG_SYS_HID2 HID2_HBE - #define CONFIG_NETDEV eth0
#define CONFIG_HOSTNAME "ve8313" diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 9b9c1ff54e2..2a14f561ed7 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -263,12 +263,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A
-#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) - -#define CONFIG_SYS_HID2 HID2_HBE - #define CONFIG_SYS_GPIO1_PRELIM #define CONFIG_SYS_GPIO1_DIR 0x00100000 #define CONFIG_SYS_GPIO1_DAT 0x00100000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 6e1f8390a07..caf216c22ce 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2973,9 +2973,6 @@ CONFIG_SYS_GPSR2_VAL CONFIG_SYS_GPSR3_VAL CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HELP_CMD_WIDTH -CONFIG_SYS_HID0_FINAL -CONFIG_SYS_HID0_INIT -CONFIG_SYS_HID2 CONFIG_SYS_HIGH CONFIG_SYS_HMI_BASE CONFIG_SYS_HOSTNAME
Migrate CONFIG_SYS_IMMR to Kconfig for MPC83xx.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/Kconfig | 7 +++++++ configs/TQM834x_defconfig | 1 + configs/ids8313_defconfig | 1 + include/configs/MPC8308RDB.h | 5 ----- include/configs/MPC8313ERDB_NAND.h | 2 -- include/configs/MPC8313ERDB_NOR.h | 2 -- include/configs/MPC8315ERDB.h | 5 ----- include/configs/MPC8323ERDB.h | 5 ----- include/configs/MPC832XEMDS.h | 5 ----- include/configs/MPC8349EMDS.h | 2 -- include/configs/MPC8349EMDS_SDRAM.h | 2 -- include/configs/MPC8349ITX.h | 5 ----- include/configs/MPC837XEMDS.h | 5 ----- include/configs/MPC837XERDB.h | 5 ----- include/configs/TQM834x.h | 3 --- include/configs/caddy2.h | 2 -- include/configs/hrcon.h | 5 ----- include/configs/ids8313.h | 2 -- include/configs/kmcoge5ne.h | 5 ----- include/configs/kmeter1.h | 5 ----- include/configs/kmopti2.h | 5 ----- include/configs/kmsupx5.h | 5 ----- include/configs/kmtegr1.h | 5 ----- include/configs/kmtepr2.h | 5 ----- include/configs/kmvect1.h | 5 ----- include/configs/mpc8308_p1m.h | 5 ----- include/configs/sbc8349.h | 2 -- include/configs/strider.h | 5 ----- include/configs/suvd3.h | 5 ----- include/configs/tuge1.h | 5 ----- include/configs/tuxx1.h | 5 ----- include/configs/ve8313.h | 2 -- include/configs/vme8349.h | 2 -- 33 files changed, 9 insertions(+), 121 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 5fb4228076e..96376837abb 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -282,6 +282,13 @@ config ARCH_MPC837X select MPC83XX_LDP_PIN select MPC83XX_SECOND_I2C_SUPPORT
+config SYS_IMMR + hex "Value for IMMR" + default 0xE0000000 + help + Address for the Internal Memory-Mapped Registers (IMMR) window used + to configure the features of the SoC. + source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig" source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index e85bfaea315..f5746cfad71 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_CLK_FREQ=66666000 CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y CONFIG_TARGET_TQM834X=y +CONFIG_SYS_IMMR=0xff400000 CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y CONFIG_CORE_PLL_RATIO_2_1=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 24590d1448b..9c16a1231c6 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y CONFIG_TARGET_IDS8313=y +CONFIG_SYS_IMMR=0xF0000000 CONFIG_CORE_PLL_RATIO_2_1=y CONFIG_PCI_HOST_MODE_ENABLE=y CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 9c4de054403..e825cfbd174 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -52,11 +52,6 @@ SICRL_I2C2_PF0 |\ SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * SERDES */ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 2f48b135c46..e23df14ec17 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -54,8 +54,6 @@ #define CONFIG_VSC7385_ENET #define CONFIG_TSEC2
-#define CONFIG_SYS_IMMR 0xE0000000 - #if !defined(CONFIG_SPL_BUILD) #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR #endif diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index bd1e54feec3..17cd8adc859 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -30,8 +30,6 @@ #define CONFIG_VSC7385_ENET #define CONFIG_TSEC2
-#define CONFIG_SYS_IMMR 0xE0000000 - #define CONFIG_SYS_MEMTEST_START 0x00001000 #define CONFIG_SYS_MEMTEST_END 0x07f00000
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 5ce213f5949..fbba2fbb50b 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -31,11 +31,6 @@
#define CONFIG_HWCONFIG
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Arbiter Setup */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index abc62f7e699..b528c2901b4 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -20,11 +20,6 @@ */ #define CONFIG_SYS_SICRL 0x00000000
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * System performance */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index a138bd6724f..195d62ce50d 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -17,11 +17,6 @@ */ #define CONFIG_SYS_SICRL 0x00000000
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * DDR Setup */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index d0d6eaf6c21..14ebc8ead3d 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -17,8 +17,6 @@ */ #define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_SYS_IMMR 0xE0000000 - #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00100000 diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 976c1e80638..67f3a9bd65f 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -17,8 +17,6 @@ */ #define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_SYS_IMMR 0xE0000000 - #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00100000 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index f37b086b1f1..eef1bdec63a 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -39,11 +39,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-/* - * High Level Configuration Options - */ -#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ - #define CONFIG_MISC_INIT_F
/* diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 7361f0e2f67..c1973703c4a 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -39,11 +39,6 @@
#define CONFIG_HWCONFIG
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * DDR Setup */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 3f17574cee9..e8173da3233 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -46,11 +46,6 @@ */ #define CONFIG_SYS_OBIR 0x30100000
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Device configurations */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index dc2bba828c3..d713c695f7c 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -16,9 +16,6 @@ */ #define CONFIG_E300 1 /* E300 Family */
-/* IMMR Base Address Register, use Freescale default: 0xff400000 */ -#define CONFIG_SYS_IMMR 0xff400000 - /* * Local Bus LCRR * LCRR: DLL bypass, Clock divider is 8 diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 016477c04fb..b4516267f15 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -25,8 +25,6 @@ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#define CONFIG_SYS_IMMR 0xE0000000 - #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00100000 diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index b28f3c1d45a..e8a4b7adf67 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -40,11 +40,6 @@ SICRL_I2C2_PF0 |\ SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * SERDES */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 1637ed9646b..b4acee058ca 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -20,8 +20,6 @@ #define CONFIG_BOOT_RETRY_MIN 30 #define CONFIG_RESET_TO_RETRY
-#define CONFIG_SYS_IMMR 0xF0000000 - #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index c359d7314de..bd24d78c1db 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -40,11 +40,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index aaa0607ed5e..48a6172349d 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -25,11 +25,6 @@ #include "km/keymile-common.h" #include "km/km-powerpc.h"
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index e9bb3f79835..e34f26e55d6 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -45,11 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 182357b0c0d..96e10325f0f 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -45,11 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 0855dd152ce..4b407af0364 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -52,11 +52,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 7edb573747f..20cbc1318ab 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -45,11 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index b88f1582656..37acb0245b6 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -44,11 +44,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 8ea3ea11dc8..76846c43d01 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -55,11 +55,6 @@ */ #define CONFIG_SYS_GPIO1_DAT 0x08008C00
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * SERDES */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index b58628262d3..775bbe417af 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -22,8 +22,6 @@ /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#define CONFIG_SYS_IMMR 0xE0000000 - #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00100000 diff --git a/include/configs/strider.h b/include/configs/strider.h index 96b31741fd2..fe2d89f2a61 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -40,11 +40,6 @@ SICRL_I2C2_PF0 |\ SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * SERDES */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 5d7d48dd391..82ebbca4db1 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -42,11 +42,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index d95147d1edb..b196c77c4e7 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -45,11 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index ce6d44e6dd5..8dfff62de56 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -45,11 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - /* * Bus Arbitration Configuration Register (ACR) */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 87160f2c341..1ac6cbefd6c 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -24,8 +24,6 @@ * On-board devices * */ -#define CONFIG_SYS_IMMR 0xE0000000 - #define CONFIG_SYS_MEMTEST_START 0x00001000 #define CONFIG_SYS_MEMTEST_END 0x07000000
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 2a14f561ed7..1a3a55b707e 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -25,8 +25,6 @@ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#define CONFIG_SYS_IMMR 0xE0000000 - #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00100000
Migrate the system IO configuration setting to Kconfig.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 1 + arch/powerpc/cpu/mpc83xx/sysio/Kconfig | 7 + .../powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308 | 323 ++++++++++++++++++ arch/powerpc/cpu/mpc83xx/sysio/sysio.h | 32 ++ configs/MPC8308RDB_defconfig | 8 + configs/hrcon_defconfig | 9 + configs/hrcon_dh_defconfig | 9 + configs/mpc8308_p1m_defconfig | 8 + configs/strider_con_defconfig | 9 + configs/strider_con_dp_defconfig | 9 + configs/strider_cpu_defconfig | 9 + configs/strider_cpu_dp_defconfig | 9 + include/configs/MPC8308RDB.h | 25 -- include/configs/hrcon.h | 25 -- include/configs/mpc8308_p1m.h | 25 -- include/configs/strider.h | 25 -- 17 files changed, 434 insertions(+), 100 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/sysio/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308 create mode 100644 arch/powerpc/cpu/mpc83xx/sysio/sysio.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 96376837abb..9f7b3a2e019 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -294,6 +294,7 @@ source "arch/powerpc/cpu/mpc83xx/bats/Kconfig" source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig" source "arch/powerpc/cpu/mpc83xx/hid/Kconfig" +source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
menu "Legacy options"
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 5ce7b794b26..3df01ee1ca1 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -14,6 +14,7 @@
#include "lblaw/lblaw.h" #include "elbc/elbc.h" +#include "sysio/sysio.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc83xx/sysio/Kconfig b/arch/powerpc/cpu/mpc83xx/sysio/Kconfig new file mode 100644 index 00000000000..9e1f1587121 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/sysio/Kconfig @@ -0,0 +1,7 @@ +menu "System I/O configuration" + +if ARCH_MPC8308 +source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308" +endif + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308 b/arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308 new file mode 100644 index 00000000000..de62171b301 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308 @@ -0,0 +1,323 @@ +choice + prompt "SPI group" + +config SICR_SPI_SPI + bool "SPI" + +config SICR_SPI_MSRCID + bool "MSRCID" + +config SICR_SPI_LSRCID + bool "LSRCID" + +endchoice + +choice + prompt "UART group" + +config SICR_UART_SPI + bool "UART" + +config SICR_UART_MSRCID + bool "MSRCID" + +config SICR_UART_LSRCID + bool "LSRCID" + +endchoice + +choice + prompt "IRQ group" + +config SICR_IRQ_SPI + bool "IRQ" + +config SICR_IRQ_MCP_CKSTOP + bool "MCP/CKSTOP" + +config SICR_IRQ_INTA + bool "INTA" + +endchoice + +choice + prompt "I2C2 group" + +config SICR_I2C2_I2C + bool "IRQ" + +config SICR_I2C2_CKSTOP + bool "CKSTOP" + +endchoice + +choice + prompt "ETSEC1 A group" + +config SICR_ETSEC1_A_TSEC2 + bool "TSEC1" + +config SICR_ETSEC1_A_TSEC_GTX_CLK125 + bool "TSEC1 GTX_CLK125" + +endchoice + +choice + prompt "eSDHC A group" + +config SICR_ESDHC_A_SD + bool "SD" + +config SICR_ESDHC_A_GTM + bool "GTM" + +config SICR_ESDHC_A_GPIO + bool "GPIO" + +endchoice + +choice + prompt "eSDHC B group" + +config SICR_ESDHC_B_SD + bool "SD" + +config SICR_ESDHC_B_GTM + bool "GTM" + +config SICR_ESDHC_B_GPIO + bool "GPIO" + +endchoice + +choice + prompt "eSDHC C group" + +config SICR_ESDHC_C_SD + bool "SD" + +config SICR_ESDHC_C_GTM + bool "GTM" + +config SICR_ESDHC_C_GPIO + bool "GPIO" + +endchoice + +choice + prompt "GPIO A group" + +config SICR_GPIO_A_GPIO + bool "GPIO" + +config SICR_GPIO_A_TSEC2 + bool "TSEC2" + +endchoice + +choice + prompt "GPIO B group" + +config SICR_GPIO_B_GPIO + bool "GPIO" + +config SICR_GPIO_B_TSEC2 + bool "TSEC2" + +config SICR_GPIO_B_TSEC_GTX_CLK125 + bool "TSEC2 GTX_CLK125" + +endchoice + +choice + prompt "IEEE1588 A group" + +config SICR_IEEE1588_A_TSEC + bool "TSEC" + +config SICR_IEEE1588_A_GPIO + bool "GPIO" + +endchoice + +choice + prompt "USB group" + +config SICR_USB_TSEC + bool "USB" + +endchoice + +choice + prompt "GTM group" + +config SICR_GTM_TSEC + bool "GTM" + +config SICR_GTM_GPIO + bool "GPIO" + +endchoice + +choice + prompt "IEEE1588 B group" + +config SICR_IEEE1588_B_GPIO + bool "GPIO" + +endchoice + +choice + prompt "ETSEC2 group" + +config SICR_ETSEC2_TSEC2 + bool "TSEC2" + +config SICR_ETSEC2_GPIO + bool "GPIO" + +endchoice + +choice + prompt "GPIO selection" + +config SICR_GPIOSEL_GPIO + bool "GPIO_A, GPIO_B" + +config SICR_GPIOSEL_IEEE1588 + bool "IEEE1588_A, IEEE1588_B, ETSEC2" + +endchoice + +choice + prompt "IEEE1588 timer output buffer impedance" + +config SICR_TMROBI_3_3_V + bool "40 Ohm, 3.3V" + +config SICR_TMROBI_2_5_V + bool "40 Ohm, 2.5V" + +endchoice + +choice + prompt "TSEC1 output buffer impedance" + +config SICR_TMSOBI1_3_3_V + bool "40 Ohm, 3.3V" + +config SICR_TMSOBI1_2_5_V + bool "40 Ohm, 2.5V" + +endchoice + +choice + prompt "TSEC2 output buffer impedance" + +config SICR_TMSOBI2_3_3_V + bool "40 Ohm, 3.3V" + +config SICR_TMSOBI2_2_5_V + bool "40 Ohm, 2.5V" + +endchoice + +config SICRL_SPI + hex + default 0x0 if SICR_SPI_SPI + default 0x10000000 if SICR_SPI_MSRCID + default 0x30000000 if SICR_SPI_LSRCID + +config SICRL_UART + hex + default 0x0 if SICR_UART_SPI + default 0x4000000 if SICR_UART_MSRCID + default 0xc000000 if SICR_UART_LSRCID + +config SICRL_IRQ + hex + default 0x0 if SICR_IRQ_SPI + default 0x1000000 if SICR_IRQ_MCP_CKSTOP + default 0x3000000 if SICR_IRQ_INTA + +config SICRL_I2C2 + hex + default 0x0 if SICR_I2C2_I2C + default 0x100000 if SICR_I2C2_CKSTOP + +config SICRL_ETSEC1_A + hex + default 0x0 if SICR_ETSEC1_A_TSEC2 + default 0x40 if SICR_ETSEC1_A_TSEC_GTX_CLK125 + +config SICRH_ESDHC_A + hex + default 0x0 if SICR_ESDHC_A_SD + default 0x40000000 if SICR_ESDHC_A_GTM + default 0xc0000000 if SICR_ESDHC_A_GPIO + +config SICRH_ESDHC_B + hex + default 0x0 if SICR_ESDHC_B_SD + default 0x10000000 if SICR_ESDHC_B_GTM + default 0x30000000 if SICR_ESDHC_B_GPIO + +config SICRH_ESDHC_C + hex + default 0x0 if SICR_ESDHC_C_SD + default 0x4000000 if SICR_ESDHC_C_GTM + default 0xc000000 if SICR_ESDHC_C_GPIO + +config SICRH_GPIO_A + hex + default 0x0 if SICR_GPIO_A_GPIO + default 0x1000000 if SICR_GPIO_A_TSEC2 + +config SICRH_GPIO_B + hex + default 0x0 if SICR_GPIO_B_GPIO + default 0x400000 if SICR_GPIO_B_TSEC2 + default 0x800000 if SICR_GPIO_B_TSEC_GTX_CLK125 + +config SICRH_IEEE1588_A + hex + default 0x100000 if SICR_IEEE1588_A_TSEC + default 0x300000 if SICR_IEEE1588_A_GPIO + +config SICRH_USB + hex + default 0x40000 if SICR_USB_TSEC + +config SICRH_GTM + hex + default 0x10000 if SICR_GTM_TSEC + default 0x30000 if SICR_GTM_GPIO + +config SICRH_IEEE1588_B + hex + default 0xc000 if SICR_IEEE1588_B_GPIO + +config SICRH_ETSEC2 + hex + default 0x1000 if SICR_ETSEC2_TSEC2 + default 0x3000 if SICR_ETSEC2_GPIO + +config SICRH_GPIOSEL + hex + default 0x0 if SICR_GPIOSEL_GPIO + default 0x100 if SICR_GPIOSEL_IEEE1588 + +config SICRH_TMROBI + hex + default 0x0 if SICR_TMROBI_3_3_V + default 0x10 if SICR_TMROBI_2_5_V + +config SICRH_TMSOBI1 + hex + default 0x0 if SICR_TMSOBI1_3_3_V + default 0x2 if SICR_TMSOBI1_2_5_V + +config SICRH_TMSOBI2 + hex + default 0x0 if SICR_TMSOBI2_3_3_V + default 0x1 if SICR_TMSOBI2_2_5_V diff --git a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h new file mode 100644 index 00000000000..f8c2f104c1b --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h @@ -0,0 +1,32 @@ +#ifdef CONFIG_ARCH_MPC8308 + +#ifndef CONFIG_SYS_SICRL +#define CONFIG_SYS_SICRL (\ + CONFIG_SICRL_SPI |\ + CONFIG_SICRL_UART |\ + CONFIG_SICRL_IRQ |\ + CONFIG_SICRL_I2C2 |\ + CONFIG_SICRL_ETSEC1_A \ +) +#endif + +#ifndef CONFIG_SYS_SICRH +#define CONFIG_SYS_SICRH (\ + CONFIG_SICRH_ESDHC_A |\ + CONFIG_SICRH_ESDHC_B |\ + CONFIG_SICRH_ESDHC_C |\ + CONFIG_SICRH_GPIO_A |\ + CONFIG_SICRH_GPIO_B |\ + CONFIG_SICRH_IEEE1588_A |\ + CONFIG_SICRH_USB |\ + CONFIG_SICRH_GTM |\ + CONFIG_SICRH_IEEE1588_B |\ + CONFIG_SICRH_ETSEC2 |\ + CONFIG_SICRH_GPIOSEL |\ + CONFIG_SICRH_TMROBI |\ + CONFIG_SICRH_TMSOBI1 |\ + CONFIG_SICRH_TMSOBI2 \ +) +#endif + +#endif diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index e674848a6c4..9be515567c1 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -62,6 +62,14 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y +CONFIG_SICR_GPIO_A_TSEC2=y +CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 2046b6067dd..3442c9c797e 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -58,6 +58,15 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y +CONFIG_SICR_GPIO_A_GPIO=y +CONFIG_SICR_GPIO_B_GPIO=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index e9d427be366..5de0eaa4d0f 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -58,6 +58,15 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y +CONFIG_SICR_GPIO_A_GPIO=y +CONFIG_SICR_GPIO_B_GPIO=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index b0da1c07047..26601ff0a68 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -60,6 +60,14 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ESDHC_A_GPIO=y +CONFIG_SICR_ESDHC_B_GPIO=y +CONFIG_SICR_ESDHC_C_GTM=y +CONFIG_SICR_GPIO_A_TSEC2=y +CONFIG_SICR_GPIO_B_TSEC2=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 82db1696735..1244652c79c 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -57,6 +57,15 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC2=y +CONFIG_SICR_GPIO_A_GPIO=y +CONFIG_SICR_GPIO_B_GPIO=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index b9f43273b0e..05040b056e4 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -57,6 +57,15 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC2=y +CONFIG_SICR_GPIO_A_GPIO=y +CONFIG_SICR_GPIO_B_GPIO=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 5dc1ddf9230..fbae6546d72 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -57,6 +57,15 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC2=y +CONFIG_SICR_GPIO_A_GPIO=y +CONFIG_SICR_GPIO_B_GPIO=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 093f3e6b8bd..e3405707e53 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -57,6 +57,15 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC2=y +CONFIG_SICR_GPIO_A_GPIO=y +CONFIG_SICR_GPIO_B_GPIO=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index e825cfbd174..7ba44044f77 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -27,31 +27,6 @@ #define CONFIG_TSEC1 #define CONFIG_VSC7385_ENET
-/* - * System IO Config - */ -#define CONFIG_SYS_SICRH (\ - SICRH_ESDHC_A_SD |\ - SICRH_ESDHC_B_SD |\ - SICRH_ESDHC_C_SD |\ - SICRH_GPIO_A_TSEC2 |\ - SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ - SICRH_IEEE1588_A_GPIO |\ - SICRH_USB |\ - SICRH_GTM_GPIO |\ - SICRH_IEEE1588_B_GPIO |\ - SICRH_ETSEC2_CRS |\ - SICRH_GPIOSEL_1 |\ - SICRH_TMROBI_V3P3 |\ - SICRH_TSOBI1_V2P5 |\ - SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ -#define CONFIG_SYS_SICRL (\ - SICRL_SPI_PF0 |\ - SICRL_UART_PF0 |\ - SICRL_IRQ_PF0 |\ - SICRL_I2C2_PF0 |\ - SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ - /* * SERDES */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index e8a4b7adf67..23e0da9624a 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -15,31 +15,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-/* - * System IO Config - */ -#define CONFIG_SYS_SICRH (\ - SICRH_ESDHC_A_SD |\ - SICRH_ESDHC_B_SD |\ - SICRH_ESDHC_C_SD |\ - SICRH_GPIO_A_GPIO |\ - SICRH_GPIO_B_GPIO |\ - SICRH_IEEE1588_A_GPIO |\ - SICRH_USB |\ - SICRH_GTM_GPIO |\ - SICRH_IEEE1588_B_GPIO |\ - SICRH_ETSEC2_GPIO |\ - SICRH_GPIOSEL_1 |\ - SICRH_TMROBI_V3P3 |\ - SICRH_TSOBI1_V2P5 |\ - SICRH_TSOBI2_V2P5) /* 0x0037f103 */ -#define CONFIG_SYS_SICRL (\ - SICRL_SPI_PF0 |\ - SICRL_UART_PF0 |\ - SICRL_IRQ_PF0 |\ - SICRL_I2C2_PF0 |\ - SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ - /* * SERDES */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 76846c43d01..d0eac0a2efe 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -21,31 +21,6 @@ #define CONFIG_TSEC1 #define CONFIG_TSEC2
-/* - * System IO Config - */ -#define CONFIG_SYS_SICRH (\ - SICRH_ESDHC_A_GPIO |\ - SICRH_ESDHC_B_GPIO |\ - SICRH_ESDHC_C_GTM |\ - SICRH_GPIO_A_TSEC2 |\ - SICRH_GPIO_B_TSEC2_TX_CLK |\ - SICRH_IEEE1588_A_GPIO |\ - SICRH_USB |\ - SICRH_GTM_GPIO |\ - SICRH_IEEE1588_B_GPIO |\ - SICRH_ETSEC2_CRS |\ - SICRH_GPIOSEL_1 |\ - SICRH_TMROBI_V3P3 |\ - SICRH_TSOBI1_V3P3 |\ - SICRH_TSOBI2_V3P3) /* 0xf577d100 */ -#define CONFIG_SYS_SICRL (\ - SICRL_SPI_PF0 |\ - SICRL_UART_PF0 |\ - SICRL_IRQ_PF0 |\ - SICRL_I2C2_PF0 |\ - SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ - #define CONFIG_SYS_GPIO1_PRELIM /* GPIO Default input/output settings */ #define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00 diff --git a/include/configs/strider.h b/include/configs/strider.h index fe2d89f2a61..8afd17d1b00 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -15,31 +15,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-/* - * System IO Config - */ -#define CONFIG_SYS_SICRH (\ - SICRH_ESDHC_A_SD |\ - SICRH_ESDHC_B_SD |\ - SICRH_ESDHC_C_SD |\ - SICRH_GPIO_A_GPIO |\ - SICRH_GPIO_B_GPIO |\ - SICRH_IEEE1588_A_GPIO |\ - SICRH_USB |\ - SICRH_GTM_GPIO |\ - SICRH_IEEE1588_B_GPIO |\ - SICRH_ETSEC2_GPIO |\ - SICRH_GPIOSEL_1 |\ - SICRH_TMROBI_V3P3 |\ - SICRH_TSOBI1_V2P5 |\ - SICRH_TSOBI2_V2P5) /* 0x0037f103 */ -#define CONFIG_SYS_SICRL (\ - SICRL_SPI_PF0 |\ - SICRL_UART_PF0 |\ - SICRL_IRQ_PF0 |\ - SICRL_I2C2_PF0 |\ - SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ - /* * SERDES */
Migrate the arbiter configuration to Kconfig.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/arbiter/Kconfig | 139 +++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h | 28 +++++ arch/powerpc/cpu/mpc83xx/cpu_init.c | 29 +---- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 8 +- configs/MPC8308RDB_defconfig | 2 + configs/MPC8313ERDB_33_defconfig | 2 + configs/MPC8313ERDB_66_defconfig | 2 + configs/MPC8313ERDB_NAND_33_defconfig | 2 + configs/MPC8313ERDB_NAND_66_defconfig | 2 + configs/MPC8315ERDB_defconfig | 2 + configs/MPC8323ERDB_defconfig | 2 + configs/MPC8349EMDS_PCI64_defconfig | 2 + configs/MPC8349EMDS_SDRAM_defconfig | 2 + configs/MPC8349EMDS_SLAVE_defconfig | 2 + configs/MPC8349EMDS_defconfig | 2 + configs/MPC8349ITXGP_defconfig | 2 + configs/MPC8349ITX_LOWBOOT_defconfig | 2 + configs/MPC8349ITX_defconfig | 2 + configs/MPC837XEMDS_HOST_defconfig | 2 + configs/MPC837XEMDS_SLAVE_defconfig | 2 + configs/MPC837XEMDS_defconfig | 2 + configs/MPC837XERDB_SLAVE_defconfig | 2 + configs/MPC837XERDB_defconfig | 2 + configs/hrcon_defconfig | 2 + configs/hrcon_dh_defconfig | 2 + configs/ids8313_defconfig | 2 + configs/kmcoge5ne_defconfig | 4 + configs/kmeter1_defconfig | 4 + configs/kmopti2_defconfig | 4 + configs/kmsupx5_defconfig | 4 + configs/kmtegr1_defconfig | 4 + configs/kmtepr2_defconfig | 4 + configs/kmvect1_defconfig | 4 + configs/mpc8308_p1m_defconfig | 2 + configs/strider_con_defconfig | 2 + configs/strider_con_dp_defconfig | 2 + configs/strider_cpu_defconfig | 2 + configs/strider_cpu_dp_defconfig | 2 + configs/suvd3_defconfig | 4 + configs/tuge1_defconfig | 4 + configs/tuxx1_defconfig | 4 + configs/ve8313_defconfig | 2 + include/configs/MPC8308RDB.h | 5 - include/configs/MPC8313ERDB_NAND.h | 3 - include/configs/MPC8313ERDB_NOR.h | 3 - include/configs/MPC8315ERDB.h | 5 - include/configs/MPC8323ERDB.h | 5 - include/configs/MPC8349EMDS.h | 2 - include/configs/MPC8349EMDS_SDRAM.h | 2 - include/configs/MPC8349ITX.h | 2 - include/configs/MPC837XEMDS.h | 4 - include/configs/MPC837XERDB.h | 4 - include/configs/hrcon.h | 5 - include/configs/ids8313.h | 3 - include/configs/kmcoge5ne.h | 8 -- include/configs/kmeter1.h | 8 -- include/configs/kmopti2.h | 8 -- include/configs/kmsupx5.h | 8 -- include/configs/kmtegr1.h | 8 -- include/configs/kmtepr2.h | 8 -- include/configs/kmvect1.h | 8 -- include/configs/mpc8308_p1m.h | 5 - include/configs/strider.h | 5 - include/configs/suvd3.h | 8 -- include/configs/tuge1.h | 8 -- include/configs/tuxx1.h | 8 -- include/configs/ve8313.h | 3 - scripts/config_whitelist.txt | 4 - 69 files changed, 269 insertions(+), 172 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/arbiter/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 9f7b3a2e019..8a3bb10466c 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -295,6 +295,7 @@ source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig" source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig" source "arch/powerpc/cpu/mpc83xx/hid/Kconfig" source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig" +source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
menu "Legacy options"
diff --git a/arch/powerpc/cpu/mpc83xx/arbiter/Kconfig b/arch/powerpc/cpu/mpc83xx/arbiter/Kconfig new file mode 100644 index 00000000000..f562476da85 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/arbiter/Kconfig @@ -0,0 +1,139 @@ +menu "Arbiter" + +choice + prompt "Pipeline depth" + +config ACR_PIPE_DEP_UNSET + bool "Don't set value" + +config ACR_PIPE_DEP_1 + bool "1" + +config ACR_PIPE_DEP_2 + bool "2" + +config ACR_PIPE_DEP_3 + bool "3" + +config ACR_PIPE_DEP_4 + bool "4" + +endchoice + +choice + prompt "Repeat count" + +config ACR_RPTCNT_UNSET + bool "Don't set value" + +config ACR_RPTCNT_1 + bool "1" + +config ACR_RPTCNT_2 + bool "2" + +config ACR_RPTCNT_3 + bool "3" + +config ACR_RPTCNT_4 + bool "4" + +config ACR_RPTCNT_5 + bool "5" + +config ACR_RPTCNT_6 + bool "6" + +config ACR_RPTCNT_7 + bool "7" + +config ACR_RPTCNT_8 + bool "8" + +endchoice + +choice + prompt "Address parking" + +config ACR_APARK_UNSET + bool "Don't set value" + +config ACR_APARK_MASTER + bool "Park to master" + +config ACR_APARK_LAST + bool "Park to last owner" + +config ACR_APARK_DISABLE + bool "Disabled" + +endchoice + +choice + prompt "Parking master" + +config ACR_PARKM_UNSET + bool "Don't set value" + +config ACR_PARKM_E300 + bool "e300 core" + +config ACR_PARKM_TSEC_1_2 + bool "TSEC1, TSEC2" + +config ACR_PARKM_USB_I2C1_BOOT + bool "USB/I2C1_BOOT" + +config ACR_PARKM_DMA_ESDHC_USB + bool "DMA, ESDHC, USB" + +config ACR_PARKM_PEX + bool "PCI Express" + +if MPC83XX_QUICC_ENGINE + +config ACR_PARKM_ENC_CORE + bool "Encryption core" + +endif + +endchoice + +config ACR_PIPE_DEP + hex + default 0x0 if ACR_PIPE_DEP_UNSET + default 0x0 if ACR_PIPE_DEP_1 + default 0x10000 if ACR_PIPE_DEP_2 + default 0x20000 if ACR_PIPE_DEP_3 + default 0x30000 if ACR_PIPE_DEP_4 + +config ACR_RPTCNT + hex + default 0x0 if ACR_RPTCNT_UNSET + default 0x0 if ACR_RPTCNT_1 + default 0x100 if ACR_RPTCNT_2 + default 0x200 if ACR_RPTCNT_3 + default 0x300 if ACR_RPTCNT_4 + default 0x400 if ACR_RPTCNT_5 + default 0x500 if ACR_RPTCNT_6 + default 0x600 if ACR_RPTCNT_7 + default 0x700 if ACR_RPTCNT_8 + +config ACR_APARK + hex + default 0x0 if ACR_APARK_UNSET + default 0x0 if ACR_APARK_MASTER + default 0x10 if ACR_APARK_LAST + default 0x20 if ACR_APARK_DISABLE + +config ACR_PARKM + hex + default 0x0 if ACR_PARKM_UNSET + default 0x0 if ACR_PARKM_E300 + default 0x2 if ACR_PARKM_TSEC_1_2 + default 0x3 if ACR_PARKM_USB_I2C1_BOOT + default 0x4 if ACR_PARKM_DMA_ESDHC_USB + default 0x5 if ACR_PARKM_PEX + default 0x5 if ACR_PARKM_ENC_CORE + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h b/arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h new file mode 100644 index 00000000000..10a47e49876 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h @@ -0,0 +1,28 @@ + const __be32 acr_mask = +#ifndef CONFIG_ACR_PIPE_DEP_UNSET + ACR_PIPE_DEP | +#endif +#ifndef CONFIG_ACR_RPTCNT_UNSET + ACR_RPTCNT | +#endif +#ifndef CONFIG_ACR_APARK_UNSET + ACR_APARK | +#endif +#ifndef CONFIG_ACR_PARKM_UNSET + ACR_PARKM | +#endif + 0; + const __be32 acr_val = +#ifndef CONFIG_ACR_PIPE_DEP_UNSET + CONFIG_ACR_PIPE_DEP | +#endif +#ifndef CONFIG_ACR_RPTCNT_UNSET + CONFIG_ACR_RPTCNT | +#endif +#ifndef CONFIG_ACR_APARK_UNSET + CONFIG_ACR_APARK | +#endif +#ifndef CONFIG_ACR_PARKM_UNSET + CONFIG_ACR_PARKM | +#endif + 0; diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 3df01ee1ca1..77502567a70 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -15,6 +15,7 @@ #include "lblaw/lblaw.h" #include "elbc/elbc.h" #include "sysio/sysio.h" +#include "arbiter/arbiter.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -51,34 +52,6 @@ static void config_qe_ioports(void) */ void cpu_init_f (volatile immap_t * im) { - __be32 acr_mask = -#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ - ACR_PIPE_DEP | -#endif -#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ - ACR_RPTCNT | -#endif -#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ - ACR_APARK | -#endif -#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */ - ACR_PARKM | -#endif - 0; - __be32 acr_val = -#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ - (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | -#endif -#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ - (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) | -#endif -#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ - (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) | -#endif -#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */ - (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) | -#endif - 0; __be32 spcr_mask = #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */ SPCR_OPT | diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index b4e2fb1119d..133f7abc31a 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -27,16 +27,16 @@ void cpu_init_f (volatile immap_t * im)
/* system performance tweaking */
-#ifdef CONFIG_SYS_ACR_PIPE_DEP +#ifndef CONFIG_ACR_PIPE_DEP_UNSET /* Arbiter pipeline depth */ im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); + CONFIG_ACR_PIPE_DEP; #endif
-#ifdef CONFIG_SYS_ACR_RPTCNT +#ifndef CONFIG_ACR_RPTCNT_UNSET /* Arbiter repeat count */ im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | - (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT); + CONFIG_ACR_RPTCNT; #endif
#ifdef CONFIG_SYS_SPCR_OPT diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 9be515567c1..00feaccc305 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -70,6 +70,8 @@ CONFIG_SICR_GTM_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index 732beab2e1c..b368aee9663 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -77,6 +77,8 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index f2ec6cc7db0..ddf9060df42 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -76,6 +76,8 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 7a308f144fe..f0c43ca2dcd 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -79,6 +79,8 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index e4de72dbdf1..ab9423f8bcc 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -78,6 +78,8 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index d19e7977311..2263b9cb51b 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -80,6 +80,8 @@ CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_DPM=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 19425abb1d5..b52d1fd62a5 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -73,6 +73,8 @@ CONFIG_LBLAW0_LENGTH_32_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index fef4f343579..9108275f3c2 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -56,6 +56,8 @@ CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index d0774431a39..8589470b2e3 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -60,6 +60,8 @@ CONFIG_LBLAW2_LENGTH_64_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_ELBC_BR0_OR0=y CONFIG_BR0_OR0_NAME="FLASH" CONFIG_BR0_OR0_BASE=0xFE000000 diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 429d273e4e9..7454dd64f1a 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -54,6 +54,8 @@ CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 8c09cd90eec..328c3aa567e 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -56,6 +56,8 @@ CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index c32c8f0d74c..fa121d721ae 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -99,6 +99,8 @@ CONFIG_LBLAW3_NAME="CF" CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 4d55fd00882..0a79d1e6254 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -99,6 +99,8 @@ CONFIG_LBLAW3_NAME="CF" CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 697567f53ed..e7461072edf 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -98,6 +98,8 @@ CONFIG_LBLAW3_NAME="CF" CONFIG_LBLAW3_LENGTH_64_KBYTES=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 45b2ee74f4c..0df5bdb2c5a 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -104,6 +104,8 @@ CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index 5d5811b85a2..99f206e719f 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -64,6 +64,8 @@ CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index 70f9df7e76f..98dc6ca7848 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -84,6 +84,8 @@ CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 1b8f33ab011..11a33d982f0 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -64,6 +64,8 @@ CONFIG_LBLAW2_LENGTH_128_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 40eaf93ac54..d43b364910a 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -104,6 +104,8 @@ CONFIG_LBLAW2_LENGTH_128_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 3442c9c797e..3dad033be02 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -67,6 +67,8 @@ CONFIG_SICR_ETSEC2_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 5de0eaa4d0f..4fb7cb5ffdb 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -67,6 +67,8 @@ CONFIG_SICR_ETSEC2_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 9c16a1231c6..f835868209f 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -74,6 +74,8 @@ CONFIG_LBLAW3_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_IMAGE_FORMAT_LEGACY=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 30af114c8c6..7751e5a8989 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -107,6 +107,10 @@ CONFIG_LBLAW3_LENGTH_512_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index e673d6c4dbb..2bb31588734 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -80,6 +80,10 @@ CONFIG_LBLAW3_LENGTH_512_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index fb4bd417481..5eb5c939ebb 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -95,6 +95,10 @@ CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 8f5e8aececa..0ad8801df95 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -81,6 +81,10 @@ CONFIG_LBLAW2_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index e3d721e093e..8dfc4438add 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -82,6 +82,10 @@ CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 749b38586f2..1a84ff5e0bb 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -95,6 +95,10 @@ CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index e8bb547b6f4..a746f195e65 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -96,6 +96,10 @@ CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index 26601ff0a68..f73084c0e1f 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -68,6 +68,8 @@ CONFIG_SICR_GPIO_B_TSEC2=y CONFIG_SICR_IEEE1588_A_GPIO=y CONFIG_SICR_GTM_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 1244652c79c..722f25d63e9 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -66,6 +66,8 @@ CONFIG_SICR_ETSEC2_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 05040b056e4..dd3c83d4fcd 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -66,6 +66,8 @@ CONFIG_SICR_ETSEC2_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index fbae6546d72..1a351329872 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -66,6 +66,8 @@ CONFIG_SICR_ETSEC2_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index e3405707e53..79fdc140e5a 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -66,6 +66,8 @@ CONFIG_SICR_ETSEC2_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index fcd57410927..28e386db246 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -95,6 +95,10 @@ CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SUVD3" diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 5f7f2289f13..fb18a46ec61 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -81,6 +81,10 @@ CONFIG_LBLAW2_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 600c6f36e05..a034f302b23 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -95,6 +95,10 @@ CONFIG_LBLAW3_LENGTH_256_MBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_ACR_APARK_MASTER=y +CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 42e0098a1c7..79f6430f913 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -77,6 +77,8 @@ CONFIG_LBLAW1_LENGTH_32_KBYTES=y CONFIG_HID0_FINAL_EMCP=y CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 7ba44044f77..60c6b920f92 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -33,11 +33,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000
-/* - * Arbiter Setup - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/* diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index e23df14ec17..aaf92fe37ab 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -67,9 +67,6 @@ */ #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ - /* * Device configurations */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 17cd8adc859..608565a139c 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -39,9 +39,6 @@ */ #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ - /* * Device configurations */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index fbba2fbb50b..9531be30721 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -31,11 +31,6 @@
#define CONFIG_HWCONFIG
-/* - * Arbiter Setup - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/* diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index b528c2901b4..23496518b31 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -20,11 +20,6 @@ */ #define CONFIG_SYS_SICRL 0x00000000
-/* - * System performance - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ #define CONFIG_SYS_SPCR_OPT 1
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 14ebc8ead3d..51c47a8221b 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -328,8 +328,6 @@ /* * System performance */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 67f3a9bd65f..35210ccfd24 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -383,8 +383,6 @@ /* * System performance */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index eef1bdec63a..1c8574a40f3 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -403,8 +403,6 @@ boards, we say we have two, but don't display a message if we find only one. */ /* * System performance */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index c1973703c4a..d8a02b8e062 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -12,10 +12,6 @@ */ #define CONFIG_E300 1 /* E300 family */
-/* Arbiter Configuration Register */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ - /* System Priority Control Register */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index e8173da3233..6fa57ebee45 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -23,10 +23,6 @@ /* System performance - define the value i.e. CONFIG_SYS_XXX */
-/* Arbiter Configuration Register */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ - /* System Priority Control Regsiter */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 23e0da9624a..76b28e07f4e 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -21,11 +21,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000
-/* - * Arbiter Setup - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/* diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index b4acee058ca..bd8f786a580 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -20,9 +20,6 @@ #define CONFIG_BOOT_RETRY_MIN 30 #define CONFIG_RESET_TO_RETRY
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ - #define CONFIG_SYS_SICRH 0x00000000 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index bd24d78c1db..bc21857651c 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -40,14 +40,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 48a6172349d..e0c3065ac6a 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -25,14 +25,6 @@ #include "km/keymile-common.h" #include "km/km-powerpc.h"
-/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index e34f26e55d6..c2f4188a224 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -45,14 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 96e10325f0f..b1ba474e786 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -45,14 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 4b407af0364..d3f7c2c4d34 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -52,14 +52,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 20cbc1318ab..796040995d5 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -45,14 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 37acb0245b6..cfbf150b119 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -44,14 +44,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index d0eac0a2efe..60871b757d5 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -36,11 +36,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000
-/* - * Arbiter Setup - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/* diff --git a/include/configs/strider.h b/include/configs/strider.h index 8afd17d1b00..95bc20203f5 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -21,11 +21,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000
-/* - * Arbiter Setup - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/* diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 82ebbca4db1..e3653ea924a 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -42,14 +42,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index b196c77c4e7..81e11d22361 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -45,14 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 8dfff62de56..8c990266582 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -45,14 +45,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * Bus Arbitration Configuration Register (ACR) - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ -#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ -#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ - /* * DDR Setup */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 1ac6cbefd6c..76fe3be4460 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -27,9 +27,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00001000 #define CONFIG_SYS_MEMTEST_END 0x07000000
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */ - /* * Device configurations */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index caf216c22ce..b892e4537e3 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1960,10 +1960,6 @@ CONFIG_SYS_64BIT_VSPRINTF CONFIG_SYS_66MHZ CONFIG_SYS_8313ERDB_BROKEN_PMC CONFIG_SYS_83XX_DDR_USES_CS0 -CONFIG_SYS_ACR_APARK -CONFIG_SYS_ACR_PARKM -CONFIG_SYS_ACR_PIPE_DEP -CONFIG_SYS_ACR_RPTCNT CONFIG_SYS_ADDRESS_MAP_A CONFIG_SYS_ADV7611_I2C CONFIG_SYS_ALT_BOOT
Migrate the SPCR setting to Kconfig.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 29 +---- arch/powerpc/cpu/mpc83xx/initreg/Kconfig | 5 + arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr | 115 ++++++++++++++++++ arch/powerpc/cpu/mpc83xx/initreg/initreg.h | 43 +++++++ configs/MPC8308RDB_defconfig | 1 + configs/MPC8315ERDB_defconfig | 1 + configs/MPC8323ERDB_defconfig | 1 + configs/MPC8349EMDS_PCI64_defconfig | 2 + configs/MPC8349EMDS_SLAVE_defconfig | 2 + configs/MPC8349EMDS_defconfig | 2 + configs/MPC8349ITXGP_defconfig | 2 + configs/MPC8349ITX_LOWBOOT_defconfig | 2 + configs/MPC8349ITX_defconfig | 2 + configs/MPC837XEMDS_HOST_defconfig | 1 + configs/MPC837XEMDS_SLAVE_defconfig | 1 + configs/MPC837XEMDS_defconfig | 1 + configs/MPC837XERDB_SLAVE_defconfig | 1 + configs/MPC837XERDB_defconfig | 1 + configs/hrcon_defconfig | 1 + configs/hrcon_dh_defconfig | 1 + configs/mpc8308_p1m_defconfig | 1 + configs/strider_con_defconfig | 1 + configs/strider_con_dp_defconfig | 1 + configs/strider_cpu_defconfig | 1 + configs/strider_cpu_dp_defconfig | 1 + include/configs/MPC8308RDB.h | 2 - include/configs/MPC8315ERDB.h | 2 - include/configs/MPC8323ERDB.h | 3 - include/configs/MPC8349EMDS.h | 2 - include/configs/MPC8349ITX.h | 2 - include/configs/MPC837XEMDS.h | 3 - include/configs/MPC837XERDB.h | 3 - include/configs/hrcon.h | 2 - include/configs/mpc8308_p1m.h | 2 - include/configs/strider.h | 2 - scripts/config_whitelist.txt | 1 - 37 files changed, 192 insertions(+), 52 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/initreg/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr create mode 100644 arch/powerpc/cpu/mpc83xx/initreg/initreg.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 8a3bb10466c..fe20e85086b 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -296,6 +296,7 @@ source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig" source "arch/powerpc/cpu/mpc83xx/hid/Kconfig" source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig" source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig" +source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
menu "Legacy options"
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 77502567a70..59faa78d24c 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -16,6 +16,7 @@ #include "elbc/elbc.h" #include "sysio/sysio.h" #include "arbiter/arbiter.h" +#include "initreg/initreg.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -52,34 +53,6 @@ static void config_qe_ioports(void) */ void cpu_init_f (volatile immap_t * im) { - __be32 spcr_mask = -#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */ - SPCR_OPT | -#endif -#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ - SPCR_TSECEP | -#endif -#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ - SPCR_TSEC1EP | -#endif -#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ - SPCR_TSEC2EP | -#endif - 0; - __be32 spcr_val = -#ifdef CONFIG_SYS_SPCR_OPT - (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) | -#endif -#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ - (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) | -#endif -#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ - (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | -#endif -#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ - (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | -#endif - 0; __be32 sccr_mask = #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ SCCR_ENCCM | diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig new file mode 100644 index 00000000000..82c24891784 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig @@ -0,0 +1,5 @@ +menu "Initial register configuration" + +source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr" + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr new file mode 100644 index 00000000000..f32309e6c0f --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr @@ -0,0 +1,115 @@ +menu "SPCR - System priority and configuration register" + +choice + prompt "Optimize" + +config SPCR_OPT_UNSET + bool "Don't set value" + +config SPCR_OPT_NONE + bool "No performance enhancement" + +config SPCR_OPT_SPEC_READ + bool "Performance enhancement by speculative read" + +endchoice + +if ARCH_MPC8308 || ARCH_MPC831X || ARCH_MPC837X + +choice + prompt "TSEC emergency priority" + +config SPCR_TSECEP_UNSET + bool "Don't set value" + +config SPCR_TSECEP_0 + bool "Level 0 (lowest priority)" + +config SPCR_TSECEP_1 + bool "Level 1" + +config SPCR_TSECEP_2 + bool "Level 2" + +config SPCR_TSECEP_3 + bool "Level 3 (highest priority)" + +endchoice + +endif + +if ARCH_MPC8349 + +choice + prompt "TSEC1 emergency priority" + +config SPCR_TSEC1EP_UNSET + bool "Don't set value" + +config SPCR_TSEC1EP_0 + bool "Level 0 (lowest priority)" + +config SPCR_TSEC1EP_1 + bool "Level 1" + +config SPCR_TSEC1EP_2 + bool "Level 2" + +config SPCR_TSEC1EP_3 + bool "Level 3 (highest priority)" + +endchoice + +choice + prompt "TSEC2 emergency priority" + +config SPCR_TSEC2EP_UNSET + bool "Don't set value" + +config SPCR_TSEC2EP_0 + bool "Level 0 (lowest priority)" + +config SPCR_TSEC2EP_1 + bool "Level 1" + +config SPCR_TSEC2EP_2 + bool "Level 2" + +config SPCR_TSEC2EP_3 + bool "Level 3 (highest priority)" + +endchoice + +endif + +config SPCR_OPT + hex + default 0x0 if SPCR_OPT_UNSET + default 0x0 if SPCR_OPT_NONE + default 0x800000 if SPCR_OPT_SPEC_READ + +config SPCR_TSECEP + hex + default 0x0 if SPCR_TSECEP_UNSET + default 0x0 if SPCR_TSECEP_0 + default 0x100 if SPCR_TSECEP_1 + default 0x200 if SPCR_TSECEP_2 + default 0x300 if SPCR_TSECEP_3 + +config SPCR_TSEC1EP + hex + default 0x0 if SPCR_TSEC1EP_UNSET + default 0x0 if SPCR_TSEC1EP_0 + default 0x100 if SPCR_TSEC1EP_1 + default 0x200 if SPCR_TSEC1EP_2 + default 0x300 if SPCR_TSEC1EP_3 + +config SPCR_TSEC2EP + hex + default 0x0 if SPCR_TSEC2EP_UNSET + default 0x0 if SPCR_TSEC2EP_0 + default 0x1 if SPCR_TSEC2EP_1 + default 0x2 if SPCR_TSEC2EP_2 + default 0x3 if SPCR_TSEC2EP_3 + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h new file mode 100644 index 00000000000..d61c70f1fa6 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h @@ -0,0 +1,43 @@ +#define SPCR_PCIHPE_MASK 0x10000000 +#define SPCR_PCIPR_MASK 0x03000000 +#define SPCR_OPT_MASK 0x00800000 +#define SPCR_TBEN_MASK 0x00400000 +#define SPCR_COREPR_MASK 0x00300000 +#define SPCR_TSEC1DP_MASK 0x00003000 +#define SPCR_TSEC1BDP_MASK 0x00000C00 +#define SPCR_TSEC1EP_MASK 0x00000300 +#define SPCR_TSEC2DP_MASK 0x00000030 +#define SPCR_TSEC2BDP_MASK 0x0000000C +#define SPCR_TSEC2EP_MASK 0x00000003 +#define SPCR_TSECDP_MASK 0x00003000 +#define SPCR_TSECBDP_MASK 0x00000C00 +#define SPCR_TSECEP_MASK 0x00000300 + + const __be32 spcr_mask = +#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET) + SPCR_OPT_MASK | +#endif +#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET) + SPCR_TSECEP_MASK | +#endif +#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET) + SPCR_TSEC1EP_MASK | +#endif +#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET) + SPCR_TSEC2EP_MASK | +#endif + 0; + const __be32 spcr_val = +#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET) + CONFIG_SPCR_OPT | +#endif +#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET) + CONFIG_SPCR_TSECEP | +#endif +#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET) + CONFIG_SPCR_TSEC1EP | +#endif +#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET) + CONFIG_SPCR_TSEC2EP | +#endif + 0; diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 00feaccc305..a01ff8920b3 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -72,6 +72,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index 2263b9cb51b..e5e1b7a29d7 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -82,6 +82,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index b52d1fd62a5..08486f81a74 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -75,6 +75,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_OPT_SPEC_READ=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index 9108275f3c2..fa646f543fb 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -58,6 +58,8 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSEC1EP_3=y +CONFIG_SPCR_TSEC2EP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 7454dd64f1a..8af1a3d3b26 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -56,6 +56,8 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSEC1EP_3=y +CONFIG_SPCR_TSEC2EP_3=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 328c3aa567e..b2b944a30da 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -58,6 +58,8 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSEC1EP_3=y +CONFIG_SPCR_TSEC2EP_3=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index fa121d721ae..fcd78338c90 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -101,6 +101,8 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSEC1EP_3=y +CONFIG_SPCR_TSEC2EP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 0a79d1e6254..319b8d8c40c 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -101,6 +101,8 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSEC1EP_3=y +CONFIG_SPCR_TSEC2EP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index e7461072edf..f60527b361a 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -100,6 +100,8 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSEC1EP_3=y +CONFIG_SPCR_TSEC2EP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 0df5bdb2c5a..33e536ce182 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -106,6 +106,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index 99f206e719f..7d1f4051711 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -66,6 +66,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index 98dc6ca7848..d4515cbb8c3 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -86,6 +86,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 11a33d982f0..9730aefd548 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -66,6 +66,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index d43b364910a..7bf081a20bf 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -106,6 +106,7 @@ CONFIG_HID0_FINAL_ICE=y CONFIG_HID2_HBE=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 3dad033be02..9c1ab75e009 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -69,6 +69,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 4fb7cb5ffdb..0f1cc637cfc 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -69,6 +69,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index f73084c0e1f..f1559bef548 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -70,6 +70,7 @@ CONFIG_SICR_GTM_GPIO=y CONFIG_SICR_GPIOSEL_IEEE1588=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 722f25d63e9..b11a26c2fc1 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index dd3c83d4fcd..72cb274348e 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 1a351329872..f36404deb4d 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 79fdc140e5a..0ade98545a3 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 60c6b920f92..c4b604cc0d0 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -33,8 +33,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ - /* * DDR Setup */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 9531be30721..10742ae312a 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -31,8 +31,6 @@
#define CONFIG_HWCONFIG
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ - /* * DDR Setup */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 23496518b31..2ef16e543d8 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -20,9 +20,6 @@ */ #define CONFIG_SYS_SICRL 0x00000000
-/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ -#define CONFIG_SYS_SPCR_OPT 1 - /* * DDR Setup */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 51c47a8221b..b64a9118384 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -328,8 +328,6 @@ /* * System performance */ -#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ -#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 1c8574a40f3..d8e86f21ea1 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -403,8 +403,6 @@ boards, we say we have two, but don't display a message if we find only one. */ /* * System performance */ -#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ -#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index d8a02b8e062..5d469073312 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -12,9 +12,6 @@ */ #define CONFIG_E300 1 /* E300 family */
-/* System Priority Control Register */ -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ - /* * IP blocks clock configuration */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 6fa57ebee45..b6756c3794c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -23,9 +23,6 @@ /* System performance - define the value i.e. CONFIG_SYS_XXX */
-/* System Priority Control Regsiter */ -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ - /* System Clock Configuration Register */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 76b28e07f4e..9cb5df4a72e 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -21,8 +21,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ - /* * DDR Setup */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 60871b757d5..ce3a8994800 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -36,8 +36,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ - /* * DDR Setup */ diff --git a/include/configs/strider.h b/include/configs/strider.h index 95bc20203f5..e4584db7d5d 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -21,8 +21,6 @@ #define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ - /* * DDR Setup */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index b892e4537e3..7cba1da3a42 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4129,7 +4129,6 @@ CONFIG_SYS_SPANSION_BOOT CONFIG_SYS_SPCR_OPT CONFIG_SYS_SPCR_TSEC1EP CONFIG_SYS_SPCR_TSEC2EP -CONFIG_SYS_SPCR_TSECEP CONFIG_SYS_SPD_BUS_NUM CONFIG_SYS_SPI0 CONFIG_SYS_SPI0_NUM_CS
Migrate the CONFIG_LCRR_* settings to Kconfig.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/cpu_init.c | 22 --- arch/powerpc/cpu/mpc83xx/initreg/Kconfig | 1 + arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr | 139 ++++++++++++++++++ arch/powerpc/cpu/mpc83xx/initreg/initreg.h | 36 +++++ configs/MPC8308RDB_defconfig | 2 + configs/MPC8313ERDB_33_defconfig | 2 + configs/MPC8313ERDB_66_defconfig | 2 + configs/MPC8313ERDB_NAND_33_defconfig | 2 + configs/MPC8313ERDB_NAND_66_defconfig | 2 + configs/MPC8315ERDB_defconfig | 2 + configs/MPC8323ERDB_defconfig | 2 + configs/MPC832XEMDS_ATM_defconfig | 2 + configs/MPC832XEMDS_HOST_33_defconfig | 2 + configs/MPC832XEMDS_HOST_66_defconfig | 2 + configs/MPC832XEMDS_SLAVE_defconfig | 2 + configs/MPC832XEMDS_defconfig | 2 + configs/MPC8349EMDS_PCI64_defconfig | 2 + configs/MPC8349EMDS_SDRAM_defconfig | 2 + configs/MPC8349EMDS_SLAVE_defconfig | 2 + configs/MPC8349EMDS_defconfig | 2 + configs/MPC8349ITXGP_defconfig | 2 + configs/MPC8349ITX_LOWBOOT_defconfig | 2 + configs/MPC8349ITX_defconfig | 2 + configs/MPC837XEMDS_HOST_defconfig | 2 + configs/MPC837XEMDS_SLAVE_defconfig | 2 + configs/MPC837XEMDS_defconfig | 2 + configs/MPC837XERDB_SLAVE_defconfig | 2 + configs/MPC837XERDB_defconfig | 2 + configs/TQM834x_defconfig | 2 + configs/hrcon_defconfig | 2 + configs/hrcon_dh_defconfig | 2 + configs/ids8313_defconfig | 2 + configs/kmcoge5ne_defconfig | 3 + configs/kmeter1_defconfig | 3 + configs/kmopti2_defconfig | 3 + configs/kmsupx5_defconfig | 3 + configs/kmtegr1_defconfig | 3 + configs/kmtepr2_defconfig | 3 + configs/kmvect1_defconfig | 3 + configs/mpc8308_p1m_defconfig | 2 + configs/sbc8349_PCI_33_defconfig | 2 + configs/sbc8349_PCI_66_defconfig | 2 + configs/sbc8349_defconfig | 2 + configs/strider_con_defconfig | 2 + configs/strider_con_dp_defconfig | 2 + configs/strider_cpu_defconfig | 2 + configs/strider_cpu_dp_defconfig | 2 + configs/suvd3_defconfig | 3 + configs/tuge1_defconfig | 3 + configs/tuxx1_defconfig | 3 + configs/ve8313_defconfig | 2 + configs/vme8349_defconfig | 1 + include/configs/MPC8308RDB.h | 2 - include/configs/MPC8313ERDB_NAND.h | 2 - include/configs/MPC8313ERDB_NOR.h | 2 - include/configs/MPC8315ERDB.h | 2 - include/configs/MPC8323ERDB.h | 2 - include/configs/MPC832XEMDS.h | 2 - include/configs/MPC8349EMDS.h | 2 - include/configs/MPC8349EMDS_SDRAM.h | 2 - include/configs/MPC8349ITX.h | 2 - include/configs/MPC837XEMDS.h | 2 - include/configs/MPC837XERDB.h | 2 - include/configs/TQM834x.h | 12 -- include/configs/caddy2.h | 1 - include/configs/hrcon.h | 2 - include/configs/ids8313.h | 2 - include/configs/kmcoge5ne.h | 7 - include/configs/kmeter1.h | 7 - include/configs/kmopti2.h | 4 - include/configs/kmsupx5.h | 4 - include/configs/kmtegr1.h | 4 - include/configs/kmtepr2.h | 4 - include/configs/kmvect1.h | 4 - include/configs/mpc8308_p1m.h | 2 - include/configs/sbc8349.h | 2 - include/configs/strider.h | 2 - include/configs/suvd3.h | 4 - include/configs/tuge1.h | 4 - include/configs/tuxx1.h | 4 - include/configs/ve8313.h | 3 - include/configs/vme8349.h | 1 - scripts/config_whitelist.txt | 3 - 83 files changed, 281 insertions(+), 120 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 59faa78d24c..af8facad534 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -127,28 +127,6 @@ void cpu_init_f (volatile immap_t * im) #endif #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | -#endif - 0; - __be32 lcrr_mask = -#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ - LCRR_DBYP | -#endif -#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */ - LCRR_EADC | -#endif -#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ - LCRR_CLKDIV | -#endif - 0; - __be32 lcrr_val = -#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ - CONFIG_SYS_LCRR_DBYP | -#endif -#ifdef CONFIG_SYS_LCRR_EADC - CONFIG_SYS_LCRR_EADC | -#endif -#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ - CONFIG_SYS_LCRR_CLKDIV | #endif 0;
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig index 82c24891784..a6b42a29af2 100644 --- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig @@ -1,5 +1,6 @@ menu "Initial register configuration"
source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr" +source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr"
endmenu diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr new file mode 100644 index 00000000000..e6b6130de25 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr @@ -0,0 +1,139 @@ +menu "LCRR - Clock Ratio Register register" + +if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X + +choice + prompt "DLL bypass" + +config LCRR_DBYP_UNSET + bool "Don't set value" + +config LCRR_DBYP_PLL_ENABLED + bool "PLL enabled" + +config LCRR_DBYP_PLL_BYPASSED + bool "PLL bypassed" + +endchoice + +endif + +if ARCH_MPC834X || ARCH_MPC8360 + +choice + prompt "Additional delay cycles for SDRAM control signals" + +config LCRR_BUFCMDC_UNSET + bool "Don't set value" + +config LCRR_BUFCMDC_4 + bool "4" + +config LCRR_BUFCMDC_1 + bool "1" + +config LCRR_BUFCMDC_2 + bool "2" + +config LCRR_BUFCMDC_3 + bool "3" + +endchoice + +choice + prompt "Extended CAS latency" + +config LCRR_ECL_UNSET + bool "Don't set value" + +config LCRR_ECL_4 + bool "4" + +config LCRR_ECL_5 + bool "5" + +config LCRR_ECL_6 + bool "6" + +config LCRR_ECL_7 + bool "7" + +endchoice + +endif # ARCH_MPC834X || ARCH_MPC8360 + +if !ARCH_MPC8308 + +choice + prompt "External address delay cycles" + +config LCRR_EADC_UNSET + bool "Don't set value" + +config LCRR_EADC_4 + bool "4" + +config LCRR_EADC_1 + bool "1" + +config LCRR_EADC_2 + bool "2" + +config LCRR_EADC_3 + bool "3" + +endchoice + +endif # !ARCH_MPC8308 + +choice + prompt "System clock divider" + +config LCRR_CLKDIV_UNSET + bool "Don't set value" + +config LCRR_CLKDIV_2 + bool "2" + +config LCRR_CLKDIV_4 + bool "4" + +config LCRR_CLKDIV_8 + bool "8" + +endchoice + +config LCRR_DBYP + hex + default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED + default 0x80000000 if LCRR_DBYP_PLL_BYPASSED + +config LCRR_BUFCMDC + hex + default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET + default 0x10000000 if LCRR_BUFCMDC_1 + default 0x20000000 if LCRR_BUFCMDC_2 + default 0x30000000 if LCRR_BUFCMDC_3 + +config LCRR_ECL + hex + default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET + default 0x1000000 if LCRR_ECL_5 + default 0x2000000 if LCRR_ECL_6 + default 0x3000000 if LCRR_ECL_7 + +config LCRR_EADC + hex + default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET + default 0x10000 if LCRR_EADC_1 + default 0x20000 if LCRR_EADC_2 + default 0x30000 if LCRR_EADC_3 + +config LCRR_CLKDIV + hex + default 0x0 if LCRR_CLKDIV_UNSET + default 0x2 if LCRR_CLKDIV_2 + default 0x4 if LCRR_CLKDIV_4 + default 0x8 if LCRR_CLKDIV_8 + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h index d61c70f1fa6..63aa5c94669 100644 --- a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h +++ b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h @@ -39,5 +39,41 @@ #endif #if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET) CONFIG_SPCR_TSEC2EP | +#endif + 0; + + const __be32 lcrr_mask = +#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET) + LCRR_DBYP | +#endif +#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET) + LCRR_BUFCMDC | +#endif +#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET) + LCRR_ECL | +#endif +#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET) + LCRR_EADC | +#endif +#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET) + LCRR_CLKDIV | +#endif + 0; + + const __be32 lcrr_val = +#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET) + CONFIG_LCRR_DBYP | +#endif +#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET) + CONFIG_LCRR_BUFCMDC | +#endif +#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET) + CONFIG_LCRR_ECL | +#endif +#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET) + CONFIG_LCRR_EADC | +#endif +#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET) + CONFIG_LCRR_CLKDIV | #endif 0; diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index a01ff8920b3..1a38ebd5492 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -73,6 +73,8 @@ CONFIG_SICR_TMSOBI2_2_5_V=y CONFIG_ACR_PIPE_DEP_4=y CONFIG_ACR_RPTCNT_4=y CONFIG_SPCR_TSECEP_3=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index b368aee9663..04eb29ab9eb 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -159,3 +159,5 @@ CONFIG_OR2_SETA_EXTERNAL=y CONFIG_OR2_XACS_EXTENDED=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index ddf9060df42..8bbeb977784 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -158,3 +158,5 @@ CONFIG_OR2_SETA_EXTERNAL=y CONFIG_OR2_XACS_EXTENDED=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index f0c43ca2dcd..17b8e9fd19f 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -166,3 +166,5 @@ CONFIG_OR2_SETA_EXTERNAL=y CONFIG_OR2_XACS_EXTENDED=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index ab9423f8bcc..d6d1983a311 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -165,3 +165,5 @@ CONFIG_OR2_SETA_EXTERNAL=y CONFIG_OR2_XACS_EXTENDED=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index e5e1b7a29d7..08b5cc50861 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -143,3 +143,5 @@ CONFIG_OR1_CHT_TWO_CLOCK=y CONFIG_OR1_CSCT_8_CYCLE=y CONFIG_OR1_CST_ONE_CLOCK=y CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 08486f81a74..8ea942d7d9f 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -108,3 +108,5 @@ CONFIG_OR0_XACS_EXTENDED=y CONFIG_OR0_XAM_SET=y CONFIG_OR0_TRLX_RELAXED=y CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 807d3e391a3..c39f449da9b 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -143,3 +143,5 @@ CONFIG_OR3_XACS_EXTENDED=y CONFIG_OR3_XAM_SET=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index e328deb9fe4..0e65d21bdbf 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -163,3 +163,5 @@ CONFIG_OR3_XACS_EXTENDED=y CONFIG_OR3_XAM_SET=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index d5bf354eeca..472384fa140 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -163,3 +163,5 @@ CONFIG_OR3_XACS_EXTENDED=y CONFIG_OR3_XAM_SET=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index 9d9d9051189..ec8a94cd2ab 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -160,3 +160,5 @@ CONFIG_OR3_XACS_EXTENDED=y CONFIG_OR3_XAM_SET=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index 518f7114d79..8a26001f7f6 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -142,3 +142,5 @@ CONFIG_OR3_XACS_EXTENDED=y CONFIG_OR3_XAM_SET=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index fa646f543fb..35b394ba6af 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -104,3 +104,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_15=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index 8589470b2e3..936458a441a 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -113,3 +113,5 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 8af1a3d3b26..9649967bf0b 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -104,3 +104,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_15=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index b2b944a30da..bb0d166e4df 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -107,3 +107,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_15=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index fcd78338c90..eddb72b1e04 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -178,3 +178,5 @@ CONFIG_BR3_MACHINE_UPMA=y CONFIG_BR3_PORTSIZE_16BIT=y CONFIG_OR3_AM_32_KBYTES=y CONFIG_OR3_BI_BURSTINHIBIT=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 319b8d8c40c..b394da3a052 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -186,3 +186,5 @@ CONFIG_BR3_MACHINE_UPMA=y CONFIG_BR3_PORTSIZE_16BIT=y CONFIG_OR3_AM_32_KBYTES=y CONFIG_OR3_BI_BURSTINHIBIT=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index f60527b361a..274fbddf996 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -185,3 +185,5 @@ CONFIG_BR3_MACHINE_UPMA=y CONFIG_BR3_PORTSIZE_16BIT=y CONFIG_OR3_AM_32_KBYTES=y CONFIG_OR3_BI_BURSTINHIBIT=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 33e536ce182..6e6fc54d510 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -178,3 +178,5 @@ CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_CHT_TWO_CLOCK=y CONFIG_OR3_CST_ONE_CLOCK=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_8=y diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig index 7d1f4051711..421e176226e 100644 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -131,3 +131,5 @@ CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_CHT_TWO_CLOCK=y CONFIG_OR3_CST_ONE_CLOCK=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_8=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index d4515cbb8c3..cd03f3ff9ec 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -154,3 +154,5 @@ CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_CHT_TWO_CLOCK=y CONFIG_OR3_CST_ONE_CLOCK=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_8=y diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index 9730aefd548..c90ebc8d7eb 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -132,3 +132,5 @@ CONFIG_OR2_SETA_EXTERNAL=y CONFIG_OR2_XACS_EXTENDED=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_8=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 7bf081a20bf..95f47962814 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -175,3 +175,5 @@ CONFIG_OR2_SETA_EXTERNAL=y CONFIG_OR2_XACS_EXTENDED=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_8=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index f5746cfad71..9d9f105f75d 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -147,3 +147,5 @@ CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y CONFIG_OR0_CSNT_EARLIER=y CONFIG_OR0_SCY_5=y CONFIG_OR0_TRLX_RELAXED=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_8=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 9c1ab75e009..bc4c2a91fb2 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -131,3 +131,5 @@ CONFIG_OR1_XACS_EXTENDED=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_TRLX_RELAXED=y CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 0f1cc637cfc..af93aef1be6 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -129,3 +129,5 @@ CONFIG_OR1_XACS_EXTENDED=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_TRLX_RELAXED=y CONFIG_OR1_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index f835868209f..d9b1642671a 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -170,3 +170,5 @@ CONFIG_OR3_AM_32_KBYTES=y CONFIG_OR3_CSNT_EARLIER=y CONFIG_OR3_SCY_1=y CONFIG_OR3_TRLX_RELAXED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 7751e5a8989..941efcdf9aa 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -192,3 +192,6 @@ CONFIG_OR4_CSNT_EARLIER=y CONFIG_OR4_EAD_EXTRA=y CONFIG_OR4_SCY_2=y CONFIG_OR4_TRLX_RELAXED=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y +CONFIG_LCRR_EADC_2=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 2bb31588734..4929a6039b4 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -154,3 +154,6 @@ CONFIG_OR3_CSNT_EARLIER=y CONFIG_OR3_EAD_EXTRA=y CONFIG_OR3_SCY_2=y CONFIG_OR3_TRLX_RELAXED=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y +CONFIG_LCRR_EADC_2=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 5eb5c939ebb..afe424b8df8 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -179,3 +179,6 @@ CONFIG_BR3_PORTSIZE_16BIT=y CONFIG_OR3_AM_256_MBYTES=y CONFIG_OR3_SCY_4=y CONFIG_OR3_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 0ad8801df95..1a78680bd0b 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -157,3 +157,6 @@ CONFIG_OR2_EAD_EXTRA=y CONFIG_OR2_SCY_2=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 8dfc4438add..d874149fe36 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -157,3 +157,6 @@ CONFIG_BR3_PORTSIZE_16BIT=y CONFIG_OR3_AM_256_MBYTES=y CONFIG_OR3_SCY_5=y CONFIG_OR3_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 1a84ff5e0bb..32d098028a7 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -179,3 +179,6 @@ CONFIG_BR3_PORTSIZE_16BIT=y CONFIG_OR3_AM_256_MBYTES=y CONFIG_OR3_SCY_4=y CONFIG_OR3_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index a746f195e65..26d9a7cf7af 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -177,3 +177,6 @@ CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y CONFIG_OR3_CSNT_EARLIER=y CONFIG_OR3_SCY_3=y CONFIG_OR3_TRLX_RELAXED=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index f1559bef548..0789ecd586a 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -122,3 +122,5 @@ CONFIG_BR2_PORTSIZE_8BIT=y CONFIG_OR2_AM_32_KBYTES=y CONFIG_OR2_SCY_4=y CONFIG_OR2_EHTR_1_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index a213f038ee4..a363070dd87 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -106,3 +106,5 @@ CONFIG_OR0_XACS_EXTENDED=y CONFIG_OR0_XAM_SET=y CONFIG_OR0_TRLX_RELAXED=y CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 321c3d40735..215f31df282 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -106,3 +106,5 @@ CONFIG_OR0_XACS_EXTENDED=y CONFIG_OR0_XAM_SET=y CONFIG_OR0_TRLX_RELAXED=y CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 865a3ef74a5..d492b861d5c 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -84,3 +84,5 @@ CONFIG_OR0_XACS_EXTENDED=y CONFIG_OR0_XAM_SET=y CONFIG_OR0_TRLX_RELAXED=y CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index b11a26c2fc1..9f05b5693f9 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_5=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 72cb274348e..a1f96625189 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_5=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index f36404deb4d..2477ee5ca43 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_5=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 0ade98545a3..da16d5dbfa6 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y CONFIG_OR1_SCY_5=y CONFIG_OR1_XAM_SET=y CONFIG_OR1_EHTR_NORMAL=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 28e386db246..c970cde05eb 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -175,3 +175,6 @@ CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y CONFIG_OR3_CSNT_EARLIER=y CONFIG_OR3_SCY_3=y CONFIG_OR3_TRLX_RELAXED=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index fb18a46ec61..550f524a3cf 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -157,3 +157,6 @@ CONFIG_OR2_EAD_EXTRA=y CONFIG_OR2_SCY_2=y CONFIG_OR2_TRLX_RELAXED=y CONFIG_OR2_EHTR_4_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index a034f302b23..d5ec8e5bf2e 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -182,3 +182,6 @@ CONFIG_OR3_CSNT_EARLIER=y CONFIG_OR3_SCY_2=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_4_CYCLE=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_EADC_1=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 79f6430f913..0a9521b2512 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -145,3 +145,5 @@ CONFIG_OR3_SCY_15=y CONFIG_OR3_XACS_EXTENDED=y CONFIG_OR3_TRLX_RELAXED=y CONFIG_OR3_EHTR_8_CYCLE=y +CONFIG_LCRR_EADC_3=y +CONFIG_LCRR_CLKDIV_2=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 9ac88c0a4ba..24bbba1aa73 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -118,3 +118,4 @@ CONFIG_BR1_MACHINE_GPCM=y CONFIG_BR1_PORTSIZE_32BIT=y CONFIG_OR1_AM_256_KBYTES=y CONFIG_OR1_SETA_EXTERNAL=y +CONFIG_LCRR_CLKDIV_4=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index c4b604cc0d0..e625f8709cb 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -126,8 +126,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000
/* diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index aaf92fe37ab..08c5b56da71 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -191,8 +191,6 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF) /* 0x0004ff0f */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 608565a139c..2a39ffa6c2c 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -164,8 +164,6 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF) /* 0x0004ff0f */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 10742ae312a..b49022b916d 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -121,8 +121,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000 #define CONFIG_FSL_ELBC 1
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 2ef16e543d8..497c60bcdaa 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -118,8 +118,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000
/* diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 195d62ce50d..520f01f177d 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -118,8 +118,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000
/* diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index b64a9118384..20433445248 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -161,8 +161,6 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000
/* diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 35210ccfd24..70fc29e8ade 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -158,8 +158,6 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000
/* diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index d8e86f21ea1..6f040a3d6dc 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -258,8 +258,6 @@ boards, we say we have two, but don't display a message if we find only one. */ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000
/* LB sdram refresh timer, about 6us */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 5d469073312..5f0050a97d5 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -139,8 +139,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_FSL_ELBC 1
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index b6756c3794c..ef23d004085 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -163,8 +163,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_FSL_ELBC 1
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index d713c695f7c..8171f8531ba 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -16,18 +16,6 @@ */ #define CONFIG_E300 1 /* E300 Family */
-/* - * Local Bus LCRR - * LCRR: DLL bypass, Clock divider is 8 - * - * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz - * - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 - /* board pre init: do not call, nothing to do */
/* detect the number of flash banks */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index b4516267f15..a0642aef112 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -104,7 +104,6 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 9cb5df4a72e..0919bb544d0 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -115,8 +115,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000
/* diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index bd8f786a580..174c181ffaf 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -39,8 +39,6 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR (0x00040000 |\ (0xFF << LBCR_BMT_SHIFT) |\ 0xF) diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index bc21857651c..4e2bd57381b 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -296,13 +296,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 - /* * PAXE on the local bus CS3 */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index e0c3065ac6a..bbf3783ef93 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -276,13 +276,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 - /* * PAXE on the local bus CS3 */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index c2f4188a224..77dc6a93b19 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -294,10 +294,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index b1ba474e786..561ae7a1483 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -294,10 +294,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index d3f7c2c4d34..b4ebde8ba5a 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -346,10 +346,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000
/* must be after the include because KMBEC_FPGA is otherwise undefined */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 796040995d5..80f6f4daa46 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -294,10 +294,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index cfbf150b119..9e301a9728d 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -338,10 +338,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index ce3a8994800..aca4a655e03 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -130,8 +130,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000
/* diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 775bbe417af..6bad6511339 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -131,8 +131,6 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ diff --git a/include/configs/strider.h b/include/configs/strider.h index e4584db7d5d..69e22fb141e 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -115,8 +115,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000
/* diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index e3653ea924a..ad3323fd0e1 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -291,10 +291,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 81e11d22361..466f75a44eb 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -294,10 +294,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 8c990266582..df9d7c9d8c9 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -294,10 +294,6 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR_DBYP 0x80000000 -#define CONFIG_SYS_LCRR_EADC 0x00010000 -#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 - #define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 76fe3be4460..8b20bfd1003 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -133,9 +133,6 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3 -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 - #define CONFIG_SYS_LBC_LBCR 0x00040000
#define CONFIG_SYS_LBC_MRTPR 0x20000000 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 1a3a55b707e..d50a5263a70 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -104,7 +104,6 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 7cba1da3a42..4fa890234bf 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3245,9 +3245,6 @@ CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_SIZE CONFIG_SYS_LB_SDRAM CONFIG_SYS_LCD_BASE -CONFIG_SYS_LCRR_CLKDIV -CONFIG_SYS_LCRR_DBYP -CONFIG_SYS_LCRR_EADC CONFIG_SYS_LDB_CLOCK CONFIG_SYS_LDSCRIPT CONFIG_SYS_LED_BASE
CONFIG_SYS_DDR_BASE is specific to mpc83xx an is always set to the same value as CONFIG_SYS_SDRAM_BASE. Just use CONFIG_SYS_SDRAM_BASE instead.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- board/esd/vme8349/vme8349.c | 2 +- board/freescale/mpc8323erdb/mpc8323erdb.c | 2 +- board/freescale/mpc832xemds/mpc832xemds.c | 2 +- board/freescale/mpc8349emds/mpc8349emds.c | 2 +- board/freescale/mpc8349itx/mpc8349itx.c | 2 +- board/ids/ids8313/ids8313.c | 2 +- board/keymile/km83xx/km83xx.c | 4 ++-- board/sbc8349/sbc8349.c | 2 +- board/tqc/tqm834x/tqm834x.c | 6 +++--- board/ve8313/ve8313.c | 2 +- include/configs/MPC8308RDB.h | 5 ++--- include/configs/MPC8313ERDB_NAND.h | 5 ++--- include/configs/MPC8313ERDB_NOR.h | 5 ++--- include/configs/MPC8315ERDB.h | 5 ++--- include/configs/MPC8323ERDB.h | 5 ++--- include/configs/MPC832XEMDS.h | 5 ++--- include/configs/MPC8349EMDS.h | 5 ++--- include/configs/MPC8349EMDS_SDRAM.h | 5 ++--- include/configs/MPC8349ITX.h | 5 ++--- include/configs/MPC837XEMDS.h | 5 ++--- include/configs/MPC837XERDB.h | 5 ++--- include/configs/TQM834x.h | 5 ++--- include/configs/caddy2.h | 5 ++--- include/configs/hrcon.h | 5 ++--- include/configs/ids8313.h | 5 ++--- include/configs/kmcoge5ne.h | 5 ++--- include/configs/kmeter1.h | 5 ++--- include/configs/kmopti2.h | 5 ++--- include/configs/kmsupx5.h | 5 ++--- include/configs/kmtegr1.h | 5 ++--- include/configs/kmtepr2.h | 5 ++--- include/configs/kmvect1.h | 5 ++--- include/configs/mpc8308_p1m.h | 5 ++--- include/configs/sbc8349.h | 5 ++--- include/configs/strider.h | 5 ++--- include/configs/suvd3.h | 5 ++--- include/configs/tuge1.h | 5 ++--- include/configs/tuxx1.h | 5 ++--- include/configs/ve8313.h | 5 ++--- include/configs/vme8349.h | 5 ++--- scripts/config_whitelist.txt | 1 - 41 files changed, 73 insertions(+), 104 deletions(-)
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index a46d0b6da63..4c220fa8e13 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -38,7 +38,7 @@ int dram_init(void) return -ENXIO;
/* DDR SDRAM - Main memory */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = spd_sdram();
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 772688186b5..2dc6d7f5f5f 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -79,7 +79,7 @@ int dram_init(void) return -ENXIO;
/* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = fixed_sdram();
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c index 869538feb92..61b95c601e6 100644 --- a/board/freescale/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -98,7 +98,7 @@ int dram_init(void) return -ENXIO;
/* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = fixed_sdram();
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index d40ed3742e0..ea018e5d201 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -56,7 +56,7 @@ int dram_init(void) return -ENXIO;
/* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) #ifndef CONFIG_SYS_FSL_DDR2 msize = spd_sdram() * 1024 * 1024; diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 62bcf235711..aaaea7ce89f 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -132,7 +132,7 @@ int dram_init(void) return -ENXIO;
/* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #ifdef CONFIG_SPD_EEPROM msize = spd_sdram(); #else diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index d547af4b05a..a37ca8a2f44 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -96,7 +96,7 @@ int fixed_sdram(unsigned long config) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); /* now check the real size */ disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); + msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); enable_addr_trans(); #endif return msize; diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 1fd6f919014..880ce67fa6c 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -311,7 +311,7 @@ static int fixed_sdram(void)
msize = CONFIG_SYS_DDR_SIZE << 20; disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); + msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); enable_addr_trans(); msize /= (1024 * 1024); if (CONFIG_SYS_DDR_SIZE != msize) { @@ -338,7 +338,7 @@ int dram_init(void) return -ENXIO;
out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_BASE & LAWBAR_BAR); + CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR); msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index b8ba29ac6da..5584b3d1796 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -45,7 +45,7 @@ int dram_init(void) return -1;
/* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) msize = spd_sdram(); #else diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index c75251e132c..04941b26be4 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -72,13 +72,13 @@ int dram_init(void) int cs;
/* during size detection, set up the max DDRLAW size */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE; im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
/* set CS bounds to maximum size */ for(cs = 0; cs < 4; ++cs) { set_cs_bounds(cs, - CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), + CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS), DDR_MAX_SIZE_PER_CS);
set_cs_config(cs, INITIAL_CS_CONFIG); @@ -102,7 +102,7 @@ int dram_init(void) debug("\nDetecting Bank%d\n", cs);
bank_size = get_ddr_bank_size(cs, - (long *)(CONFIG_SYS_DDR_BASE + size)); + (long *)(CONFIG_SYS_SDRAM_BASE + size)); size += bank_size;
debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20); diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index f0fc1fe3b31..609585bc653 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -80,7 +80,7 @@ static long fixed_sdram(void)
/* now check the real size */ disable_addr_trans (); - msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize); + msize = get_ram_size (CONFIG_SYS_SDRAM_BASE, msize); enable_addr_trans (); #endif
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index e625f8709cb..d9361fd8a03 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -36,9 +36,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 08c5b56da71..08c83996c73 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -86,9 +86,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 2a39ffa6c2c..169cc09d06b 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -58,9 +58,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index b49022b916d..c5a229deb4c 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -34,9 +34,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 497c60bcdaa..3e6febfc9d3 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -23,9 +23,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
#undef CONFIG_SPD_EEPROM #if defined(CONFIG_SPD_EEPROM) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 520f01f177d..4b3f70c916c 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -20,9 +20,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
#undef CONFIG_SPD_EEPROM diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 20433445248..1a96be0895c 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -52,9 +52,8 @@ */ #undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 70fc29e8ade..311f87b5b3c 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -52,9 +52,8 @@ */ #undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 6f040a3d6dc..bb3bcfcc448 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -142,9 +142,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x2000 diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 5f0050a97d5..e34a36cadd8 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -35,9 +35,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index ef23d004085..33d4ced92f7 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -58,9 +58,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 #define CONFIG_SYS_83XX_DDR_USES_CS0
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 8171f8531ba..53fac4d675a 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -24,9 +24,8 @@ * DDR Setup */ /* DDR is system memory*/ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index a0642aef112..f14e5faafa6 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -51,9 +51,8 @@ */ #undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 0919bb544d0..ae3fcfd3d79 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -24,9 +24,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 174c181ffaf..504a136daab 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -51,9 +51,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 4e2bd57381b..8f40f964958 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -43,11 +43,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index bbf3783ef93..2e8affb6180 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -28,11 +28,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 77dc6a93b19..3be53285dbc 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 561ae7a1483..74e719cc79f 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index b4ebde8ba5a..c6913838ce7 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -55,11 +55,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 80f6f4daa46..4af86195c5e 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 9e301a9728d..d8f4d269ed4 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -47,11 +47,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index aca4a655e03..8836b70b762 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -39,9 +39,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 6bad6511339..709387ecf79 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -46,9 +46,8 @@ */ #undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/strider.h b/include/configs/strider.h index 69e22fb141e..c01531c3ca2 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -24,9 +24,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index ad3323fd0e1..3521de8d2ee 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -45,11 +45,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 466f75a44eb..86e402ae233 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index df9d7c9d8c9..5009349c9bd 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 8b20bfd1003..cd6c686b890 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -34,9 +34,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index d50a5263a70..14a84fabc97 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -51,9 +51,8 @@ */ #undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 4fa890234bf..35198df9828 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2295,7 +2295,6 @@ CONFIG_SYS_DDRCDR_VALUE CONFIG_SYS_DDRD CONFIG_SYS_DDRTC CONFIG_SYS_DDRUA -CONFIG_SYS_DDR_BASE CONFIG_SYS_DDR_BLOCK1_SIZE CONFIG_SYS_DDR_BLOCK2_BASE CONFIG_SYS_DDR_CDR_1
CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- board/freescale/mpc8308rdb/sdram.c | 4 ++-- board/freescale/mpc8313erdb/sdram.c | 8 ++++---- board/freescale/mpc8315erdb/sdram.c | 2 +- board/freescale/mpc8349emds/mpc8349emds.c | 8 ++++---- board/freescale/mpc8349itx/mpc8349itx.c | 8 ++++---- board/freescale/mpc837xemds/mpc837xemds.c | 2 +- board/freescale/mpc837xerdb/mpc837xerdb.c | 2 +- board/gdsys/mpc8308/sdram.c | 4 ++-- board/ids/ids8313/ids8313.c | 2 +- board/mpc8308_p1m/sdram.c | 4 ++-- board/sbc8349/sbc8349.c | 8 ++++---- board/ve8313/ve8313.c | 8 ++++---- drivers/ddr/fsl/main.c | 4 ++++ include/configs/MPC8308RDB.h | 1 - include/configs/MPC8313ERDB_NAND.h | 1 - include/configs/MPC8313ERDB_NOR.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8323ERDB.h | 1 - include/configs/MPC832XEMDS.h | 1 - include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349EMDS_SDRAM.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/configs/TQM834x.h | 1 - include/configs/caddy2.h | 1 - include/configs/hrcon.h | 1 - include/configs/ids8313.h | 1 - include/configs/kmcoge5ne.h | 1 - include/configs/kmeter1.h | 1 - include/configs/kmopti2.h | 1 - include/configs/kmsupx5.h | 1 - include/configs/kmtegr1.h | 1 - include/configs/kmtepr2.h | 1 - include/configs/kmvect1.h | 1 - include/configs/mpc8308_p1m.h | 1 - include/configs/sbc8349.h | 1 - include/configs/strider.h | 1 - include/configs/suvd3.h | 1 - include/configs/tuge1.h | 1 - include/configs/tuxx1.h | 1 - include/configs/ve8313.h | 1 - include/configs/vme8349.h | 1 - 44 files changed, 35 insertions(+), 61 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index b3cbf9f8823..5ca307ca583 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -281,7 +281,7 @@ long int spd_sdram() /* * Set up LAWBAR for all of DDR. */ - ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); debug("DDR:bar=0x%08x\n", ecm->bar); debug("DDR:ar=0x%08x\n", ecm->ar); diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c index e64b3107b5f..317e63ea6a1 100644 --- a/board/freescale/mpc8308rdb/sdram.c +++ b/board/freescale/mpc8308rdb/sdram.c @@ -33,7 +33,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -61,7 +61,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync();
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); }
int dram_init(void) diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 5e074e3d87b..090412d4b6c 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -47,7 +47,7 @@ static long fixed_sdram(void) volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
@@ -57,12 +57,12 @@ static long fixed_sdram(void) */ __udelay(50000);
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index b9f94c83324..2f0f29a0e57 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -44,7 +44,7 @@ static long fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index ea018e5d201..f14276f6a87 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -91,7 +91,7 @@ int fixed_sdram(void) u32 ddr_size = msize << 20; /* DDR size in bytes */ u32 ddr_size_log2 = __ilog2(ddr_size);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256) @@ -112,12 +112,12 @@ int fixed_sdram(void) im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index aaaea7ce89f..81b3f00b56e 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -37,14 +37,14 @@ int fixed_sdram(void)
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 09a046dff8d..16922087c01 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -252,7 +252,7 @@ int fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
#if (CONFIG_SYS_DDR_SIZE != 512) diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index d9a47b90b2f..18f396aac8b 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -95,7 +95,7 @@ int fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 5ced8eb0819..3eb0e37b7b5 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -34,7 +34,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -62,7 +62,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync();
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); }
int dram_init(void) diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index a37ca8a2f44..a66234aa857 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -57,7 +57,7 @@ int fixed_sdram(unsigned long config) u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); sync(); diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c index 4118c019ccf..baf70d8807b 100644 --- a/board/mpc8308_p1m/sdram.c +++ b/board/mpc8308_p1m/sdram.c @@ -29,7 +29,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -57,7 +57,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync();
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); }
int dram_init(void) diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 5584b3d1796..e51eeae065d 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -79,19 +79,19 @@ int fixed_sdram(void) u32 ddr_size = msize << 20; /* DDR size in bytes */ u32 ddr_size_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256) #warning Currently any ddr size other than 256 is not supported #endif
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index 609585bc653..f4148a21e3b 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -38,7 +38,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1))); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -48,12 +48,12 @@ static long fixed_sdram(void) */ __udelay(50000);
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif out_be32(&im->ddr.csbnds[0].csbnds, - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA)); out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 6d018fde2b2..e1f69a1d25c 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -23,8 +23,12 @@ * 0x80_8000_0000 ~ 0xff_ffff_ffff */ #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY +#ifdef CONFIG_MPC83xx +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE +#else #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE #endif +#endif
#ifdef CONFIG_PPC #include <asm/fsl_law.h> diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index d9361fd8a03..5d31d4a0b6b 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -37,7 +37,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 08c83996c73..6f100fc7e7b 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -87,7 +87,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 169cc09d06b..0f246dc5186 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -59,7 +59,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index c5a229deb4c..0b94b0c5cf9 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -35,7 +35,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 3e6febfc9d3..a90a9a86f8d 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -24,7 +24,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
#undef CONFIG_SPD_EEPROM #if defined(CONFIG_SPD_EEPROM) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 4b3f70c916c..88b6f873978 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -21,7 +21,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
#undef CONFIG_SPD_EEPROM diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 1a96be0895c..fdbd15ea93e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -53,7 +53,6 @@ #undef CONFIG_DDR_32BIT
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 311f87b5b3c..1e0e297351e 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -53,7 +53,6 @@ #undef CONFIG_DDR_32BIT
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index bb3bcfcc448..388910ac38d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -143,7 +143,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x2000 diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e34a36cadd8..61f9eaf7150 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -36,7 +36,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 33d4ced92f7..07b206ff9f9 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -59,7 +59,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 #define CONFIG_SYS_83XX_DDR_USES_CS0
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 53fac4d675a..0da34d05afc 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -25,7 +25,6 @@ */ /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index f14e5faafa6..928136f325f 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -52,7 +52,6 @@ #undef CONFIG_DDR_32BIT
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index ae3fcfd3d79..d73e848b0c7 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -25,7 +25,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 504a136daab..155815a8815 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -52,7 +52,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 8f40f964958..720d28d61a0 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -46,7 +46,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2e8affb6180..290108d4fc4 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -31,7 +31,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 3be53285dbc..0759604810a 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 74e719cc79f..319e3bc1ece 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index c6913838ce7..85e9101b054 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -58,7 +58,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 4af86195c5e..6ec944f9429 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index d8f4d269ed4..d7cbdde215d 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -50,7 +50,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 8836b70b762..0392c3e8b40 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -40,7 +40,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 709387ecf79..b4ae7b75543 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -47,7 +47,6 @@ #undef CONFIG_DDR_32BIT
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/strider.h b/include/configs/strider.h index c01531c3ca2..e92bd1e8f10 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -25,7 +25,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 3521de8d2ee..8b3b45416da 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -48,7 +48,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 86e402ae233..5dc9e8997e5 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 5009349c9bd..658080eeefc 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index cd6c686b890..2116d6bbcf8 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -35,7 +35,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 14a84fabc97..1bce6c732d9 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -52,7 +52,6 @@ #undef CONFIG_DDR_32BIT
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING
Except for one counter example, CONFIG_SYS_LBC_LBCR always has a value of either 0x00040000 or 0x00000000.
CONFIG_SYS_LBC_MRTPR always has the value 0x20000000.
CONFIG_SYS_LBC_LSDMR_{1,2,4,5} are not set for any mpc83xx board.
CONFIG_SYS_LBC_LSRT is set by one board (to 0x32000000).
To simplify the configuration files, hardcode the setting of these values for mpc83xx.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- board/freescale/mpc8313erdb/sdram.c | 5 +++-- board/freescale/mpc8349emds/mpc8349emds.c | 27 +++++++++++++++-------- board/ids/ids8313/ids8313.c | 4 ++-- board/sbc8349/sbc8349.c | 25 ++++++++++++++------- board/ve8313/ve8313.c | 4 ++-- include/configs/MPC8308RDB.h | 5 ----- include/configs/MPC8313ERDB_NAND.h | 10 --------- include/configs/MPC8313ERDB_NOR.h | 10 --------- include/configs/MPC8315ERDB.h | 6 +---- include/configs/MPC8323ERDB.h | 5 ----- include/configs/MPC832XEMDS.h | 5 ----- include/configs/MPC8349EMDS.h | 8 ------- include/configs/MPC8349EMDS_SDRAM.h | 8 ------- include/configs/MPC8349ITX.h | 13 ----------- include/configs/MPC837XEMDS.h | 4 ---- include/configs/MPC837XERDB.h | 4 ---- include/configs/caddy2.h | 8 ------- include/configs/hrcon.h | 5 ----- include/configs/ids8313.h | 9 -------- include/configs/kmopti2.h | 5 ----- include/configs/kmsupx5.h | 5 ----- include/configs/kmtegr1.h | 5 ----- include/configs/kmtepr2.h | 5 ----- include/configs/kmvect1.h | 5 ----- include/configs/mpc8308_p1m.h | 5 ----- include/configs/sbc8349.h | 8 ------- include/configs/strider.h | 5 ----- include/configs/suvd3.h | 5 ----- include/configs/tuge1.h | 5 ----- include/configs/tuxx1.h | 5 ----- include/configs/ve8313.h | 7 ------ include/configs/vme8349.h | 8 ------- 32 files changed, 43 insertions(+), 195 deletions(-)
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 090412d4b6c..c8e30a09478 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -109,8 +109,9 @@ int dram_init(void) msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */ - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF); + /* LB refresh timer prescal, 266MHz/32 */ + lbc->mrtpr = 0x20000000; sync();
#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index f14276f6a87..913b5843e95 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -183,28 +183,36 @@ void sdram_init(void) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile fsl_lbc_t *lbc = &immap->im_lbc; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - + const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 | + LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 | + LSDMR_WRC3 | LSDMR_CL3; /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */
/* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->lbcr = 0x00000000; + /* LB refresh timer prescal, 266MHz/32 */ + lbc->mrtpr = 0x20000000; + /* LB sdram refresh timer, about 6us */ + lbc->lsrt = 0x32000000; asm("sync");
/* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; + + /* 0x68636733; precharge all the banks */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; asm("sync"); *sdram_addr = 0xff; udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + /* 0x48636733; auto refresh */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; asm("sync"); /*1 times*/ *sdram_addr = 0xff; @@ -232,12 +240,13 @@ void sdram_init(void) udelay(100);
/* 0x58636733; mode register write operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; + lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; asm("sync"); *sdram_addr = 0xff; udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; asm("sync"); *sdram_addr = 0xff; udelay(100); diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index a66234aa857..caa36064f05 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -129,8 +129,8 @@ int dram_init(void)
msize = setup_sdram();
- out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); - out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); + out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF)); + out_be32(&lbc->mrtpr, 0x20000000); sync();
gd->ram_size = msize; diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index e51eeae065d..a647de6b112 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -147,6 +147,9 @@ void sdram_init(void) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile fsl_lbc_t *lbc = &immap->im_lbc; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; + const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 | + LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 | + LSDMR_WRC3 | LSDMR_CL3;
puts("\n SDRAM on Local Bus: "); print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); @@ -156,22 +159,27 @@ void sdram_init(void) */
/* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->lbcr = 0x00000000; + /* LB refresh timer prescal, 266MHz/32 */ + lbc->mrtpr = 0x20000000; + /* LB sdram refresh timer, about 6us */ + lbc->lsrt = 0x32000000; asm("sync");
/* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + /* 0x68636733; precharge all the banks */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; asm("sync"); *sdram_addr = 0xff; udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + /* 0x48636733; auto refresh */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; asm("sync"); /*1 times*/ *sdram_addr = 0xff; @@ -199,12 +207,13 @@ void sdram_init(void) udelay(100);
/* 0x58636733; mode register write operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; + lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; asm("sync"); *sdram_addr = 0xff; udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; asm("sync"); *sdram_addr = 0xff; udelay(100); diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index f4148a21e3b..1559ff210da 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -100,8 +100,8 @@ int dram_init(void) msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */ - out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); - out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); + out_be32(&lbc->lbcr, 0x00040000); + out_be32(&lbc->mrtpr, 0x20000000); sync();
/* return total bus SDRAM size(bytes) -- DDR */ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 5d31d4a0b6b..85d7ff6c521 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -121,11 +121,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - /* * FLASH on the Local Bus */ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 6f100fc7e7b..4153d609be4 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -186,16 +186,6 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-/* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ - | (0xFF << LBCR_BMT_SHIFT) \ - | 0xF) /* 0x0004ff0f */ - - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ - /* drivers/mtd/nand/raw/nand.c */ #if defined(CONFIG_SPL_BUILD) #define CONFIG_SYS_NAND_BASE 0xFFF00000 diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 0f246dc5186..ff8dedf03e4 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -159,16 +159,6 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-/* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ - | (0xFF << LBCR_BMT_SHIFT) \ - | 0xF) /* 0x0004ff0f */ - - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ - /* drivers/mtd/nand/nand.c */ #define CONFIG_SYS_NAND_BASE 0xE2800000
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 0b94b0c5cf9..521c5ca6eec 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -116,11 +116,7 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 -#define CONFIG_FSL_ELBC 1 +#define CONFIG_FSL_ELBC
/* * FLASH on the Local Bus diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index a90a9a86f8d..418c6729e19 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -113,11 +113,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - /* * FLASH on the Local Bus */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 88b6f873978..df9cc48417f 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -113,11 +113,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - /* * FLASH on the Local Bus */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index fdbd15ea93e..7640d7610d6 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -153,14 +153,6 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - /* * Serial Port */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 1e0e297351e..493f6df1874 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -150,14 +150,6 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - /* * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 388910ac38d..a3f704c73b2 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -250,19 +250,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32*/ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - /* * Serial Port */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 61f9eaf7150..724f8afb76d 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -134,10 +134,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_FSL_ELBC 1
/* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 07b206ff9f9..13a76829585 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -158,10 +158,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_FSL_ELBC 1
/* diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 928136f325f..15ac17985f3 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -96,14 +96,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
-/* - * Local Bus LCRR and LBCR regs - * LCRR: no DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
/* diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index d73e848b0c7..8029ae9dd75 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -110,11 +110,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - /* * FLASH on the Local Bus */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 155815a8815..b1d01c58f97 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -36,15 +36,6 @@ - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-/* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LBC_LBCR (0x00040000 |\ - (0xFF << LBCR_BMT_SHIFT) |\ - 0xF) - -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - /* * Internal Definitions */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 0759604810a..0094f34ef1b 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 319e3bc1ece..5afb969379b 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 85e9101b054..4f61ed0346d 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -341,11 +341,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - /* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 6ec944f9429..862fdb7e2d7 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index d7cbdde215d..802ab9c9344 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -333,11 +333,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 0392c3e8b40..3ce4b705b70 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -125,11 +125,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - /* * FLASH on the Local Bus */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index b4ae7b75543..d2053cc0597 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -123,14 +123,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
/* diff --git a/include/configs/strider.h b/include/configs/strider.h index e92bd1e8f10..22d255aabb8 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -110,11 +110,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - /* * FLASH on the Local Bus */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 8b3b45416da..9421204f2c3 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -286,11 +286,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 5dc9e8997e5..3364b5379ea 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 658080eeefc..4a3edf9be08 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 2116d6bbcf8..66f771d818f 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -128,13 +128,6 @@ #define CONFIG_SYS_MONITOR_LEN (384 * 1024) #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-/* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - /* * NAND settings */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 1bce6c732d9..1c3430d8491 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -96,14 +96,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
-/* - * Local Bus LCRR and LBCR regs - * LCRR: no DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
/*
The fsl-esdhc driver can be used for the SDHC functionality on MPC83xx, but it needs some additional definitions.
Add a clock.h file, so we can use the driver for MPC83xx.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/include/asm/arch-mpc83xx/clock.h | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 arch/powerpc/include/asm/arch-mpc83xx/clock.h
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/clock.h b/arch/powerpc/include/asm/arch-mpc83xx/clock.h new file mode 100644 index 00000000000..d57e93c2df9 --- /dev/null +++ b/arch/powerpc/include/asm/arch-mpc83xx/clock.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_POWERPC_CLOCK_H +#define __ASM_POWERPC_CLOCK_H + +/* Make fsl_esdhc driver happy */ +enum mxc_clock { + MXC_ESDHC_CLK, +}; + +DECLARE_GLOBAL_DATA_PTR; + +uint mxc_get_clock(int clk) +{ + return gd->arch.sdhc_clk; +} +#endif /* __ASM_POWERPC_CLOCK_H */
Don't use the legacy method of initializing the ethernet controller on MPC83xx when DM is active.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/cpu.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 8a88068fdba..4ea4249aff0 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -199,6 +199,7 @@ void watchdog_reset (void) } #endif
+#ifndef CONFIG_DM_ETH /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() @@ -214,6 +215,7 @@ int cpu_eth_init(bd_t *bis) #endif return 0; } +#endif /* !CONFIG_DM_ETH */
/* * Initializes on-chip MMC controllers.
ppcDWstore/ppcDWload are hardly used by any board, but since they're implemented in start.S, they're always present in every U-Boot image, even if they're not needed.
Re-implement these fuctions in C with inline assembly, so that the compiler can decide when to actually include them.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/cpu.c | 18 ++++++++++++++++++ arch/powerpc/cpu/mpc83xx/start.S | 12 ------------ 2 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 4ea4249aff0..9c67099a17a 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -229,3 +229,21 @@ int cpu_mmc_init(bd_t *bis) return 0; #endif } + +void ppcDWstore(unsigned int *addr, unsigned int *value) +{ + asm("lfd 1, 0(%1)\n\t" + "stfd 1, 0(%0)" + : + : "r" (addr), "r" (value) + : "memory"); +} + +void ppcDWload(unsigned int *addr, unsigned int *ret) +{ + asm("lfd 1, 0(%0)\n\t" + "stfd 1, 0(%1)" + : + : "r" (addr), "r" (ret) + : "memory"); +} diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 4df22f64fec..ee8c2e68dda 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -119,18 +119,6 @@ disable_addr_trans: mtspr SRR1, r3 rfi
- .globl ppcDWstore -ppcDWstore: - lfd 1, 0(r4) - stfd 1, 0(r3) - blr - - .globl ppcDWload -ppcDWload: - lfd 1, 0(r3) - stfd 1, 0(r4) - blr - #ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined #endif /* CONFIG_DEFAULT_IMMR */
For a lot of inline assembly calls in the mpc8xxx and mpc83xx directories, we already have convenient pre-defined helper functions, but they're not used, resulting in hard-to-read code.
Use these helper functions where ever possible and useful.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: No changes
v1 -> v2: New in v2
--- arch/powerpc/cpu/mpc83xx/cpu.c | 19 +++++++-------- arch/powerpc/cpu/mpc83xx/ecc.c | 36 ++++++++++++++-------------- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 36 +++++++++++++++++++++------- arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 12 +++++----- arch/powerpc/lib/cache.c | 6 ++--- 5 files changed, 63 insertions(+), 46 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 9c67099a17a..3048ecf34ad 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -133,18 +133,18 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) #ifdef MPC83xx_RESET
/* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~( MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + msr = mfmsr(); + msr &= ~(MSR_EE | MSR_IR | MSR_DR); + mtmsr(msr);
/* enable Reset Control Reg */ immap->reset.rpr = 0x52535445; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); + sync(); + isync();
/* confirm Reset Control Reg is enabled */ - while(!((immap->reset.rcer) & RCER_CRE)); + while(!((immap->reset.rcer) & RCER_CRE)) + ;
udelay(200);
@@ -156,10 +156,9 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
/* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - + msr = mfmsr(); msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + mtmsr(msr);
/* * Trying to execute the next instruction at a non-existing address diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index 73f0be2a30e..10e9b96add1 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -191,8 +191,8 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) }
ddr->err_disable = val; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); + sync(); + isync(); return 0; } else if (strcmp(argv[1], "errdetectclr") == 0) { val = ddr->err_detect; @@ -249,8 +249,8 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) printf("Incorrect command\n");
ddr->ecc_err_inject = val; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); + sync(); + isync(); return 0; } else if (strcmp(argv[1], "mirror") == 0) { val = ddr->ecc_err_inject; @@ -282,26 +282,26 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
/* enable injects */ ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); + sync(); + isync();
/* write memory location injecting errors */ ppcDWstore((u32 *) i, pattern); - __asm__ __volatile__("sync"); + sync();
/* disable injects */ ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); + sync(); + isync();
/* read data, this generates ECC error */ ppcDWload((u32 *) i, ret); - __asm__ __volatile__("sync"); + sync();
/* re-initialize memory, double word write the location again, * generates new ECC code this time */ ppcDWstore((u32 *) i, writeback); - __asm__ __volatile__("sync"); + sync(); } enable_interrupts(); return 0; @@ -321,29 +321,29 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
/* enable injects */ ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); + sync(); + isync();
/* write memory location injecting errors */ *(u32 *) i = 0xfedcba98UL; - __asm__ __volatile__("sync"); + sync();
/* sub double word write, * bus will read-modify-write, * generates ECC error */ *((u32 *) i + 1) = 0x76543210UL; - __asm__ __volatile__("sync"); + sync();
/* disable injects */ ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); + sync(); + isync();
/* re-initialize memory, * double word write the location again, * generates new ECC code this time */ ppcDWstore((u32 *) i, writeback); - __asm__ __volatile__("sync"); + sync(); } enable_interrupts(); return 0; diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 5ca307ca583..8b5ecdb9ad1 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -436,7 +436,7 @@ long int spd_sdram() else if (caslat == 4) ddr->debug_reg = 0x202c0000; /* CL=3.0 */
- __asm__ __volatile__ ("sync"); + sync();
debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); } @@ -765,7 +765,8 @@ long int spd_sdram() #endif debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
- asm("sync;isync"); + sync(); + isync();
udelay(600);
@@ -834,7 +835,8 @@ long int spd_sdram() #endif /* Enable controller, and GO! */ ddr->sdram_cfg = sdram_cfg; - asm("sync;isync"); + sync(); + isync(); udelay(500);
debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg); @@ -843,6 +845,22 @@ long int spd_sdram() #endif /* CONFIG_SPD_EEPROM */
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +static inline u32 mftbu(void) +{ + u32 rval; + + asm volatile("mftbu %0" : "=r" (rval)); + return rval; +} + +static inline u32 mftb(void) +{ + u32 rval; + + asm volatile("mftb %0" : "=r" (rval)); + return rval; +} + /* * Use timebase counter, get_timer() is not available * at this point of initialization yet. @@ -858,9 +876,9 @@ static __inline__ unsigned long get_tbms (void)
/* get the timebase ticks */ do { - asm volatile ("mftbu %0":"=r" (tbu1):); - asm volatile ("mftb %0":"=r" (tbl):); - asm volatile ("mftbu %0":"=r" (tbu2):); + tbu1 = mftbu(); + tbl = mftb(); + tbu2 = mftbu(); } while (tbu1 != tbu2);
/* convert ticks to ms */ @@ -897,7 +915,7 @@ void ddr_enable_ecc(unsigned int dram_size) for (p = 0; p < (u64*)(size); p++) { ppcDWstore((u32*)p, pattern); } - __asm__ __volatile__ ("sync"); + sync(); #endif
t_end = get_tbms(); @@ -922,8 +940,8 @@ void ddr_enable_ecc(unsigned int dram_size) /* Enable errors for ECC */ ddr->err_disable &= ECC_ERROR_ENABLE;
- __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); + sync(); + isync(); } #endif /* CONFIG_DDR_ECC */
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 23cc5a32acd..d81af70f440 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -131,10 +131,10 @@ static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr, set_bf(ppaace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL); }
- asm volatile("sync" : : : "memory"); + sync(); /* Mark the ppace entry valid */ ppaace->addr_bitfields |= PAACE_V_VALID; - asm volatile("sync" : : : "memory"); + sync();
return 0; } @@ -279,7 +279,7 @@ int pamu_init(void) out_be32(®s->splah, spaact_lim >> 32); out_be32(®s->splal, (uint32_t)spaact_lim); } - asm volatile("sync" : : : "memory"); + sync();
base_addr += PAMU_OFFSET; } @@ -294,7 +294,7 @@ void pamu_enable(void) for (i = 0; i < CONFIG_NUM_PAMU; i++) { setbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); - asm volatile("sync" : : : "memory"); + sync(); base_addr += PAMU_OFFSET; } } @@ -318,7 +318,7 @@ void pamu_reset(void) out_be32(®s->splal, 0);
clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE); - asm volatile("sync" : : : "memory"); + sync(); base_addr += PAMU_OFFSET; } } @@ -331,7 +331,7 @@ void pamu_disable(void)
for (i = 0; i < CONFIG_NUM_PAMU; i++) { clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); - asm volatile("sync" : : : "memory"); + sync(); base_addr += PAMU_OFFSET; } } diff --git a/arch/powerpc/lib/cache.c b/arch/powerpc/lib/cache.c index 2d36c3aa082..e99d42c9145 100644 --- a/arch/powerpc/lib/cache.c +++ b/arch/powerpc/lib/cache.c @@ -22,15 +22,15 @@ void flush_cache(ulong start_addr, ulong size) WATCHDOG_RESET(); } /* wait for all dcbst to complete on bus */ - asm volatile("sync" : : : "memory"); + sync();
for (addr = start; (addr <= end) && (addr >= start); addr += CONFIG_SYS_CACHELINE_SIZE) { asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); WATCHDOG_RESET(); } - asm volatile("sync" : : : "memory"); + sync(); /* flush prefetch queue */ - asm volatile("isync" : : : "memory"); + isync(); #endif }
CONFIG_SYS_APP1_BASE, CONFIG_SYS_APP2_BASE, CONFIG_SYS_APP1_SIZE, and CONFIG_SYS_APP2_SIZE are no longer used in the keymile config files (they were used for setting values, which were converted to Kconfig earlier in the series).
Remove them from the configs and the whitelist.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: New in v3
--- include/configs/kmopti2.h | 5 ----- include/configs/kmsupx5.h | 3 --- include/configs/kmtegr1.h | 5 ----- include/configs/kmtepr2.h | 5 ----- include/configs/kmvect1.h | 5 ----- include/configs/suvd3.h | 5 ----- include/configs/tuge1.h | 3 --- include/configs/tuxx1.h | 5 ----- scripts/config_whitelist.txt | 4 ---- 9 files changed, 40 deletions(-)
diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 0094f34ef1b..f1b7c2f02e3 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - /* * Init Local Bus Memory Controller: * Device on board diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 5afb969379b..0dd7420e8c9 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -289,9 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ - /* * Init Local Bus Memory Controller: * Device on board diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 4f61ed0346d..8f9bbefa7fa 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -344,11 +344,6 @@ /* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
-#define CONFIG_SYS_APP1_BASE 0xA0000000 -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 862fdb7e2d7..b77219f72cb 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - /* * Init Local Bus Memory Controller: * Device on board diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 802ab9c9344..785475ef458 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -333,11 +333,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_APP1_BASE 0xA0000000 -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 9421204f2c3..456cd9dd707 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -286,11 +286,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_APP1_BASE 0xA0000000 -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 3364b5379ea..01d8d6b3039 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -289,9 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ - /* * Init Local Bus Memory Controller: * Device on board diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 4a3edf9be08..c1d06f00676 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - /* * Init Local Bus Memory Controller: * Device on board diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 35198df9828..db6d722a997 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1976,10 +1976,6 @@ CONFIG_SYS_AMASK4 CONFIG_SYS_AMASK5 CONFIG_SYS_AMASK6 CONFIG_SYS_AMASK7 -CONFIG_SYS_APP1_BASE -CONFIG_SYS_APP1_SIZE -CONFIG_SYS_APP2_BASE -CONFIG_SYS_APP2_SIZE CONFIG_SYS_ARM_CACHE_WRITETHROUGH CONFIG_SYS_AT91_CPU_NAME CONFIG_SYS_AT91_MAIN_CLOCK
Not that the Kconfig conversion of a lot of variables is done, we can factor out the common include files for the keymile boards again (which now contain hardly any #ifdef logic at all).
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v2 -> v3: New in v3
--- include/configs/km/km-mpc8309.h | 137 +++++++++++++ include/configs/km/km-mpc832x.h | 91 +++++++++ include/configs/km/km-mpc8360.h | 91 +++++++++ include/configs/km/km-mpc83xx.h | 160 +++++++++++++++ include/configs/kmcoge5ne.h | 262 +------------------------ include/configs/kmeter1.h | 258 +------------------------ include/configs/kmopti2.h | 286 +-------------------------- include/configs/kmsupx5.h | 277 +------------------------- include/configs/kmtegr1.h | 331 +------------------------------ include/configs/kmtepr2.h | 278 +------------------------- include/configs/kmvect1.h | 332 +------------------------------- include/configs/suvd3.h | 278 +------------------------- include/configs/tuge1.h | 277 +------------------------- include/configs/tuxx1.h | 278 +------------------------- 14 files changed, 500 insertions(+), 2836 deletions(-) create mode 100644 include/configs/km/km-mpc8309.h create mode 100644 include/configs/km/km-mpc832x.h create mode 100644 include/configs/km/km-mpc8360.h create mode 100644 include/configs/km/km-mpc83xx.h
diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h new file mode 100644 index 00000000000..e89b7af0610 --- /dev/null +++ b/include/configs/km/km-mpc8309.h @@ -0,0 +1,137 @@ +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +/* between the u-boot partition and env */ +#ifndef CONFIG_SYS_QE_FW_ADDR +#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 +#endif + +/* + * System IO Config + */ +/* 0x14000180 SICR_1 */ +#define CONFIG_SYS_SICRL (0 \ + | SICR_1_UART1_UART1RTS \ + | SICR_1_I2C_CKSTOP \ + | SICR_1_IRQ_A_IRQ \ + | SICR_1_IRQ_B_IRQ \ + | SICR_1_GPIO_A_GPIO \ + | SICR_1_GPIO_B_GPIO \ + | SICR_1_GPIO_C_GPIO \ + | SICR_1_GPIO_D_GPIO \ + | SICR_1_GPIO_E_GPIO \ + | SICR_1_GPIO_F_GPIO \ + | SICR_1_USB_A_UART2S \ + | SICR_1_USB_B_UART2RTS \ + | SICR_1_FEC1_FEC1 \ + | SICR_1_FEC2_FEC2 \ + ) + +/* 0x00080400 SICR_2 */ +#define CONFIG_SYS_SICRH (0 \ + | SICR_2_FEC3_FEC3 \ + | SICR_2_HDLC1_A_HDLC1 \ + | SICR_2_ELBC_A_LA \ + | SICR_2_ELBC_B_LCLK \ + | SICR_2_HDLC2_A_HDLC2 \ + | SICR_2_USB_D_GPIO \ + | SICR_2_PCI_PCI \ + | SICR_2_HDLC1_B_HDLC1 \ + | SICR_2_HDLC1_C_HDLC1 \ + | SICR_2_HDLC2_B_GPIO \ + | SICR_2_HDLC2_C_HDLC2 \ + | SICR_2_QUIESCE_B \ + ) + +/* GPR_1 */ +#define CONFIG_SYS_GPR1 0x50008060 + +#define CONFIG_SYS_GP1DIR 0x00000000 +#define CONFIG_SYS_GP1ODR 0x00000000 +#define CONFIG_SYS_GP2DIR 0xFF000000 +#define CONFIG_SYS_GP2ODR 0x00000000 + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_RD_NEVER | \ + CSCONFIG_ODT_WR_ONLY_CURRENT | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* ethernet port connected to piggy (UEC2) */ +#define CONFIG_HAS_ETH1 +#define CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h new file mode 100644 index 00000000000..3c2173d3642 --- /dev/null +++ b/include/configs/km/km-mpc832x.h @@ -0,0 +1,91 @@ +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRL SICRL_IRQ_CKS + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_WR_CFG | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h new file mode 100644 index 00000000000..8f26e059e98 --- /dev/null +++ b/include/configs/km/km-mpc8360.h @@ -0,0 +1,91 @@ +/* KMBEC FPGA (PRIO) */ +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 + +/* + * High Level Configuration Options + */ +#define CONFIG_QE /* Has QE */ + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 + +/* + * System IO Setup + */ +#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) + +/** + * DDR RAM settings + */ +#define CONFIG_SYS_DDR_SDRAM_CFG (\ + SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 + +#define CONFIG_SYS_DDR_CLK_CNTL (\ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CONFIG_SYS_DDR_INTERVAL (\ + (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f + +#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_Q_DRN) +#define CONFIG_SYS_DDR_MODE 0x47860452 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 (\ + (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 (\ + (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * PAXE on the local bus CS3 + */ +#define CONFIG_SYS_PAXE_BASE 0xA0000000 +#define CONFIG_SYS_PAXE_SIZE 256 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h new file mode 100644 index 00000000000..455e5236deb --- /dev/null +++ b/include/configs/km/km-mpc83xx.h @@ -0,0 +1,160 @@ +/* + * Internal Definitions + */ +#define BOOTFLASH_START 0xF0000000 + +#define CONFIG_KM_CONSOLE_TTY "ttyS0" + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ + +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +/* Reserve 768 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 128MB GPIO/PIGGY + * + */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 200000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 200000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ + {1, {I2C_NULL_HOP} } } + +#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_KMETER1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#ifndef CONFIG_ENV_OFFSET +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) +#endif + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_SYS_RAMBOOT */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_SYS_RAMBOOT */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV "km-common=empty\0" +#endif + +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + CONFIG_KM_DEF_ARCH \ + "newenv=" \ + "prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \ + "era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0" \ + "unlock=yes\0" \ + "" + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "UEC0" diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 720d28d61a0..a041a3ece52 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -8,10 +8,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-/* KMBEC FPGA (PRIO) */ -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 - #define CONFIG_HOSTNAME "kmcoge5ne" #define CONFIG_KM_BOARD_NAME "kmcoge5ne" #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0" @@ -24,14 +20,11 @@ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
-/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" +#include "km/km-mpc83xx.h" +#include "km/km-mpc8360.h"
/* * System Clock Setup @@ -40,201 +33,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000
-/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Setup - */ -#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) - -/** - * DDR RAM settings - */ -#define CONFIG_SYS_DDR_SDRAM_CFG (\ - SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 - /** * KMCOGE5NE has 512 MB RAM */ @@ -246,68 +44,12 @@ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10)
-#define CONFIG_SYS_DDR_CLK_CNTL (\ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CONFIG_SYS_DDR_INTERVAL (\ - (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_Q_DRN) -#define CONFIG_SYS_DDR_MODE 0x47860452 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 (\ - (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 (\ - (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * PAXE on the local bus CS3 - */ -#define CONFIG_SYS_PAXE_BASE 0xA0000000 -#define CONFIG_SYS_PAXE_SIZE 256 - - /* * BFTIC3 on the local bus CS4 */ #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 #define CONFIG_SYS_BFTIC3_SIZE 256
- /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 290108d4fc4..bfa7ca27c74 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -8,277 +8,23 @@ #ifndef __CONFIG_H #define __CONFIG_H
-/* KMBEC FPGA (PRIO) */ -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 - #define CONFIG_HOSTNAME "kmeter1" #define CONFIG_KM_BOARD_NAME "kmeter1" #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
-/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - +#include "km/km-mpc83xx.h" +#include "km/km-mpc8360.h"
/* * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Setup - */ -#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) - -/** - * DDR RAM settings - */ -#define CONFIG_SYS_DDR_SDRAM_CFG (\ - SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10 | \ CSCONFIG_ODT_WR_ONLY_CURRENT) - -#define CONFIG_SYS_DDR_CLK_CNTL (\ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CONFIG_SYS_DDR_INTERVAL (\ - (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_Q_DRN) -#define CONFIG_SYS_DDR_MODE 0x47860452 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 (\ - (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 (\ - (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * PAXE on the local bus CS3 - */ -#define CONFIG_SYS_PAXE_BASE 0xA0000000 -#define CONFIG_SYS_PAXE_SIZE 256 - - #endif /* CONFIG */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index f1b7c2f02e3..67e864fc987 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -26,292 +26,10 @@ #define CONFIG_KM_BOARD_NAME "kmopti2" #define CONFIG_HOSTNAME "kmopti2"
-/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * Device on board - * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE - * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) - * - * Device on board (continued) - * Bank Bus Machine PortSz Size KMTEPR2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB NVRAM - * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) - */ - -/* - * Configuration for C2 on the local bus - */ - - -/* - * Configuration for C3 on the local bus - */ - +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h"
#endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 0dd7420e8c9..ba33e6074bf 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -26,283 +26,10 @@ #define CONFIG_KM_BOARD_NAME "kmsupx5" #define CONFIG_HOSTNAME "kmsupx5"
-/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * Device on board - * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE - * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) - * - * Device on board (continued) - * Bank Bus Machine PortSz Size KMTEPR2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB NVRAM - * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) - */ - +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h"
#endif /* __CONFIG_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 8f9bbefa7fa..701eb53f631 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -33,340 +33,13 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1
-/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -/* between the u-boot partition and env */ -#ifndef CONFIG_SYS_QE_FW_ADDR -#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 -#endif - -/* - * System IO Config - */ -/* 0x14000180 SICR_1 */ -#define CONFIG_SYS_SICRL (0 \ - | SICR_1_UART1_UART1RTS \ - | SICR_1_I2C_CKSTOP \ - | SICR_1_IRQ_A_IRQ \ - | SICR_1_IRQ_B_IRQ \ - | SICR_1_GPIO_A_GPIO \ - | SICR_1_GPIO_B_GPIO \ - | SICR_1_GPIO_C_GPIO \ - | SICR_1_GPIO_D_GPIO \ - | SICR_1_GPIO_E_GPIO \ - | SICR_1_GPIO_F_GPIO \ - | SICR_1_USB_A_UART2S \ - | SICR_1_USB_B_UART2RTS \ - | SICR_1_FEC1_FEC1 \ - | SICR_1_FEC2_FEC2 \ - ) - -/* 0x00080400 SICR_2 */ -#define CONFIG_SYS_SICRH (0 \ - | SICR_2_FEC3_FEC3 \ - | SICR_2_HDLC1_A_HDLC1 \ - | SICR_2_ELBC_A_LA \ - | SICR_2_ELBC_B_LCLK \ - | SICR_2_HDLC2_A_HDLC2 \ - | SICR_2_USB_D_GPIO \ - | SICR_2_PCI_PCI \ - | SICR_2_HDLC1_B_HDLC1 \ - | SICR_2_HDLC1_C_HDLC1 \ - | SICR_2_HDLC2_B_GPIO \ - | SICR_2_HDLC2_C_HDLC2 \ - | SICR_2_QUIESCE_B \ - ) - -/* GPR_1 */ -#define CONFIG_SYS_GPR1 0x50008060 - -#define CONFIG_SYS_GP1DIR 0x00000000 -#define CONFIG_SYS_GP1ODR 0x00000000 -#define CONFIG_SYS_GP2DIR 0xFF000000 -#define CONFIG_SYS_GP2ODR 0x00000000 - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_RD_NEVER | \ - CSCONFIG_ODT_WR_ONLY_CURRENT | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#include "km/km-mpc83xx.h" +#include "km/km-mpc8309.h"
/* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
-/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 2 Local UPMA 16 bit 256MB APP1 - * 3 Local GPCM 16 bit 256MB APP2 - * - */ - - -/* ethernet port connected to piggy (UEC2) */ -#define CONFIG_HAS_ETH1 -#define CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 - #endif /* __CONFIG_H */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index b77219f72cb..e0c907d11a4 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -26,284 +26,10 @@ #define CONFIG_KM_BOARD_NAME "kmtepr2" #define CONFIG_HOSTNAME "kmtepr2"
-/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * Device on board - * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE - * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) - * - * Device on board (continued) - * Bank Bus Machine PortSz Size KMTEPR2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB NVRAM - * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) - */ - - +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h"
#endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 785475ef458..6e5d50700c0 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -25,328 +25,11 @@ /* at end of uboot partition, before env */ #define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
-/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -/* between the u-boot partition and env */ -#ifndef CONFIG_SYS_QE_FW_ADDR -#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 -#endif - -/* - * System IO Config - */ -/* 0x14000180 SICR_1 */ -#define CONFIG_SYS_SICRL (0 \ - | SICR_1_UART1_UART1RTS \ - | SICR_1_I2C_CKSTOP \ - | SICR_1_IRQ_A_IRQ \ - | SICR_1_IRQ_B_IRQ \ - | SICR_1_GPIO_A_GPIO \ - | SICR_1_GPIO_B_GPIO \ - | SICR_1_GPIO_C_GPIO \ - | SICR_1_GPIO_D_GPIO \ - | SICR_1_GPIO_E_GPIO \ - | SICR_1_GPIO_F_GPIO \ - | SICR_1_USB_A_UART2S \ - | SICR_1_USB_B_UART2RTS \ - | SICR_1_FEC1_FEC1 \ - | SICR_1_FEC2_FEC2 \ - ) - -/* 0x00080400 SICR_2 */ -#define CONFIG_SYS_SICRH (0 \ - | SICR_2_FEC3_FEC3 \ - | SICR_2_HDLC1_A_HDLC1 \ - | SICR_2_ELBC_A_LA \ - | SICR_2_ELBC_B_LCLK \ - | SICR_2_HDLC2_A_HDLC2 \ - | SICR_2_USB_D_GPIO \ - | SICR_2_PCI_PCI \ - | SICR_2_HDLC1_B_HDLC1 \ - | SICR_2_HDLC1_C_HDLC1 \ - | SICR_2_HDLC2_B_GPIO \ - | SICR_2_HDLC2_C_HDLC2 \ - | SICR_2_QUIESCE_B \ - ) - -/* GPR_1 */ -#define CONFIG_SYS_GPR1 0x50008060 - -#define CONFIG_SYS_GP1DIR 0x00000000 -#define CONFIG_SYS_GP1ODR 0x00000000 -#define CONFIG_SYS_GP2DIR 0xFF000000 -#define CONFIG_SYS_GP2ODR 0x00000000 - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_RD_NEVER | \ - CSCONFIG_ODT_WR_ONLY_CURRENT | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 2 Local UPMA 16 bit 256MB APP1 - * 3 Local GPCM 16 bit 256MB APP2 - * - */ - - +#include "km/km-mpc83xx.h" +#include "km/km-mpc8309.h"
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ @@ -375,15 +58,4 @@ #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-/* ethernet port connected to piggy (UEC2) */ -#define CONFIG_HAS_ETH1 -#define CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 - #endif /* __CONFIG_H */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 456cd9dd707..1705f9cafba 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -21,285 +21,13 @@ */
#define CONFIG_HOSTNAME "suvd3" -#define CONFIG_KM_BOARD_NAME "suvd3" - -/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" +#define CONFIG_KM_BOARD_NAME "suvd3"
/* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 2 Local UPMA 16 bit 256MB APP1 - * 3 Local GPCM 16 bit 256MB APP2 - * - */ - - +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h"
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 01d8d6b3039..808538ef9d6 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -26,283 +26,10 @@ #define CONFIG_KM_BOARD_NAME "tuge1" #define CONFIG_HOSTNAME "tuge1"
-/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * Device on board - * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE - * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) - * - * Device on board (continued) - * Bank Bus Machine PortSz Size KMTEPR2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB NVRAM - * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) - */ - +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h"
#endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index c1d06f00676..295e92d4a18 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -26,285 +26,11 @@ #define CONFIG_KM_BOARD_NAME "tuxx1" #define CONFIG_HOSTNAME "tuxx1"
-/* - * High Level Configuration Options - */ -#define CONFIG_QE /* Has QE */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" - /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * PRIO1/PIGGY on the local bus CS1 - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ - "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * Init Local Bus Memory Controller: - * Device on board - * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE - * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) - * - * Device on board (continued) - * Bank Bus Machine PortSz Size KMTEPR2 - * ----------------------------------------------------------------------------- - * 2 Local GPCM 8 bit 256MB NVRAM - * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) - */ - - +#include "km/km-mpc83xx.h" +#include "km/km-mpc832x.h"
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \
On 1/21/19 12:19 AM, Mario Six wrote:
Replace CONFIG_MPC830* with proper CONFIG_ARCH_MPC830* Kconfig options.
Signed-off-by: Mario Six mario.six@gdsys.cc
I browse through the entire patch set. The patches look good. Since NXP doesn't make new mpc83xx SoCs and I have no board to verify, I don't comment on specific changes.
There were many config macros which have been replace with hard-coded value inline by you. That's OK. The original plan was to allow different config but that didn't happen mostly.
York
Hi York, On Tue, Jan 22, 2019 at 5:17 PM York Sun york.sun@nxp.com wrote:
On 1/21/19 12:19 AM, Mario Six wrote:
Replace CONFIG_MPC830* with proper CONFIG_ARCH_MPC830* Kconfig options.
Signed-off-by: Mario Six mario.six@gdsys.cc
I browse through the entire patch set. The patches look good. Since NXP doesn't make new mpc83xx SoCs and I have no board to verify, I don't comment on specific changes.
There were many config macros which have been replace with hard-coded value inline by you. That's OK. The original plan was to allow different config but that didn't happen mostly.
Sounds good. Thanks for reviewing!
York
Best regards, Mario
On Mon, Jan 28, 2019 at 9:13 AM Mario Six mario.six@gdsys.cc wrote:
Hi York, On Tue, Jan 22, 2019 at 5:17 PM York Sun york.sun@nxp.com wrote:
On 1/21/19 12:19 AM, Mario Six wrote:
Replace CONFIG_MPC830* with proper CONFIG_ARCH_MPC830* Kconfig options.
Signed-off-by: Mario Six mario.six@gdsys.cc
I browse through the entire patch set. The patches look good. Since NXP doesn't make new mpc83xx SoCs and I have no board to verify, I don't comment on specific changes.
There were many config macros which have been replace with hard-coded value inline by you. That's OK. The original plan was to allow different config but that didn't happen mostly.
Sounds good. Thanks for reviewing!
York
Best regards, Mario
Whole series applied to u-boot/mpc83xx/next.
Best regards, Mario
participants (2)
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Mario Six -
York Sun