Schema file in YAML must be provided in board/ti/common for validating input config files and packaging system firmware. The schema includes entries for rm-cfg, board-cfg, pm-cfg and sec-cfg.

Board config file must be provided in board/ti/<devicename> in YAML. These can then be consumed for generation of binaries to package system firmware. Added YAML config for J721E EVM in particular.

It is to be noted that the bootflow followed by J721E requires tiboot3.bin, TIFS and board config binaries to be packaged into sysfw.itb along with u-boot.img. It also requires DM, ATF, OPTEE packaged into tispl.bin.

Signed-off-by: Tarun Sahu t-sahu@ti.com [n-francis@ti.com: prepared patch for upstreaming] Signed-off-by: Neha Malcom Francis n-francis@ti.com --- board/ti/common/schema.yaml | 355 ++++ board/ti/j721e/config.yaml | 3162 +++++++++++++++++++++++++++++++++++ 2 files changed, 3517 insertions(+) create mode 100644 board/ti/common/schema.yaml create mode 100644 board/ti/j721e/config.yaml

diff --git a/board/ti/common/schema.yaml b/board/ti/common/schema.yaml new file mode 100644 index 0000000000..070ff797e0 --- /dev/null +++ b/board/ti/common/schema.yaml @@ -0,0 +1,355 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +# +# Config schema for TI K3 devices +# + +--- + +definitions: + u8: + type: integer + minimum: 0 + maximum: 0xff + u16: + type: integer + minimum: 0 + maximum: 0xffff + u32: + type: integer + minimum: 0 + maximum: 0xffffffff + + + +type: object +properties: + pm-cfg: + type: object + properties: + rev: + type: object + properties: + boardcfg_abi_maj: + $ref: "#/definitions/u8" + boardcfg_abi_min: + $ref: "#/definitions/u8" + board-cfg: + type: object + properties: + rev: + type: object + properties: + boardcfg_abi_maj: + $ref: "#/definitions/u8" + boardcfg_abi_min: + $ref: "#/definitions/u8" + control: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + main_isolation_enable: + $ref: "#/definitions/u8" + main_isolation_hostid: + $ref: "#/definitions/u16" + + + secproxy: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + scaling_factor: + $ref: "#/definitions/u8" + scaling_profile: + $ref: "#/definitions/u8" + disable_main_nav_secure_proxy: + $ref: "#/definitions/u8" + + msmc: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + msmc_cache_size: + $ref: "#/definitions/u8" + debug_cfg: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + trace_dst_enables: + $ref: "#/definitions/u16" + trace_src_enables: + $ref: "#/definitions/u16" + + sec-cfg: + type: object + properties: + rev: + type: object + properties: + boardcfg_abi_maj: + $ref: "#/definitions/u8" + boardcfg_abi_min: + $ref: "#/definitions/u8" + + processor_acl_list: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + proc_acl_entries: + type: array + minItems: 32 + maxItems: 32 + items: + type: object + properties: + processor_id: + $ref: "#/definitions/u8" + proc_access_master: + $ref: "#/definitions/u8" + proc_access_secondary: + type: array + minItems: 3 + maxItems: 3 + items: + $ref: "#/definitions/u8" + host_hierarchy: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + host_hierarchy_entries: + type: array + minItems: 32 + maxItems: 32 + items: + type: object + properties: + host_id: + $ref: "#/definitions/u8" + supervisor_host_id: + $ref: "#/definitions/u8" + + otp_config: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + otp_entry: + type: array + minItems: 32 + maxItems: 32 + items: + type: object + properties: + host_id: + $ref: "#/definitions/u8" + host_perms: + $ref: "#/definitions/u8" + write_host_id: + $ref: "#/definitions/u8" + + dkek_config: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + allowed_hosts: + type: array + minItems: 4 + maxItems: 4 + items: + $ref: "#/definitions/u8" + allow_dkek_export_tisci: + $ref: "#/definitions/u8" + rsvd: + type: array + minItems: 3 + maxItems: 3 + items: + $ref: "#/definitions/u8" + + sa2ul_cfg: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + rsvd: + type: array + minItems: 4 + maxItems: 4 + items: + $ref: "#/definitions/u8" + sec_dbg_config: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + allow_jtag_unlock: + $ref: "#/definitions/u8" + allow_wildcard_unlock: + $ref: "#/definitions/u8" + allowed_debug_level_rsvd: + $ref: "#/definitions/u8" + rsvd: + $ref: "#/definitions/u8" + min_cert_rev: + $ref: "#/definitions/u32" + jtag_unlock_hosts: + type: array + minItems: 4 + maxItems: 4 + items: + $ref: "#/definitions/u8" + + + sec_handover_cfg: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + handover_msg_sender: + $ref: "#/definitions/u8" + handover_to_host_id: + $ref: "#/definitions/u8" + rsvd: + type: array + minItems: 4 + maxItems: 4 + items: + $ref: "#/definitions/u8" + + rm-cfg: + type: object + properties: + rm_boardcfg: + type: object + properties: + rev: + type: object + properties: + boardcfg_abi_maj: + $ref: "#/definitions/u8" + boardcfg_abi_min: + $ref: "#/definitions/u8" + + host_cfg: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + host_cfg_entries: + type: array + minItems: 0 + maxItems: 32 + items: + type: object + properties: + host_id: + $ref: "#/definitions/u8" + allowed_atype: + $ref: "#/definitions/u8" + allowed_qos: + $ref: "#/definitions/u16" + allowed_orderid: + $ref: "#/definitions/u32" + allowed_priority: + $ref: "#/definitions/u16" + allowed_sched_priority: + $ref: "#/definitions/u8" + resasg: + type: object + properties: + subhdr: + type: object + properties: + magic: + $ref: "#/definitions/u16" + size: + $ref: "#/definitions/u16" + resasg_entries_size: + $ref: "#/definitions/u16" + reserved: + $ref: "#/definitions/u16" + + resasg_entries: + type: array + minItems: 0 + maxItems: 418 + items: + type: object + properties: + start_resource: + $ref: "#/definitions/u16" + num_resource: + $ref: "#/definitions/u16" + type: + $ref: "#/definitions/u16" + host_id: + $ref: "#/definitions/u8" + reserved: + $ref: "#/definitions/u8" diff --git a/board/ti/j721e/config.yaml b/board/ti/j721e/config.yaml new file mode 100644 index 0000000000..710517404f --- /dev/null +++ b/board/ti/j721e/config.yaml @@ -0,0 +1,3162 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for J721E EVM +# + +--- + +pm-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + +board-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable: 0x5A + main_isolation_hostid: 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor: 0x1 + scaling_profile: 0x1 + disable_main_nav_secure_proxy: 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size: 0x0 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables: 0x00 + trace_src_enables: 0x00 + +sec-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - #1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - #32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - #1 + host_id: 0 + supervisor_host_id: 0 + - #2 + host_id: 0 + supervisor_host_id: 0 + - #3 + host_id: 0 + supervisor_host_id: 0 + - #4 + host_id: 0 + supervisor_host_id: 0 + - #5 + host_id: 0 + supervisor_host_id: 0 + - #6 + host_id: 0 + supervisor_host_id: 0 + - #7 + host_id: 0 + supervisor_host_id: 0 + - #8 + host_id: 0 + supervisor_host_id: 0 + - #9 + host_id: 0 + supervisor_host_id: 0 + - #10 + host_id: 0 + supervisor_host_id: 0 + - #11 + host_id: 0 + supervisor_host_id: 0 + - #12 + host_id: 0 + supervisor_host_id: 0 + - #13 + host_id: 0 + supervisor_host_id: 0 + - #14 + host_id: 0 + supervisor_host_id: 0 + - #15 + host_id: 0 + supervisor_host_id: 0 + - #16 + host_id: 0 + supervisor_host_id: 0 + - #17 + host_id: 0 + supervisor_host_id: 0 + - #18 + host_id: 0 + supervisor_host_id: 0 + - #19 + host_id: 0 + supervisor_host_id: 0 + - #20 + host_id: 0 + supervisor_host_id: 0 + - #21 + host_id: 0 + supervisor_host_id: 0 + - #22 + host_id: 0 + supervisor_host_id: 0 + - #23 + host_id: 0 + supervisor_host_id: 0 + - #24 + host_id: 0 + supervisor_host_id: 0 + - #25 + host_id: 0 + supervisor_host_id: 0 + - #26 + host_id: 0 + supervisor_host_id: 0 + - #27 + host_id: 0 + supervisor_host_id: 0 + - #28 + host_id: 0 + supervisor_host_id: 0 + - #29 + host_id: 0 + supervisor_host_id: 0 + - #30 + host_id: 0 + supervisor_host_id: 0 + - #31 + host_id: 0 + supervisor_host_id: 0 + - #32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + otp_entry: + - #1 + host_id: 0 + host_perms: 0 + - #2 + host_id: 0 + host_perms: 0 + - #3 + host_id: 0 + host_perms: 0 + - #4 + host_id: 0 + host_perms: 0 + - #5 + host_id: 0 + host_perms: 0 + - #6 + host_id: 0 + host_perms: 0 + - #7 + host_id: 0 + host_perms: 0 + - #8 + host_id: 0 + host_perms: 0 + - #9 + host_id: 0 + host_perms: 0 + - #10 + host_id: 0 + host_perms: 0 + - #11 + host_id: 0 + host_perms: 0 + - #12 + host_id: 0 + host_perms: 0 + - #13 + host_id: 0 + host_perms: 0 + - #14 + host_id: 0 + host_perms: 0 + - #15 + host_id: 0 + host_perms: 0 + - #16 + host_id: 0 + host_perms: 0 + - #17 + host_id: 0 + host_perms: 0 + - #18 + host_id: 0 + host_perms: 0 + - #19 + host_id: 0 + host_perms: 0 + - #20 + host_id: 0 + host_perms: 0 + - #21 + host_id: 0 + host_perms: 0 + - #22 + host_id: 0 + host_perms: 0 + - #23 + host_id: 0 + host_perms: 0 + - #24 + host_id: 0 + host_perms: 0 + - #25 + host_id: 0 + host_perms: 0 + - #26 + host_id: 0 + host_perms: 0 + - #27 + host_id: 0 + host_perms: 0 + - #28 + host_id: 0 + host_perms: 0 + - #29 + host_id: 0 + host_perms: 0 + - #30 + host_id: 0 + host_perms: 0 + - #31 + host_id: 0 + host_perms: 0 + - #32 + host_id: 0 + host_perms: 0 + write_host_id: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci: 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size: 0 + rsvd: [0, 0, 0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock: 0x5A + allow_wildcard_unlock: 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev: 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender: 0 + handover_to_host_id: 0 + rsvd: [0, 0, 0, 0] + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - #1 + host_id: 3 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #2 + host_id: 5 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #3 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #4 + host_id: 13 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #5 + host_id: 21 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #6 + host_id: 26 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #7 + host_id: 28 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #8 + host_id: 35 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #9 + host_id: 37 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #10 + host_id: 40 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #11 + host_id: 42 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 3344 + reserved: 0 + resasg_entries: + - + start_resource: 4 + num_resource: 93 + type: 7744 + host_id: 26 + reserved: 0 + - + start_resource: 4 + num_resource: 93 + type: 7808 + host_id: 28 + reserved: 0 + - + start_resource: 0 + num_resource: 32 + type: 7872 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 32 + type: 8192 + host_id: 3 + reserved: 0 + - + start_resource: 32 + num_resource: 32 + type: 8192 + host_id: 5 + reserved: 0 + - + start_resource: 0 + num_resource: 24 + type: 8320 + host_id: 3 + reserved: 0 + - + start_resource: 24 + num_resource: 24 + type: 8320 + host_id: 5 + reserved: 0 + - + start_resource: 0 + num_resource: 8 + type: 8384 + host_id: 3 + reserved: 0 + - + start_resource: 8 + num_resource: 8 + type: 8384 + host_id: 5 + reserved: 0 + - + start_resource: 16 + num_resource: 4 + type: 8384 + host_id: 40 + reserved: 0 + - + start_resource: 20 + num_resource: 4 + type: 8384 + host_id: 42 + reserved: 0 + - + start_resource: 24 + num_resource: 4 + type: 8384 + host_id: 35 + reserved: 0 + - + start_resource: 28 + num_resource: 4 + type: 8384 + host_id: 37 + reserved: 0 + - + start_resource: 32 + num_resource: 4 + type: 8384 + host_id: 26 + reserved: 0 + - + start_resource: 36 + num_resource: 4 + type: 8384 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host_id: 5 + reserved: 0 + - + start_resource: 35 + num_resource: 1 + type: 15043 + host_id: 40 + reserved: 0 + - + start_resource: 36 + num_resource: 1 + type: 15043 + host_id: 42 + reserved: 0 + - + start_resource: 37 + num_resource: 1 + type: 15043 + host_id: 21 + reserved: 0 + - + start_resource: 38 + num_resource: 1 + type: 15043 + host_id: 26 + reserved: 0 + - + start_resource: 39 + num_resource: 1 + type: 15043 + host_id: 28 + reserved: 0 + - + start_resource: 40 + num_resource: 2 + type: 15043 + host_id: 35 + reserved: 0 + - + start_resource: 42 + num_resource: 1 + type: 15043 + host_id: 37 + reserved: 0 + - + start_resource: 43 + num_resource: 3 + type: 15043 + host_id: 128 + reserved: 0 + - + start_resource: 48 + num_resource: 0 + type: 15045 + host_id: 3 + reserved: 0 + - + start_resource: 48 + num_resource: 2 + type: 15045 + host_id: 3 + reserved: 0 + - + start_resource: 0 + num_resource: 0 + type: 15047 + host_id: 3 + reserved: 0 + - + start_resource: 0 + num_resource: 2 + type: 15047 + host_id: 3 + reserved: 0 + - + start_resource: 2 + num_resource: 5 + type: 15050 + host_id: 12 + reserved: 0 + - + start_resource: 7 + num_resource: 1 + type: 15050 + host_id: 13 + reserved: 0 + - + start_resource: 0 + num_resource: 3 + type: 15051 + host_id: 12 + reserved: 0 + - + start_resource: 3 + num_resource: 2 + type: 15051 + host_id: 13 + reserved: 0 + - + start_resource: 5 + num_resource: 3 + type: 15051 + host_id: 3 + reserved: 0 + - + start_resource: 8 + num_resource: 3 + type: 15051 + host_id: 5 + reserved: 0 + - + start_resource: 11 + num_resource: 3 + type: 15051 + host_id: 40 + reserved: 0 + - + start_resource: 14 + num_resource: 3 + type: 15051 + host_id: 42 + reserved: 0 + - + start_resource: 17 + num_resource: 3 + type: 15051 + host_id: 21 + reserved: 0 + - + start_resource: 20 + num_resource: 3 + type: 15051 + host_id: 26 + reserved: 0 + - + start_resource: 23 + num_resource: 3 + type: 15051 + host_id: 28 + reserved: 0 + - + start_resource: 26 + num_resource: 3 + type: 15051 + host_id: 35 + reserved: 0 + - + start_resource: 29 + num_resource: 3 + type: 15051 + host_id: 37 + reserved: 0 + - + start_resource: 48 + num_resource: 8 + type: 15104 + host_id: 12 + reserved: 0 + - + start_resource: 56 + num_resource: 4 + type: 15104 + host_id: 13 + reserved: 0 + - + start_resource: 60 + num_resource: 8 + type: 15104 + host_id: 3 + reserved: 0 + - + start_resource: 68 + num_resource: 4 + type: 15104 + host_id: 5 + reserved: 0 + - + start_resource: 72 + num_resource: 4 + type: 15104 + host_id: 40 + reserved: 0 + - + start_resource: 76 + num_resource: 4 + type: 15104 + host_id: 42 + reserved: 0 + - + start_resource: 80 + num_resource: 8 + type: 15104 + host_id: 35 + reserved: 0 + - + start_resource: 88 + num_resource: 4 + type: 15104 + host_id: 37 + reserved: 0 + - + start_resource: 92 + num_resource: 4 + type: 15104 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 1 + type: 15105 + host_id: 128 + reserved: 0 + - + start_resource: 56320 + num_resource: 256 + type: 15106 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 1 + type: 15107 + host_id: 128 + reserved: 0 + - + start_resource: 2 + num_resource: 4 + type: 15114 + host_id: 12 + reserved: 0 + - + start_resource: 6 + num_resource: 2 + type: 15114 + host_id: 3 + reserved: 0 + - + start_resource: 6 + num_resource: 0 + type: 15114 + host_id: 13 + reserved: 0 + - + start_resource: 8 + num_resource: 0 + type: 15114 + host_id: 5 + reserved: 0 + - + start_resource: 8 + num_resource: 1 + type: 15114 + host_id: 40 + reserved: 0 + - + start_resource: 9 + num_resource: 1 + type: 15114 + host_id: 42 + reserved: 0 + - + start_resource: 10 + num_resource: 1 + type: 15114 + host_id: 21 + reserved: 0 + - + start_resource: 11 + num_resource: 1 + type: 15114 + host_id: 26 + reserved: 0 + - + start_resource: 12 + num_resource: 1 + type: 15114 + host_id: 28 + reserved: 0 + - + start_resource: 13 + num_resource: 1 + type: 15114 + host_id: 35 + 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+ type: 15117 + host_id: 28 + reserved: 0 + - + start_resource: 13 + num_resource: 1 + type: 15117 + host_id: 35 + reserved: 0 + - + start_resource: 14 + num_resource: 1 + type: 15117 + host_id: 37 + reserved: 0 + - + start_resource: 15 + num_resource: 9 + type: 15117 + host_id: 12 + reserved: 0 + - + start_resource: 24 + num_resource: 6 + type: 15117 + host_id: 13 + reserved: 0 + - + start_resource: 30 + num_resource: 3 + type: 15117 + host_id: 3 + reserved: 0 + - + start_resource: 33 + num_resource: 2 + type: 15117 + host_id: 5 + reserved: 0 + - + start_resource: 35 + num_resource: 1 + type: 15117 + host_id: 40 + reserved: 0 + - + start_resource: 36 + num_resource: 1 + type: 15117 + host_id: 42 + reserved: 0 + - + start_resource: 37 + num_resource: 1 + type: 15117 + host_id: 21 + reserved: 0 + - + start_resource: 38 + num_resource: 1 + type: 15117 + host_id: 26 + reserved: 0 + - + start_resource: 39 + num_resource: 1 + type: 15117 + host_id: 28 + reserved: 0 + - + start_resource: 40 + num_resource: 2 + type: 15117 + host_id: 35 + reserved: 0 + - + start_resource: 42 + num_resource: 1 + type: 15117 + host_id: 37 + reserved: 0 + - + start_resource: 43 + num_resource: 3 + type: 15117 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 0 + type: 15119 + host_id: 3 + reserved: 0 + - + start_resource: 0 + num_resource: 2 + type: 15119 + host_id: 3 + reserved: 0 + - + start_resource: 12 + num_resource: 20 + type: 15168 + host_id: 3 + reserved: 0 + - + start_resource: 36 + num_resource: 28 + type: 15168 + host_id: 5 + reserved: 0

Intention of patch is to move the signing and packaging of tiboot3.bin image for J721E to binman. So patch excludes tiboot3.bin target for J721E.

The functionality of tools/k3_gen_x509_cert.sh has been replicated in binman with the etype x509_cert. This can be used for J721E by binman.

Signed-off-by: Neha Malcom Francis n-francis@ti.com --- arch/arm/mach-k3/config.mk | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk index ed605adf39..d706d17788 100644 --- a/arch/arm/mach-k3/config.mk +++ b/arch/arm/mach-k3/config.mk @@ -46,6 +46,7 @@ INPUTS-y += sec-cfg.bin endif endif

+ifneq ($(CONFIG_TARGET_J721E_R5_EVM), y) # tiboot3.bin is mandated by ROM and ROM only supports R5 boot. # So restrict tiboot3.bin creation for CPU_V7R. ifdef CONFIG_CPU_V7R @@ -65,6 +66,8 @@ tiboot3.bin: image_check FORCE INPUTS-y += tiboot3.bin endif

+endif + ifdef CONFIG_ARM64

ifeq ($(CONFIG_SOC_K3_J721E),)

By providing entries in the binman node of the device tree, binman will be able to find and package board config binary artifacts generated by TIBoardConfig with sysfw.bin and generate the final image sysfw.itb.

k3-j721e-r5-binman.dtsi has been introduced for R5 specific binman node. It can be then be include by files that require it like k3-j721e-r5-common-proc-board-u-boot.dtsi.

Signed-off-by: Tarun Sahu t-sahu@ti.com [n-francis@ti.com: prepared patch for upstreaming] Signed-off-by: Neha Malcom Francis n-francis@ti.com --- arch/arm/dts/k3-j721e-r5-binman.dtsi | 88 +++++++++++++++++++ .../k3-j721e-r5-common-proc-board-u-boot.dtsi | 1 + board/ti/j721e/Kconfig | 1 + 3 files changed, 90 insertions(+) create mode 100644 arch/arm/dts/k3-j721e-r5-binman.dtsi

diff --git a/arch/arm/dts/k3-j721e-r5-binman.dtsi b/arch/arm/dts/k3-j721e-r5-binman.dtsi new file mode 100644 index 0000000000..e3aeefb08f --- /dev/null +++ b/arch/arm/dts/k3-j721e-r5-binman.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + +#include <config.h> + +/ { + binman: binman { + multiple-images; + }; +}; + +&binman { + tiboot3 { + filename = "tiboot3.bin"; + ti-x509-cert { + content = <&image1>; + core = <16>; + load = <CONFIG_SPL_TEXT_BASE>; + }; + image1: u-boot-spl { + no-expanded; + }; + }; + binary { + filename = "sysfw.bin"; + ti-x509-cert { + content = <&image2>; + core = <0>; + load = <0x0040000>; + }; + image2: ti-sysfw { + }; + }; + itb { + filename = "sysfw.itb"; + fit { + description = "SYSFW and Config Fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob { + filename = "sysfw.bin"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "board-cfg.bin"; + }; + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "pm-cfg.bin"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "rm-cfg.bin"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sec-cfg.bin"; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi index 48c6ddf672..75ec722e89 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi @@ -4,6 +4,7 @@ */

#include "k3-j721e-common-proc-board-u-boot.dtsi" +#include "k3-j721e-r5-binman.dtsi"

/ { chosen { diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index c28752a658..a3a9d504ae 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -24,6 +24,7 @@ config TARGET_J721E_R5_EVM select RAM select SPL_RAM select K3_DDRSS + select BINMAN imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT

tispl.bin must be packaged (with ATF, OPTEE, DM and A72 SPL) for J721E. Binman picks up and packages entries according to the description given in the device tree.

k3-j721e-a72-binman.dtsi has been introduced for A72 specific binman node. It is included by k3-j721e-common-proc-board-u-boot.dtsi

Signed-off-by: Neha Malcom Francis n-francis@ti.com --- arch/arm/dts/k3-j721e-a72-binman.dtsi | 86 +++++++++++++++++++ .../k3-j721e-common-proc-board-u-boot.dtsi | 1 + board/ti/j721e/Kconfig | 1 + 3 files changed, 88 insertions(+) create mode 100644 arch/arm/dts/k3-j721e-a72-binman.dtsi

diff --git a/arch/arm/dts/k3-j721e-a72-binman.dtsi b/arch/arm/dts/k3-j721e-a72-binman.dtsi new file mode 100644 index 0000000000..beb3424bb9 --- /dev/null +++ b/arch/arm/dts/k3-j721e-a72-binman.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + +#include <config.h> + +#ifdef CONFIG_ARM64 +/ { + binman: binman { + multiple-images; + }; +}; + +&binman { + tispl { + filename = "tispl.bin"; + fit { + description = "FIT IMAGE"; + #address-cells = <1>; + images { + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = <CONFIG_K3_ATF_LOAD_ADDR>; + entry = <CONFIG_K3_ATF_LOAD_ADDR>; + atf-bl31 { + }; + }; + tee { + description = "OPTEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <0x9e800000>; + entry = <0x9e800000>; + tee-os { + }; + }; + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + ti-dm { + }; + }; + spl { + description = "SPL (64-bit)"; + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_SPL_TEXT_BASE>; + entry = <CONFIG_SPL_TEXT_BASE>; + u-boot-spl-nodtb { + }; + }; + k3-j721e-common-proc-board.dtb { + description = "k3-j721e-common-proc-board"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "spl/dts/k3-j721e-common-proc-board.dtb"; + }; + }; + }; + configurations { + default = "conf"; + conf { + description = "k3-j721e-common-proc-board"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "k3-j721e-common-proc-board.dtb"; + }; + }; + }; + }; +}; +#endif diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 677a72d2a2..6490d71f7e 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -4,6 +4,7 @@ */

#include <dt-bindings/net/ti-dp83867.h> +#include "k3-j721e-a72-binman.dtsi"

/ { chosen { diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index a3a9d504ae..3cf05f0d3b 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -14,6 +14,7 @@ config TARGET_J721E_A72_EVM select BOARD_LATE_INIT imply TI_I2C_BOARD_DETECT select SYS_DISABLE_DCACHE_OPS + select BINMAN

config TARGET_J721E_R5_EVM bool "TI K3 based J721E EVM running on R5"

To avoid ModuleNotFoundErrors during World Build in CI tests, add installation of test/py/requirements.txt to .azure-pipelines.yml

Signed-off-by: Neha Malcom Francis n-francis@ti.com --- .azure-pipelines.yml | 1 + 1 file changed, 1 insertion(+)

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index ad540ea635..0fd57f59f4 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -551,6 +551,7 @@ stages: EOF cat << "EOF" >> build.sh if [[ "${BUILDMAN}" != "" ]]; then + pip install -r test/py/requirements.txt ret=0; tools/buildman/buildman -o /tmp -P -E -W ${BUILDMAN} ${OVERRIDE} || ret=$?; if [[ $ret -ne 0 ]]; then