c29xpcie REV_A board DDR ECC chip has bad impedance in hardware, force that kind of board to be DDR ECC off when booting. Other version board config ECC on/off by hwconfig=fsl_ddr:ecc=on in uboot enviroment.

Signed-off-by: Po Liu Po.Liu@freescale.com --- Add this patch after the camelcase patch http://patchwork.ozlabs.org/patch/271670/ was added. changes for v2: - Default ecc on by hwconfig=fsl_ddr:ecc=on - Keep the macro define CONFIG_DEF_HWCONFIG

board/freescale/c29xpcie/ddr.c | 8 ++++++++ include/configs/C29XPCIE.h | 2 ++ 2 files changed, 10 insertions(+)

diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c index b017cfd..4077ed9 100644 --- a/board/freescale/c29xpcie/ddr.c +++ b/board/freescale/c29xpcie/ddr.c @@ -9,6 +9,9 @@ #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h>

+#include "cpld.h" + +#define C29XPCIE_HARDWARE_REVA 0x40 /* * Micron MT41J128M16HA-15E * */ @@ -61,7 +64,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); int i; + popts->clk_adjust = 2; popts->cpo_override = 0x1f; popts->write_data_delay = 4; @@ -79,6 +84,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->trwt_override = 1; popts->trwt = 0;

+ if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA) + popts->ecc_mode = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 83779ef..8ccc904 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -431,6 +431,8 @@

#define CONFIG_BAUDRATE 115200

+#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on + #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ "netdev=eth0\0" \