[U-Boot] [PATCH v4 00/22] imx: vybrid: Update BK4 and PCM052 boards to only use DM/DTS
This patch series converts PCM052 and BK4 to use Driver Model and Device Tree.
Some notable changes: - The way how MAC address is read from fuses can now be adjusted - DTS improvement/sync with kernel (also extract u-boot specific properties) - Using generic code instead of one from board
The output of u-boot boot: U-Boot 2019.01-rc3-00076-gc149229be0 (Jan 14 2019 - 08:38:48 +0100)
CPU: Freescale Vybrid VF610 at 396 MHz Reset cause: POWER ON RESET Model: Liebherr (LVF) BK4 Vybrid Board Board: BK4r1 (L333) DRAM: 512 MiB NAND: 1024 MiB MMC: FSL_SDHC: 0 Loading Environment from NAND... OK In: serial@40028000 Out: serial@40028000 Err: serial@40028000 Net: eth0: fec@400d0000, eth1: fec@400d1000 Enter passphrase to stop autoboot, booting in 3 seconds
Buildman CI: ./tools/buildman/buildman.py --branch=HEAD vf610 mx6 vybrid --detail --verbose --show_errors --force-build --count=22 --output-dir=../BUILD/
Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/492731495
U-boot master branch: SHA1: b1b1bab7f92b838a252ab977f56d9c3584c14fb7
Changes in v4: - Fix maming of DDRBYTE0 -> DDRBYTE2 (as it is in the documentation) - Update DDRBYTE0 -> DDRBYTE2 as in VF610 user manual
Changes in v3: - Add code to enable I2C0 code as suggested by Stefan (so the code can be reused by other boards without regressions) - Exclude the pcm052.c related code to a separate patch - New patch (separate board code patch)
Changes in v2: - Rename pcm052.dts to vf610-pcm052.dts - Rename bk4r1.dts to vf610-bk4r1.dts - Extract 'u-boot,dm-pre-reloc;' property to separate file (to facilitate sync with Linux kernel dts files) - New patch - Disable EFI related support and commands (as we do not plan to use EFI on this setup)
Lukasz Majewski (22): net: FEC: Add compatible for vybrid (vf610) to reuse fec_mxc.c driver net: Kconfig: FEC: Add dependency on VF610 vybrid: ddr: Extend vf610-pinfunc.h with DDR pads definitions vybrid: clock: Provide enable_i2c_clk() function for Vybrid pcm052: board: Do not enable I2C2 code in the board file vybrid: Define the imx_get_mac_from_fuse() as a __weak function pcm052: board: Remove "m4go" command as it is superseded by "bootaux" pcm052: board: vybrid: Update the board name for BK4 device ARM: DTS: vybrid: Update vf.dtsi file to descibe more vf610 hardware pcm052: board: cosmetic: Add copyright notice to pcm052.c ARM: DTS: Update pcm052 based dts files (bk4r1/pcm052) ARM: DTS: Provide vf610-bk4r1-u-boot.dtsi for U-Boot specific properties defconfig: bk4/pcm052: Update bk4r1|pcm052_defconfig to support DM/DT config: pcm052: Use SZ_X{MK} from linux/sizes.h for include/configs/pcm052.h config: bk4: Update include/configs/bk4r1.h file pcm052: board: Remove in-board setup code (it is now replaced by DM setup) config: bk4: Update u-boot script to support recovery via SD card config: bk4: Update u-boot envs to support NOR memories initial setup pcm052: bk4: sdcard: Add support for SD card booting/recovery pcm052: board: Add code to setup LED default states pcm052: mac: Provide board specific imx_get_mac_from_fuse() function pcm052: bk4: Add board_phy_config() for BK4 to setup ksz8081 phy
arch/arm/cpu/armv7/vf610/Kconfig | 1 + arch/arm/cpu/armv7/vf610/generic.c | 24 +- arch/arm/dts/Makefile | 4 +- arch/arm/dts/bk4r1.dts | 47 ---- arch/arm/dts/vf.dtsi | 62 +++++ arch/arm/dts/vf610-bk4r1-u-boot.dtsi | 27 ++ arch/arm/dts/vf610-bk4r1.dts | 97 +++++++ arch/arm/dts/{pcm052.dts => vf610-pcm052.dts} | 6 +- arch/arm/dts/vf610-pcm052.dtsi | 259 +++++++++++++++++ arch/arm/dts/vf610-pinfunc.h | 50 ++++ arch/arm/include/asm/arch-vf610/clock.h | 3 + arch/arm/include/asm/arch-vf610/imx-regs.h | 2 + board/phytec/pcm052/pcm052.c | 386 ++++++-------------------- configs/bk4r1_defconfig | 49 +++- configs/pcm052_defconfig | 36 ++- drivers/net/Kconfig | 2 +- drivers/net/fec_mxc.c | 1 + include/configs/bk4r1.h | 263 +++++++++++++++++- include/configs/pcm052.h | 51 +--- 19 files changed, 959 insertions(+), 411 deletions(-) delete mode 100644 arch/arm/dts/bk4r1.dts create mode 100644 arch/arm/dts/vf610-bk4r1-u-boot.dtsi create mode 100644 arch/arm/dts/vf610-bk4r1.dts rename arch/arm/dts/{pcm052.dts => vf610-pcm052.dts} (81%) create mode 100644 arch/arm/dts/vf610-pcm052.dtsi
The NXP's FEC driver can be reused on vf610 device (with DM).
Signed-off-by: Lukasz Majewski lukma@denx.de Reviewed-by: Stefan Agner stefan.agner@toradex.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
drivers/net/fec_mxc.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 1a59026a62..5ff49224f4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1486,6 +1486,7 @@ static const struct udevice_id fecmxc_ids[] = { { .compatible = "fsl,imx6ul-fec" }, { .compatible = "fsl,imx53-fec" }, { .compatible = "fsl,imx7d-fec" }, + { .compatible = "fsl,mvf600-fec" }, { } };
The NXP's FEC driver can be reused on vf610 device (with DM). Signed-off-by: Lukasz Majewski lukma@denx.de Reviewed-by: Stefan Agner stefan.agner@toradex.com
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
Signed-off-by: Lukasz Majewski lukma@denx.de Reviewed-by: Stefan Agner stefan.agner@toradex.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
drivers/net/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 6a570285aa..a3e1b4f411 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -187,7 +187,7 @@ config FEC_MXC_MDIO_BASE
config FEC_MXC bool "FEC Ethernet controller" - depends on MX5 || MX6 || MX7 || IMX8 + depends on MX5 || MX6 || MX7 || IMX8 || VF610 help This driver supports the 10/100 Fast Ethernet controller for NXP i.MX processors.
Signed-off-by: Lukasz Majewski lukma@denx.de Reviewed-by: Stefan Agner stefan.agner@toradex.com
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
This patch provides definitions necessary for VF610 DDR pad configurations.
Signed-off-by: Lukasz Majewski lukma@denx.de Reviewed-by: Stefan Agner stefan.agner@toradex.com
---
Changes in v4: - Fix maming of DDRBYTE0 -> DDRBYTE2 (as it is in the documentation)
Changes in v3: None Changes in v2: None
arch/arm/dts/vf610-pinfunc.h | 50 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+)
diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h index fcad7132c8..9456719074 100644 --- a/arch/arm/dts/vf610-pinfunc.h +++ b/arch/arm/dts/vf610-pinfunc.h @@ -807,4 +807,54 @@ #define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 #define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1
+#define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A15__DDR_A_15 0x220 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A14__DDR_A_14 0x224 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A13__DDR_A_13 0x228 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A12__DDR_A_12 0x22c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A11__DDR_A_11 0x230 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A10__DDR_A_10 0x234 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A9__DDR_A_9 0x238 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A8__DDR_A_8 0x23c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A7__DDR_A_7 0x240 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A6__DDR_A_6 0x244 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A5__DDR_A_5 0x248 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A4__DDR_A_4 0x24c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A3__DDR_A_3 0x250 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A2__DDR_A_2 0x254 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A1__DDR_A_1 0x258 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A0__DDR_A_0 0x25c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA2__DDR_BA_2 0x260 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA1__DDR_BA_1 0x264 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA0__DDR_BA_0 0x268 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CAS__DDR_CAS_B 0x26c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CKE__DDR_CKE_0 0x270 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CLK__DDR_CLK_0 0x274 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CS__DDR_CS_B_0 0x278 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D15__DDR_D_15 0x27c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D14__DDR_D_14 0x280 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D13__DDR_D_13 0x284 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D12__DDR_D_12 0x288 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D11__DDR_D_11 0x28c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D10__DDR_D_10 0x290 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D9__DDR_D_9 0x294 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D8__DDR_D_8 0x298 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D7__DDR_D_7 0x29c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D6__DDR_D_6 0x2a0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D5__DDR_D_5 0x2a4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D4__DDR_D_4 0x2a8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D3__DDR_D_3 0x2ac 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D2__DDR_D_2 0x2b0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D1__DDR_D_1 0x2b4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D0__DDR_D_0 0x2b8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQM1__DDR_DQM_1 0x2bc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQM0__DDR_DQM_0 0x2c0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQS1__DDR_DQS_1 0x2c4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQS0__DDR_DQS_0 0x2c8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_RAS__DDR_RAS_B 0x2cc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_WE__DDR_WE_B 0x2d0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_ODT1__DDR_ODT_0 0x2d4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x2d8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x2e0 0x000 ALT0 0x0 #endif
This patch provides definitions necessary for VF610 DDR pad configurations. Signed-off-by: Lukasz Majewski lukma@denx.de Reviewed-by: Stefan Agner stefan.agner@toradex.com
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
Provide function to enable I2C clocks for vf610 - in the generic code. This function overrides the default weak function implementation (which only returns 1).
Signed-off-by: Lukasz Majewski lukma@denx.de Tested-by: Marcel Ziswiler marcel.ziswiler@toradex.com
---
Changes in v4: None Changes in v3: - Add code to enable I2C0 code as suggested by Stefan (so the code can be reused by other boards without regressions) - Exclude the pcm052.c related code to a separate patch
Changes in v2: None
arch/arm/cpu/armv7/vf610/generic.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/arch-vf610/clock.h | 3 +++ 2 files changed, 25 insertions(+)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index cbd3391918..e0c0b1bcb0 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -375,3 +375,25 @@ void enable_caches(void) mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option); } #endif + +#ifdef CONFIG_SYS_I2C_MXC +/* i2c_num can be from 0 - 3 */ +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + + switch (i2c_num) { + case 0: + clrsetbits_le32(&ccm->ccgr4, CCM_CCGR4_I2C0_CTRL_MASK, + CCM_CCGR4_I2C0_CTRL_MASK); + case 2: + clrsetbits_le32(&ccm->ccgr10, CCM_CCGR10_I2C2_CTRL_MASK, + CCM_CCGR10_I2C2_CTRL_MASK); + break; + default: + return -EINVAL; + } + + return 0; +} +#endif diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h index 3bd73a01f3..72184fd608 100644 --- a/arch/arm/include/asm/arch-vf610/clock.h +++ b/arch/arm/include/asm/arch-vf610/clock.h @@ -22,6 +22,9 @@ enum mxc_clock { void enable_ocotp_clk(unsigned char enable); unsigned int mxc_get_clock(enum mxc_clock clk); u32 get_lpuart_clk(void); +#ifdef CONFIG_SYS_I2C_MXC +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); +#endif
#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
Provide function to enable I2C clocks for vf610 - in the generic code. This function overrides the default weak function implementation (which only returns 1). Signed-off-by: Lukasz Majewski lukma@denx.de Tested-by: Marcel Ziswiler marcel.ziswiler@toradex.com
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
As the I2C2 clock is now enabled in the generic clock code, we can remove this code from a board file.
Signed-off-by: Lukasz Majewski lukma@denx.de Tested-by: Marcel Ziswiler marcel.ziswiler@toradex.com
---
Changes in v4: None Changes in v3: - New patch (separate board code patch)
Changes in v2: None
board/phytec/pcm052/pcm052.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index f988af2abc..cfc8009102 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -485,7 +485,7 @@ static void clock_init(void) clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, - CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK); + CCM_CCGR10_NFC_CTRL_MASK);
clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
As the I2C2 clock is now enabled in the generic clock code, we can remove this code from a board file. Signed-off-by: Lukasz Majewski lukma@denx.de Tested-by: Marcel Ziswiler marcel.ziswiler@toradex.com
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
The proposed way of reading fused MAC in the imx_get_mac_from_fuse() may be different for other boards.
This commit defines the imx_get_mac_from_fuse() as a weak function to allow board file overriding it with customized function.
Signed-off-by: Lukasz Majewski lukma@denx.de ---
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/armv7/vf610/generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index e0c0b1bcb0..90fa695e98 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -252,7 +252,7 @@ U_BOOT_CMD( );
#ifdef CONFIG_FEC_MXC -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +__weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; struct fuse_bank *bank = &ocotp->bank[4];
The proposed way of reading fused MAC in the imx_get_mac_from_fuse() may be different for other boards. This commit defines the imx_get_mac_from_fuse() as a weak function to allow board file overriding it with customized function. Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
The "m4go" provides exactly the same functionality as the IMX generic "bootaux" command. Remove it to not duplicate the code.
Signed-off-by: Lukasz Majewski lukma@denx.de ---
Changes in v4: None Changes in v3: None Changes in v2: None
board/phytec/pcm052/pcm052.c | 38 -------------------------------------- 1 file changed, 38 deletions(-)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index cfc8009102..4e4b870304 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -577,41 +577,3 @@ int checkboard(void)
return 0; } - -static int do_m4go(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - ulong addr; - - /* Consume 'm4go' */ - argc--; argv++; - - /* - * Parse provided address - default to load_addr in case not provided. - */ - - if (argc) - addr = simple_strtoul(argv[0], NULL, 16); - else - addr = load_addr; - - /* - * Write boot address in PERSISTENT_ENTRY1[31:0] aka SRC_GPR2[31:0] - */ - writel(addr + 0x401, 0x4006E028); - - /* - * Start secondary processor by enabling its clock - */ - writel(0x15a5a, 0x4006B08C); - - return 1; -} - -U_BOOT_CMD( - m4go, 2 /* one arg max */, 1 /* repeatable */, do_m4go, - "start the secondary Cortex-M4 from scatter file image", - "[<addr>]\n" - " - start secondary Cortex-M4 core using a scatter file image\n" - "The argument needs to be a scatter file\n" -);
The "m4go" provides exactly the same functionality as the IMX generic "bootaux" command. Remove it to not duplicate the code. Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
This commit provides distinction between PCM052 and BK4.
Signed-off-by: Lukasz Majewski lukma@denx.de ---
Changes in v4: None Changes in v3: None Changes in v2: None
board/phytec/pcm052/pcm052.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 4e4b870304..5f2c9a9c12 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -573,7 +573,10 @@ int board_init(void)
int checkboard(void) { +#ifdef CONFIG_TARGET_BK4R1 + puts("Board: BK4r1 (L333)\n"); +#else puts("Board: PCM-052\n"); - +#endif return 0; }
This commit provides distinction between PCM052 and BK4. Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
This patch allows moving vf610 based boards to a device tree and model. Ported from Linux kernel - v4.20 (tag)
Signed-off-by: Lukasz Majewski lukma@denx.de Reviewed-by: Stefan Agner stefan.agner@toradex.com Tested-by: Marcel Ziswiler marcel.ziswiler@toradex.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/dts/vf.dtsi | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+)
diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi index ad30059b9a..5e3b2c5b9d 100644 --- a/arch/arm/dts/vf.dtsi +++ b/arch/arm/dts/vf.dtsi @@ -22,6 +22,10 @@ spi1 = &dspi1; ehci0 = &ehci0; ehci1 = &ehci1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; };
soc { @@ -89,6 +93,22 @@ status = "disabled"; };
+ i2c0: i2c@40066000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x40066000 0x1000>; + status = "disabled"; + }; + + i2c1: i2c@40067000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x40067000 0x1000>; + status = "disabled"; + }; + iomuxc: iomuxc@40048000 { compatible = "fsl,vf610-iomuxc"; reg = <0x40048000 0x1000>; @@ -156,6 +176,48 @@ reg = <0x400b4000 0x800>; status = "disabled"; }; + + esdhc1: esdhc@400b2000 { + compatible = "fsl,esdhc"; + reg = <0x400b2000 0x1000>; + status = "disabled"; + }; + + fec0: fec@400d0000 { + compatible = "fsl,mvf600-fec"; + reg = <0x400d0000 0x1000>; + status = "disabled"; + }; + + fec1: fec@400d1000 { + compatible = "fsl,mvf600-fec"; + reg = <0x400d1000 0x1000>; + status = "disabled"; + }; + + nfc: nand@400e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-nfc"; + reg = <0x400e0000 0x4000>; + status = "disabled"; + }; + + i2c2: i2c@400e6000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x400e6000 0x1000>; + status = "disabled"; + }; + + i2c3: i2c@400e7000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x400e7000 0x1000>; + status = "disabled"; + }; }; }; };
This patch allows moving vf610 based boards to a device tree and model. Ported from Linux kernel - v4.20 (tag) Signed-off-by: Lukasz Majewski lukma@denx.de Reviewed-by: Stefan Agner stefan.agner@toradex.com Tested-by: Marcel Ziswiler marcel.ziswiler@toradex.com
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
Signed-off-by: Lukasz Majewski lukma@denx.de ---
Changes in v4: None Changes in v3: None Changes in v2: None
board/phytec/pcm052/pcm052.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 5f2c9a9c12..95df0be6c1 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * (C) Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de. + * * Copyright 2013 Freescale Semiconductor, Inc. */
Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
This commit provides update and renames the bk4r1.dts to vf610-bk4r1.dts file with more on SoC HW description. The pcm052.dts has been renamed to vf610-pcm052.dts as well.
Moreover, a new vf610-pcm052.drsi file has been introduced to reuse the common code between devices based on Phytec's pcm052 modules. Ported from Linux kernel - v4.20 (tag)
Signed-off-by: Lukasz Majewski lukma@denx.de
---
Changes in v4: - Update DDRBYTE0 -> DDRBYTE2 as in VF610 user manual
Changes in v3: None Changes in v2: - Rename pcm052.dts to vf610-pcm052.dts - Rename bk4r1.dts to vf610-bk4r1.dts - Extract 'u-boot,dm-pre-reloc;' property to separate file (to facilitate sync with Linux kernel dts files)
arch/arm/dts/Makefile | 4 +- arch/arm/dts/bk4r1.dts | 47 ----- arch/arm/dts/vf610-bk4r1.dts | 97 ++++++++++ arch/arm/dts/{pcm052.dts => vf610-pcm052.dts} | 6 +- arch/arm/dts/vf610-pcm052.dtsi | 259 ++++++++++++++++++++++++++ configs/bk4r1_defconfig | 2 +- configs/pcm052_defconfig | 2 +- 7 files changed, 361 insertions(+), 56 deletions(-) delete mode 100644 arch/arm/dts/bk4r1.dts create mode 100644 arch/arm/dts/vf610-bk4r1.dts rename arch/arm/dts/{pcm052.dts => vf610-pcm052.dts} (81%) create mode 100644 arch/arm/dts/vf610-pcm052.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ca50623480..8861827fcc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -432,8 +432,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ vf610-colibri.dtb \ vf610-twr.dtb \ - pcm052.dtb \ - bk4r1.dtb + vf610-pcm052.dtb \ + vf610-bk4r1.dtb
dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
diff --git a/arch/arm/dts/bk4r1.dts b/arch/arm/dts/bk4r1.dts deleted file mode 100644 index 866b80e0b0..0000000000 --- a/arch/arm/dts/bk4r1.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2016 Toradex AG - */ - -/dts-v1/; -#include "vf.dtsi" - -/ { - model = "Phytec phyCORE-Vybrid"; - compatible = "phytec,pcm052", "fsl,vf610"; - - chosen { - stdout-path = &uart1; - }; - - aliases { - spi0 = &qspi0; - }; - -}; - -&uart1 { - status = "okay"; -}; - -&qspi0 { - bus-num = <0>; - num-cs = <2>; - status = "okay"; - - qflash0: spi_flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-flash"; - spi-max-frequency = <108000000>; - reg = <0>; - }; - - qflash1: spi_flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-flash"; - spi-max-frequency = <66000000>; - reg = <1>; - }; -}; diff --git a/arch/arm/dts/vf610-bk4r1.dts b/arch/arm/dts/vf610-bk4r1.dts new file mode 100644 index 0000000000..55cd53384a --- /dev/null +++ b/arch/arm/dts/vf610-bk4r1.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * (C) Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de. + * + * Copyright 2016 Toradex AG + */ + +/dts-v1/; +#include "vf610-pcm052.dtsi" +#include "vf610-pinfunc.h" + +/ { + model = "Liebherr (LVF) BK4 Vybrid Board"; + compatible = "lvf,bk4", "fsl,vf610"; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + compatible = "gpio-leds"; + + /* PTE15 PORT3[24] H6 green */ + led@0 { + label = "0"; + gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + /* PTA12 PORT0[5] H5 green */ + led@1 { + label = "1"; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + /* PTE20 PORT3[39] H4 green */ + led@2 { + label = "2"; + gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + /* PTE12 PORT3[21] H3 green */ + led@3 { + label = "3"; + gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + /* LED6 is now PRESET ETH -> PTA16 PORT0[6] H6 red */ + /* PTE9 PORT3[18] H5 red */ + led@4 { + label = "5"; + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + /* PTE23 PORT4[0] H4 red */ + led@5 { + label = "6"; + gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + /* PTE16 PORT3[25] H3 red */ + led@6 { + label = "7"; + gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_ddr &pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* ETH control pins */ + VF610_PAD_PTE17__GPIO_122 0x1183 + VF610_PAD_PTA16__GPIO_6 0x1183 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + /* LEDS */ + VF610_PAD_PTE15__GPIO_120 0x1183 + VF610_PAD_PTA12__GPIO_5 0x1183 + VF610_PAD_PTE9__GPIO_114 0x1183 + VF610_PAD_PTE20__GPIO_125 0x1183 + VF610_PAD_PTE23__GPIO_128 0x1183 + VF610_PAD_PTE16__GPIO_121 0x1183 + >; + }; +}; diff --git a/arch/arm/dts/pcm052.dts b/arch/arm/dts/vf610-pcm052.dts similarity index 81% rename from arch/arm/dts/pcm052.dts rename to arch/arm/dts/vf610-pcm052.dts index 6489fdc6f4..22026024ea 100644 --- a/arch/arm/dts/pcm052.dts +++ b/arch/arm/dts/vf610-pcm052.dts @@ -4,7 +4,7 @@ */
/dts-v1/; -#include "vf.dtsi" +#include "vf610-pcm052.dtsi"
/ { model = "Phytec phyCORE-Vybrid"; @@ -15,7 +15,3 @@ };
}; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm/dts/vf610-pcm052.dtsi b/arch/arm/dts/vf610-pcm052.dtsi new file mode 100644 index 0000000000..1383d03c22 --- /dev/null +++ b/arch/arm/dts/vf610-pcm052.dtsi @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * (C) Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de. + * + */ + +/dts-v1/; +#include "vf.dtsi" +#include "vf610-pinfunc.h" + +/ { + chosen { + stdout-path = &uart1; + }; + + aliases { + spi0 = &qspi0; + mmc0 = &esdhc1; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth>; + + phy-mode = "rmii"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth1>; + + phy-mode = "rmii"; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + u-boot,i2c-offset-len = <2>; + }; + + m41t62: rtc@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ddr>; + + pinctrl_ddr: ddrgrp { + fsl,pins = < + VF610_PAD_DDR_A15__DDR_A_15 0x1c0 + VF610_PAD_DDR_A14__DDR_A_14 0x1c0 + VF610_PAD_DDR_A13__DDR_A_13 0x1c0 + VF610_PAD_DDR_A12__DDR_A_12 0x1c0 + VF610_PAD_DDR_A11__DDR_A_11 0x1c0 + VF610_PAD_DDR_A10__DDR_A_10 0x1c0 + VF610_PAD_DDR_A9__DDR_A_9 0x1c0 + VF610_PAD_DDR_A8__DDR_A_8 0x1c0 + VF610_PAD_DDR_A7__DDR_A_7 0x1c0 + VF610_PAD_DDR_A6__DDR_A_6 0x1c0 + VF610_PAD_DDR_A5__DDR_A_5 0x1c0 + VF610_PAD_DDR_A4__DDR_A_4 0x1c0 + VF610_PAD_DDR_A3__DDR_A_3 0x1c0 + VF610_PAD_DDR_A2__DDR_A_2 0x1c0 + VF610_PAD_DDR_A1__DDR_A_1 0x1c0 + VF610_PAD_DDR_A0__DDR_A_0 0x1c0 + VF610_PAD_DDR_BA2__DDR_BA_2 0x1c0 + VF610_PAD_DDR_BA1__DDR_BA_1 0x1c0 + VF610_PAD_DDR_BA0__DDR_BA_0 0x1c0 + VF610_PAD_DDR_CAS__DDR_CAS_B 0x1c0 + VF610_PAD_DDR_CKE__DDR_CKE_0 0x1c0 + VF610_PAD_DDR_CLK__DDR_CLK_0 0x101c0 + VF610_PAD_DDR_CS__DDR_CS_B_0 0x1c0 + VF610_PAD_DDR_D15__DDR_D_15 0x1c0 + VF610_PAD_DDR_D14__DDR_D_14 0x1c0 + VF610_PAD_DDR_D13__DDR_D_13 0x1c0 + VF610_PAD_DDR_D12__DDR_D_12 0x1c0 + VF610_PAD_DDR_D11__DDR_D_11 0x1c0 + VF610_PAD_DDR_D10__DDR_D_10 0x1c0 + VF610_PAD_DDR_D9__DDR_D_9 0x1c0 + VF610_PAD_DDR_D8__DDR_D_8 0x1c0 + VF610_PAD_DDR_D7__DDR_D_7 0x1c0 + VF610_PAD_DDR_D6__DDR_D_6 0x1c0 + VF610_PAD_DDR_D5__DDR_D_5 0x1c0 + VF610_PAD_DDR_D4__DDR_D_4 0x1c0 + VF610_PAD_DDR_D3__DDR_D_3 0x1c0 + VF610_PAD_DDR_D2__DDR_D_2 0x1c0 + VF610_PAD_DDR_D1__DDR_D_1 0x1c0 + VF610_PAD_DDR_D0__DDR_D_0 0x1c0 + VF610_PAD_DDR_DQM1__DDR_DQM_1 0x1c0 + VF610_PAD_DDR_DQM0__DDR_DQM_0 0x1c0 + VF610_PAD_DDR_DQS1__DDR_DQS_1 0x101c0 + VF610_PAD_DDR_DQS0__DDR_DQS_0 0x101c0 + VF610_PAD_DDR_RAS__DDR_RAS_B 0x1c0 + VF610_PAD_DDR_WE__DDR_WE_B 0x1c0 + VF610_PAD_DDR_ODT1__DDR_ODT_0 0x1c0 + VF610_PAD_DDR_ODT0__DDR_ODT_1 0x1c0 + VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x1c0 + VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x1c0 + VF610_PAD_DDR_RESETB 0x1006c + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_eth: ethgrp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30dd + VF610_PAD_PTC0__ENET_RMII0_MDC 0x30de + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df + VF610_PAD_PTC2__ENET_RMII0_CRS 0x30dd + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de + >; + }; + + pinctrl_eth1: eth1grp { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30dd + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30dd + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30dd + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30de + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30de + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30de + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + VF610_PAD_PTA22__I2C2_SCL 0x34df + VF610_PAD_PTA23__I2C2_SDA 0x34df + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + VF610_PAD_PTD31__NF_IO15 0x28df + VF610_PAD_PTD30__NF_IO14 0x28df + VF610_PAD_PTD29__NF_IO13 0x28df + VF610_PAD_PTD28__NF_IO12 0x28df + VF610_PAD_PTD27__NF_IO11 0x28df + VF610_PAD_PTD26__NF_IO10 0x28df + VF610_PAD_PTD25__NF_IO9 0x28df + VF610_PAD_PTD24__NF_IO8 0x28df + VF610_PAD_PTD23__NF_IO7 0x28df + VF610_PAD_PTD22__NF_IO6 0x28df + VF610_PAD_PTD21__NF_IO5 0x28df + VF610_PAD_PTD20__NF_IO4 0x28df + VF610_PAD_PTD19__NF_IO3 0x28df + VF610_PAD_PTD18__NF_IO2 0x28df + VF610_PAD_PTD17__NF_IO1 0x28df + VF610_PAD_PTD16__NF_IO0 0x28df + VF610_PAD_PTB24__NF_WE_B 0x28c2 + VF610_PAD_PTB25__NF_CE0_B 0x28c2 + VF610_PAD_PTB27__NF_RE_B 0x28c2 + VF610_PAD_PTC26__NF_RB_B 0x283d + VF610_PAD_PTC27__NF_ALE 0x28c2 + VF610_PAD_PTC28__NF_CLE 0x28c2 + >; + }; + + pinctrl_qspi0: qspi0grp { + fsl,pins = < + VF610_PAD_PTD0__QSPI0_A_QSCK 0x397f + VF610_PAD_PTD1__QSPI0_A_CS0 0x397f + VF610_PAD_PTD2__QSPI0_A_DATA3 0x397f + VF610_PAD_PTD3__QSPI0_A_DATA2 0x397f + VF610_PAD_PTD4__QSPI0_A_DATA1 0x397f + VF610_PAD_PTD5__QSPI0_A_DATA0 0x397f + VF610_PAD_PTD7__QSPI0_B_QSCK 0x397f + VF610_PAD_PTD8__QSPI0_B_CS0 0x397f + VF610_PAD_PTD11__QSPI0_B_DATA1 0x397f + VF610_PAD_PTD12__QSPI0_B_DATA0 0x397f + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + + status = "okay"; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + + bus-num = <0>; + num-cs = <2>; + status = "okay"; + + qflash0: spi_flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <108000000>; + reg = <0>; + }; + + qflash1: spi_flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <66000000>; + reg = <1>; + }; +}; diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 9e31b4ac97..b67a3946ac 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -25,7 +25,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=NAND,nor0=NOR" CONFIG_MTDPARTS_DEFAULT="mtdparts=NAND:640k(bootloader),128k(env1),128k(env2),128k(dtb),6144k(kernel),-(root);NOR:-(nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="bk4r1" +CONFIG_DEFAULT_DEVICE_TREE="vf610-bk4r1" CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_DM_GPIO=y diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index e207df51a8..26ee823df3 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -24,7 +24,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=NAND" CONFIG_MTDPARTS_DEFAULT="mtdparts=NAND:640k(bootloader),128k(env1),128k(env2),128k(dtb),6144k(kernel),-(root)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="pcm052" +CONFIG_DEFAULT_DEVICE_TREE="vf610-pcm052" CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_DM_GPIO=y
This commit provides update and renames the bk4r1.dts to vf610-bk4r1.dts file with more on SoC HW description. The pcm052.dts has been renamed to vf610-pcm052.dts as well. Moreover, a new vf610-pcm052.drsi file has been introduced to reuse the common code between devices based on Phytec's pcm052 modules. Ported from Linux kernel - v4.20 (tag) Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
This commit brings a separate file in which the U-Boot specific properties (like 'dm-pre-reloc') are provided.
Such approach allows easy sync with upstream Linux kernel in the future.
Signed-off-by: Lukasz Majewski lukma@denx.de Reviewed-by: Tom Rini trini@konsulko.com
---
Changes in v4: None Changes in v3: None Changes in v2: - New patch
arch/arm/dts/vf610-bk4r1-u-boot.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 arch/arm/dts/vf610-bk4r1-u-boot.dtsi
diff --git a/arch/arm/dts/vf610-bk4r1-u-boot.dtsi b/arch/arm/dts/vf610-bk4r1-u-boot.dtsi new file mode 100644 index 0000000000..088926bde2 --- /dev/null +++ b/arch/arm/dts/vf610-bk4r1-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/ { + soc { + u-boot,dm-pre-reloc; + }; +}; + +&aips0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ddr { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +};
This commit brings a separate file in which the U-Boot specific properties (like 'dm-pre-reloc') are provided. Such approach allows easy sync with upstream Linux kernel in the future. Signed-off-by: Lukasz Majewski lukma@denx.de Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
This commit updates BK4's and PCM052's config files to support as much as possible device tree and model in u-boot.
Moreover, remove CONFIG_* from pcm052.h (as those are now in bk4|pcm052_defconfig)
Signed-off-by: Lukasz Majewski lukma@denx.de
---
Changes in v4: None Changes in v3: None Changes in v2: - Disable EFI related support and commands (as we do not plan to use EFI on this setup)
configs/bk4r1_defconfig | 47 ++++++++++++++++++++++++++++++++++++++++++----- configs/pcm052_defconfig | 34 ++++++++++++++++++++++++++++++++-- include/configs/pcm052.h | 34 ---------------------------------- 3 files changed, 74 insertions(+), 41 deletions(-)
diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index b67a3946ac..e3852f4856 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -2,15 +2,18 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 +CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_TARGET_BK4R1=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_EEPROM=y +# CONFIG_CMD_ELF is not set CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DM=y +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -19,19 +22,45 @@ CONFIG_CMD_SF=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=NAND,nor0=NOR" -CONFIG_MTDPARTS_DEFAULT="mtdparts=NAND:640k(bootloader),128k(env1),128k(env2),128k(dtb),6144k(kernel),-(root);NOR:-(nor)" +CONFIG_MTDIDS_DEFAULT="nand0=vf610_nfc,nor0=NOR" +CONFIG_MTDPARTS_DEFAULT="mtdparts=vf610_nfc:2048k(bootloader),128k(env1),128k(env2),10240k(initrd),40960k(dtbkernel),-(system);NOR:-(nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="vf610-bk4r1" CONFIG_ENV_IS_IN_NAND=y +CONFIG_NETCONSOLE=y CONFIG_DM=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_SYS_BOOTCOUNT_ADDR=0x4006e02c CONFIG_DM_GPIO=y CONFIG_VYBRID_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_MXC_OCOTP=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_EEPROM_SIZE=32768 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y +CONFIG_MTD=y CONFIG_NAND_VF610_NFC=y +CONFIG_NAND_VF610_NFC_DT=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y @@ -39,10 +68,18 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_VYBRID=y +CONFIG_DM_RTC=y CONFIG_RTC_M41T62=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_TPL_SERIAL_PRESENT is not set CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index 26ee823df3..906abbfd69 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -9,7 +9,6 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y -CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -18,7 +17,6 @@ CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=NAND" CONFIG_MTDPARTS_DEFAULT="mtdparts=NAND:640k(bootloader),128k(env1),128k(env2),128k(dtb),6144k(kernel),-(root)" @@ -29,12 +27,44 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_VYBRID_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_MISC=y +CONFIG_MXC_OCOTP=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_EEPROM_SIZE=32768 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y +CONFIG_MTD=y CONFIG_NAND_VF610_NFC=y +CONFIG_NAND_VF610_NFC_DT=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_VYBRID=y +CONFIG_DM_RTC=y CONFIG_RTC_M41T62=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index e125a38e7d..c2ecb7ec18 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -24,48 +24,14 @@ /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION
-#ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR - -#define CONFIG_JFFS2_NAND - -/* Dynamic MTD partition support */ - -#endif - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 - /* QSPI Configs*/ - #ifdef CONFIG_FSL_QSPI #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SYS_FSL_QSPI_LE #endif
-/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC - -/* RTC (actually an RV-4162 but M41T62-compatible) */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_RTC_BUS_NUM 2 - -/* EEPROM (24FC256) */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_BUS 2 -
#define CONFIG_LOADADDR 0x82000000
This commit updates BK4's and PCM052's config files to support as much as possible device tree and model in u-boot. Moreover, remove CONFIG_* from pcm052.h (as those are now in bk4|pcm052_defconfig) Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
Signed-off-by: Lukasz Majewski lukma@denx.de Reviewed-by: Marcel Ziswiler marcel.ziswiler@toradex.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
include/configs/pcm052.h | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index c2ecb7ec18..fb8f3c8609 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -9,6 +9,7 @@ #define __CONFIG_H
#include <asm/arch/imx-regs.h> +#include <linux/sizes.h>
#define CONFIG_SKIP_LOWLEVEL_INIT
@@ -16,7 +17,7 @@ #define CONFIG_CMDLINE_TAG
/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M)
/* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -27,7 +28,7 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* QSPI Configs*/ #ifdef CONFIG_FSL_QSPI -#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_SIZE (SZ_16M) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SYS_FSL_QSPI_LE #endif @@ -154,7 +155,7 @@
/* Physical memory map */ #define PHYS_SDRAM (0x80000000) -#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * 1024 * 1024) +#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR @@ -167,17 +168,17 @@
/* environment organization */ #ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SIZE (SZ_8K)
-#define CONFIG_ENV_OFFSET (12 * 64 * 1024) +#define CONFIG_ENV_OFFSET (12 * SZ_64K) #define CONFIG_SYS_MMC_ENV_DEV 0 #endif
#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SECT_SIZE (SZ_128K) +#define CONFIG_ENV_SIZE (SZ_8K) #define CONFIG_ENV_OFFSET 0xA0000 -#define CONFIG_ENV_SIZE_REDUND (8 * 1024) +#define CONFIG_ENV_SIZE_REDUND (SZ_8K) #define CONFIG_ENV_OFFSET_REDUND 0xC0000 #endif
Signed-off-by: Lukasz Majewski lukma@denx.de Reviewed-by: Marcel Ziswiler marcel.ziswiler@toradex.com
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
The BK4's config file has changed since its initial posting to main line. This commit reflects those changes.
Signed-off-by: Lukasz Majewski lukma@denx.de ---
Changes in v4: None Changes in v3: None Changes in v2: None
include/configs/bk4r1.h | 214 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 206 insertions(+), 8 deletions(-)
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index a012705870..bbd3e4e636 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -1,24 +1,222 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright (C) 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * * Copyright 2016 3ADEV http://3adev.com * Written-by: Albert ARIBAUD albert.aribaud@3adev.fr * - * Configuration settings for the phytec PCM-052 SoM-based BK4R1. + * Configuration settings for BK4R1. */
+#ifndef __CONFIG_H +#define __CONFIG_H + /* Define the BK4r1-specific env commands */ -#define PCM052_EXTRA_ENV_SETTINGS \ +#define BK4_EXTRA_ENV_SETTINGS \ + "bootlimit=3\0" \ + "eraseuserdata=false\0" \ + "altbootcmd=led 5 on; " \ + "boot\0" \ "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \ - "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0" + "set_gpio102=mw 0x400ff0c4 0x40; mw 0x40048198 0x000011bf\0" \ + "set_gpio96=mw 0x40048180 0x282; mw 0x400ff0c4 0x1\0"\ + "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"\ + "set_gpio6=mw 0x40048018 0x282; mw 0x400ff008 0x40\0"\ + "manage_userdata=" MANAGE_USERDATA "\0"\ + "ncenable=true\0"\ + "ncserverip=192.168.0.77\0"\ + "if_netconsole=ping $ncserverip\0"\ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10;" \ + "setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "preboot=" BK4_NET_INIT \ + "if ${ncenable}; then run if_netconsole start_netconsole; fi\0"
/* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/ -#define PCM052_BOOTCOMMAND "run set_gpio103; sf probe; " +#define BK4_BOOTCOMMAND "run set_gpio122; run set_gpio96; sf probe; " \ + "run manage_userdata; " + +/* Enable PREBOOT variable */ +#define CONFIG_PREBOOT + +/* Set ARP_TIMEOUT to 500ms */ +#define CONFIG_ARP_TIMEOUT 500UL + +/* Set ARP_TIMEOUT_COUNT to 3 repetitions */ +#define CONFIG_NET_RETRY_COUNT 5
/* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */ -#define PCM052_NET_INIT "run set_gpio122; " +#define BK4_NET_INIT "run set_gpio122;" + +/* Check if userdata volume shall be erased */ +#define MANAGE_USERDATA "if ${eraseuserdata}; " \ + "then ubi part system; " \ + "ubi remove userdata; " \ + "ubi create userdata; " \ + "ubi detach; " \ + "setenv eraseuserdata false; " \ + "saveenv; " \ + "fi; " + +/* Autoboot options */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT \ + "Enter passphrase to stop autoboot, booting in %d seconds\n" +#define CONFIG_AUTOBOOT_STOP_STR "123" + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 4 * SZ_1M) + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* NAND support */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define IMX_FEC1_BASE ENET1_BASE_ADDR + +/* QSPI Configs*/ +#ifdef CONFIG_FSL_QSPI +#define FSL_QSPI_FLASH_SIZE (SZ_16M) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SYS_FSL_QSPI_LE +#endif + +#define CONFIG_LOADADDR 0x82000000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_BOARD_SIZE_LIMIT 520192 + +/* boot command, including the target-defined one if any */ +#define CONFIG_BOOTCOMMAND BK4_BOOTCOMMAND "run bootcmd_nand" + +/* Extra env settings (including the target-defined ones if any) */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BK4_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "blimg_file=u-boot.vyb\0" \ + "blimg_addr=0x81000000\0" \ + "dtbkernel_file=fitImage\0" \ + "dtbkernel_addr=0x82000000\0" \ + "ram_file=uRamdisk\0" \ + "ram_addr=0x83000000\0" \ + "filesys=rootfs.ubifs\0" \ + "sys_addr=0x81000000\0" \ + "nfs_root=/path/to/nfs/root\0" \ + "tftptimeout=1000\0" \ + "tftptimeoutcountmax=1000000\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "ipaddr=192.168.0.60\0" \ + "serverip=192.168.0.1\0" \ + "bootargs_base=setenv bootargs rw " \ + "console=ttyLP1,115200n8\0" \ + "bootargs_sd=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootargs_nand=setenv bootargs ${bootargs} " \ + "ubi.mtd=5 rootfstype=" \ + "ubifs root=ubi0:rootfs${active_workset}\0" \ + "bootargs_ram=setenv bootargs ${bootargs} " \ + "root=/dev/ram rw initrd=${ram_addr}\0" \ + "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ + "fatload mmc 0:2 ${dtbkernel_addr} ${dtbkernel_file}; " \ + "bootm ${dtbkernel_addr}\0" \ + "bootcmd_nand=sf probe;run bootargs_base bootargs_nand bootargs_mtd; " \ + "ubi part dtbkernel; " \ + "ubi readvol ${dtbkernel_addr} dtbkernel${active_workset}; " \ + "led 0 on; " \ + "bootm ${dtbkernel_addr}\0" \ + "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ + "nand read ${fdt_addr} dtb; " \ + "nand read ${kernel_addr} kernel; " \ + "nand read ${ram_addr} root; " \ + "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ + "update_bootloader_from_sd=if fatload mmc 0:2 ${blimg_addr} " \ + "${blimg_file}; " \ + "then sf probe; " \ + "mtdparts default; " \ + "nand erase.part bootloader; " \ + "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ + "update_bootloader_from_tftp=if tftp ${blimg_addr} "\ + "${tftpdir}${blimg_file}; "\ + "then sf probe; " \ + "mtdparts default; " \ + "nand erase.part bootloader; " \ + "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ + "update_dtbkernel_from_sd=if fatload mmc 0:2 ${dtbkernel_addr} " \ + "${dtbkernel_file}; " \ + "then sf probe; " \ + "ubi part dtbkernel; " \ + "ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \ + "${filesize}; " \ + "ubi detach; fi\0" \ + "update_dtbkernel_from_tftp=if tftp ${dtbkernel_addr} " \ + "${tftpdir}${dtbkernel_file}; " \ + "then sf probe; " \ + "ubi part dtbkernel; " \ + "ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \ + "${filesize}; " \ + "ubi detach; fi\0" \ + "update_ramdisk_from_sd=if fatload mmc 0:2 ${ram_addr} " \ + "${ram_file}; " \ + "then sf probe; " \ + "mtdparts default; " \ + "nand erase.part initrd; " \ + "nand write ${ram_addr} initrd ${filesize}; fi\0" \ + "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ + "then sf probe; " \ + "nand erase.part initrd; " \ + "nand write ${ram_addr} initrd ${filesize}; fi\0" \ + "update_rootfs_from_sd=if fatload mmc 0:2 ${sys_addr} " \ + "${filesys}; " \ + "then sf probe; " \ + "ubi part system; " \ + "ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \ + "ubi detach; fi\0" \ + "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \ + "then sf probe; " \ + "ubi part system; " \ + "ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \ + "ubi detach; fi\0" \ + "active_workset=1\0" + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_MEMTEST_START 0x80010000 +#define CONFIG_SYS_MEMTEST_END 0x87C00000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical memory map */ +#define PHYS_SDRAM (0x80000000) +#define PHYS_SDRAM_SIZE (SZ_512M) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-/* add NOR to MTD env */ +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* now include standard PCM052 config */ +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE (SZ_128K) +#define CONFIG_ENV_SIZE (SZ_8K) +#define CONFIG_ENV_OFFSET 0x200000 +#define CONFIG_ENV_SIZE_REDUND (SZ_8K) +#define CONFIG_ENV_OFFSET_REDUND 0x220000 +#endif
-#include "configs/pcm052.h" +#endif /* __CONFIG_H */
The BK4's config file has changed since its initial posting to main line. This commit reflects those changes. Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
This commit cleans up the pcm052.c file to remove dead code after moving to DTS and DM.
Signed-off-by: Lukasz Majewski lukma@denx.de ---
Changes in v4: None Changes in v3: None Changes in v2: None
board/phytec/pcm052/pcm052.c | 267 ------------------------------------------- 1 file changed, 267 deletions(-)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 95df0be6c1..4a18b0e0f4 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -13,79 +13,9 @@ #include <asm/arch/ddrmc-vf610.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> -#include <mmc.h> -#include <fsl_esdhc.h> -#include <miiphy.h> -#include <netdev.h> -#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
-/* - * Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h - * do not match our settings. Let us (re)define our own settings here. - */ - -#define PCM052_VF610_DDR_PAD_CTRL PAD_CTL_DSE_20ohm -#define PCM052_VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_20ohm | \ - PAD_CTL_INPUT_DIFFERENTIAL) -#define PCM052_VF610_DDR_RESET_PAD_CTL (PAD_CTL_DSE_150ohm | \ - PAD_CTL_PUS_100K_UP | \ - PAD_CTL_INPUT_DIFFERENTIAL) - -enum { - PCM052_VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL), - PCM052_VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), - PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), - PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), - PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 = IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), -}; - static struct ddrmc_cr_setting pcm052_cr_settings[] = { /* not in the datasheets, but in the original code */ { 0x00002000, 105 }, @@ -154,59 +84,6 @@ static struct ddrmc_phy_setting pcm052_phy_settings[] = {
int dram_init(void) { - static const iomux_v3_cfg_t pcm052_pads[] = { - PCM052_VF610_PAD_DDR_A15__DDR_A_15, - PCM052_VF610_PAD_DDR_A14__DDR_A_14, - PCM052_VF610_PAD_DDR_A13__DDR_A_13, - PCM052_VF610_PAD_DDR_A12__DDR_A_12, - PCM052_VF610_PAD_DDR_A11__DDR_A_11, - PCM052_VF610_PAD_DDR_A10__DDR_A_10, - PCM052_VF610_PAD_DDR_A9__DDR_A_9, - PCM052_VF610_PAD_DDR_A8__DDR_A_8, - PCM052_VF610_PAD_DDR_A7__DDR_A_7, - PCM052_VF610_PAD_DDR_A6__DDR_A_6, - PCM052_VF610_PAD_DDR_A5__DDR_A_5, - PCM052_VF610_PAD_DDR_A4__DDR_A_4, - PCM052_VF610_PAD_DDR_A3__DDR_A_3, - PCM052_VF610_PAD_DDR_A2__DDR_A_2, - PCM052_VF610_PAD_DDR_A1__DDR_A_1, - PCM052_VF610_PAD_DDR_A0__DDR_A_0, - PCM052_VF610_PAD_DDR_BA2__DDR_BA_2, - PCM052_VF610_PAD_DDR_BA1__DDR_BA_1, - PCM052_VF610_PAD_DDR_BA0__DDR_BA_0, - PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B, - PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0, - PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0, - PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0, - PCM052_VF610_PAD_DDR_D15__DDR_D_15, - PCM052_VF610_PAD_DDR_D14__DDR_D_14, - PCM052_VF610_PAD_DDR_D13__DDR_D_13, - PCM052_VF610_PAD_DDR_D12__DDR_D_12, - PCM052_VF610_PAD_DDR_D11__DDR_D_11, - PCM052_VF610_PAD_DDR_D10__DDR_D_10, - PCM052_VF610_PAD_DDR_D9__DDR_D_9, - PCM052_VF610_PAD_DDR_D8__DDR_D_8, - PCM052_VF610_PAD_DDR_D7__DDR_D_7, - PCM052_VF610_PAD_DDR_D6__DDR_D_6, - PCM052_VF610_PAD_DDR_D5__DDR_D_5, - PCM052_VF610_PAD_DDR_D4__DDR_D_4, - PCM052_VF610_PAD_DDR_D3__DDR_D_3, - PCM052_VF610_PAD_DDR_D2__DDR_D_2, - PCM052_VF610_PAD_DDR_D1__DDR_D_1, - PCM052_VF610_PAD_DDR_D0__DDR_D_0, - PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1, - PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0, - PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1, - PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0, - PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B, - PCM052_VF610_PAD_DDR_WE__DDR_WE_B, - PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0, - PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1, - PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1, - PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0, - PCM052_VF610_PAD_DDR_RESETB, - }; - #if defined(CONFIG_TARGET_PCM052)
static const struct ddr3_jedec_timings pcm052_ddr_timings = { @@ -323,8 +200,6 @@ int dram_init(void)
#endif
- imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); - ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, pcm052_phy_settings, 1, row_diff);
@@ -333,135 +208,6 @@ int dram_init(void) return 0; }
-static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart1_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) - -static void setup_iomux_enet(void) -{ - static const iomux_v3_cfg_t enet0_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); -} - -/* - * I2C2 is the only I2C used, on pads PTA22/PTA23. - */ - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c_pads[] = { - VF610_PAD_PTA22__I2C2_SCL, - VF610_PAD_PTA23__I2C2_SDA, - }; - - imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); -} - -#ifdef CONFIG_NAND_VF610_NFC -static void setup_iomux_nfc(void) -{ - static const iomux_v3_cfg_t nfc_pads[] = { - VF610_PAD_PTD31__NF_IO15, - VF610_PAD_PTD30__NF_IO14, - VF610_PAD_PTD29__NF_IO13, - VF610_PAD_PTD28__NF_IO12, - VF610_PAD_PTD27__NF_IO11, - VF610_PAD_PTD26__NF_IO10, - VF610_PAD_PTD25__NF_IO9, - VF610_PAD_PTD24__NF_IO8, - VF610_PAD_PTD23__NF_IO7, - VF610_PAD_PTD22__NF_IO6, - VF610_PAD_PTD21__NF_IO5, - VF610_PAD_PTD20__NF_IO4, - VF610_PAD_PTD19__NF_IO3, - VF610_PAD_PTD18__NF_IO2, - VF610_PAD_PTD17__NF_IO1, - VF610_PAD_PTD16__NF_IO0, - VF610_PAD_PTB24__NF_WE_B, - VF610_PAD_PTB25__NF_CE0_B, - VF610_PAD_PTB27__NF_RE_B, - VF610_PAD_PTC26__NF_RB_B, - VF610_PAD_PTC27__NF_ALE, - VF610_PAD_PTC28__NF_CLE - }; - - imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); -} -#endif - -static void setup_iomux_qspi(void) -{ - static const iomux_v3_cfg_t qspi0_pads[] = { - VF610_PAD_PTD0__QSPI0_A_QSCK, - VF610_PAD_PTD1__QSPI0_A_CS0, - VF610_PAD_PTD2__QSPI0_A_DATA3, - VF610_PAD_PTD3__QSPI0_A_DATA2, - VF610_PAD_PTD4__QSPI0_A_DATA1, - VF610_PAD_PTD5__QSPI0_A_DATA0, - VF610_PAD_PTD7__QSPI0_B_QSCK, - VF610_PAD_PTD8__QSPI0_B_CS0, - VF610_PAD_PTD9__QSPI0_B_DATA3, - VF610_PAD_PTD10__QSPI0_B_DATA2, - VF610_PAD_PTD11__QSPI0_B_DATA1, - VF610_PAD_PTD12__QSPI0_B_DATA0, - }; - - imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); -} - -#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) - -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {ESDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* eSDHC1 is always present */ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t esdhc1_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), - }; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - imx_iomux_v3_setup_multiple_pads( - esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} - static void clock_init(void) { struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; @@ -534,23 +280,10 @@ static void mscm_init(void) writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); }
-int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - int board_early_init_f(void) { clock_init(); mscm_init(); - setup_iomux_uart(); - setup_iomux_enet(); - setup_iomux_i2c(); - setup_iomux_qspi(); - setup_iomux_nfc();
return 0; }
This commit cleans up the pcm052.c file to remove dead code after moving to DTS and DM. Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
Signed-off-by: Lukasz Majewski lukma@denx.de ---
Changes in v4: None Changes in v3: None Changes in v2: None
include/configs/bk4r1.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index bbd3e4e636..7bd3411ff2 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -189,6 +189,37 @@ "ubi part system; " \ "ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \ "ubi detach; fi\0" \ + "setup_dtbkernel=nand erase.part dtbkernel; " \ + "ubi part dtbkernel; " \ + "ubi create dtbkernel1 972000 s; " \ + "ubi create dtbkernel2 972000 s; " \ + "ubi detach\0" \ + "setup_system=nand erase.part system; " \ + "ubi part system; " \ + "ubi create rootfs1 15E15000 d; " \ + "ubi create rootfs2 15E15000 d; " \ + "ubi create userdata; " \ + "ubi detach\0" \ + "prepare_install_bk4r1_envs=" \ + "echo 'Preparing envs for SD card recovery!';" \ + "setenv ipaddr 192.168.0.99;" \ + "setenv serverip 192.168.0.50;" \ + "\0" \ + "install_bk4r1rs="\ + "led 0 on; " \ + "nand erase.chip; mtdparts default; "\ + "led 1 on; "\ + "run setup_dtbkernel; " \ + "run setup_system; " \ + "led 2 on;" \ + "run update_bootloader_from_sd; "\ + "run update_dtbkernel_from_sd; "\ + "run update_rootfs_from_sd; "\ + "setenv bootcmd 'run bootcmd_nand'; "\ + "saveenv; " \ + "led 3 on; " \ + "echo Finished - Please Power off, REMOVE SDCARD and set boot" \ + "source to NAND\0" \ "active_workset=1\0"
/* Miscellaneous configurable options */
Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
Signed-off-by: Lukasz Majewski lukma@denx.de ---
Changes in v4: None Changes in v3: None Changes in v2: None
include/configs/bk4r1.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index 7bd3411ff2..05ebb7d9c5 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -200,6 +200,24 @@ "ubi create rootfs2 15E15000 d; " \ "ubi create userdata; " \ "ubi detach\0" \ + "setup_nor1=" BK4_NET_INIT \ + "if tftp ${sys_addr} ${tftpdir}ubinor1.img; " \ + "then sf probe 0:0; " \ + "sf erase 0 01000000; " \ + "mtdparts default; " \ + "ubi part nor; " \ + "ubi create nor1fs; " \ + "ubi write ${sys_addr} nor1fs ${filesize}; " \ + "ubi detach; fi\0" \ + "setup_nor2=" BK4_NET_INIT \ + "if tftp ${sys_addr} ${tftpdir}ubinor2.img; " \ + "then sf probe 0:1; " \ + "sf erase 0 01000000; " \ + "mtdparts default; " \ + "ubi part nor; " \ + "ubi create nor2fs; " \ + "ubi write ${sys_addr} nor2fs ${filesize}; " \ + "ubi detach; fi\0" \ "prepare_install_bk4r1_envs=" \ "echo 'Preparing envs for SD card recovery!';" \ "setenv ipaddr 192.168.0.99;" \
Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
This code allows reusing the default u-boot as in the late board init, the default envs are restored and proper recovery scripts executed.
Signed-off-by: Lukasz Majewski lukma@denx.de ---
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/cpu/armv7/vf610/Kconfig | 1 + arch/arm/include/asm/arch-vf610/imx-regs.h | 2 ++ board/phytec/pcm052/pcm052.c | 32 ++++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+)
diff --git a/arch/arm/cpu/armv7/vf610/Kconfig b/arch/arm/cpu/armv7/vf610/Kconfig index 13905b5281..5d485a3ce2 100644 --- a/arch/arm/cpu/armv7/vf610/Kconfig +++ b/arch/arm/cpu/armv7/vf610/Kconfig @@ -23,6 +23,7 @@ config TARGET_BK4R1 bool "BK4r1" select SYS_FSL_ERRATUM_ESDHC135 select SYS_FSL_ERRATUM_ESDHC_A001 + select BOARD_LATE_INIT
endchoice
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 5d1f63c98b..ae0a187c4d 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -289,6 +289,8 @@ #define SRC_SRSR_WDOG_M4 (0x1 << 4) #define SRC_SRSR_WDOG_A5 (0x1 << 3) #define SRC_SRSR_POR_RST (0x1 << 0) +#define SRC_SBMR1_BOOTCFG1_SDMMC BIT(6) +#define SRC_SBMR1_BOOTCFG1_MMC BIT(4) #define SRC_SBMR2_BMOD_MASK (0x3 << 24) #define SRC_SBMR2_BMOD_SHIFT 24 #define SRC_SBMR2_BMOD_FUSES 0x0 diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 4a18b0e0f4..d4f170a503 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -13,6 +13,7 @@ #include <asm/arch/ddrmc-vf610.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> +#include <environment.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -307,6 +308,37 @@ int board_init(void) return 0; }
+#ifdef CONFIG_TARGET_BK4R1 +int board_late_init(void) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + u32 reg; + + /* + * BK4r1 handle emergency/service SD card boot + * Checking the SBMR1 register BOOTCFG1 byte: + * NAND: + * bit [2] - NAND data width - 16 + * bit [5] - NAND fast boot + * bit [7] = 1 - NAND as a source of booting + * SD card (0x64): + * bit [4] = 0 - SD card source + * bit [6] = 1 - SD/MMC source + */ + + reg = readl(&psrc->sbmr1); + if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) && + !(reg & SRC_SBMR1_BOOTCFG1_MMC)) { + printf("------ SD card boot -------\n"); + set_default_env("!LVFBootloader", 0); + env_set("bootcmd", + "run prepare_install_bk4r1_envs; run install_bk4r1rs"); + } + + return 0; +} +#endif /* CONFIG_TARGET_BK4R1 */ + int checkboard(void) { #ifdef CONFIG_TARGET_BK4R1
This code allows reusing the default u-boot as in the late board init, the default envs are restored and proper recovery scripts executed. Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
As one has moved to DM based LEDs, this code is required to setup the default state.
Signed-off-by: Lukasz Majewski lukma@denx.de ---
Changes in v4: None Changes in v3: None Changes in v2: None
board/phytec/pcm052/pcm052.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index d4f170a503..721e25105a 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -13,6 +13,7 @@ #include <asm/arch/ddrmc-vf610.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> +#include <led.h> #include <environment.h>
DECLARE_GLOBAL_DATA_PTR; @@ -314,6 +315,9 @@ int board_late_init(void) struct src *psrc = (struct src *)SRC_BASE_ADDR; u32 reg;
+ if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + /* * BK4r1 handle emergency/service SD card boot * Checking the SBMR1 register BOOTCFG1 byte:
As one has moved to DM based LEDs, this code is required to setup the default state. Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
This commit introduces the board specific function to read fused mac address.
Signed-off-by: Lukasz Majewski lukma@denx.de ---
Changes in v4: None Changes in v3: None Changes in v2: None
board/phytec/pcm052/pcm052.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 721e25105a..1e443a5850 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -310,6 +310,47 @@ int board_init(void) }
#ifdef CONFIG_TARGET_BK4R1 +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[4]; + struct fuse_bank4_regs *fuse = + (struct fuse_bank4_regs *)bank->fuse_regs; + u32 value; + + /* + * BK4 has different layout of stored MAC address + * than one used in imx_get_mac_from_fuse() @ generic.c + */ + + switch (dev_id) { + case 0: + value = readl(&fuse->mac_addr1); + + mac[0] = value >> 8; + mac[1] = value; + + value = readl(&fuse->mac_addr0); + mac[2] = value >> 24; + mac[3] = value >> 16; + mac[4] = value >> 8; + mac[5] = value; + break; + case 1: + value = readl(&fuse->mac_addr2); + + mac[0] = value >> 24; + mac[1] = value >> 16; + mac[2] = value >> 8; + mac[3] = value; + + value = readl(&fuse->mac_addr1); + mac[4] = value >> 24; + mac[5] = value >> 16; + break; + } +} + int board_late_init(void) { struct src *psrc = (struct src *)SRC_BASE_ADDR;
This commit introduces the board specific function to read fused mac address. Signed-off-by: Lukasz Majewski lukma@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
BK4 requires setup of 50MHz reference clock for its KSZ8081 PHY devices.
Signed-off-by: Lukasz Majewski lukma@denx.de
---
Changes in v4: None Changes in v3: None Changes in v2: None
board/phytec/pcm052/pcm052.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 1e443a5850..c30df5df9d 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -15,6 +15,7 @@ #include <asm/arch/clock.h> #include <led.h> #include <environment.h> +#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -382,6 +383,21 @@ int board_late_init(void)
return 0; } + +/** + * KSZ8081 + */ +#define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f +#define RMII_50MHz_CLOCK 0x8180 + +int board_phy_config(struct phy_device *phydev) +{ + /* Set 50 MHz reference clock */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT, + RMII_50MHz_CLOCK); + + return genphy_config(phydev); +} #endif /* CONFIG_TARGET_BK4R1 */
int checkboard(void)
On Wed, Feb 13, 2019 at 3:51 PM Lukasz Majewski lukma@denx.de wrote:
BK4 requires setup of 50MHz reference clock for its KSZ8081 PHY devices.
Signed-off-by: Lukasz Majewski lukma@denx.de
Acked-by: Joe Hershberger joe.hershberger@ni.com
Changes in v4: None Changes in v3: None Changes in v2: None
board/phytec/pcm052/pcm052.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 1e443a5850..c30df5df9d 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -15,6 +15,7 @@ #include <asm/arch/clock.h> #include <led.h> #include <environment.h> +#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -382,6 +383,21 @@ int board_late_init(void)
return 0;}
+/**
- KSZ8081
- */
+#define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f +#define RMII_50MHz_CLOCK 0x8180
+int board_phy_config(struct phy_device *phydev) +{
/* Set 50 MHz reference clock */phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,RMII_50MHz_CLOCK);
Is it reasonable to use the clock infrastructure? Not necessarily instead of fixing this now, but would be a good direction.
return genphy_config(phydev);+} #endif /* CONFIG_TARGET_BK4R1 */
int checkboard(void)
2.11.0
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Hi Joe,
On Wed, Feb 13, 2019 at 3:51 PM Lukasz Majewski lukma@denx.de wrote:
BK4 requires setup of 50MHz reference clock for its KSZ8081 PHY devices.
Signed-off-by: Lukasz Majewski lukma@denx.de
Acked-by: Joe Hershberger joe.hershberger@ni.com
Changes in v4: None Changes in v3: None Changes in v2: None
board/phytec/pcm052/pcm052.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 1e443a5850..c30df5df9d 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -15,6 +15,7 @@ #include <asm/arch/clock.h> #include <led.h> #include <environment.h> +#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -382,6 +383,21 @@ int board_late_init(void)
return 0;}
+/**
- KSZ8081
- */
+#define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f +#define RMII_50MHz_CLOCK 0x8180
+int board_phy_config(struct phy_device *phydev) +{
/* Set 50 MHz reference clock */phy_write(phydev, MDIO_DEVAD_NONE,MII_KSZ8081_REFERENCE_CLOCK_SELECT,
RMII_50MHz_CLOCK);Is it reasonable to use the clock infrastructure?
Yes, I do have in the back of my head that this shall be done via clock API. However, it is a long way to and I would like first to have the DM/DTS cleanup patches in main line.
Not necessarily instead of fixing this now, but would be a good direction.
return genphy_config(phydev);+} #endif /* CONFIG_TARGET_BK4R1 */
int checkboard(void)
2.11.0
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
BK4 requires setup of 50MHz reference clock for its KSZ8081 PHY devices. Signed-off-by: Lukasz Majewski lukma@denx.de Acked-by: Joe Hershberger joe.hershberger@ni.com
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
participants (3)
-
Joe Hershberger -
Lukasz Majewski -
sbabic＠denx.de