Manorit Chawdhry m-chawdhry@ti.com writes:

From: Pratyush Yadav p.yadav@ti.com

On DTR capable flashes like Micron Xcella the writes cannot start or end at an odd address in DTR mode. Extra 0xff bytes need to be prepended or appended respectively to make sure both the start and end addresses are even.

Signed-off-by: Pratyush Yadav p.yadav@ti.com Reviewed-by: Vignesh Raghavendra vigneshr@ti.com Signed-off-by: Apurva Nandan a-nandan@ti.com Signed-off-by: Vignesh Raghavendra vigneshr@ti.com Signed-off-by: Manorit Chawdhry m-chawdhry@ti.com

---

drivers/mtd/spi/spi-nor-core.c | 59 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 55 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f86003ca8c06..2b000151c97d 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1805,11 +1805,62 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, if (ret < 0) return ret; #endif

• write_enable(nor);

• ret = nor->write(nor, addr, page_remain, buf + i);
  

• if (ret < 0)
  

• 	goto write_err;
  

• written = ret;
  

• /*
  

•  * On DTR capable flashes like Micron Xcella the writes cannot
  

•  * start or end at an odd address in DTR mode. So we need to
  

•  * append or prepend extra 0xff bytes to make sure the start
  

•  * address and end address are even.
  

•  */
  

• if (spi_nor_protocol_is_dtr(nor->write_proto) &&
  

•     ((addr | page_remain) & 1)) {
  

• 	u_char *tmp;
  

• 	size_t extra_bytes = 0;
  

• 	tmp = kmalloc(nor->page_size, 0);
  

• 	if (!tmp) {
  

• 		ret = -ENOMEM;
  

• 		goto write_err;
  

• 	}
  

• 	/* Prepend a 0xff byte if the start address is odd. */
  

• 	if (addr & 1) {
  

• 		tmp[0] = 0xff;
  

• 		memcpy(tmp + 1, buf + i, page_remain);
  

• 		addr--;
  

• 		page_remain++;
  

• 		extra_bytes++;
  

• 	} else {
  

• 		memcpy(tmp, buf + i, page_remain);
  

• 	}
  

• 	/* Append a 0xff byte if the end address is odd. */
  

• 	if ((addr + page_remain) & 1) {
  

• 		tmp[page_remain + extra_bytes] = 0xff;
  

• 		extra_bytes++;
  

• 		page_remain++;
  

• 	}
  

• 	ret = nor->write(nor, addr, page_remain, tmp);
  

• 	kfree(tmp);
  

• 	if (ret < 0)
  

• 		goto write_err;
  

• 	/*
  

• 	 * We write extra bytes but they are not part of the
  

• 	 * original write.
  

• 	 */
  

• 	written = ret - extra_bytes;
  

• } else {
  

• 	ret = nor->write(nor, addr, page_remain, buf + i);
  

• 	if (ret < 0)
  

• 		goto write_err;
  

• 	written = ret;
  

• }
  
  

  ret = spi_nor_wait_till_ready(nor); if (ret)

-- 2.43.2

Thanks for upstreaming!

Tested-by: Jonathan Humphreys j-humphreys@ti.com

On 01/04/24 11:16, Manorit Chawdhry wrote:

R5 being a 32-bit processor can't understand the 64-bit mapping being done in ospi node. Override the ospi node for 32-bit register ranges and the fss node ( the parent node of ospi ) to map the ranges for the updated child node correctly.

Signed-off-by: Manorit Chawdhry m-chawdhry@ti.com

arch/arm/dts/k3-j721s2-r5-common-proc-board.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+)

diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts index 03bd680f4421..5c4b34915ccf 100644 --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts @@ -86,3 +86,16 @@ &mcu_udmap { ti,sci = <&dm_tifs>; };

+&ospi0 {

• reg = <0x0 0x47040000 0x0 0x100>,
  

• 	  <0x0 0x50000000 0x0 0x8000000>;
  

+};

+&fss {

• /* fss node has 64 bit address regions mapped to it and since the ospi

• * nodes is being override, override the fss node ranges as well
  

• */
  

• ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,

• 	 <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
  

+};

Reviewed-by: Apurva Nandan a-nandan@ti.com

On 01/04/24 11:16, Manorit Chawdhry wrote:

Enable ospi0 node for all boot stages

Signed-off-by: Manorit Chawdhry m-chawdhry@ti.com

arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index a3ebf5996eac..132cd5a456ba 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -110,7 +110,9 @@ };

&ospi0 {

• status = "disabled";

• flash@0 {

• bootph-all;
  

• }; };

  &ospi1 {

Reviewed-by: Apurva Nandan a-nandan@ti.com

On 01/04/24 11:16, Manorit Chawdhry wrote:

Enable OSPI related configs to boot using OSPI

Signed-off-by: Manorit Chawdhry m-chawdhry@ti.com

configs/j721s2_evm_a72_defconfig | 3 +++ configs/j721s2_evm_r5_defconfig | 3 +++ 2 files changed, 6 insertions(+)

diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 92f69413fa40..6e7e161fa359 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -50,6 +50,7 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD=y +CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y @@ -58,6 +59,8 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_THERMAL=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index cb6b4a44864f..197b3284c12d 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -57,6 +57,7 @@ CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_MTD=y +CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y @@ -66,6 +67,8 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_THERMAL=y

Reviewed-by: Apurva Nandan a-nandan@ti.com