[U-Boot] Enabling L2 cache on mx53
Hi,
I notice slow tftp transfer on mx53qsb and I suspected it could be due to L2 cache being disabled.
Tried enabling with:
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,11 @@ #endif
mcr 15, 1, r0, c9, c0, 2 + + /* enable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #(1 << 1) /* enable l2 cache */ + mcr 15, 0, r0, c1, c0, 1 .endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
,but still see the same low tftp throughput (720 kB/s - on mx28 I see the double rate).
Any suggestions as to how properly enable L2 cache on mx53?
Thanks,
Fabio Estevam
Am 19.08.2013 15:55, schrieb Fabio Estevam:
Hi,
I notice slow tftp transfer on mx53qsb and I suspected it could be due to L2 cache being disabled.
Tried enabling with:
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,11 @@ #endif
mcr 15, 1, r0, c9, c0, 2
/* enable L2 cache */mrc 15, 0, r0, c1, c0, 1orr r0, r0, #(1 << 1) /* enable l2 cache */mcr 15, 0, r0, c1, c0, 1.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
,but still see the same low tftp throughput (720 kB/s - on mx28 I see the double rate).
Any suggestions as to how properly enable L2 cache on mx53?
Is the mx53 L2 cache the same like on mx6?
If so, besides enabling it, it needs a proper configuration. Have a look to
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=5...
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=b...
Best regards
Dirk
Hi Dirk,
On Mon, Aug 19, 2013 at 12:16 PM, Dirk Behme dirk.behme@gmail.com wrote:
Is the mx53 L2 cache the same like on mx6?
I think they are different.
On mx6 the L2 cache controller is memory mapped ,but on mx53 there is no L2 cache entry in its memory map.
Regards,
Fabio Estevam
Dear Fabio Estevam,
Hi Dirk,
On Mon, Aug 19, 2013 at 12:16 PM, Dirk Behme dirk.behme@gmail.com wrote:
Is the mx53 L2 cache the same like on mx6?
I think they are different.
On mx6 the L2 cache controller is memory mapped ,but on mx53 there is no L2 cache entry in its memory map.
Regards,
Fabio Estevam
L2CC on MX53 is enabled by setting just the L2ON and C bits in CP15, there's no configuration. Not even Linux enables the L2CC on MX53, so if it's not on in U- Boot, then it's not on at all (and that sucks).
Best regards, Marek Vasut
Hi Marek,
On Mon, Aug 19, 2013 at 4:51 PM, Marek Vasut marex@denx.de wrote:
L2CC on MX53 is enabled by setting just the L2ON and C bits in CP15, there's no configuration. Not even Linux enables the L2CC on MX53, so if it's not on in U- Boot, then it's not on at all (and that sucks).
This is what I have done:
--- a/arch/arm/cpu/armv7/mx5/ lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,11 @@ #endif
mcr 15, 1, r0, c9, c0, 2 + + /* enable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #(1 << 1) /* enable l2 cache */ + mcr 15, 0, r0, c1, c0, 1 .endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
Anything else I am missing?
Dear Fabio Estevam,
Hi Marek,
On Mon, Aug 19, 2013 at 4:51 PM, Marek Vasut marex@denx.de wrote:
L2CC on MX53 is enabled by setting just the L2ON and C bits in CP15, there's no configuration. Not even Linux enables the L2CC on MX53, so if it's not on in U- Boot, then it's not on at all (and that sucks).
This is what I have done:
--- a/arch/arm/cpu/armv7/mx5/ lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,11 @@ #endif
mcr 15, 1, r0, c9, c0, 2
/* enable L2 cache */mrc 15, 0, r0, c1, c0, 1orr r0, r0, #(1 << 1) /* enable l2 cache */mcr 15, 0, r0, c1, c0, 1.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
Anything else I am missing?
Try profiling the RX routine, maybe it's looping somewhere there for too long.
Best regards, Marek Vasut
Hi Marek,
On 19/08/2013 22:31, Marek Vasut wrote:
Dear Fabio Estevam,
Hi Marek,
On Mon, Aug 19, 2013 at 4:51 PM, Marek Vasut marex@denx.de wrote:
L2CC on MX53 is enabled by setting just the L2ON and C bits in CP15, there's no configuration. Not even Linux enables the L2CC on MX53, so if it's not on in U- Boot, then it's not on at all (and that sucks).
This is what I have done:
--- a/arch/arm/cpu/armv7/mx5/ lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,11 @@ #endif
mcr 15, 1, r0, c9, c0, 2
/* enable L2 cache */mrc 15, 0, r0, c1, c0, 1orr r0, r0, #(1 << 1) /* enable l2 cache */mcr 15, 0, r0, c1, c0, 1.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
Anything else I am missing?
Try profiling the RX routine, maybe it's looping somewhere there for too long.
But the RX routine belongs to the FEC driver that it is used by all i.MXes. Is there maybe a problem with the phy and the negotiated speed is less than expected ?
Best regards, Stefano Babic
participants (4)
-
Dirk Behme -
Fabio Estevam -
Marek Vasut -
Stefano Babic