BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller.

Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar.

Signed-off-by: Manish Jaggi manish.jaggi@freescale.com Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com --- Changes for v2: Added Manish's email-id

arch/powerpc/include/asm/immap_85xx.h | 6 ++++++ board/freescale/bsc9132qds/bsc9132qds.c | 22 ++++++++++++++++++++++ 2 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index db70d04..ae9a016 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -3047,6 +3047,12 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000

+#if defined(CONFIG_BSC9132) +#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 +#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ + (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) +#endif + #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) #define CONFIG_SYS_FSL_QMAN_ADDR \ diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index ddc9d0a..b084c1b 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -141,6 +141,27 @@ void board_config_serdes_mux(void) } }

+/* Configure DSP DDR controller */ +void dsp_ddr_configure(void) +{ + /* + *There are separate DDR-controllers for DSP and PowerPC side DDR. + *copy the ddr controller settings from PowerPC side DDR controller + *to the DSP DDR controller as connected DDR memories are similar. + */ + ccsr_ddr_t __iomem *pa_ddr = + (ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ccsr_ddr_t temp_ddr; + ccsr_ddr_t __iomem *dsp_ddr = + (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; + + memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t)); + temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS; + temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN; + memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t)); + dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN; +} + int board_early_init_r(void) { #ifndef CONFIG_SYS_NO_FLASH @@ -169,6 +190,7 @@ int board_early_init_r(void) 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); #endif board_config_serdes_mux(); + dsp_ddr_configure(); return 0; }