-- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli@arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ======================================================================== Index: README =================================================================== RCS file: /home/CVS/u-boot/u-boot/README,v retrieving revision 1.1.1.4 diff -p -u -r1.1.1.4 README --- README 16 Jul 2003 11:23:40 -0000 1.1.1.4 +++ README 16 Jul 2003 13:12:52 -0000 @@ -197,7 +197,7 @@ Directory Hierarchy: - board/lwmon Files specific to LWMON boards - board/mbx8xx Files specific to MBX boards - board/mpc8260ads - Files specific to MMPC8260ADS boards + Files specific to MPC8260ADS and PQ2FADS-ZU boards - board/mpl/ Files specific to boards manufactured by MPL - board/mpl/common Common files for MPL boards - board/mpl/pip405 Files specific to PIP405 boards @@ -383,6 +383,14 @@ The following options need to be configu the lcd display every second with a "rotator" |-/|-/ +- Board flavour: (if CONFIG_MPC8260ADS is defined) + CONFIG_ADSTYPE + + Possible values are: + CFG_8260ADS - original MPC8260ADS + CFG_8266ADS - MPC8266ADS (untested) + CFG_PQ2FADS - PQ2FADS-ZU + - MPC824X Family Member (if CONFIG_MPC824X is defined) Define exactly one of CONFIG_MPC8240, CONFIG_MPC8245 @@ -1687,9 +1695,9 @@ Low Level (hardware related) configurati - CFG_DEFAULT_IMMR: Default address of the IMMR after system reset. - Needed on some 8260 systems (MPC8260ADS and RPXsuper) - to be able to adjust the position of the IMMR - register after a reset. + Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU, + and RPXsuper) to be able to adjust the position of + the IMMR register after a reset. - Floppy Disk Support: CFG_FDC_DRIVE_NUMBER @@ -1862,7 +1870,7 @@ configurations; the following names are GENIETV_config TQM823L_config PIP405_config GEN860T_config EBONY_config FPS860L_config ELPT860_config cmi_mpc5xx_config NETVIA_config - at91rm9200dk_config omap1510inn_config + at91rm9200dk_config omap1510inn_config MPC8260ADS_config Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for Index: board/mpc8260ads/mpc8260ads.c =================================================================== RCS file: /home/CVS/u-boot/u-boot/board/mpc8260ads/mpc8260ads.c,v retrieving revision 1.1.1.4 retrieving revision 1.7 diff -p -u -r1.1.1.4 -r1.7 --- board/mpc8260ads/mpc8260ads.c 16 Jul 2003 11:23:42 -0000 1.1.1.4 +++ board/mpc8260ads/mpc8260ads.c 16 Jul 2003 12:24:41 -0000 1.7 @@ -198,11 +198,19 @@ void reset_phy (void) vu_long *bcsr = (vu_long *)CFG_BCSR; /* reset the FEC port */ - bcsr[1] &= ~FETH_RST; + bcsr[1] &= ~FETH1_RST; udelay(2); - bcsr[1] |= FETH_RST; + bcsr[1] |= FETH1_RST; udelay(1000); #ifdef CONFIG_MII +#if CONFIG_ADSTYPE == CFG_PQ2FADS + /* + * Do not bypass Rx/Tx (de)scrambler (fix configuration error) + * Enable autonegotiation. + */ + miiphy_write(0, 16, 0x610); + miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#else /* * Ethernet PHY is configured (by means of configuration pins) * to work at 10Mb/s only. We reconfigure it using MII @@ -212,6 +220,7 @@ void reset_phy (void) miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */ miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */ miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ #endif /* CONFIG_MII */ } @@ -219,7 +228,7 @@ int board_pre_init (void) { vu_long *bcsr = (vu_long *)CFG_BCSR; - bcsr[1] = ~FETHIEN & ~RS232EN_1; + bcsr[1] = ~FETHIEN1 & ~RS232EN_1; return 0; } @@ -231,12 +240,10 @@ long int initdram (int board_type) volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar *ramaddr, c = 0xff; - - /* Initialisation is for 16MB DIMM the board is shipped with */ - long int msize = 16; - uint or = 0xFF000CA0; - uint psdmr = CFG_PSDMR; - uint psrt = CFG_PSRT; + long int msize; + uint or; + uint psdmr; + uint psrt; int i; @@ -246,22 +253,29 @@ long int initdram (int board_type) immap->im_siu_conf.sc_tescr1 = 0x00004000; memctl->memc_mptpr = CFG_MPTPR; - /* init local sdram, bank 4 */ - memctl->memc_lsrt = 0x00000010; +#ifdef CFG_LSDRAM_BASE + /* Init local bus SDRAM */ + memctl->memc_lsrt = CFG_LSRT; +#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */ + memctl->memc_or3 = 0xFF803280; + memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861; +#else /* CS4 */ memctl->memc_or4 = 0xFFC01480; - memctl->memc_br4 = 0x04001861; - memctl->memc_lsdmr = 0x2886A522; + memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ + memctl->memc_lsdmr = CFG_LSDMR | 0x28000000; ramaddr = (uchar *) CFG_LSDRAM_BASE; *ramaddr = c; - memctl->memc_lsdmr = 0x0886A522; + memctl->memc_lsdmr = CFG_LSDMR | 0x08000000; for (i = 0; i < 8; i++) { *ramaddr = c; } - memctl->memc_lsdmr = 0x1886A522; + memctl->memc_lsdmr = CFG_LSDMR | 0x18000000; *ramaddr = c; - memctl->memc_lsdmr = 0x4086A522; + memctl->memc_lsdmr = CFG_LSDMR | 0x40000000; +#endif /* CFG_LSDRAM_BASE */ - /* init sdram dimm */ + /* Init 60x bus SDRAM */ #ifdef CONFIG_SPD_EEPROM { spd_eeprom_t spd; @@ -398,6 +412,16 @@ long int initdram (int board_type) printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt); #endif /* SPD_DEBUG */ } +#else /* !CONFIG_SPD_EEPROM */ +#if CONFIG_ADSTYPE == CFG_PQ2FADS + msize = 32; + or = 0xFE002EC0; +#else + msize = 16; + or = 0xFF000CA0; +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ + psdmr = CFG_PSDMR; + psrt = CFG_PSRT; #endif /* CONFIG_SPD_EEPROM */ memctl->memc_psrt = psrt; memctl->memc_or2 = or; @@ -415,12 +439,20 @@ long int initdram (int board_type) *ramaddr = c; #endif - /* return total ram size of DIMM */ + /* return total 60x bus SDRAM size */ return (msize * 1024 * 1024); } int checkboard (void) { +#if CONFIG_ADSTYPE == CFG_8260ADS puts ("Board: Motorola MPC8260ADS\n"); +#elif CONFIG_ADSTYPE == CFG_8266ADS + puts ("Board: Motorola MPC8266ADS\n"); +#elif CONFIG_ADSTYPE == CFG_PQ2FADS + puts ("Board: Motorola PQ2FADS-ZU\n"); +#else + puts ("Board: unknown\n"); +#endif return 0; } Index: include/configs/MPC8260ADS.h =================================================================== RCS file: /home/CVS/u-boot/u-boot/include/configs/MPC8260ADS.h,v retrieving revision 1.1.1.4 retrieving revision 1.9 diff -p -u -r1.1.1.4 -r1.9 --- include/configs/MPC8260ADS.h 16 Jul 2003 11:23:52 -0000 1.1.1.4 +++ include/configs/MPC8260ADS.h 14 Jul 2003 17:15:25 -0000 1.9 @@ -9,7 +9,8 @@ * * (C) Copyright 2003 Arabella Software Ltd. * Yuli Barcohen yuli@arabellasw.com - * Added support for SDRAM DIMMs SPD EEPROM, MII. + * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2. + * Ported to PQ2FADS-ZU board. * * See file CREDITS for list of people who contributed to this * project. @@ -41,6 +42,15 @@ #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */ +/* ADS flavours */ +#define CFG_8260ADS 1 /* MPC8260ADS */ +#define CFG_8266ADS 2 /* MPC8266ADS */ +#define CFG_PQ2FADS 3 /* PQ2FADS-ZU */ + +#ifndef CONFIG_ADSTYPE +#define CONFIG_ADSTYPE CFG_8260ADS +#endif /* CONFIG_ADSTYPE */ + #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ /* allow serial and ethaddr to be overwritten */ @@ -116,7 +126,9 @@ #endif /* CONFIG_ETHER_ON_FCC */ -/* other options */ +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#undef CONFIG_SPD_EEPROM /* On PQ2FADS-ZU, SDRAM is soldered */ +#else #define CONFIG_HARD_I2C 1 /* To enable I2C support */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -124,18 +136,23 @@ #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) #define CONFIG_SPD_ADDR 0x50 #endif +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ #ifndef CONFIG_SDRAM_PBI #define CONFIG_SDRAM_PBI 1 /* By default, use page-based interleaving */ #endif #ifndef CONFIG_8260_CLKIN +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#define CONFIG_8260_CLKIN 100000000 /* in Hz */ +#else #define CONFIG_8260_CLKIN 66666666 /* in Hz */ #endif +#endif + #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_BEDBUG | \ +#define CFG_EXCLUDE CFG_CMD_BEDBUG | \ CFG_CMD_BMP | \ CFG_CMD_BSP | \ CFG_CMD_DATE | \ @@ -143,11 +160,11 @@ CFG_CMD_DTT | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ + CFG_CMD_FAT | \ CFG_CMD_FDC | \ CFG_CMD_FDOS | \ CFG_CMD_HWFLOW | \ CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ CFG_CMD_KGDB | \ CFG_CMD_MMC | \ CFG_CMD_NAND | \ @@ -155,8 +172,18 @@ CFG_CMD_PCMCIA | \ CFG_CMD_SCSI | \ CFG_CMD_SPI | \ - CFG_CMD_VFD | \ - CFG_CMD_USB ) ) + CFG_CMD_USB | \ + CFG_CMD_VFD + +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_SDRAM | \ + CFG_CMD_I2C | \ + CFG_EXCLUDE ) ) +#else +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_EXCLUDE ) ) +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -200,7 +227,6 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CFG_FLASH_BASE 0xff800000 -#define FLASH_BASE 0xff800000 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ #define CFG_FLASH_SIZE 8 @@ -219,14 +245,16 @@ #define CFG_DEFAULT_IMMR 0x0F010000 #define CFG_IMMR 0xF0000000 -#define CFG_BCSR 0x04500000 +#define CFG_BCSR 0xF4500000 #define CFG_SDRAM_BASE 0x00000000 -#define CFG_LSDRAM_BASE 0x04000000 +#define CFG_LSDRAM_BASE 0xD0000000 #define RS232EN_1 0x02000002 #define RS232EN_2 0x01000001 -#define FETHIEN 0x08000008 -#define FETH_RST 0x04000004 +#define FETHIEN1 0x08000008 +#define FETH1_RST 0x04000004 +#define FETHIEN2 0x01000000 +#define FETH2_RST 0x08000000 #define CFG_INIT_RAM_ADDR CFG_IMMR #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ @@ -288,19 +316,30 @@ #define CFG_SYPCR 0xFFFFFFC3 #define CFG_BCR 0x100C0000 #define CFG_SIUMCR 0x0A200000 -#define CFG_SCCR 0x00000000 -#define CFG_BR0_PRELIM 0xFF801801 -#define CFG_OR0_PRELIM 0xFF800836 -#define CFG_BR1_PRELIM 0x04501801 +#define CFG_SCCR SCCR_DFBRG01 +#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801 +#define CFG_OR0_PRELIM 0xFF800876 +#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801 #define CFG_OR1_PRELIM 0xFFFF8010 -#define CFG_RMR 0 +#define CFG_RMR RMR_CSRE #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) #define CFG_RCCR 0 + +#if CONFIG_ADSTYPE == CFG_PQ2FADS +#define CFG_PSDMR 0x824B36A3 +#define CFG_PSRT 0x13 +#define CFG_LSDMR 0x828737A3 +#define CFG_LSRT 0x13 +#define CFG_MPTPR 0x2800 +#else #define CFG_PSDMR 0x016EB452 -#define CFG_MPTPR 0x00001900 -#define CFG_PSRT 0x00000021 +#define CFG_PSRT 0x21 +#define CFG_LSDMR 0x0086A522 +#define CFG_LSRT 0x21 +#define CFG_MPTPR 0x1900 +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ #define CFG_RESET_ADDRESS 0x04400000 N: Yuli Barcohen E: yuli@arabellasw.com D: Support for Motorola PQ2FADS-ZU board