[U-Boot] [PATCH] Tegra114: pinmux: Fix bad CAM_MCLK func 3 table entry
This caused CAM_MCLK's pinmux reg to be locked out, since the table parsing code couldn't find a matching entry for VI_ALT3 and wrote garbage to the register.
Signed-off-by: Tom Warren twarren@nvidia.com --- arch/arm/cpu/tegra114-common/pinmux.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c index f037320..4f3c352 100644 --- a/arch/arm/cpu/tegra114-common/pinmux.c +++ b/arch/arm/cpu/tegra114-common/pinmux.c @@ -239,7 +239,7 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4), PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4), PIN_RESERVED, /* Reserved by t114: 0x3280 */ - PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT2, RSVD4), + PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4), PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4), PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3), PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
On 03/13/2013 04:10 PM, Tom Warren wrote:
This caused CAM_MCLK's pinmux reg to be locked out, since the table parsing code couldn't find a matching entry for VI_ALT3 and wrote garbage to the register.
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -239,7 +239,7 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
- PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT2, RSVD4),
- PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
This doesn't seem right; the "alt" settings should be assigned in order non-alt, alt1, alt2, alt3.
You say, "the table parsing code couldn't find a matching entry for VI_ALT3". What was looking for that entry?
Also, shouldn't the pinmux driver be fixed not to write garbage to a register, but instead return an error, if it can't find the table entry it's looking for?
On Wed, Mar 13, 2013 at 3:34 PM, Stephen Warren swarren@wwwdotorg.org wrote:
On 03/13/2013 04:10 PM, Tom Warren wrote:
This caused CAM_MCLK's pinmux reg to be locked out, since the table parsing code couldn't find a matching entry for VI_ALT3 and wrote garbage to the register.
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -239,7 +239,7 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT2, RSVD4),
PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),This doesn't seem right; the "alt" settings should be assigned in order non-alt, alt1, alt2, alt3.
According to the TRM, CAM_MCLK takes the following 4 possible mux settings:
0 = VI 1 = VI_ALT1 2 = VI_ALT3 3 = RSVD3
There is no VI_ALT2 in the Tegra114 TRM. There was in the T30 TRM.
You say, "the table parsing code couldn't find a matching entry for VI_ALT3". What was looking for that entry?
The pinmux table entry in board/nvidia/dalmore/pinmux-config-dalmore.h, table tegra114_pinmux_common[], VI_PINMUX(CAM_MCLK, VI_ALT3, ...), which is parsed by pinmux_config_pingroup in pinmux.c.
Also, shouldn't the pinmux driver be fixed not to write garbage to a register, but instead return an error, if it can't find the table entry it's looking for?
There's an assert if the mux isn't found - I thought that would handle it, but it appears that it will only if DEBUG is enabled. I'll add more error checking to the code - I have a pinmux.c/pinmux.h update coming for other problems I found while chasing this down.
Tom
On 03/13/2013 04:55 PM, Tom Warren wrote:
On Wed, Mar 13, 2013 at 3:34 PM, Stephen Warren swarren@wwwdotorg.org wrote:
On 03/13/2013 04:10 PM, Tom Warren wrote:
This caused CAM_MCLK's pinmux reg to be locked out, since the table parsing code couldn't find a matching entry for VI_ALT3 and wrote garbage to the register.
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -239,7 +239,7 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT2, RSVD4),
PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),This doesn't seem right; the "alt" settings should be assigned in order non-alt, alt1, alt2, alt3.
According to the TRM, CAM_MCLK takes the following 4 possible mux settings:
0 = VI 1 = VI_ALT1 2 = VI_ALT3 3 = RSVD3
There is no VI_ALT2 in the Tegra114 TRM. There was in the T30 TRM.
Uggh, yes. The TRM is screwed up. Best to match it though I suppose.
So, the change is fine, and ends up matching the kernel's pinmux table too. It might be a good idea to check for any other diffs.
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Stephen Warren -
Tom Warren