Add a driver for RXAUI control on IHS FPGAs.

Signed-off-by: Mario Six mario.six@gdsys.cc --- drivers/misc/Kconfig | 6 ++- drivers/misc/Makefile | 1 + drivers/misc/gdsys_rxaui_ctrl.c | 91 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+), 1 deletion(-) create mode 100644 drivers/misc/gdsys_rxaui_ctrl.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index d774569cbc..be900cf4d6 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -263,5 +263,9 @@ config SYS_I2C_EEPROM_ADDR_OVERFLOW

endif

- +config GDSYS_RXAUI_CTRL + bool "Enable gdsys RXAUI control driver" + depends on MISC + help + Support gdsys FPGA's RXAUI control. endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index e8d598cd47..4ab17129b1 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -54,3 +54,4 @@ obj-$(CONFIG_QFW) += qfw.o obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o obj-$(CONFIG_STM32_RCC) += stm32_rcc.o obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o +obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o diff --git a/drivers/misc/gdsys_rxaui_ctrl.c b/drivers/misc/gdsys_rxaui_ctrl.c new file mode 100644 index 0000000000..f9f84d4ff9 --- /dev/null +++ b/drivers/misc/gdsys_rxaui_ctrl.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <fpgamap.h> +#include <misc.h> + +#include "../misc/gdsys_soc.h" + +enum { + REG_RXAUI_GEN_CNT = 0x0, + REG_RXAUI_ERR_CNT = 0x2, + REG_RXAUI_SUCC_CNT = 0x4, + REG_RXAUI_STATUS = 0x6, + REG_RXAUI_CTRL_0 = 0x8, + REG_RXAUI_CTRL_1 = 0xA, +}; + +struct gdsys_rxaui_ctrl_priv { + int addr; +}; + +int gdsys_rxaui_disable_polarity_inversion(struct udevice *dev) +{ + struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev); + struct udevice *fpga; + u16 val; + + gdsys_soc_get_fpga(dev, &fpga); + + fpgamap_read(fpga, priv->addr + REG_RXAUI_CTRL_1, &val, + FPGAMAP_SIZE_16); + val &= ~0x7800; + fpgamap_write(fpga, priv->addr + REG_RXAUI_CTRL_1, &val, + FPGAMAP_SIZE_16); + + return 0; +} + +int gdsys_rxaui_enable_polarity_inversion(struct udevice *dev) +{ + struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev); + struct udevice *fpga; + u16 val; + + gdsys_soc_get_fpga(dev, &fpga); + + fpgamap_read(fpga, priv->addr + REG_RXAUI_CTRL_1, &val, + FPGAMAP_SIZE_16); + val |= ~0x7800; + fpgamap_write(fpga, priv->addr + REG_RXAUI_CTRL_1, &val, + FPGAMAP_SIZE_16); + + return 0; +} + +static const struct misc_ops gdsys_rxaui_ctrl_ops = { + .disable = gdsys_rxaui_disable_polarity_inversion, + .enable = gdsys_rxaui_enable_polarity_inversion, +}; + +int gdsys_rxaui_ctrl_probe(struct udevice *dev) +{ + struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev); + + priv->addr = dev_read_u32_default(dev, "reg", -1); + + return 0; +} + +static const struct udevice_id gdsys_rxaui_ctrl_ids[] = { + { .compatible = "gdsys,rxaui_ctrl" }, + { } +}; + +U_BOOT_DRIVER(gdsys_rxaui_ctrl) = { + .name = "gdsys_rxaui_ctrl", + .id = UCLASS_MISC, + .ops = &gdsys_rxaui_ctrl_ops, + .of_match = gdsys_rxaui_ctrl_ids, + .probe = gdsys_rxaui_ctrl_probe, + .priv_auto_alloc_size = sizeof(struct gdsys_rxaui_ctrl_priv), +}; -- 2.16.1