Add option to include RESET driver and uclass in SPL. That can be useful to handle IP reset with same driver in U-Boot and in SPL.

Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---

common/spl/Kconfig | 9 +++++++++ drivers/Makefile | 1 + 2 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index f58163c..baec39e 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -568,6 +568,15 @@ config SPL_POST_MEM_SUPPORT performed before booting. This enables the drivers in post/drivers as part of an SPL build.

+config SPL_RESET_SUPPORT + bool "Support reset drivers" + depends on SPL + help + Enable support for reset control in SPL. + That can be useful in SPL to handle IP reset in driver, as in U-Boot, + by using the generic reset API provided by driver model. + This enables the drivers in drivers/reset as part of an SPL build. + config SPL_POWER_SUPPORT bool "Support power drivers" help diff --git a/drivers/Makefile b/drivers/Makefile index e6062a5..9648ebd 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ +obj-$(CONFIG_SPL_RESET_SUPPORT) += reset/ obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/ obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/ obj-$(CONFIG_SPL_UBI) += mtd/ubispl/

The current value timer_rate_hz causes a problem with function timer_get_us() from lib time and then an issue with readx_poll_timeout() function.

With corrected value for tbclk() = timer_rate_hz = CONFIG_SYS_HZ_CLOCK the weak functions in lib timer can be used: - get_timer() - __udelay() So the specific function in this file are removed.

Signed-off-by: Patrick Delaunay patrick.delaunay@st.com --- this patch avoid issue in driver with readl_poll_timeout()

Following source code has been used to demonstrate the issue (with CONFIG_SYS_HZ_CLOCK = 64 MHz)

printf("Tick= %llx us=%lx boot us=%lx\n", get_ticks(), timer_get_us(), timer_get_boot_us()); mdelay(1000); printf("Tick= %llx us=%lx boot us=%lx\n", get_ticks(), timer_get_us(), timer_get_boot_us());

Result:

Tick= 36fad40 us=35b0f45f boot us=dbeb8 Tick= 743b21e us=7181c02e boot us=1d0ecb

=> 1000ms : 0x1d0ecb-0xdbeb8 = 0xF5013 for timer_get_boot_us = 1000000 us => timer_get_boot_us is OK => 1000ms : 0x7181c02e-0x35b0f45f = 0x3BD0CBCF = 1.000.000.000 us for timer_get_us() which gives a invalid value (based on CONFIG_SYS_HZ and get_tbclk())

This patch resolves the issue.

arch/arm/cpu/armv7/arch_timer.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-)

diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index 30915d2..545c518 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -17,7 +17,7 @@ int timer_init(void) gd->arch.tbl = 0; gd->arch.tbu = 0;

- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ; + gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; return 0; }

@@ -34,27 +34,9 @@ unsigned long long get_ticks(void) }

-ulong get_timer(ulong base) -{ - return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base; -} - ulong timer_get_boot_us(void) { - return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000)); -} - -void __udelay(unsigned long usec) -{ - unsigned long long endtime; - - endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz, - 1000UL); - - endtime += get_ticks(); - - while (get_ticks() < endtime) - ; + return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / 1000000); }

ulong get_tbclk(void)

Kmalloc is using memalign allocation function. It is not necessary to align this structure so to save bytes, we move to calloc.

And kmalloc function can't be used in SPL early stage (in board_init_f())

Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---

drivers/i2c/stm32f7_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index 8662487..81f061a 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -533,7 +533,7 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, if (((sdadel >= sdadel_min) && (sdadel <= sdadel_max)) && (p != p_prev)) { - v = kmalloc(sizeof(*v), GFP_KERNEL); + v = calloc(1, sizeof(*v)); if (!v) return -ENOMEM;

@@ -689,7 +689,7 @@ exit: /* Release list and memory */ list_for_each_entry_safe(v, _v, &solutions, node) { list_del(&v->node); - kfree(v); + free(v); }

return ret;

Add driver and binding for stm32mp1 ddr controller and phy

Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---

MAINTAINERS | 1 + arch/arm/mach-stm32mp/include/mach/ddr.h | 12 + doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt | 299 ++++++++++++++ drivers/ram/Kconfig | 2 + drivers/ram/Makefile | 1 + drivers/ram/stm32mp1/Kconfig | 12 + drivers/ram/stm32mp1/Makefile | 8 + drivers/ram/stm32mp1/stm32mp1_ddr.c | 496 +++++++++++++++++++++++ drivers/ram/stm32mp1/stm32mp1_ddr.h | 210 ++++++++++ drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 365 +++++++++++++++++ drivers/ram/stm32mp1/stm32mp1_ram.c | 197 +++++++++ 11 files changed, 1603 insertions(+) create mode 100644 arch/arm/mach-stm32mp/include/mach/ddr.h create mode 100644 doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt create mode 100644 drivers/ram/stm32mp1/Kconfig create mode 100644 drivers/ram/stm32mp1/Makefile create mode 100644 drivers/ram/stm32mp1/stm32mp1_ddr.c create mode 100644 drivers/ram/stm32mp1/stm32mp1_ddr.h create mode 100644 drivers/ram/stm32mp1/stm32mp1_ddr_regs.h create mode 100644 drivers/ram/stm32mp1/stm32mp1_ram.c

diff --git a/MAINTAINERS b/MAINTAINERS index 9b19019..ff7b837 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -195,6 +195,7 @@ ARM STM STM32MP M: Patrick Delaunay patrick.delaunay@st.com S: Maintained F: arch/arm/mach-stm32mp +F: ram/stm32mp1

ARM STM STV0991 M: Vikas Manocha vikas.manocha@st.com diff --git a/arch/arm/mach-stm32mp/include/mach/ddr.h b/arch/arm/mach-stm32mp/include/mach/ddr.h new file mode 100644 index 0000000..b635001 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/ddr.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#ifndef __MACH_STM32MP_DDR_H_ +#define __MACH_STM32MP_DDR_H_ + +int board_ddr_power_init(void); + +#endif diff --git a/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt new file mode 100644 index 0000000..3028636 --- /dev/null +++ b/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt @@ -0,0 +1,299 @@ +ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC) + +-------------------- +Required properties: +-------------------- +- compatible : Should be "st,stm32mp1-ddr" +- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address +- clocks : controller clocks handle +- clock-names : associated controller clock names + the "ddrphyc" clock is used to check the DDR frequency + at phy level according the expected value in "mem-speed" field + +the next attributes are DDR parameters, they are generated by DDR tools +included in STM32 Cube tool + +info attributes: +---------------- +- st,mem-name : name for DDR configuration, simple string for information +- st,mem-speed : DDR expected speed for the setting in MHz +- st,mem-size : DDR mem size in byte + + +controlleur attributes: +----------------------- +- st,ctl-reg : controleur values depending of the DDR type + (DDR3/LPDDR2/LPDDR3) + for STM32MP15x: 25 values are requested in this order + MSTR + MRCTRL0 + MRCTRL1 + DERATEEN + DERATEINT + PWRCTL + PWRTMG + HWLPCTL + RFSHCTL0 + RFSHCTL3 + CRCPARCTL0 + ZQCTL0 + DFITMG0 + DFITMG1 + DFILPCFG0 + DFIUPD0 + DFIUPD1 + DFIUPD2 + DFIPHYMSTR + ODTMAP + DBG0 + DBG1 + DBGCMD + POISONCFG + PCCFG + +- st,ctl-timing : controleur values depending of frequency and timing parameter + of DDR + for STM32MP15x: 12 values are requested in this order + RFSHTMG + DRAMTMG0 + DRAMTMG1 + DRAMTMG2 + DRAMTMG3 + DRAMTMG4 + DRAMTMG5 + DRAMTMG6 + DRAMTMG7 + DRAMTMG8 + DRAMTMG14 + ODTCFG + +- st,ctl-map : controleur values depending of address mapping + for STM32MP15x: 9 values are requested in this order + ADDRMAP1 + ADDRMAP2 + ADDRMAP3 + ADDRMAP4 + ADDRMAP5 + ADDRMAP6 + ADDRMAP9 + ADDRMAP10 + ADDRMAP11 + +- st,ctl-perf : controleur values depending of performance and scheduling + for STM32MP15x: 17 values are requested in this order + SCHED + SCHED1 + PERFHPR1 + PERFLPR1 + PERFWR1 + PCFGR_0 + PCFGW_0 + PCFGQOS0_0 + PCFGQOS1_0 + PCFGWQOS0_0 + PCFGWQOS1_0 + PCFGR_1 + PCFGW_1 + PCFGQOS0_1 + PCFGQOS1_1 + PCFGWQOS0_1 + PCFGWQOS1_1 + +phyc attributes: +---------------- +- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3) + for STM32MP15x: 10 values are requested in this order + PGCR + ACIOCR + DXCCR + DSGCR + DCR + ODTCR + ZQ0CR1 + DX0GCR + DX1GCR + DX2GCR + DX3GCR + +- st,phy-timing : phy values depending of frequency and timing parameter of DDR + for STM32MP15x: 10 values are requested in this order + PTR0 + PTR1 + PTR2 + DTPR0 + DTPR1 + DTPR2 + MR0 + MR1 + MR2 + MR3 + +- st,phy-cal : phy cal depending of calibration or tuning of DDR + for STM32MP15x: 12 values are requested in this order + DX0DLLCR + DX0DQTR + DX0DQSTR + DX1DLLCR + DX1DQTR + DX1DQSTR + DX2DLLCR + DX2DQTR + DX2DQSTR + DX3DLLCR + DX3DQTR + DX3DQSTR + +Example: + +/ { + soc { + u-boot,dm-spl; + + ddr: ddr@0x5A003000{ + u-boot,dm-spl; + u-boot,dm-pre-reloc; + + compatible = "st,stm32mp1-ddr"; + + reg = <0x5A003000 0x550 + 0x5A004000 0x234>; + + clocks = <&rcc_clk AXIDCG>, + <&rcc_clk DDRC1>, + <&rcc_clk DDRC2>, + <&rcc_clk DDRPHYC>, + <&rcc_clk DDRCAPB>, + <&rcc_clk DDRPHYCAPB>; + + clock-names = "axidcg", + "ddrc1", + "ddrc2", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + + st,mem-name = "DDR3 2x4Gb 533MHz"; + st,mem-speed = <533>; + st,mem-size = <0x40000000>; + + st,ctl-reg = < + 0x00040401 /*MSTR*/ + 0x00000010 /*MRCTRL0*/ + 0x00000000 /*MRCTRL1*/ + 0x00000000 /*DERATEEN*/ + 0x00800000 /*DERATEINT*/ + 0x00000000 /*PWRCTL*/ + 0x00400010 /*PWRTMG*/ + 0x00000000 /*HWLPCTL*/ + 0x00210000 /*RFSHCTL0*/ + 0x00000000 /*RFSHCTL3*/ + 0x00000000 /*CRCPARCTL0*/ + 0xC2000040 /*ZQCTL0*/ + 0x02050105 /*DFITMG0*/ + 0x00000202 /*DFITMG1*/ + 0x07000000 /*DFILPCFG0*/ + 0xC0400003 /*DFIUPD0*/ + 0x00000000 /*DFIUPD1*/ + 0x00000000 /*DFIUPD2*/ + 0x00000000 /*DFIPHYMSTR*/ + 0x00000001 /*ODTMAP*/ + 0x00000000 /*DBG0*/ + 0x00000000 /*DBG1*/ + 0x00000000 /*DBGCMD*/ + 0x00000000 /*POISONCFG*/ + 0x00000010 /*PCCFG*/ + >; + + st,ctl-timing = < + 0x0080008A /*RFSHTMG*/ + 0x121B2414 /*DRAMTMG0*/ + 0x000D041B /*DRAMTMG1*/ + 0x0607080E /*DRAMTMG2*/ + 0x0050400C /*DRAMTMG3*/ + 0x07040407 /*DRAMTMG4*/ + 0x06060303 /*DRAMTMG5*/ + 0x02020002 /*DRAMTMG6*/ + 0x00000202 /*DRAMTMG7*/ + 0x00001005 /*DRAMTMG8*/ + 0x000D041B /*DRAMTMG1*/4 + 0x06000600 /*ODTCFG*/ + >; + + st,ctl-map = < + 0x00080808 /*ADDRMAP1*/ + 0x00000000 /*ADDRMAP2*/ + 0x00000000 /*ADDRMAP3*/ + 0x00001F1F /*ADDRMAP4*/ + 0x07070707 /*ADDRMAP5*/ + 0x0F070707 /*ADDRMAP6*/ + 0x00000000 /*ADDRMAP9*/ + 0x00000000 /*ADDRMAP10*/ + 0x00000000 /*ADDRMAP11*/ + >; + + st,ctl-perf = < + 0x00001201 /*SCHED*/ + 0x00001201 /*SCHED*/1 + 0x01000001 /*PERFHPR1*/ + 0x08000200 /*PERFLPR1*/ + 0x08000400 /*PERFWR1*/ + 0x00010000 /*PCFGR_0*/ + 0x00000000 /*PCFGW_0*/ + 0x02100B03 /*PCFGQOS0_0*/ + 0x00800100 /*PCFGQOS1_0*/ + 0x01100B03 /*PCFGWQOS0_0*/ + 0x01000200 /*PCFGWQOS1_0*/ + 0x00010000 /*PCFGR_1*/ + 0x00000000 /*PCFGW_1*/ + 0x02100B03 /*PCFGQOS0_1*/ + 0x00800000 /*PCFGQOS1_1*/ + 0x01100B03 /*PCFGWQOS0_1*/ + 0x01000200 /*PCFGWQOS1_1*/ + >; + + st,phy-reg = < + 0x01442E02 /*PGCR*/ + 0x10400812 /*ACIOCR*/ + 0x00000C40 /*DXCCR*/ + 0xF200001F /*DSGCR*/ + 0x0000000B /*DCR*/ + 0x00010000 /*ODTCR*/ + 0x0000007B /*ZQ0CR1*/ + 0x0000CE81 /*DX0GCR*/ + 0x0000CE81 /*DX1GCR*/ + 0x0000CE81 /*DX2GCR*/ + 0x0000CE81 /*DX3GCR*/ + >; + + st,phy-timing = < + 0x0022A41B /*PTR0*/ + 0x047C0740 /*PTR1*/ + 0x042D9C80 /*PTR2*/ + 0x369477D0 /*DTPR0*/ + 0x098A00D8 /*DTPR1*/ + 0x10023600 /*DTPR2*/ + 0x00000830 /*MR0*/ + 0x00000000 /*MR1*/ + 0x00000208 /*MR2*/ + 0x00000000 /*MR3*/ + >; + + st,phy-cal = < + 0x40000000 /*DX0DLLCR*/ + 0xFFFFFFFF /*DX0DQTR*/ + 0x3DB02000 /*DX0DQSTR*/ + 0x40000000 /*DX1DLLCR*/ + 0xFFFFFFFF /*DX1DQTR*/ + 0x3DB02000 /*DX1DQSTR*/ + 0x40000000 /*DX2DLLCR*/ + 0xFFFFFFFF /*DX2DQTR*/ + 0x3DB02000 /*DX2DQSTR*/ + 0x40000000 /*DX3DLLCR*/ + 0xFFFFFFFF /*DX3DQTR*/ + 0x3DB02000 /*DX3DQSTR*/ + >; + + status = "okay"; + }; + }; +}; diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 47969f3..496e2b7 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -33,3 +33,5 @@ config STM32_SDRAM STM32F7 family devices support flexible memory controller(FMC) to support external memories like sdram, psram & nand. This driver is for the sdram memory interface with the FMC. + +source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 51ae6be..3820d03 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -6,6 +6,7 @@ # obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o +obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/ obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o

diff --git a/drivers/ram/stm32mp1/Kconfig b/drivers/ram/stm32mp1/Kconfig new file mode 100644 index 0000000..b9c8166 --- /dev/null +++ b/drivers/ram/stm32mp1/Kconfig @@ -0,0 +1,12 @@ + +config STM32MP1_DDR + bool "STM32MP1 DDR driver" + depends on DM && OF_CONTROL && ARCH_STM32MP + select RAM + select SPL_RAM if SPL + default y + help + activate STM32MP1 DDR controller driver for STM32MP1 soc + family: support for LPDDR2, LPDDR3 and DDR3 + the SDRAM parameters for controleur and phy need to be provided + in device tree (computed by DDR tuning tools) diff --git a/drivers/ram/stm32mp1/Makefile b/drivers/ram/stm32mp1/Makefile new file mode 100644 index 0000000..9f05cd4 --- /dev/null +++ b/drivers/ram/stm32mp1/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# +# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause +# + +obj-y += stm32mp1_ram.o +obj-y += stm32mp1_ddr.o diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c new file mode 100644 index 0000000..ffe50d9 --- /dev/null +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -0,0 +1,496 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#include <common.h> +#include <clk.h> +#include <ram.h> +#include <reset.h> +#include <timer.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <linux/iopoll.h> +#include "stm32mp1_ddr.h" +#include "stm32mp1_ddr_regs.h" + +#define RCC_DDRITFCR 0xD8 + +#define RCC_DDRITFCR_DDRCAPBRST (BIT(14)) +#define RCC_DDRITFCR_DDRCAXIRST (BIT(15)) +#define RCC_DDRITFCR_DDRCORERST (BIT(16)) +#define RCC_DDRITFCR_DPHYAPBRST (BIT(17)) +#define RCC_DDRITFCR_DPHYRST (BIT(18)) +#define RCC_DDRITFCR_DPHYCTLRST (BIT(19)) + +struct reg_desc { + const char *name; + u16 offset; /* offset for base address */ + u8 par_offset; /* offset for parameter array */ +}; + +#define INVALID_OFFSET 0xFF + +#define DDRCTL_REG(x, y) \ + {#x,\ + offsetof(struct stm32mp1_ddrctl, x),\ + offsetof(struct y, x)} + +#define DDRPHY_REG(x, y) \ + {#x,\ + offsetof(struct stm32mp1_ddrphy, x),\ + offsetof(struct y, x)} + +#define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg) +static const struct reg_desc ddr_reg[] = { + DDRCTL_REG_REG(mstr), + DDRCTL_REG_REG(mrctrl0), + DDRCTL_REG_REG(mrctrl1), + DDRCTL_REG_REG(derateen), + DDRCTL_REG_REG(derateint), + DDRCTL_REG_REG(pwrctl), + DDRCTL_REG_REG(pwrtmg), + DDRCTL_REG_REG(hwlpctl), + DDRCTL_REG_REG(rfshctl0), + DDRCTL_REG_REG(rfshctl3), + DDRCTL_REG_REG(crcparctl0), + DDRCTL_REG_REG(zqctl0), + DDRCTL_REG_REG(dfitmg0), + DDRCTL_REG_REG(dfitmg1), + DDRCTL_REG_REG(dfilpcfg0), + DDRCTL_REG_REG(dfiupd0), + DDRCTL_REG_REG(dfiupd1), + DDRCTL_REG_REG(dfiupd2), + DDRCTL_REG_REG(dfiphymstr), + DDRCTL_REG_REG(odtmap), + DDRCTL_REG_REG(dbg0), + DDRCTL_REG_REG(dbg1), + DDRCTL_REG_REG(dbgcmd), + DDRCTL_REG_REG(poisoncfg), + DDRCTL_REG_REG(pccfg), +}; + +#define DDRCTL_REG_TIMING(x) DDRCTL_REG(x, stm32mp1_ddrctrl_timing) +static const struct reg_desc ddr_timing[] = { + DDRCTL_REG_TIMING(rfshtmg), + DDRCTL_REG_TIMING(dramtmg0), + DDRCTL_REG_TIMING(dramtmg1), + DDRCTL_REG_TIMING(dramtmg2), + DDRCTL_REG_TIMING(dramtmg3), + DDRCTL_REG_TIMING(dramtmg4), + DDRCTL_REG_TIMING(dramtmg5), + DDRCTL_REG_TIMING(dramtmg6), + DDRCTL_REG_TIMING(dramtmg7), + DDRCTL_REG_TIMING(dramtmg8), + DDRCTL_REG_TIMING(dramtmg14), + DDRCTL_REG_TIMING(odtcfg), +}; + +#define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp1_ddrctrl_map) +static const struct reg_desc ddr_map[] = { + DDRCTL_REG_MAP(addrmap1), + DDRCTL_REG_MAP(addrmap2), + DDRCTL_REG_MAP(addrmap3), + DDRCTL_REG_MAP(addrmap4), + DDRCTL_REG_MAP(addrmap5), + DDRCTL_REG_MAP(addrmap6), + DDRCTL_REG_MAP(addrmap9), + DDRCTL_REG_MAP(addrmap10), + DDRCTL_REG_MAP(addrmap11), +}; + +#define DDRCTL_REG_PERF(x) DDRCTL_REG(x, stm32mp1_ddrctrl_perf) +static const struct reg_desc ddr_perf[] = { + DDRCTL_REG_PERF(sched), + DDRCTL_REG_PERF(sched1), + DDRCTL_REG_PERF(perfhpr1), + DDRCTL_REG_PERF(perflpr1), + DDRCTL_REG_PERF(perfwr1), + DDRCTL_REG_PERF(pcfgr_0), + DDRCTL_REG_PERF(pcfgw_0), + DDRCTL_REG_PERF(pcfgqos0_0), + DDRCTL_REG_PERF(pcfgqos1_0), + DDRCTL_REG_PERF(pcfgwqos0_0), + DDRCTL_REG_PERF(pcfgwqos1_0), + DDRCTL_REG_PERF(pcfgr_1), + DDRCTL_REG_PERF(pcfgw_1), + DDRCTL_REG_PERF(pcfgqos0_1), + DDRCTL_REG_PERF(pcfgqos1_1), + DDRCTL_REG_PERF(pcfgwqos0_1), + DDRCTL_REG_PERF(pcfgwqos1_1), +}; + +#define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg) +static const struct reg_desc ddrphy_reg[] = { + DDRPHY_REG_REG(pgcr), + DDRPHY_REG_REG(aciocr), + DDRPHY_REG_REG(dxccr), + DDRPHY_REG_REG(dsgcr), + DDRPHY_REG_REG(dcr), + DDRPHY_REG_REG(odtcr), + DDRPHY_REG_REG(zq0cr1), + DDRPHY_REG_REG(dx0gcr), + DDRPHY_REG_REG(dx1gcr), + DDRPHY_REG_REG(dx2gcr), + DDRPHY_REG_REG(dx3gcr), +}; + +#define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing) +static const struct reg_desc ddrphy_timing[] = { + DDRPHY_REG_TIMING(ptr0), + DDRPHY_REG_TIMING(ptr1), + DDRPHY_REG_TIMING(ptr2), + DDRPHY_REG_TIMING(dtpr0), + DDRPHY_REG_TIMING(dtpr1), + DDRPHY_REG_TIMING(dtpr2), + DDRPHY_REG_TIMING(mr0), + DDRPHY_REG_TIMING(mr1), + DDRPHY_REG_TIMING(mr2), + DDRPHY_REG_TIMING(mr3), +}; + +#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal) +static const struct reg_desc ddrphy_cal[] = { + DDRPHY_REG_CAL(dx0dllcr), + DDRPHY_REG_CAL(dx0dqtr), + DDRPHY_REG_CAL(dx0dqstr), + DDRPHY_REG_CAL(dx1dllcr), + DDRPHY_REG_CAL(dx1dqtr), + DDRPHY_REG_CAL(dx1dqstr), + DDRPHY_REG_CAL(dx2dllcr), + DDRPHY_REG_CAL(dx2dqtr), + DDRPHY_REG_CAL(dx2dqstr), + DDRPHY_REG_CAL(dx3dllcr), + DDRPHY_REG_CAL(dx3dqtr), + DDRPHY_REG_CAL(dx3dqstr), +}; + +enum reg_type { + REG_REG, + REG_TIMING, + REG_PERF, + REG_MAP, + REGPHY_REG, + REGPHY_TIMING, + REGPHY_CAL, + REG_TYPE_NB +}; + +enum base_type { + DDR_BASE, + DDRPHY_BASE, + NONE_BASE +}; + +struct ddr_reg_info { + const char *name; + const struct reg_desc *desc; + u8 size; + enum base_type base; +}; + +#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal) + +const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = { +[REG_REG] = { + "static", ddr_reg, ARRAY_SIZE(ddr_reg), DDR_BASE}, +[REG_TIMING] = { + "timing", ddr_timing, ARRAY_SIZE(ddr_timing), DDR_BASE}, +[REG_PERF] = { + "perf", ddr_perf, ARRAY_SIZE(ddr_perf), DDR_BASE}, +[REG_MAP] = { + "map", ddr_map, ARRAY_SIZE(ddr_map), DDR_BASE}, +[REGPHY_REG] = { + "static", ddrphy_reg, ARRAY_SIZE(ddrphy_reg), DDRPHY_BASE}, +[REGPHY_TIMING] = { + "timing", ddrphy_timing, ARRAY_SIZE(ddrphy_timing), DDRPHY_BASE}, +[REGPHY_CAL] = { + "cal", ddrphy_cal, ARRAY_SIZE(ddrphy_cal), DDRPHY_BASE}, +}; + +const char *base_name[] = { + [DDR_BASE] = "ctl", + [DDRPHY_BASE] = "phy", +}; + +static u32 get_base_addr(const struct ddr_info *priv, enum base_type base) +{ + if (base == DDRPHY_BASE) + return (u32)priv->phy; + else + return (u32)priv->ctl; +} + +static void set_reg(const struct ddr_info *priv, + enum reg_type type, + const void *param) +{ + unsigned int i; + unsigned int *ptr, value; + enum base_type base = ddr_registers[type].base; + u32 base_addr = get_base_addr(priv, base); + const struct reg_desc *desc = ddr_registers[type].desc; + + debug("init %s\n", ddr_registers[type].name); + for (i = 0; i < ddr_registers[type].size; i++) { + ptr = (unsigned int *)(base_addr + desc[i].offset); + if (desc[i].par_offset == INVALID_OFFSET) { + pr_err("invalid parameter offset for %s", desc[i].name); + } else { + value = *((u32 *)((u32)param + + desc[i].par_offset)); + writel(value, ptr); + debug("[0x%x] %s= 0x%08x\n", + (u32)ptr, desc[i].name, value); + } + } +} + +static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy) +{ + u32 pgsr; + int ret; + + ret = readl_poll_timeout(&phy->pgsr, pgsr, + pgsr & (DDRPHYC_PGSR_IDONE | + DDRPHYC_PGSR_DTERR | + DDRPHYC_PGSR_DTIERR | + DDRPHYC_PGSR_DFTERR | + DDRPHYC_PGSR_RVERR | + DDRPHYC_PGSR_RVEIRR), + 1000000); + debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n", + (u32)&phy->pgsr, pgsr, ret); +} + +void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir) +{ + pir |= DDRPHYC_PIR_INIT; + writel(pir, &phy->pir); + debug("[0x%08x] pir = 0x%08x -> 0x%08x\n", + (u32)&phy->pir, pir, readl(&phy->pir)); + + /* need to wait 10 configuration clock before start polling */ + udelay(10); + + /* Wait DRAM initialization and Gate Training Evaluation complete */ + ddrphy_idone_wait(phy); +} + +/* start quasi dynamic register update */ +static void start_sw_done(struct stm32mp1_ddrctl *ctl) +{ + clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); +} + +/* wait quasi dynamic register update */ +static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl) +{ + int ret; + u32 swstat; + + setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); + + ret = readl_poll_timeout(&ctl->swstat, swstat, + swstat & DDRCTRL_SWSTAT_SW_DONE_ACK, + 1000000); + if (ret) + panic("Timeout initialising DRAM : DDR->swstat = %x\n", + swstat); + + debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat); +} + +/* wait quasi dynamic register update */ +static void wait_operating_mode(struct ddr_info *priv, int mode) +{ + u32 stat, val, mask, val2 = 0, mask2 = 0; + int ret; + + mask = DDRCTRL_STAT_OPERATING_MODE_MASK; + val = mode; + /* self-refresh due to software => check also STAT.selfref_type */ + if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { + mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK; + stat |= DDRCTRL_STAT_SELFREF_TYPE_SR; + } else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) { + /* normal mode: handle also automatic self refresh */ + mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK | + DDRCTRL_STAT_SELFREF_TYPE_MASK; + val2 = DDRCTRL_STAT_OPERATING_MODE_SR | + DDRCTRL_STAT_SELFREF_TYPE_ASR; + } + + ret = readl_poll_timeout(&priv->ctl->stat, stat, + ((stat & mask) == val) || + (mask2 && ((stat & mask2) == val2)), + 1000000); + + if (ret) + panic("Timeout DRAM : DDR->stat = %x\n", stat); + + debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat); +} + +void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl) +{ + start_sw_done(ctl); + /* quasi-dynamic register update*/ + setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); + clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); + clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + wait_sw_done_ack(ctl); +} + +void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, + u32 rfshctl3, u32 pwrctl) +{ + start_sw_done(ctl); + if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH)) + clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); + if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN) + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); + setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + wait_sw_done_ack(ctl); +} + +/* board-specific DDR power initializations. */ +__weak int board_ddr_power_init(void) +{ + return 0; +} + +__maybe_unused +void stm32mp1_ddr_init(struct ddr_info *priv, + const struct stm32mp1_ddr_config *config) +{ + u32 pir; + int ret; + + ret = board_ddr_power_init(); + + if (ret) + panic("ddr power init failed\n"); + + debug("name = %s\n", config->info.name); + debug("speed = %d MHz\n", config->info.speed); + debug("size = 0x%x\n", config->info.size); +/* + * 1. Program the DWC_ddr_umctl2 registers + * 1.1 RESETS: presetn, core_ddrc_rstn, aresetn + */ + /* Assert All DDR part */ + setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); + setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); + setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); + setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); + setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); + setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); + +/* 1.2. start CLOCK */ + if (stm32mp1_ddr_clk_enable(priv, config->info.speed)) + panic("invalid DRAM clock : %d MHz\n", + config->info.speed); + +/* 1.3. deassert reset */ + /* de-assert PHY rstn and ctl_rstn via DPHYRST and DPHYCTLRST */ + clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); + clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); + /* De-assert presetn once the clocks are active + * and stable via DDRCAPBRST bit + */ + clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); + +/* 1.4. wait 4 cycles for synchronization */ + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + +/* 1.5. initialize registers ddr_umctl2 */ + /* Stop uMCTL2 before PHY is ready */ + clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + debug("[0x%08x] dfimisc = 0x%08x\n", + (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc)); + + set_reg(priv, REG_REG, &config->c_reg); + set_reg(priv, REG_TIMING, &config->c_timing); + set_reg(priv, REG_MAP, &config->c_map); + + /* skip CTRL init, SDRAM init is done by PHY PUBL */ + clrsetbits_le32(&priv->ctl->init0, + DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK, + DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL); + + set_reg(priv, REG_PERF, &config->c_perf); + +/* 2. deassert reset signal core_ddrc_rstn, aresetn and presetn */ + clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); + clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); + clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); + +/* 3. start PHY init by accessing relevant PUBL registers + * (DXGCR, DCR, PTR*, MR*, DTPR*) + */ + set_reg(priv, REGPHY_REG, &config->p_reg); + set_reg(priv, REGPHY_TIMING, &config->p_timing); + set_reg(priv, REGPHY_CAL, &config->p_cal); + +/* 4. Monitor PHY init status by polling PUBL register PGSR.IDONE + * Perform DDR PHY DRAM initialization and Gate Training Evaluation + */ + ddrphy_idone_wait(priv->phy); + +/* 5. Indicate to PUBL that controller performs SDRAM initialization + * by setting PIR.INIT and PIR CTLDINIT and pool PGSR.IDONE + * DRAM init is done by PHY, init0.skip_dram.init = 1 + */ + pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL | + DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_DRAMINIT | DDRPHYC_PIR_ICPC; + + if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3) + pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */ + + stm32mp1_ddrphy_init(priv->phy, pir); + +/* 6. SET DFIMISC.dfi_init_complete_en to 1 */ + /* Enable quasi-dynamic register programming*/ + start_sw_done(priv->ctl); + setbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + wait_sw_done_ack(priv->ctl); + +/* 7. Wait for DWC_ddr_umctl2 to move to normal operation mode + * by monitoring STAT.operating_mode signal + */ + /* wait uMCTL2 ready */ + + wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); + + debug("DDR DQS training : "); +/* 8. Disable Auto refresh and power down by setting + * - RFSHCTL3.dis_au_refresh = 1 + * - PWRCTL.powerdown_en = 0 + * - DFIMISC.dfiinit_complete_en = 0 + */ + stm32mp1_refresh_disable(priv->ctl); + +/* 9. Program PUBL PGCR to enable refresh during training and rank to train + * not done => keep the programed value in PGCR + */ + +/* 10. configure PUBL PIR register to specify which training step to run */ + /* warning : RVTRN is not supported by this PUBL */ + stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN); + +/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */ + ddrphy_idone_wait(priv->phy); + +/* 12. set back registers in step 8 to the orginal values if desidered */ + stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, + config->c_reg.pwrctl); + + /* enable uMCTL2 AXI port 0 and 1 */ + setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); + setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN); +} diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h b/drivers/ram/stm32mp1/stm32mp1_ddr.h new file mode 100644 index 0000000..b77d823 --- /dev/null +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#ifndef _RAM_STM32MP1_DDR_H +#define _RAM_STM32MP1_DDR_H + +enum stm32mp1_ddr_interact_step { + STEP_DDR_RESET, + STEP_CTL_INIT, + STEP_PHY_INIT, + STEP_DDR_READY, + STEP_RUN, +}; + +/* DDR CTL and DDR PHY REGISTERS */ +struct stm32mp1_ddrctl; +struct stm32mp1_ddrphy; + +/** + * struct ddr_info + * + * @dev: pointer for the device + * @info: UCLASS RAM information + * @ctl: DDR controleur base address + * @clk: DDR clock + * @phy: DDR PHY base address + * @rcc: rcc base address + */ +struct ddr_info { + struct udevice *dev; + struct ram_info info; + struct clk clk; + struct stm32mp1_ddrctl *ctl; + struct stm32mp1_ddrphy *phy; + u32 rcc; +}; + +struct stm32mp1_ddrctrl_reg { + u32 mstr; + u32 mrctrl0; + u32 mrctrl1; + u32 derateen; + u32 derateint; + u32 pwrctl; + u32 pwrtmg; + u32 hwlpctl; + u32 rfshctl0; + u32 rfshctl3; + u32 crcparctl0; + u32 zqctl0; + u32 dfitmg0; + u32 dfitmg1; + u32 dfilpcfg0; + u32 dfiupd0; + u32 dfiupd1; + u32 dfiupd2; + u32 dfiphymstr; + u32 odtmap; + u32 dbg0; + u32 dbg1; + u32 dbgcmd; + u32 poisoncfg; + u32 pccfg; + +}; + +struct stm32mp1_ddrctrl_timing { + u32 rfshtmg; + u32 dramtmg0; + u32 dramtmg1; + u32 dramtmg2; + u32 dramtmg3; + u32 dramtmg4; + u32 dramtmg5; + u32 dramtmg6; + u32 dramtmg7; + u32 dramtmg8; + u32 dramtmg14; + u32 odtcfg; +}; + +struct stm32mp1_ddrctrl_map { + u32 addrmap1; + u32 addrmap2; + u32 addrmap3; + u32 addrmap4; + u32 addrmap5; + u32 addrmap6; + u32 addrmap9; + u32 addrmap10; + u32 addrmap11; +}; + +struct stm32mp1_ddrctrl_perf { + u32 sched; + u32 sched1; + u32 perfhpr1; + u32 perflpr1; + u32 perfwr1; + u32 pcfgr_0; + u32 pcfgw_0; + u32 pcfgqos0_0; + u32 pcfgqos1_0; + u32 pcfgwqos0_0; + u32 pcfgwqos1_0; + u32 pcfgr_1; + u32 pcfgw_1; + u32 pcfgqos0_1; + u32 pcfgqos1_1; + u32 pcfgwqos0_1; + u32 pcfgwqos1_1; +}; + +struct stm32mp1_ddrphy_reg { + u32 pgcr; + u32 aciocr; + u32 dxccr; + u32 dsgcr; + u32 dcr; + u32 odtcr; + u32 zq0cr1; + u32 dx0gcr; + u32 dx1gcr; + u32 dx2gcr; + u32 dx3gcr; +}; + +struct stm32mp1_ddrphy_timing { + u32 ptr0; + u32 ptr1; + u32 ptr2; + u32 dtpr0; + u32 dtpr1; + u32 dtpr2; + u32 mr0; + u32 mr1; + u32 mr2; + u32 mr3; +}; + +struct stm32mp1_ddrphy_cal { + u32 dx0dllcr; + u32 dx0dqtr; + u32 dx0dqstr; + u32 dx1dllcr; + u32 dx1dqtr; + u32 dx1dqstr; + u32 dx2dllcr; + u32 dx2dqtr; + u32 dx2dqstr; + u32 dx3dllcr; + u32 dx3dqtr; + u32 dx3dqstr; +}; + +struct stm32mp1_ddr_info { + const char *name; + u16 speed; /* in MHZ */ + u32 size; /* memory size in byte = col * row * width */ +}; + +struct stm32mp1_ddr_config { + struct stm32mp1_ddr_info info; + struct stm32mp1_ddrctrl_reg c_reg; + struct stm32mp1_ddrctrl_timing c_timing; + struct stm32mp1_ddrctrl_map c_map; + struct stm32mp1_ddrctrl_perf c_perf; + struct stm32mp1_ddrphy_reg p_reg; + struct stm32mp1_ddrphy_timing p_timing; + struct stm32mp1_ddrphy_cal p_cal; +}; + +int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u16 mem_speed); +void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir); +void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl); +void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, + u32 rfshctl3, + u32 pwrctl); + +void stm32mp1_ddr_init( + struct ddr_info *priv, + const struct stm32mp1_ddr_config *config); + +int stm32mp1_dump_reg(const struct ddr_info *priv, + const char *name); + +void stm32mp1_edit_reg(const struct ddr_info *priv, + char *name, + char *string); + +int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config, + const char *name); + +void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config, + char *name, + char *string); + +void stm32mp1_dump_info( + const struct ddr_info *priv, + const struct stm32mp1_ddr_config *config); + +bool stm32mp1_ddr_interactive( + void *priv, + enum stm32mp1_ddr_interact_step step, + const struct stm32mp1_ddr_config *config); + +#endif diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h new file mode 100644 index 0000000..82c254b --- /dev/null +++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h @@ -0,0 +1,365 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#ifndef _RAM_STM32MP1_DDR_REGS_H +#define _RAM_STM32MP1_DDR_REGS_H + +/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */ +struct stm32mp1_ddrctl { + u32 mstr ; /* 0x0 Master*/ + u32 stat; /* 0x4 Operating Mode Status*/ + u8 reserved008[0x10 - 0x8]; + u32 mrctrl0; /* 0x10 Control 0.*/ + u32 mrctrl1; /* 0x14 Control 1*/ + u32 mrstat; /* 0x18 Status*/ + u32 reserved01c; /* 0x1c */ + u32 derateen; /* 0x20 Temperature Derate Enable*/ + u32 derateint; /* 0x24 Temperature Derate Interval*/ + u8 reserved028[0x30 - 0x28]; + u32 pwrctl; /* 0x30 Low Power Control*/ + u32 pwrtmg; /* 0x34 Low Power Timing*/ + u32 hwlpctl; /* 0x38 Hardware Low Power Control*/ + u8 reserved03c[0x50 - 0x3C]; + u32 rfshctl0; /* 0x50 Refresh Control 0*/ + u32 reserved054; /* 0x54 Refresh Control 1*/ + u32 reserved058; /* 0x58 Refresh Control 2*/ + u32 reserved05C; + u32 rfshctl3; /* 0x60 Refresh Control 0*/ + u32 rfshtmg; /* 0x64 Refresh Timing*/ + u8 reserved068[0xc0 - 0x68]; + u32 crcparctl0; /* 0xc0 CRC Parity Control0*/ + u32 reserved0c4; /* 0xc4 CRC Parity Control1*/ + u32 reserved0c8; /* 0xc8 CRC Parity Control2*/ + u32 crcparstat; /* 0xcc CRC Parity Status*/ + u32 init0; /* 0xd0 SDRAM Initialization 0*/ + u32 init1; /* 0xd4 SDRAM Initialization 1*/ + u32 init2; /* 0xd8 SDRAM Initialization 2*/ + u32 init3; /* 0xdc SDRAM Initialization 3*/ + u32 init4; /* 0xe0 SDRAM Initialization 4*/ + u32 init5; /* 0xe4 SDRAM Initialization 5*/ + u32 reserved0e8; + u32 reserved0ec; + u32 dimmctl; /* 0xf0 DIMM Control*/ + u8 reserved0f4[0x100 - 0xf4]; + u32 dramtmg0; /* 0x100 SDRAM Timing 0*/ + u32 dramtmg1; /* 0x104 SDRAM Timing 1*/ + u32 dramtmg2; /* 0x108 SDRAM Timing 2*/ + u32 dramtmg3; /* 0x10c SDRAM Timing 3*/ + u32 dramtmg4; /* 0x110 SDRAM Timing 4*/ + u32 dramtmg5; /* 0x114 SDRAM Timing 5*/ + u32 dramtmg6; /* 0x118 SDRAM Timing 6*/ + u32 dramtmg7; /* 0x11c SDRAM Timing 7*/ + u32 dramtmg8; /* 0x120 SDRAM Timing 8*/ + u8 reserved124[0x138 - 0x124]; + u32 dramtmg14; /* 0x138 SDRAM Timing 14*/ + u32 dramtmg15; /* 0x13C SDRAM Timing 15*/ + u8 reserved140[0x180 - 0x140]; + u32 zqctl0; /* 0x180 ZQ Control 0*/ + u32 zqctl1; /* 0x184 ZQ Control 1*/ + u32 zqctl2; /* 0x188 ZQ Control 2*/ + u32 zqstat; /* 0x18c ZQ Status*/ + u32 dfitmg0; /* 0x190 DFI Timing 0*/ + u32 dfitmg1; /* 0x194 DFI Timing 1*/ + u32 dfilpcfg0; /* 0x198 DFI Low Power Configuration 0*/ + u32 reserved19c; + u32 dfiupd0; /* 0x1a0 DFI Update 0*/ + u32 dfiupd1; /* 0x1a4 DFI Update 1*/ + u32 dfiupd2; /* 0x1a8 DFI Update 2*/ + u32 reserved1ac; + u32 dfimisc; /* 0x1b0 DFI Miscellaneous Control*/ + u8 reserved1b4[0x1bc - 0x1b4]; + u32 dfistat; /* 0x1bc DFI Miscellaneous Control*/ + u8 reserved1c0[0x1c4 - 0x1c0]; + u32 dfiphymstr; /* 0x1c4 DFI PHY Master interface*/ + u8 reserved1c8[0x204 - 0x1c8]; + u32 addrmap1; /* 0x204 Address Map 1*/ + u32 addrmap2; /* 0x208 Address Map 2*/ + u32 addrmap3; /* 0x20c Address Map 3*/ + u32 addrmap4; /* 0x210 Address Map 4*/ + u32 addrmap5; /* 0x214 Address Map 5*/ + u32 addrmap6; /* 0x218 Address Map 6*/ + u8 reserved21c[0x224 - 0x21c]; + u32 addrmap9; /* 0x224 Address Map 9*/ + u32 addrmap10; /* 0x228 Address Map 10*/ + u32 addrmap11; /* 0x22C Address Map 11*/ + u8 reserved230[0x240 - 0x230]; + u32 odtcfg; /* 0x240 ODT Configuration*/ + u32 odtmap; /* 0x244 ODT/Rank Map*/ + u8 reserved248[0x250 - 0x248]; + u32 sched; /* 0x250 Scheduler Control*/ + u32 sched1; /* 0x254 Scheduler Control 1*/ + u32 reserved258; + u32 perfhpr1; /* 0x25c High Priority Read CAM 1*/ + u32 reserved260; + u32 perflpr1; /* 0x264 Low Priority Read CAM 1*/ + u32 reserved268; + u32 perfwr1; /* 0x26c Write CAM 1*/ + u8 reserved27c[0x300 - 0x270]; + u32 dbg0; /* 0x300 Debug 0*/ + u32 dbg1; /* 0x304 Debug 1*/ + u32 dbgcam; /* 0x308 CAM Debug*/ + u32 dbgcmd; /* 0x30c Command Debug*/ + u32 dbgstat; /* 0x310 Status Debug*/ + u8 reserved314[0x320 - 0x314]; + u32 swctl; /* 0x320 Software Programming Control Enable*/ + u32 swstat; /* 0x324 Software Programming Control Status*/ + u8 reserved328[0x36c - 0x328]; + u32 poisoncfg; /* 0x36c AXI Poison Configuration Register*/ + u32 poisonstat; /* 0x370 AXI Poison Status Register*/ + u8 reserved374[0x3fc - 0x374]; + + /* Multi Port registers */ + u32 pstat; /* 0x3fc Port Status*/ + u32 pccfg; /* 0x400 Port Common Configuration*/ + + /* PORT 0 */ + u32 pcfgr_0; /* 0x404 Configuration Read*/ + u32 pcfgw_0; /* 0x408 Configuration Write*/ + u8 reserved40c[0x490 - 0x40c]; + u32 pctrl_0; /* 0x490 Port Control Register */ + u32 pcfgqos0_0; /* 0x494 Read QoS Configuration 0*/ + u32 pcfgqos1_0; /* 0x498 Read QoS Configuration 1*/ + u32 pcfgwqos0_0; /* 0x49c Write QoS Configuration 0*/ + u32 pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1*/ + u8 reserved4a4[0x4b4 - 0x4a4]; + + /* PORT 1 */ + u32 pcfgr_1; /* 0x4b4 Configuration Read*/ + u32 pcfgw_1; /* 0x4b8 Configuration Write*/ + u8 reserved4bc[0x540 - 0x4bc]; + u32 pctrl_1; /* 0x540 Port 2 Control Register */ + u32 pcfgqos0_1; /* 0x544 Read QoS Configuration 0*/ + u32 pcfgqos1_1; /* 0x548 Read QoS Configuration 1*/ + u32 pcfgwqos0_1; /* 0x54c Write QoS Configuration 0*/ + u32 pcfgwqos1_1; /* 0x550 Write QoS Configuration 1*/ +}; + +/* DDR Physical Interface Control (DDRPHYC) registers*/ +struct stm32mp1_ddrphy { + u32 ridr; /* 0x00 R Revision Identification*/ + u32 pir; /* 0x04 R/W PHY Initialization*/ + u32 pgcr; /* 0x08 R/W PHY General Configuration*/ + u32 pgsr; /* 0x0C PHY General Status*/ + u32 dllgcr; /* 0x10 R/W DLL General Control*/ + u32 acdllcr; /* 0x14 R/W AC DLL Control*/ + u32 ptr0; /* 0x18 R/W PHY Timing 0*/ + u32 ptr1; /* 0x1C R/W PHY Timing 1*/ + u32 ptr2; /* 0x20 R/W PHY Timing 2*/ + u32 aciocr; /* 0x24 AC I/O Configuration*/ + u32 dxccr; /* 0x28 DATX8 Common Configuration*/ + u32 dsgcr; /* 0x2C DDR System General Configuration*/ + u32 dcr; /* 0x30 DRAM Configuration*/ + u32 dtpr0; /* 0x34 DRAM Timing Parameters0*/ + u32 dtpr1; /* 0x38 DRAM Timing Parameters1*/ + u32 dtpr2; /* 0x3C DRAM Timing Parameters2*/ + u32 mr0; /* 0x40 Mode 0*/ + u32 mr1; /* 0x44 Mode 1*/ + u32 mr2; /* 0x48 Mode 2*/ + u32 mr3; /* 0x4C Mode 3*/ + u32 odtcr; /* 0x50 ODT Configuration*/ + u32 dtar; /* 0x54 data training address*/ + u32 dtdr0; /* 0x58 */ + u32 dtdr1; /* 0x5c */ + u8 res1[0x0c0 - 0x060]; /* 0x60 */ + u32 dcuar; /* 0xc0 Address*/ + u32 dcudr; /* 0xc4 DCU Data*/ + u32 dcurr; /* 0xc8 DCU Run*/ + u32 dculr; /* 0xcc DCU Loop*/ + u32 dcugcr; /* 0xd0 DCU General Configuration*/ + u32 dcutpr; /* 0xd4 DCU Timing Parameters */ + u32 dcusr0; /* 0xd8 DCU Status 0*/ + u32 dcusr1; /* 0xdc DCU Status 1*/ + u8 res2[0x100 - 0xe0]; /* 0xe0 */ + u32 bistrr; /* 0x100 BIST Run*/ + u32 bistmskr0; /* 0x104 BIST Mask 0*/ + u32 bistmskr1; /* 0x108 BIST Mask 0*/ + u32 bistwcr; /* 0x10c BIST Word Count*/ + u32 bistlsr; /* 0x110 BIST LFSR Seed*/ + u32 bistar0; /* 0x114 BIST Address 0*/ + u32 bistar1; /* 0x118 BIST Address 1*/ + u32 bistar2; /* 0x11c BIST Address 2*/ + u32 bistupdr; /* 0x120 BIST User Data Pattern*/ + u32 bistgsr; /* 0x124 BIST General Status*/ + u32 bistwer; /* 0x128 BIST Word Error*/ + u32 bistber0; /* 0x12c BIST Bit Error 0*/ + u32 bistber1; /* 0x130 BIST Bit Error 1*/ + u32 bistber2; /* 0x134 BIST Bit Error 2*/ + u32 bistwcsr; /* 0x138 BIST Word Count Status*/ + u32 bistfwr0; /* 0x13c BIST Fail Word 0*/ + u32 bistfwr1; /* 0x140 BIST Fail Word 1*/ + u8 res3[0x178 - 0x144]; /* 0x144 */ + u32 gpr0; /* 0x178 General Purpose 0 (GPR0)*/ + u32 gpr1; /* 0x17C General Purpose 1 (GPR1)*/ + u32 zq0cr0; /* 0x180 zq 0 control 0 */ + u32 zq0cr1; /* 0x184 zq 0 control 1 */ + u32 zq0sr0; /* 0x188 zq 0 status 0 */ + u32 zq0sr1; /* 0x18C zq 0 status 1 */ + u8 res4[0x1C0 - 0x190]; /* 0x190 */ + u32 dx0gcr; /* 0x1c0 Byte lane 0 General Configuration*/ + u32 dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0*/ + u32 dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1*/ + u32 dx0dllcr; /* 0x1cc Byte lane 0 DLL Control*/ + u32 dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing*/ + u32 dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing*/ + u8 res5[0x200 - 0x1d8]; /* 0x1d8 */ + u32 dx1gcr; /* 0x200 Byte lane 1 General Configuration*/ + u32 dx1gsr0; /* 0x204 Byte lane 1 General Status 0*/ + u32 dx1gsr1; /* 0x208 Byte lane 1 General Status 1*/ + u32 dx1dllcr; /* 0x20c Byte lane 1 DLL Control*/ + u32 dx1dqtr; /* 0x210 Byte lane 1 DQ Timing*/ + u32 dx1dqstr; /* 0x214 Byte lane 1 QS Timing*/ + u8 res6[0x240 - 0x218]; /* 0x218 */ + u32 dx2gcr; /* 0x240 Byte lane 2 General Configuration*/ + u32 dx2gsr0; /* 0x244 Byte lane 2 General Status 0*/ + u32 dx2gsr1; /* 0x248 Byte lane 2 General Status 1*/ + u32 dx2dllcr; /* 0x24c Byte lane 2 DLL Control*/ + u32 dx2dqtr; /* 0x250 Byte lane 2 DQ Timing*/ + u32 dx2dqstr; /* 0x254 Byte lane 2 QS Timing*/ + u8 res7[0x280 - 0x258]; /* 0x258 */ + u32 dx3gcr; /* 0x280 Byte lane 3 General Configuration*/ + u32 dx3gsr0; /* 0x284 Byte lane 3 General Status 0*/ + u32 dx3gsr1; /* 0x288 Byte lane 3 General Status 1*/ + u32 dx3dllcr; /* 0x28c Byte lane 3 DLL Control*/ + u32 dx3dqtr; /* 0x290 Byte lane 3 DQ Timing*/ + u32 dx3dqstr; /* 0x294 Byte lane 3 QS Timing*/ +}; + +#define DXN(phy, offset, byte) ((u32)(phy) + (offset) + ((u32)(byte) * 0x40)) +#define DXNGCR(phy, byte) DXN(phy, 0x1c0, byte) +#define DXNDLLCR(phy, byte) DXN(phy, 0x1cc, byte) +#define DXNDQTR(phy, byte) DXN(phy, 0x1d0, byte) +#define DXNDQSTR(phy, byte) DXN(phy, 0x1d4, byte) + +/* DDRCTRL REGISTERS */ +#define DDRCTRL_MSTR_DDR3 BIT(0) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL (0 << 12) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF (1 << 12) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER (2 << 12) +#define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15) + +#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0) +#define DDRCTRL_STAT_OPERATING_MODE_NORMAL 1 +#define DDRCTRL_STAT_OPERATING_MODE_SR 3 +#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4) +#define DDRCTRL_STAT_SELFREF_TYPE_ASR (3 << 4) +#define DDRCTRL_STAT_SELFREF_TYPE_SR (2 << 4) + +#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE 0 +/* only one rank supported */ +#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4 +#define DDRCTRL_MRCTRL0_MR_RANK_ALL \ + (0x1 << DDRCTRL_MRCTRL0_MR_RANK_SHIFT) +#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12 +#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12) +#define DDRCTRL_MRCTRL0_MR_WR BIT(31) + +#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0) + +#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) +#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) + +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) + +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16 + +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK (0xC0000000) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL (BIT(30)) + +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) + +#define DDRCTRL_DBG1_DIS_HIF BIT(1) + +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0) +#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \ + (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \ + DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY) +#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \ + (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \ + DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \ + DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH) + +#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0) + +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0) + +#define DDRCTRL_SWCTL_SW_DONE BIT(0) + +#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0) + +#define DDRCTRL_PCTRL_N_PORT_EN BIT(0) + +/* DDRPHYC registers */ +#define DDRPHYC_PIR_INIT BIT(0) +#define DDRPHYC_PIR_DLLSRST BIT(1) +#define DDRPHYC_PIR_DLLLOCK BIT(2) +#define DDRPHYC_PIR_ZCAL BIT(3) +#define DDRPHYC_PIR_ITMSRST BIT(4) +#define DDRPHYC_PIR_DRAMRST BIT(5) +#define DDRPHYC_PIR_DRAMINIT BIT(6) +#define DDRPHYC_PIR_QSTRN BIT(7) +#define DDRPHYC_PIR_ICPC BIT(16) +#define DDRPHYC_PIR_ZCALBYP BIT(30) +#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7) + +#define DDRPHYC_PGCR_DFTCMP BIT(2) +#define DDRPHYC_PGCR_PDDISDX BIT(24) +#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25) + +#define DDRPHYC_PGSR_IDONE BIT(0) +#define DDRPHYC_PGSR_DTERR BIT(5) +#define DDRPHYC_PGSR_DTIERR BIT(6) +#define DDRPHYC_PGSR_DFTERR BIT(7) +#define DDRPHYC_PGSR_RVERR BIT(8) +#define DDRPHYC_PGSR_RVEIRR BIT(9) + +#define DDRPHYC_DLLGCR_BPS200 BIT(23) + +#define DDRPHYC_ACDLLCR_DLLDIS BIT(31) + +#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0) +#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0 +#define DDRPHYC_ZQ0CRN_ZDEN BIT(28) + +#define DDRPHYC_DXNGCR_DXEN BIT(0) + +#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31) +#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14) +#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14 + +#define DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit) (4 * (bit)) +#define DDRPHYC_DXNDQTR_DQDLY_MASK GENMASK(3, 0) +#define DDRPHYC_DXNDQTR_DQDLY_LOW_MASK GENMASK(1, 0) +#define DDRPHYC_DXNDQTR_DQDLY_HIGH_MASK GENMASK(3, 2) + +#define DDRPHYC_DXNDQSTR_DQSDLY_MASK GENMASK(22, 20) +#define DDRPHYC_DXNDQSTR_DQSDLY_SHIFT 20 +#define DDRPHYC_DXNDQSTR_DQSNDLY_MASK GENMASK(25, 23) +#define DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT 23 +#define DDRPHYC_DXNDQSTR_R0DGSL_MASK GENMASK(2, 0) +#define DDRPHYC_DXNDQSTR_R0DGSL_SHIFT 0 +#define DDRPHYC_DXNDQSTR_R0DGPS_MASK GENMASK(13, 12) +#define DDRPHYC_DXNDQSTR_R0DGPS_SHIFT 12 + +#define DDRPHYC_BISTRR_BDXSEL_MASK GENMASK(22, 19) +#define DDRPHYC_BISTRR_BDXSEL_SHIFT 19 + +#define DDRPHYC_BISTGSR_BDDONE BIT(0) +#define DDRPHYC_BISTGSR_BDXERR BIT(2) + +#define DDRPHYC_BISTWCSR_DXWCNT_SHIFT 16 + +/* PWR registers */ +#define PWR_CR3 0x00C +#define PWR_CR3_DDRSRDIS BIT(11) +#define PWR_CR3_DDRRETEN BIT(12) + +#endif diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c new file mode 100644 index 0000000..9599444 --- /dev/null +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include "stm32mp1_ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +static const char *const clkname[] = { + "ddrc1", + "ddrc2", + "ddrcapb", + "ddrphycapb", + "ddrphyc" /* LAST clock => used for get_rate() */ +}; + +int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed) +{ + unsigned long ddrphy_clk; + unsigned long ddr_clk; + struct clk clk; + int ret; + int idx; + + for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) { + ret = clk_get_by_name(priv->dev, clkname[idx], &clk); + + if (!ret) + ret = clk_enable(&clk); + + if (ret) { + printf("error for %s : %d\n", clkname[idx], ret); + return ret; + } + } + + priv->clk = clk; + ddrphy_clk = clk_get_rate(&priv->clk); + + debug("DDR: mem_speed (%d MHz), RCC %d MHz\n", + mem_speed, (u32)(ddrphy_clk / 1000 / 1000)); + /* max 10% frequency delta */ + ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000); + if (ddr_clk > (mem_speed * 1000 * 100)) { + pr_err("DDR expected freq %d MHz, current is %d MHz\n", + mem_speed, (u32)(ddrphy_clk / 1000 / 1000)); + return -EINVAL; + } + + return 0; +} + +static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) +{ + struct ddr_info *priv = dev_get_priv(dev); + int ret, idx; + struct clk axidcg; + struct stm32mp1_ddr_config config; + +#define PARAM(x, y) \ + { x,\ + offsetof(struct stm32mp1_ddr_config, y),\ + sizeof(config.y) / sizeof(u32)} + +#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x) +#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x) + + const struct { + const char *name; /* name in DT */ + const u32 offset; /* offset in config struct */ + const u32 size; /* size of parameters */ + } param[] = { + CTL_PARAM(reg), + CTL_PARAM(timing), + CTL_PARAM(map), + CTL_PARAM(perf), + PHY_PARAM(reg), + PHY_PARAM(timing), + PHY_PARAM(cal) + }; + + config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0); + config.info.size = dev_read_u32_default(dev, "st,mem-size", 0); + config.info.name = dev_read_string(dev, "st,mem-name"); + if (!config.info.name) { + debug("%s: no st,mem-name\n", __func__); + return -EINVAL; + } + printf("RAM: %s\n", config.info.name); + + for (idx = 0; idx < ARRAY_SIZE(param); idx++) { + ret = dev_read_u32_array(dev, param[idx].name, + (void *)((u32)&config + + param[idx].offset), + param[idx].size); + debug("%s: %s[0x%x] = %d\n", __func__, + param[idx].name, param[idx].size, ret); + if (ret) { + pr_err("%s: Cannot read %s\n", + __func__, param[idx].name); + return -EINVAL; + } + } + + ret = clk_get_by_name(dev, "axidcg", &axidcg); + if (ret) { + debug("%s: Cannot found axidcg\n", __func__); + return -EINVAL; + } + clk_disable(&axidcg); /* disable clock gating during init */ + + stm32mp1_ddr_init(priv, &config); + + clk_enable(&axidcg); /* enable clock gating */ + + /* check size */ + debug("%s : get_ram_size(%x, %x)\n", __func__, + (u32)priv->info.base, (u32)STM32_DDR_SIZE); + + priv->info.size = get_ram_size((long *)priv->info.base, + STM32_DDR_SIZE); + + debug("%s : %x\n", __func__, (u32)priv->info.size); + + /* check memory access for all memory */ + if (config.info.size != priv->info.size) { + printf("DDR invalid size : 0x%x, expected 0x%x\n", + priv->info.size, config.info.size); + return -EINVAL; + } + return 0; +} + +static int stm32mp1_ddr_probe(struct udevice *dev) +{ + struct ddr_info *priv = dev_get_priv(dev); + struct regmap *map; + int ret; + + debug("STM32MP1 DDR probe\n"); + priv->dev = dev; + + ret = regmap_init_mem(dev, &map); + if (ret) + return ret; + + priv->ctl = regmap_get_range(map, 0); + priv->phy = regmap_get_range(map, 1); + + priv->rcc = STM32_RCC_BASE; + + priv->info.base = STM32_DDR_BASE; + +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + priv->info.size = 0; + return stm32mp1_ddr_setup(dev); +#else + priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0); + return 0; +#endif +} + +static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info) +{ + struct ddr_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops stm32mp1_ddr_ops = { + .get_info = stm32mp1_ddr_get_info, +}; + +static const struct udevice_id stm32mp1_ddr_ids[] = { + { .compatible = "st,stm32mp1-ddr" }, + { } +}; + +U_BOOT_DRIVER(ddr_stm32mp1) = { + .name = "stm32mp1_ddr", + .id = UCLASS_RAM, + .of_match = stm32mp1_ddr_ids, + .ops = &stm32mp1_ddr_ops, + .probe = stm32mp1_ddr_probe, + .priv_auto_alloc_size = sizeof(struct ddr_info), +};

- add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port

Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---

drivers/pinctrl/pinctrl_stm32.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 2066e11..31285cd 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -41,9 +41,10 @@ static int stm32_gpio_config(struct gpio_desc *desc,

return 0; } + static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin) { - gpio_dsc->port = (port_pin & 0xF000) >> 12; + gpio_dsc->port = (port_pin & 0x1F000) >> 12; gpio_dsc->pin = (port_pin & 0x0F00) >> 8; debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port, gpio_dsc->pin); @@ -115,11 +116,13 @@ static int stm32_pinctrl_config(int offset) return -EINVAL; for (i = 0; i < len; i++) { struct gpio_desc desc; + debug("%s: pinmux = %x\n", __func__, *(pin_mux + i)); prep_gpio_dsc(&gpio_dsc, *(pin_mux + i)); prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset); rv = uclass_get_device_by_seq(UCLASS_GPIO, - gpio_dsc.port, &desc.dev); + gpio_dsc.port, + &desc.dev); if (rv) return rv; desc.offset = gpio_dsc.pin; @@ -186,6 +189,8 @@ static const struct udevice_id stm32_pinctrl_ids[] = { { .compatible = "st,stm32f469-pinctrl" }, { .compatible = "st,stm32f746-pinctrl" }, { .compatible = "st,stm32h743-pinctrl" }, + { .compatible = "st,stm32mp157-pinctrl" }, + { .compatible = "st,stm32mp157-z-pinctrl" }, { } };

add RCC clock driver for STMP32MP157 - base on driver model = UCLASS_CLK - support ops to enable, disable and get rate of all SOC clock needed by U-Boot

Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---

MAINTAINERS | 1 + drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk_stm32mp1.c | 1157 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 1167 insertions(+) create mode 100644 drivers/clk/clk_stm32mp1.c

diff --git a/MAINTAINERS b/MAINTAINERS index ff7b837..052b9f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -195,6 +195,7 @@ ARM STM STM32MP M: Patrick Delaunay patrick.delaunay@st.com S: Maintained F: arch/arm/mach-stm32mp +F: clk/clk_stm32mp1.c F: ram/stm32mp1

ARM STM STV0991 diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index cdfa052..c382e88 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -75,6 +75,14 @@ config CLK_ZYNQMP This clock driver adds support for clock realted settings for ZynqMP platform.

+config CLK_STM32MP1 + bool "Enable RCC clock driver for STM32MP1" + depends on ARCH_STM32MP && CLK + default y + help + Enable the STM32 clock (RCC) driver. Enable support for + manipulating STM32MP1's on-SoC clocks. + source "drivers/clk/tegra/Kconfig" source "drivers/clk/uniphier/Kconfig" source "drivers/clk/exynos/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index dab106a..e05c607 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o +obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c new file mode 100644 index 0000000..0ea2035 --- /dev/null +++ b/drivers/clk/clk_stm32mp1.c @@ -0,0 +1,1157 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#include <common.h> +#include <clk-uclass.h> +#include <div64.h> +#include <dm.h> +#include <regmap.h> +#include <spl.h> +#include <syscon.h> +#include <linux/io.h> +#include <dt-bindings/clock/stm32mp1-clks.h> + +#define MAX_HSI_HZ 64000000 + +/* RCC registers */ +#define RCC_OCENSETR 0x0C +#define RCC_OCENCLRR 0x10 +#define RCC_HSICFGR 0x18 +#define RCC_MPCKSELR 0x20 +#define RCC_ASSCKSELR 0x24 +#define RCC_RCK12SELR 0x28 +#define RCC_MPCKDIVR 0x2C +#define RCC_AXIDIVR 0x30 +#define RCC_APB4DIVR 0x3C +#define RCC_APB5DIVR 0x40 +#define RCC_RTCDIVR 0x44 +#define RCC_MSSCKSELR 0x48 +#define RCC_PLL1CR 0x80 +#define RCC_PLL1CFGR1 0x84 +#define RCC_PLL1CFGR2 0x88 +#define RCC_PLL1FRACR 0x8C +#define RCC_PLL1CSGR 0x90 +#define RCC_PLL2CR 0x94 +#define RCC_PLL2CFGR1 0x98 +#define RCC_PLL2CFGR2 0x9C +#define RCC_PLL2FRACR 0xA0 +#define RCC_PLL2CSGR 0xA4 +#define RCC_I2C46CKSELR 0xC0 +#define RCC_CPERCKSELR 0xD0 +#define RCC_STGENCKSELR 0xD4 +#define RCC_DDRITFCR 0xD8 +#define RCC_BDCR 0x140 +#define RCC_RDLSICR 0x144 +#define RCC_MP_APB4ENSETR 0x200 +#define RCC_MP_APB5ENSETR 0x208 +#define RCC_MP_AHB5ENSETR 0x210 +#define RCC_MP_AHB6ENSETR 0x218 +#define RCC_OCRDYR 0x808 +#define RCC_DBGCFGR 0x80C +#define RCC_RCK3SELR 0x820 +#define RCC_RCK4SELR 0x824 +#define RCC_MCUDIVR 0x830 +#define RCC_APB1DIVR 0x834 +#define RCC_APB2DIVR 0x838 +#define RCC_APB3DIVR 0x83C +#define RCC_PLL3CR 0x880 +#define RCC_PLL3CFGR1 0x884 +#define RCC_PLL3CFGR2 0x888 +#define RCC_PLL3FRACR 0x88C +#define RCC_PLL3CSGR 0x890 +#define RCC_PLL4CR 0x894 +#define RCC_PLL4CFGR1 0x898 +#define RCC_PLL4CFGR2 0x89C +#define RCC_PLL4FRACR 0x8A0 +#define RCC_PLL4CSGR 0x8A4 +#define RCC_I2C12CKSELR 0x8C0 +#define RCC_I2C35CKSELR 0x8C4 +#define RCC_UART6CKSELR 0x8E4 +#define RCC_UART24CKSELR 0x8E8 +#define RCC_UART35CKSELR 0x8EC +#define RCC_UART78CKSELR 0x8F0 +#define RCC_SDMMC12CKSELR 0x8F4 +#define RCC_SDMMC3CKSELR 0x8F8 +#define RCC_ETHCKSELR 0x8FC +#define RCC_QSPICKSELR 0x900 +#define RCC_FMCCKSELR 0x904 +#define RCC_USBCKSELR 0x91C +#define RCC_MP_APB1ENSETR 0xA00 +#define RCC_MP_APB2ENSETR 0XA08 +#define RCC_MP_AHB2ENSETR 0xA18 +#define RCC_MP_AHB4ENSETR 0xA28 + +/* used for most of SELR register */ +#define RCC_SELR_SRC_MASK GENMASK(2, 0) +#define RCC_SELR_SRCRDY BIT(31) + +/* Values of RCC_MPCKSELR register */ +#define RCC_MPCKSELR_HSI 0 +#define RCC_MPCKSELR_HSE 1 +#define RCC_MPCKSELR_PLL 2 +#define RCC_MPCKSELR_PLL_MPUDIV 3 + +/* Values of RCC_ASSCKSELR register */ +#define RCC_ASSCKSELR_HSI 0 +#define RCC_ASSCKSELR_HSE 1 +#define RCC_ASSCKSELR_PLL 2 + +/* Values of RCC_MSSCKSELR register */ +#define RCC_MSSCKSELR_HSI 0 +#define RCC_MSSCKSELR_HSE 1 +#define RCC_MSSCKSELR_CSI 2 +#define RCC_MSSCKSELR_PLL 3 + +/* Values of RCC_CPERCKSELR register */ +#define RCC_CPERCKSELR_HSI 0 +#define RCC_CPERCKSELR_CSI 1 +#define RCC_CPERCKSELR_HSE 2 + +/* used for most of DIVR register : max div for RTC */ +#define RCC_DIVR_DIV_MASK GENMASK(5, 0) +#define RCC_DIVR_DIVRDY BIT(31) + +/* Masks for specific DIVR registers */ +#define RCC_APBXDIV_MASK GENMASK(2, 0) +#define RCC_MPUDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIV_MASK GENMASK(2, 0) +#define RCC_MCUDIV_MASK GENMASK(3, 0) + +/* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ +#define RCC_MP_ENCLRR_OFFSET 4 + +/* Fields of RCC_BDCR register */ +#define RCC_BDCR_LSEON BIT(0) +#define RCC_BDCR_LSEBYP BIT(1) +#define RCC_BDCR_LSERDY BIT(2) +#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSECSSON BIT(8) +#define RCC_BDCR_RTCCKEN BIT(20) +#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) +#define RCC_BDCR_RTCSRC_SHIFT 16 + +/* Fields of RCC_RDLSICR register */ +#define RCC_RDLSICR_LSION BIT(0) +#define RCC_RDLSICR_LSIRDY BIT(1) + +/* used for ALL PLLNCR registers */ +#define RCC_PLLNCR_PLLON BIT(0) +#define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_DIVPEN BIT(4) +#define RCC_PLLNCR_DIVQEN BIT(5) +#define RCC_PLLNCR_DIVREN BIT(6) +#define RCC_PLLNCR_DIVEN_SHIFT 4 + +/* used for ALL PLLNCFGR1 registers */ +#define RCC_PLLNCFGR1_DIVM_SHIFT 16 +#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) +#define RCC_PLLNCFGR1_DIVN_SHIFT 0 +#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) +/* only for PLL3 and PLL4 */ +#define RCC_PLLNCFGR1_IFRGE_SHIFT 24 +#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) + +/* used for ALL PLLNCFGR2 registers */ +#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVP_SHIFT 0 +#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVQ_SHIFT 8 +#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLLNCFGR2_DIVR_SHIFT 16 +#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) + +/* used for ALL PLLNFRACR registers */ +#define RCC_PLLNFRACR_FRACV_SHIFT 3 +#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLLNFRACR_FRACLE BIT(16) + +/* used for ALL PLLNCSGR registers */ +#define RCC_PLLNCSGR_INC_STEP_SHIFT 16 +#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLLNCSGR_MOD_PER_SHIFT 0 +#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 +#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) + +/* used for RCC_OCENSETR and RCC_OCENCLRR registers */ +#define RCC_OCENR_HSION BIT(0) +#define RCC_OCENR_CSION BIT(4) +#define RCC_OCENR_HSEON BIT(8) +#define RCC_OCENR_HSEBYP BIT(10) +#define RCC_OCENR_HSECSSON BIT(11) + +/* Fields of RCC_OCRDYR register */ +#define RCC_OCRDYR_HSIRDY BIT(0) +#define RCC_OCRDYR_HSIDIVRDY BIT(2) +#define RCC_OCRDYR_CSIRDY BIT(4) +#define RCC_OCRDYR_HSERDY BIT(8) + +/* Fields of DDRITFCR register */ +#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) +#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 +#define RCC_DDRITFCR_DDRCKMOD_SSR 0 + +/* Fields of RCC_HSICFGR register */ +#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) + +/* used for MCO related operations */ +#define RCC_MCOCFG_MCOON BIT(12) +#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) +#define RCC_MCOCFG_MCODIV_SHIFT 4 +#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) + +enum stm32mp1_parent_id { +/* + * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved + * they are used as index in osc[] as entry point + */ + _HSI, + _HSE, + _CSI, + _LSI, + _LSE, + _I2S_CKIN, + _USB_PHY_48, + NB_OSC, + +/* other parent source */ + _HSI_KER = NB_OSC, + _HSE_KER, + _HSE_KER_DIV2, + _CSI_KER, + _PLL1_P, + _PLL1_Q, + _PLL1_R, + _PLL2_P, + _PLL2_Q, + _PLL2_R, + _PLL3_P, + _PLL3_Q, + _PLL3_R, + _PLL4_P, + _PLL4_Q, + _PLL4_R, + _ACLK, + _PCLK1, + _PCLK2, + _PCLK3, + _PCLK4, + _PCLK5, + _HCLK6, + _HCLK2, + _CK_PER, + _CK_MPU, + _CK_MCU, + _PARENT_NB, + _UNKNOWN_ID = 0xff, +}; + +enum stm32mp1_parent_sel { + _I2C12_SEL, + _I2C35_SEL, + _I2C46_SEL, + _UART6_SEL, + _UART24_SEL, + _UART35_SEL, + _UART78_SEL, + _SDMMC12_SEL, + _SDMMC3_SEL, + _ETH_SEL, + _QSPI_SEL, + _FMC_SEL, + _USBPHY_SEL, + _USBO_SEL, + _STGEN_SEL, + _PARENT_SEL_NB, + _UNKNOWN_SEL = 0xff, +}; + +enum stm32mp1_pll_id { + _PLL1, + _PLL2, + _PLL3, + _PLL4, + _PLL_NB +}; + +enum stm32mp1_div_id { + _DIV_P, + _DIV_Q, + _DIV_R, + _DIV_NB, +}; + +enum stm32mp1_clksrc_id { + CLKSRC_MPU, + CLKSRC_AXI, + CLKSRC_MCU, + CLKSRC_PLL12, + CLKSRC_PLL3, + CLKSRC_PLL4, + CLKSRC_RTC, + CLKSRC_MCO1, + CLKSRC_MCO2, + CLKSRC_NB +}; + +enum stm32mp1_clkdiv_id { + CLKDIV_MPU, + CLKDIV_AXI, + CLKDIV_MCU, + CLKDIV_APB1, + CLKDIV_APB2, + CLKDIV_APB3, + CLKDIV_APB4, + CLKDIV_APB5, + CLKDIV_RTC, + CLKDIV_MCO1, + CLKDIV_MCO2, + CLKDIV_NB +}; + +enum stm32mp1_pllcfg { + PLLCFG_M, + PLLCFG_N, + PLLCFG_P, + PLLCFG_Q, + PLLCFG_R, + PLLCFG_O, + PLLCFG_NB +}; + +enum stm32mp1_pllcsg { + PLLCSG_MOD_PER, + PLLCSG_INC_STEP, + PLLCSG_SSCG_MODE, + PLLCSG_NB +}; + +enum stm32mp1_plltype { + PLL_800, + PLL_1600, + PLL_TYPE_NB +}; + +struct stm32mp1_pll { + u8 refclk_min; + u8 refclk_max; + u8 divn_max; +}; + +struct stm32mp1_clk_gate { + u16 offset; + u8 bit; + u8 index; + u8 set_clr; + u8 sel; + u8 fixed; +}; + +struct stm32mp1_clk_sel { + u16 offset; + u8 src; + u8 msk; + u8 nb_parent; + const u8 *parent; +}; + +#define REFCLK_SIZE 4 +struct stm32mp1_clk_pll { + enum stm32mp1_plltype plltype; + u16 rckxselr; + u16 pllxcfgr1; + u16 pllxcfgr2; + u16 pllxfracr; + u16 pllxcr; + u16 pllxcsgr; + u8 refclk[REFCLK_SIZE]; +}; + +struct stm32mp1_clk_data { + const struct stm32mp1_clk_gate *gate; + const struct stm32mp1_clk_sel *sel; + const struct stm32mp1_clk_pll *pll; + const int nb_gate; +}; + +struct stm32mp1_clk_priv { + fdt_addr_t base; + const struct stm32mp1_clk_data *data; + ulong osc[NB_OSC]; + struct udevice *osc_dev[NB_OSC]; +}; + +#define STM32MP1_CLK(off, b, idx, s) \ + { \ + .offset = (off), \ + .bit = (b), \ + .index = (idx), \ + .set_clr = 0, \ + .sel = (s), \ + .fixed = _UNKNOWN_ID, \ + } + +#define STM32MP1_CLK_F(off, b, idx, f) \ + { \ + .offset = (off), \ + .bit = (b), \ + .index = (idx), \ + .set_clr = 0, \ + .sel = _UNKNOWN_SEL, \ + .fixed = (f), \ + } + +#define STM32MP1_CLK_SET_CLR(off, b, idx, s) \ + { \ + .offset = (off), \ + .bit = (b), \ + .index = (idx), \ + .set_clr = 1, \ + .sel = (s), \ + .fixed = _UNKNOWN_ID, \ + } + +#define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \ + { \ + .offset = (off), \ + .bit = (b), \ + .index = (idx), \ + .set_clr = 1, \ + .sel = _UNKNOWN_SEL, \ + .fixed = (f), \ + } + +#define STM32MP1_CLK_PARENT(idx, off, s, m, p) \ + [(idx)] = { \ + .offset = (off), \ + .src = (s), \ + .msk = (m), \ + .parent = (p), \ + .nb_parent = ARRAY_SIZE((p)) \ + } + +#define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\ + p1, p2, p3, p4) \ + [(idx)] = { \ + .plltype = (type), \ + .rckxselr = (off1), \ + .pllxcfgr1 = (off2), \ + .pllxcfgr2 = (off3), \ + .pllxfracr = (off4), \ + .pllxcr = (off5), \ + .pllxcsgr = (off6), \ + .refclk[0] = (p1), \ + .refclk[1] = (p2), \ + .refclk[2] = (p3), \ + .refclk[3] = (p4), \ + } + +static const u8 stm32mp1_clks[][2] = { + {CK_PER, _CK_PER}, + {CK_MPU, _CK_MPU}, + {CK_AXI, _ACLK}, + {CK_MCU, _CK_MCU}, + {CK_HSE, _HSE}, + {CK_CSI, _CSI}, + {CK_LSI, _LSI}, + {CK_LSE, _LSE}, + {CK_HSI, _HSI}, + {CK_HSE_DIV2, _HSE_KER_DIV2}, +}; + +static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { + STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL), + STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL), + STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL), + STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL), + STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), + STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL), + STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL), + STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL), + STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL), + STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL), + STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL), + + STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), + + STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), + + STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), + + STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), + + STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), + + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), + + STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL), + + STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL), + STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), + + STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), +}; + +static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER}; +static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER}; +static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER}; +static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, + _HSE_KER}; +static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, + _HSE_KER}; +static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, + _HSE_KER}; +static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, + _HSE_KER}; +static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER}; +static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER}; +static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q}; +static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; +static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; +static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2}; +static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48}; +static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER}; + +static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { + STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents), + STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents), + STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), + STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), + STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, + uart24_parents), + STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, + uart35_parents), + STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, + uart78_parents), + STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, + sdmmc12_parents), + STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, + sdmmc3_parents), + STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents), + STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), + STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), + STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), + STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), + STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), +}; + +#ifdef STM32MP1_CLOCK_TREE_INIT +/* define characteristic of PLL according type */ +#define DIVN_MIN 24 +static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { + [PLL_800] = { + .refclk_min = 4, + .refclk_max = 16, + .divn_max = 99, + }, + [PLL_1600] = { + .refclk_min = 8, + .refclk_max = 16, + .divn_max = 199, + }, +}; +#endif /* STM32MP1_CLOCK_TREE_INIT */ + +static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { + STM32MP1_CLK_PLL(_PLL1, PLL_1600, + RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, + RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, + _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), + STM32MP1_CLK_PLL(_PLL2, PLL_1600, + RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, + RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, + _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), + STM32MP1_CLK_PLL(_PLL3, PLL_800, + RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, + RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, + _HSI, _HSE, _CSI, _UNKNOWN_ID), + STM32MP1_CLK_PLL(_PLL4, PLL_800, + RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, + RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, + _HSI, _HSE, _CSI, _I2S_CKIN), +}; + +/* Prescaler table lookups for clock computation */ +/* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ +static const u8 stm32mp1_mcu_div[16] = { + 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 +}; + +/* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/ +#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div +#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div +static const u8 stm32mp1_mpu_apbx_div[8] = { + 0, 1, 2, 3, 4, 4, 4, 4 +}; + +/* div = /1 /2 /3 /4 */ +static const u8 stm32mp1_axi_div[8] = { + 1, 2, 3, 4, 4, 4, 4, 4 +}; + +#ifdef DEBUG +static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = { + [_HSI] = "HSI", + [_HSE] = "HSE", + [_CSI] = "CSI", + [_LSI] = "LSI", + [_LSE] = "LSE", + [_I2S_CKIN] = "I2S_CKIN", + [_HSI_KER] = "HSI_KER", + [_HSE_KER] = "HSE_KER", + [_HSE_KER_DIV2] = "HSE_KER_DIV2", + [_CSI_KER] = "CSI_KER", + [_PLL1_P] = "PLL1_P", + [_PLL1_Q] = "PLL1_Q", + [_PLL1_R] = "PLL1_R", + [_PLL2_P] = "PLL2_P", + [_PLL2_Q] = "PLL2_Q", + [_PLL2_R] = "PLL2_R", + [_PLL3_P] = "PLL3_P", + [_PLL3_Q] = "PLL3_Q", + [_PLL3_R] = "PLL3_R", + [_PLL4_P] = "PLL4_P", + [_PLL4_Q] = "PLL4_Q", + [_PLL4_R] = "PLL4_R", + [_ACLK] = "ACLK", + [_PCLK1] = "PCLK1", + [_PCLK2] = "PCLK2", + [_PCLK3] = "PCLK3", + [_PCLK4] = "PCLK4", + [_PCLK5] = "PCLK5", + [_HCLK6] = "KCLK6", + [_HCLK2] = "HCLK2", + [_CK_PER] = "CK_PER", + [_CK_MPU] = "CK_MPU", + [_CK_MCU] = "CK_MCU", + [_USB_PHY_48] = "USB_PHY_48" +}; + +static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { + [_I2C12_SEL] = "I2C12", + [_I2C35_SEL] = "I2C35", + [_I2C46_SEL] = "I2C46", + [_UART6_SEL] = "UART6", + [_UART24_SEL] = "UART24", + [_UART35_SEL] = "UART35", + [_UART78_SEL] = "UART78", + [_SDMMC12_SEL] = "SDMMC12", + [_SDMMC3_SEL] = "SDMMC3", + [_ETH_SEL] = "ETH", + [_QSPI_SEL] = "QSPI", + [_FMC_SEL] = "FMC", + [_USBPHY_SEL] = "USBPHY", + [_USBO_SEL] = "USBO", + [_STGEN_SEL] = "STGEN" +}; +#endif + +static const struct stm32mp1_clk_data stm32mp1_data = { + .gate = stm32mp1_clk_gate, + .sel = stm32mp1_clk_sel, + .pll = stm32mp1_clk_pll, + .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate), +}; + +static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx) +{ + if (idx >= NB_OSC) { + debug("%s: clk id %d not found\n", __func__, idx); + return 0; + } + + debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx, + (u32)priv->osc[idx], priv->osc[idx] / 1000); + + return priv->osc[idx]; +} + +static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) +{ + const struct stm32mp1_clk_gate *gate = priv->data->gate; + int i, nb_clks = priv->data->nb_gate; + + for (i = 0; i < nb_clks; i++) { + if (gate[i].index == id) + break; + } + + if (i == nb_clks) { + printf("%s: clk id %d not found\n", __func__, (u32)id); + return -EINVAL; + } + + return i; +} + +static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv, + int i) +{ + const struct stm32mp1_clk_gate *gate = priv->data->gate; + + if (gate[i].sel > _PARENT_SEL_NB) { + printf("%s: parents for clk id %d not found\n", + __func__, i); + return -EINVAL; + } + + return gate[i].sel; +} + +static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv, + int i) +{ + const struct stm32mp1_clk_gate *gate = priv->data->gate; + + if (gate[i].fixed == _UNKNOWN_ID) + return -ENOENT; + + return gate[i].fixed; +} + +static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, + unsigned long id) +{ + const struct stm32mp1_clk_sel *sel = priv->data->sel; + int i; + int s, p; + + for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++) + if (stm32mp1_clks[i][0] == id) + return stm32mp1_clks[i][1]; + + i = stm32mp1_clk_get_id(priv, id); + if (i < 0) + return i; + + p = stm32mp1_clk_get_fixed_parent(priv, i); + if (p >= 0 && p < _PARENT_NB) + return p; + + s = stm32mp1_clk_get_sel(priv, i); + if (s < 0) + return s; + + p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk; + + if (p < sel[s].nb_parent) { +#ifdef DEBUG + debug("%s: %s clock is the parent %s of clk id %d\n", __func__, + stm32mp1_clk_parent_name[sel[s].parent[p]], + stm32mp1_clk_parent_sel_name[s], + (u32)id); +#endif + return sel[s].parent[p]; + } + + pr_err("%s: no parents defined for clk id %d\n", + __func__, (u32)id); + + return -EINVAL; +} + +static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, + int pll_id, int div_id) +{ + const struct stm32mp1_clk_pll *pll = priv->data->pll; + int divm, divn, divy, src; + ulong refclk, dfout; + u32 selr, cfgr1, cfgr2, fracr; + const u8 shift[_DIV_NB] = { + [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, + [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, + [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT }; + + debug("%s(%d, %d)\n", __func__, pll_id, div_id); + if (div_id > _DIV_NB) + return 0; + + selr = readl(priv->base + pll[pll_id].rckxselr); + cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1); + cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2); + fracr = readl(priv->base + pll[pll_id].pllxfracr); + + debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n", + pll_id, selr, cfgr1, cfgr2, fracr); + + divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; + divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; + divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; + + debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy); + + src = selr & RCC_SELR_SRC_MASK; + refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); + + debug(" refclk = %d kHz\n", (u32)(refclk / 1000)); + + /* + * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2 + * So same final result than PLL2 et 4 + * with FRACV : + * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13) + * / (DIVM + 1) * (DIVy + 1) + * without FRACV + * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1) + */ + if (fracr & RCC_PLLNFRACR_FRACLE) { + u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) + >> RCC_PLLNFRACR_FRACV_SHIFT; + dfout = (ulong)lldiv((unsigned long long)refclk * + (((divn + 1) << 13) + fracv), + ((unsigned long long)(divm + 1) * + (divy + 1)) << 13); + } else { + dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1)); + } + debug(" => dfout = %d kHz\n", (u32)(dfout / 1000)); + + return dfout; +} + +static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) +{ + u32 reg; + ulong clock = 0; + + switch (p) { + case _CK_MPU: + /* MPU sub system */ + reg = readl(priv->base + RCC_MPCKSELR); + switch (reg & RCC_SELR_SRC_MASK) { + case RCC_MPCKSELR_HSI: + clock = stm32mp1_clk_get_fixed(priv, _HSI); + break; + case RCC_MPCKSELR_HSE: + clock = stm32mp1_clk_get_fixed(priv, _HSE); + break; + case RCC_MPCKSELR_PLL: + case RCC_MPCKSELR_PLL_MPUDIV: + clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); + if (p == RCC_MPCKSELR_PLL_MPUDIV) { + reg = readl(priv->base + RCC_MPCKDIVR); + clock /= stm32mp1_mpu_div[reg & + RCC_MPUDIV_MASK]; + } + break; + } + break; + /* AXI sub system */ + case _ACLK: + case _HCLK2: + case _HCLK6: + case _PCLK4: + case _PCLK5: + reg = readl(priv->base + RCC_ASSCKSELR); + switch (reg & RCC_SELR_SRC_MASK) { + case RCC_ASSCKSELR_HSI: + clock = stm32mp1_clk_get_fixed(priv, _HSI); + break; + case RCC_ASSCKSELR_HSE: + clock = stm32mp1_clk_get_fixed(priv, _HSE); + break; + case RCC_ASSCKSELR_PLL: + clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); + break; + } + + /* System clock divider */ + reg = readl(priv->base + RCC_AXIDIVR); + clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; + + switch (p) { + case _PCLK4: + reg = readl(priv->base + RCC_APB4DIVR); + clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; + break; + case _PCLK5: + reg = readl(priv->base + RCC_APB5DIVR); + clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; + break; + default: + break; + } + break; + /* MCU sub system */ + case _CK_MCU: + case _PCLK1: + case _PCLK2: + case _PCLK3: + reg = readl(priv->base + RCC_MSSCKSELR); + switch (reg & RCC_SELR_SRC_MASK) { + case RCC_MSSCKSELR_HSI: + clock = stm32mp1_clk_get_fixed(priv, _HSI); + break; + case RCC_MSSCKSELR_HSE: + clock = stm32mp1_clk_get_fixed(priv, _HSE); + break; + case RCC_MSSCKSELR_CSI: + clock = stm32mp1_clk_get_fixed(priv, _CSI); + break; + case RCC_MSSCKSELR_PLL: + clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P); + break; + } + + /* MCU clock divider */ + reg = readl(priv->base + RCC_MCUDIVR); + clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; + + switch (p) { + case _PCLK1: + reg = readl(priv->base + RCC_APB1DIVR); + clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; + break; + case _PCLK2: + reg = readl(priv->base + RCC_APB2DIVR); + clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; + break; + case _PCLK3: + reg = readl(priv->base + RCC_APB3DIVR); + clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; + break; + case _CK_MCU: + default: + break; + } + break; + case _CK_PER: + reg = readl(priv->base + RCC_CPERCKSELR); + switch (reg & RCC_SELR_SRC_MASK) { + case RCC_CPERCKSELR_HSI: + clock = stm32mp1_clk_get_fixed(priv, _HSI); + break; + case RCC_CPERCKSELR_HSE: + clock = stm32mp1_clk_get_fixed(priv, _HSE); + break; + case RCC_CPERCKSELR_CSI: + clock = stm32mp1_clk_get_fixed(priv, _CSI); + break; + } + break; + case _HSI: + case _HSI_KER: + clock = stm32mp1_clk_get_fixed(priv, _HSI); + break; + case _CSI: + case _CSI_KER: + clock = stm32mp1_clk_get_fixed(priv, _CSI); + break; + case _HSE: + case _HSE_KER: + case _HSE_KER_DIV2: + clock = stm32mp1_clk_get_fixed(priv, _HSE); + if (p == _HSE_KER_DIV2) + clock >>= 1; + break; + case _LSI: + clock = stm32mp1_clk_get_fixed(priv, _LSI); + break; + case _LSE: + clock = stm32mp1_clk_get_fixed(priv, _LSE); + break; + /* PLL */ + case _PLL1_P: + case _PLL1_Q: + case _PLL1_R: + clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P); + break; + case _PLL2_P: + case _PLL2_Q: + case _PLL2_R: + clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P); + break; + case _PLL3_P: + case _PLL3_Q: + case _PLL3_R: + clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P); + break; + case _PLL4_P: + case _PLL4_Q: + case _PLL4_R: + clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P); + break; + /* other */ + case _USB_PHY_48: + clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48); + break; + + default: + break; + } + + debug("%s(%d) clock = %lx : %ld kHz\n", + __func__, p, clock, clock / 1000); + + return clock; +} + +static int stm32mp1_clk_enable(struct clk *clk) +{ + struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); + const struct stm32mp1_clk_gate *gate = priv->data->gate; + int i = stm32mp1_clk_get_id(priv, clk->id); + + if (i < 0) + return i; + + if (gate[i].set_clr) + writel(BIT(gate[i].bit), priv->base + gate[i].offset); + else + setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); + + debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id); + + return 0; +} + +static int stm32mp1_clk_disable(struct clk *clk) +{ + struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); + const struct stm32mp1_clk_gate *gate = priv->data->gate; + int i = stm32mp1_clk_get_id(priv, clk->id); + + if (i < 0) + return i; + + if (gate[i].set_clr) + writel(BIT(gate[i].bit), + priv->base + gate[i].offset + + RCC_MP_ENCLRR_OFFSET); + else + clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); + + debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id); + + return 0; +} + +static ulong stm32mp1_clk_get_rate(struct clk *clk) +{ + struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); + int p = stm32mp1_clk_get_parent(priv, clk->id); + ulong rate; + + if (p < 0) + return 0; + + rate = stm32mp1_clk_get(priv, p); + +#ifdef DEBUG + debug("%s: computed rate for id clock %d is %d (parent is %s)\n", + __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]); +#endif + return rate; +} + +static void stm32mp1_osc_clk_init(const char *name, + struct stm32mp1_clk_priv *priv, + int index) +{ + struct clk clk; + struct udevice *dev = NULL; + + priv->osc[index] = 0; + clk.id = 0; + if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { + if (clk_request(dev, &clk)) + pr_err("%s request", name); + else + priv->osc[index] = clk_get_rate(&clk); + } + priv->osc_dev[index] = dev; +} + +static void stm32mp1_osc_init(struct udevice *dev) +{ + struct stm32mp1_clk_priv *priv = dev_get_priv(dev); + int i; + const char *name[NB_OSC] = { + [_LSI] = "clk-lsi", + [_LSE] = "clk-lse", + [_HSI] = "clk-hsi", + [_HSE] = "clk-hse", + [_CSI] = "clk-csi", + [_I2S_CKIN] = "i2s_ckin", + [_USB_PHY_48] = "ck_usbo_48m"}; + + for (i = 0; i < NB_OSC; i++) { + stm32mp1_osc_clk_init(name[i], priv, i); + debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]); + } +} + +static int stm32mp1_clk_probe(struct udevice *dev) +{ + int result = 0; + struct stm32mp1_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev->parent); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->data = (void *)&stm32mp1_data; + + if (!priv->data->gate || !priv->data->sel || + !priv->data->pll) + return -EINVAL; + + stm32mp1_osc_init(dev); + + return result; +} + +static const struct clk_ops stm32mp1_clk_ops = { + .enable = stm32mp1_clk_enable, + .disable = stm32mp1_clk_disable, + .get_rate = stm32mp1_clk_get_rate, +}; + +static const struct udevice_id stm32mp1_clk_ids[] = { + { .compatible = "st,stm32mp1-rcc-clk" }, + { } +}; + +U_BOOT_DRIVER(stm32mp1_clock) = { + .name = "stm32mp1_clk", + .id = UCLASS_CLK, + .of_match = stm32mp1_clk_ids, + .ops = &stm32mp1_clk_ops, + .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv), + .probe = stm32mp1_clk_probe, +};

Add minimal devicetree for STM32MP157C-ED1 board, with only the devices to allow boot from SDCARD: - RCC for clock and reset - UART4 for console - I2C and PMIC - DDR - SDMMC0 for SDCard

Waiting Kernel upstream for alignment.

Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---

arch/arm/dts/Makefile | 3 + arch/arm/dts/stm32mp15-ddr.dtsi | 155 +++++++++++ arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 122 +++++++++ arch/arm/dts/stm32mp157-u-boot.dtsi | 134 +++++++++ arch/arm/dts/stm32mp157.dtsi | 303 +++++++++++++++++++++ arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 133 +++++++++ arch/arm/dts/stm32mp157c-ed1.dts | 167 ++++++++++++ include/dt-bindings/clock/stm32mp1-clks.h | 243 +++++++++++++++++ .../dt-bindings/reset-controller/stm32mp1-resets.h | 97 +++++++ 9 files changed, 1357 insertions(+) create mode 100644 arch/arm/dts/stm32mp15-ddr.dtsi create mode 100644 arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi create mode 100644 arch/arm/dts/stm32mp157-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157.dtsi create mode 100644 arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157c-ed1.dts create mode 100644 include/dt-bindings/clock/stm32mp1-clks.h create mode 100644 include/dt-bindings/reset-controller/stm32mp1-resets.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c7695aa..95e7c06 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -496,6 +496,9 @@ dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb

dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb

+dtb-$(CONFIG_TARGET_STM32MP1) += \ + stm32mp157c-ed1.dtb + targets += $(dtb-y)

# Add any required device tree compiler flags here diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi new file mode 100644 index 0000000..ddfa079 --- /dev/null +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -0,0 +1,155 @@ +/* + * Copyright : STMicroelectronics 2018 + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +/ { + soc { + ddr: ddr@0x5A003000{ + u-boot,dm-pre-reloc; + + compatible = "st,stm32mp1-ddr"; + + reg = <0x5A003000 0x550 + 0x5A004000 0x234>; + + clocks = <&rcc_clk AXIDCG>, + <&rcc_clk DDRC1>, + <&rcc_clk DDRC2>, + <&rcc_clk DDRPHYC>, + <&rcc_clk DDRCAPB>, + <&rcc_clk DDRPHYCAPB>; + + clock-names = "axidcg", + "ddrc1", + "ddrc2", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + + st,mem-name = DDR_MEM_NAME; + st,mem-speed = <DDR_MEM_SPEED>; + st,mem-size = <DDR_MEM_SIZE>; + + st,ctl-reg = < + DDR_MSTR + DDR_MRCTRL0 + DDR_MRCTRL1 + DDR_DERATEEN + DDR_DERATEINT + DDR_PWRCTL + DDR_PWRTMG + DDR_HWLPCTL + DDR_RFSHCTL0 + DDR_RFSHCTL3 + DDR_CRCPARCTL0 + DDR_ZQCTL0 + DDR_DFITMG0 + DDR_DFITMG1 + DDR_DFILPCFG0 + DDR_DFIUPD0 + DDR_DFIUPD1 + DDR_DFIUPD2 + DDR_DFIPHYMSTR + DDR_ODTMAP + DDR_DBG0 + DDR_DBG1 + DDR_DBGCMD + DDR_POISONCFG + DDR_PCCFG + >; + + st,ctl-timing = < + DDR_RFSHTMG + DDR_DRAMTMG0 + DDR_DRAMTMG1 + DDR_DRAMTMG2 + DDR_DRAMTMG3 + DDR_DRAMTMG4 + DDR_DRAMTMG5 + DDR_DRAMTMG6 + DDR_DRAMTMG7 + DDR_DRAMTMG8 + DDR_DRAMTMG14 + DDR_ODTCFG + >; + + st,ctl-map = < + DDR_ADDRMAP1 + DDR_ADDRMAP2 + DDR_ADDRMAP3 + DDR_ADDRMAP4 + DDR_ADDRMAP5 + DDR_ADDRMAP6 + DDR_ADDRMAP9 + DDR_ADDRMAP10 + DDR_ADDRMAP11 + >; + + st,ctl-perf = < + DDR_SCHED + DDR_SCHED1 + DDR_PERFHPR1 + DDR_PERFLPR1 + DDR_PERFWR1 + DDR_PCFGR_0 + DDR_PCFGW_0 + DDR_PCFGQOS0_0 + DDR_PCFGQOS1_0 + DDR_PCFGWQOS0_0 + DDR_PCFGWQOS1_0 + DDR_PCFGR_1 + DDR_PCFGW_1 + DDR_PCFGQOS0_1 + DDR_PCFGQOS1_1 + DDR_PCFGWQOS0_1 + DDR_PCFGWQOS1_1 + >; + + st,phy-reg = < + DDR_PGCR + DDR_ACIOCR + DDR_DXCCR + DDR_DSGCR + DDR_DCR + DDR_ODTCR + DDR_ZQ0CR1 + DDR_DX0GCR + DDR_DX1GCR + DDR_DX2GCR + DDR_DX3GCR + >; + + st,phy-timing = < + DDR_PTR0 + DDR_PTR1 + DDR_PTR2 + DDR_DTPR0 + DDR_DTPR1 + DDR_DTPR2 + DDR_MR0 + DDR_MR1 + DDR_MR2 + DDR_MR3 + >; + + st,phy-cal = < + DDR_DX0DLLCR + DDR_DX0DQTR + DDR_DX0DQSTR + DDR_DX1DLLCR + DDR_DX1DQTR + DDR_DX1DQSTR + DDR_DX2DLLCR + DDR_DX2DQTR + DDR_DX2DQSTR + DDR_DX3DLLCR + DDR_DX3DQTR + DDR_DX3DQSTR + >; + + status = "okay"; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi new file mode 100644 index 0000000..352e470 --- /dev/null +++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +/* STM32MP157C ED1 and ED2 BOARD configuration + * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used NT5CC256M16DP-DI from NANYA + * + * DDR type / Platform DDR3/3L + * freq 533MHz + * width 32 + * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G + * DDR density 8 + * timing mode optimized + * Scheduling/QoS options : type = 2 + * address mapping : RBC + */ + +#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36" +#define DDR_MEM_SPEED 533 +#define DDR_MEM_SIZE 0x40000000 + +#define DDR_MSTR 0x00040401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041C +#define DDR_DRAMTMG2 0x0608090F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x08040608 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02060105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x07070707 +#define DDR_ADDRMAP6 0x0F070707 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00001201 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x01000001 +#define DDR_PERFLPR1 0x08000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00010000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x02100B03 +#define DDR_PCFGQOS1_0 0x00800100 +#define DDR_PCFGWQOS0_0 0x01100B03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PCFGR_1 0x00010000 +#define DDR_PCFGW_1 0x00000000 +#define DDR_PCFGQOS0_1 0x02100B03 +#define DDR_PCFGQOS1_1 0x00800100 +#define DDR_PCFGWQOS0_1 0x01100B03 +#define DDR_PCFGWQOS1_1 0x01000200 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200001F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x38D488D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000840 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x0000005B +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX0DLLCR 0x40000000 +#define DDR_DX0DQTR 0xFFFFFFFF +#define DDR_DX0DQSTR 0x3DB02000 +#define DDR_DX1GCR 0x0000CE81 +#define DDR_DX1DLLCR 0x40000000 +#define DDR_DX1DQTR 0xFFFFFFFF +#define DDR_DX1DQSTR 0x3DB02000 +#define DDR_DX2GCR 0x0000CE81 +#define DDR_DX2DLLCR 0x40000000 +#define DDR_DX2DQTR 0xFFFFFFFF +#define DDR_DX2DQSTR 0x3DB02000 +#define DDR_DX3GCR 0x0000CE81 +#define DDR_DX3DLLCR 0x40000000 +#define DDR_DX3DQTR 0xFFFFFFFF +#define DDR_DX3DQSTR 0x3DB02000 + +#include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi new file mode 100644 index 0000000..d374b2b --- /dev/null +++ b/arch/arm/dts/stm32mp157-u-boot.dtsi @@ -0,0 +1,134 @@ +/* + * Copyright : STMicroelectronics 2018 + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +/ { + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + gpio25 = &gpioz; + }; + + config { + u-boot,dm-pre-reloc; + }; + + clocks { + u-boot,dm-pre-reloc; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&clk_hsi { + u-boot,dm-pre-reloc; +}; + +&clk_hse { + u-boot,dm-pre-reloc; +}; + +&clk_lse { + u-boot,dm-pre-reloc; +}; + +&clk_lsi { + u-boot,dm-pre-reloc; +}; + +&clk_csi { + u-boot,dm-pre-reloc; +}; + +&rcc { + u-boot,dm-pre-reloc; +}; + +&rcc_clk { + u-boot,dm-pre-reloc; +}; + +&rcc_rst { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pinctrl_z { + u-boot,dm-pre-reloc; +}; + +&gpioa { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiob { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioc { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiod { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioe { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiof { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiog { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioh { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioi { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioj { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiok { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioz { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi new file mode 100644 index 0000000..32d3984 --- /dev/null +++ b/arch/arm/dts/stm32mp157.dtsi @@ -0,0 +1,303 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/stm32mp1-clks.h> +#include <dt-bindings/reset-controller/stm32mp1-resets.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + aliases { + serial3 = &uart4; + }; + + intc: interrupt-controller@a0021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xa0021000 0x1000>, + <0xa0022000 0x2000>; + }; + + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_csi: clk-csi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; + clocks = <&rcc_clk UART4_K>; + status = "disabled"; + }; + + rcc: rcc@50000000 { + compatible = "syscon", "simple-mfd"; + + reg = <0x50000000 0x1000>; + + rcc_clk: rcc-clk@50000000 { + #clock-cells = <1>; + compatible = "st,stm32mp1-rcc-clk"; + }; + + rcc_rst: rcc-reset@50000000 { + #reset-cells = <1>; + compatible = "st,stm32mp1-rcc-rst"; + }; + }; + + pinctrl: pin-controller { + compatible = "st,stm32mp157-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50002000 0xa400>; + pins-are-numbered; + + gpioa: gpio@50002000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc_clk GPIOA>; + st,bank-name = "GPIOA"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + status = "disabled"; + }; + + gpiob: gpio@50003000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc_clk GPIOB>; + st,bank-name = "GPIOB"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + status = "disabled"; + }; + + gpioc: gpio@50004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc_clk GPIOC>; + st,bank-name = "GPIOC"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + status = "disabled"; + }; + + gpiod: gpio@50005000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x400>; + clocks = <&rcc_clk GPIOD>; + st,bank-name = "GPIOD"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + status = "disabled"; + }; + + gpioe: gpio@50006000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x400>; + clocks = <&rcc_clk GPIOE>; + st,bank-name = "GPIOE"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + status = "disabled"; + }; + + gpiof: gpio@50007000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x400>; + clocks = <&rcc_clk GPIOF>; + st,bank-name = "GPIOF"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + status = "disabled"; + }; + + gpiog: gpio@50008000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x6000 0x400>; + clocks = <&rcc_clk GPIOG>; + st,bank-name = "GPIOG"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + status = "disabled"; + }; + + gpioh: gpio@50009000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x7000 0x400>; + clocks = <&rcc_clk GPIOH>; + st,bank-name = "GPIOH"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + status = "disabled"; + }; + + gpioi: gpio@5000a000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x8000 0x400>; + clocks = <&rcc_clk GPIOI>; + st,bank-name = "GPIOI"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + status = "disabled"; + }; + + gpioj: gpio@5000b000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x9000 0x400>; + clocks = <&rcc_clk GPIOJ>; + st,bank-name = "GPIOJ"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + status = "disabled"; + }; + + gpiok: gpio@5000c000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa000 0x400>; + clocks = <&rcc_clk GPIOK>; + st,bank-name = "GPIOK"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + status = "disabled"; + }; + }; + + pinctrl_z: pin-controller-z { + compatible = "st,stm32mp157-z-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x54004000 0x400>; + pins-are-numbered; + + gpioz: gpio@54004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&rcc_clk GPIOZ>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + ngpios = <8>; + gpio-ranges = <&pinctrl_z 0 400 8>; + status = "disabled"; + }; + }; + + sdmmc1: sdmmc@58005000 { + compatible = "st,stm32-sdmmc2"; + reg = <0x58005000 0x1000>, <0x58006000 0x1000>; + reg-names = "sdmmc", "delay"; + clocks = <&rcc_clk SDMMC1_K>; + resets = <&rcc_rst SDMMC1_R>; + st,idma = <1>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + + i2c4: i2c@5c002000 { + compatible = "st,stm32f7-i2c"; + reg = <0x5c002000 0x400>; + interrupt-names = "event", "error", "wakeup"; + clocks = <&rcc_clk I2C4_K>; + resets = <&rcc_rst I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-source; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi new file mode 100644 index 0000000..94d27fb --- /dev/null +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -0,0 +1,133 @@ +/* + * Copyright : STMicroelectronics 2018 + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#include <dt-bindings/clock/stm32mp1-clksrc.h> +#include "stm32mp157-u-boot.dtsi" +#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" + +/ { + aliases { + mmc0 = &sdmmc1; + i2c3 = &i2c4; + }; +}; + +&uart4_pins_a { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; +}; + +&i2c4_pins_a { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&i2c4 { + u-boot,dm-pre-reloc; +}; + +&pmic { + u-boot,dm-pre-reloc; +}; + +/* CLOCK init */ +&rcc_clk { + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; + + st,pkcs = < + CLK_CKPER_DISABLED + CLK_SDMMC12_PLL3R + CLK_I2C46_PCLK5 + CLK_I2C12_PCLK1 + CLK_I2C35_PCLK1 + CLK_UART1_PCLK5 + CLK_UART24_PCLK1 + CLK_UART35_PCLK1 + CLK_UART6_PCLK2 + CLK_UART78_PCLK1 + >; + + /* VCO = 1300.0 MHz => P = 650 (CPU) */ + pll1: st,pll@0 { + cfg = < 2 80 0 0 0 PQR(1,0,0) >; + frac = < 0x800 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ + pll2: st,pll@1 { + cfg = < 2 65 1 0 0 PQR(1,1,1) >; + frac = < 0x1400 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */ + pll3: st,pll@2 { + cfg = < 3 128 3 20 7 PQR(1,1,1) >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */ + pll4: st,pll@3 { + cfg = < 5 126 8 8 8 PQR(1,1,1) >; + u-boot,dm-pre-reloc; + }; +}; + +/* SPL part **************************************/ +/* MMC1 boot */ +&sdmmc1_b4_pins_a { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&sdmmc1_dir_pins_a { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&sdmmc1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts new file mode 100644 index 0000000..4b20fab --- /dev/null +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Ludovic Barre ludovic.barre@st.com for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +/ { + model = "STMicroelectronics STM32MP157C pmic eval daughter"; + compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; + + chosen { + bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram"; + stdout-path = "serial3:115200n8"; + }; + + memory { + reg = <0xC0000000 0x40000000>; + }; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +&gpiog { + status = "okay"; +}; + +&gpioh { + status = "okay"; +}; + +&gpioi { + status = "okay"; +}; + +&gpioj { + status = "okay"; +}; + +&gpiok { + status = "okay"; +}; + +&gpioz { + status = "okay"; +}; + +&pinctrl { + uart4_pins_a: uart4@0 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4@0 { + pins { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir@0 { + pins { + pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */ + <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + }; +}; + +&pinctrl_z { + i2c4_pins_a: i2c4@0 { + pins { + pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ + <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + pmic: stpmu1@33 { + compatible = "st,stpmu1"; + reg = <0x33>; + interrupts = <0 2>; + interrupt-parent = <&gpioa>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + broken-cd; + st,dirpol; + st,negedge; + st,pin-ckin; + bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h new file mode 100644 index 0000000..1643158 --- /dev/null +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Gabriel Fernandez gabriel.fernandez@st.com for STMicroelectronics. + */ +/* OSCILLATOR clocks */ +#define CK_HSE 0 +#define CK_CSI 1 +#define CK_LSI 2 +#define CK_LSE 3 +#define CK_HSI 4 +#define CK_HSE_DIV2 5 + +/* Bus clocks */ +#define TIM2 6 +#define TIM3 7 +#define TIM4 8 +#define TIM5 9 +#define TIM6 10 +#define TIM7 11 +#define TIM12 12 +#define TIM13 13 +#define TIM14 14 +#define LPTIM1 15 +#define SPI2 16 +#define SPI3 17 +#define USART2 18 +#define USART3 19 +#define UART4 20 +#define UART5 21 +#define UART7 22 +#define UART8 23 +#define I2C1 24 +#define I2C2 25 +#define I2C3 26 +#define I2C5 27 +#define SPDIF 28 +#define CEC 29 +#define DAC12 30 +#define MDIO 31 +#define TIM1 32 +#define TIM8 33 +#define TIM15 34 +#define TIM16 35 +#define TIM17 36 +#define SPI1 37 +#define SPI4 38 +#define SPI5 39 +#define USART6 40 +#define SAI1 41 +#define SAI2 42 +#define SAI3 43 +#define DFSDM 44 +#define FDCAN 45 +#define LPTIM2 46 +#define LPTIM3 47 +#define LPTIM4 48 +#define LPTIM5 49 +#define SAI4 50 +#define SYSCFG 51 +#define VREF 52 +#define TMPSENS 53 +#define PMBCTRL 54 +#define HDP 55 +#define LTDC 56 +#define DSI 57 +#define IWDG2 58 +#define USBPHY 59 +#define STGENRO 60 +#define SPI6 61 +#define I2C4 62 +#define I2C6 63 +#define USART1 64 +#define RTCAPB 65 +#define TZC 66 +#define TZPC 67 +#define IWDG1 68 +#define BSEC 69 +#define STGEN 70 +#define DMA1 71 +#define DMA2 72 +#define DMAMUX 73 +#define ADC12 74 +#define USBO 75 +#define SDMMC3 76 +#define DCMI 77 +#define CRYP2 78 +#define HASH2 79 +#define RNG2 80 +#define CRC2 81 +#define HSEM 82 +#define IPCC 83 +#define GPIOA 84 +#define GPIOB 85 +#define GPIOC 86 +#define GPIOD 87 +#define GPIOE 88 +#define GPIOF 89 +#define GPIOG 90 +#define GPIOH 91 +#define GPIOI 92 +#define GPIOJ 93 +#define GPIOK 94 +#define GPIOZ 95 +#define CRYP1 96 +#define HASH1 97 +#define RNG1 98 +#define BKPSRAM 99 +#define MDMA 100 +#define DMA2D 101 +#define GPU 102 +#define ETHCK 103 +#define ETHTX 104 +#define ETHRX 105 +#define ETHMAC 106 +#define FMC 107 +#define QSPI 108 +#define SDMMC1 109 +#define SDMMC2 110 +#define CRC1 111 +#define USBH 112 +#define ETHSTP 113 + +/* Kernel clocks */ +#define SDMMC1_K 114 +#define SDMMC2_K 115 +#define SDMMC3_K 116 +#define FMC_K 117 +#define QSPI_K 118 +#define ETHMAC_K 119 +#define RNG1_K 120 +#define RNG2_K 121 +#define GPU_K 122 +#define USBPHY_K 123 +#define STGEN_K 124 +#define SPDIF_K 125 +#define SPI1_K 126 +#define SPI2_K 127 +#define SPI3_K 128 +#define SPI4_K 129 +#define SPI5_K 130 +#define SPI6_K 131 +#define CEC_K 132 +#define I2C1_K 133 +#define I2C2_K 134 +#define I2C3_K 135 +#define I2C4_K 136 +#define I2C5_K 137 +#define I2C6_K 138 +#define LPTIM1_K 139 +#define LPTIM2_K 140 +#define LPTIM3_K 141 +#define LPTIM4_K 142 +#define LPTIM5_K 143 +#define USART1_K 144 +#define USART2_K 145 +#define USART3_K 146 +#define UART4_K 147 +#define UART5_K 148 +#define USART6_K 149 +#define UART7_K 150 +#define UART8_K 151 +#define DFSDM_K 152 +#define FDCAN_K 153 +#define SAI1_K 154 +#define SAI2_K 155 +#define SAI3_K 156 +#define SAI4_K 157 +#define ADC12_K 158 +#define DSI_K 159 +#define ADFSDM_K 160 +#define USBO_K 161 +#define LTDC_K 162 + +/* PLL */ +#define PLL1 163 +#define PLL2 164 +#define PLL3 165 +#define PLL4 166 + +/* ODF */ +#define PLL1_P 167 +#define PLL1_Q 168 +#define PLL1_R 169 +#define PLL2_P 170 +#define PLL2_Q 171 +#define PLL2_R 172 +#define PLL3_P 173 +#define PLL3_Q 174 +#define PLL3_R 175 +#define PLL4_P 176 +#define PLL4_Q 177 +#define PLL4_R 178 + +/* AUX */ +#define RTC 179 + +/* MCLK */ +#define CK_PER 180 +#define CK_MPU 181 +#define CK_AXI 182 +#define CK_MCU 183 + +/* Time base */ +#define TIM2_K 184 +#define TIM3_K 185 +#define TIM4_K 186 +#define TIM5_K 187 +#define TIM6_K 188 +#define TIM7_K 189 +#define TIM12_K 190 +#define TIM13_K 191 +#define TIM14_K 192 +#define TIM1_K 193 +#define TIM8_K 194 +#define TIM15_K 195 +#define TIM16_K 196 +#define TIM17_K 197 + +/* MCO clocks */ +#define CK_MCO1 198 +#define CK_MCO2 199 + +/* TRACE & DEBUG clocks */ +#define DBG 200 +#define CK_DBG 201 +#define CK_TRACE 202 + +/* DDR */ +#define DDRC1 203 +#define DDRC1LP 204 +#define DDRC2 205 +#define DDRC2LP 206 +#define DDRPHYC 207 +#define DDRPHYCLP 208 +#define DDRCAPB 209 +#define DDRCAPBLP 210 +#define AXIDCG 211 +#define DDRPHYCAPB 212 +#define DDRPHYCAPBLP 213 +#define DDRPERFM 214 + +#define STM32MP1_LAST_CLK 215 diff --git a/include/dt-bindings/reset-controller/stm32mp1-resets.h b/include/dt-bindings/reset-controller/stm32mp1-resets.h new file mode 100644 index 0000000..f279f8f --- /dev/null +++ b/include/dt-bindings/reset-controller/stm32mp1-resets.h @@ -0,0 +1,97 @@ +#define LTDC_R 3072 +#define DSI_R 3076 +#define DDRPERFM_R 3080 +#define USBPHY_R 3088 +#define SPI6_R 3136 +#define I2C4_R 3138 +#define I2C6_R 3139 +#define USART1_R 3140 +#define STGEN_R 3156 +#define GPIOZ_R 3200 +#define CRYP1_R 3204 +#define HASH1_R 3205 +#define RNG1_R 3206 +#define AXIM_R 3216 +#define GPU_R 3269 +#define ETHMAC_R 3274 +#define FMC_R 3276 +#define QSPI_R 3278 +#define SDMMC1_R 3280 +#define SDMMC2_R 3281 +#define CRC1_R 3284 +#define USBH_R 3288 +#define MDMA_R 3328 +#define MCU_R 8225 +#define TIM2_R 19456 +#define TIM3_R 19457 +#define TIM4_R 19458 +#define TIM5_R 19459 +#define TIM6_R 19460 +#define TIM7_R 19461 +#define TIM12_R 16462 +#define TIM13_R 16463 +#define TIM14_R 16464 +#define LPTIM1_R 19465 +#define SPI2_R 19467 +#define SPI3_R 19468 +#define USART2_R 19470 +#define USART3_R 19471 +#define UART4_R 19472 +#define UART5_R 19473 +#define UART7_R 19474 +#define UART8_R 19475 +#define I2C1_R 19477 +#define I2C2_R 19478 +#define I2C3_R 19479 +#define I2C5_R 19480 +#define SPDIF_R 19482 +#define CEC_R 19483 +#define DAC12_R 19485 +#define MDIO_R 19847 +#define TIM1_R 19520 +#define TIM8_R 19521 +#define TIM15_R 19522 +#define TIM16_R 19523 +#define TIM17_R 19524 +#define SPI1_R 19528 +#define SPI4_R 19529 +#define SPI5_R 19530 +#define USART6_R 19533 +#define SAI1_R 19536 +#define SAI2_R 19537 +#define SAI3_R 19538 +#define DFSDM_R 19540 +#define FDCAN_R 19544 +#define LPTIM2_R 19584 +#define LPTIM3_R 19585 +#define LPTIM4_R 19586 +#define LPTIM5_R 19587 +#define SAI4_R 19592 +#define SYSCFG_R 19595 +#define VREF_R 19597 +#define TMPSENS_R 19600 +#define PMBCTRL_R 19601 +#define DMA1_R 19648 +#define DMA2_R 19649 +#define DMAMUX_R 19650 +#define ADC12_R 19653 +#define USBO_R 19656 +#define SDMMC3_R 19664 +#define CAMITF_R 19712 +#define CRYP2_R 19716 +#define HASH2_R 19717 +#define RNG2_R 19718 +#define CRC2_R 19719 +#define HSEM_R 19723 +#define MBOX_R 19724 +#define GPIOA_R 19776 +#define GPIOB_R 19777 +#define GPIOC_R 19778 +#define GPIOD_R 19779 +#define GPIOE_R 19780 +#define GPIOF_R 19781 +#define GPIOG_R 19782 +#define GPIOH_R 19783 +#define GPIOI_R 19784 +#define GPIOJ_R 19785 +#define GPIOK_R 19786