[v1 0/2] Store QSPI reference clock in kHz for SOCFPGA SOC64
This patchset is extracted from "Add Intel Diamond Mesa SoC support" series. We are in preparation to support new Intel N5X (Diamond Mesa) SOC64 device and we would like to clean up some code before enable N5X device.
This patchset move duplicated function 'cm_get_qspi_controller_clk_hz' to clock_manager.c and change to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex.
History: --------
The first version of this patchset is extracted from "Add Intel Diamond Mesa SoC support" series. https://patchwork.ozlabs.org/project/uboot/cover/20201110064439.9683-1-elly....
This patchset has dependency on: -------- 1. arm: socfpga: Move Stratix10 and Agilex SPL common code https://patchwork.ozlabs.org/project/uboot/patch/20210315075916.26336-1-elly...
2. Restructure Stratix10 and Agilex handoff code https://patchwork.ozlabs.org/project/uboot/cover/20210315094329.30282-1-elly...
Siew Chin Lim (2): arm: socfpga: Move Stratix10 and Agilex clock manager common code arm: socfpga: Changed to store QSPI reference clock in kHz
arch/arm/mach-socfpga/clock_manager.c | 16 +++++++-- arch/arm/mach-socfpga/clock_manager_agilex.c | 6 ---- arch/arm/mach-socfpga/clock_manager_s10.c | 6 ---- arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 +++ .../mach-socfpga/include/mach/clock_manager_s10.h | 1 - .../include/mach/system_manager_soc64.h | 16 ++++++++- arch/arm/mach-socfpga/mailbox_s10.c | 40 +++++++++++++++++++--- include/configs/socfpga_soc64_common.h | 1 + 8 files changed, 69 insertions(+), 21 deletions(-)
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com --- arch/arm/mach-socfpga/clock_manager.c | 15 ++++++++++++--- arch/arm/mach-socfpga/clock_manager_agilex.c | 6 ------ arch/arm/mach-socfpga/clock_manager_s10.c | 6 ------ arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 ++++ arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 - 5 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index f0b15f770c..be426a5cfb 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -4,12 +4,13 @@ */
#include <common.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/global_data.h> +#include <asm/io.h> #include <command.h> #include <init.h> #include <wait_bit.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -63,6 +64,14 @@ int set_cpu_clk_info(void) return 0; }
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +unsigned int cm_get_qspi_controller_clk_hz(void) +{ + return readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); +} +#endif + #ifndef CONFIG_SPL_BUILD static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c index 6377f2ce3b..e035c09aae 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -65,12 +65,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void) return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK); }
-u32 cm_get_qspi_controller_clk_hz(void) -{ - return readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_BOOT_SCRATCH_COLD0); -} - void cm_print_clock_quick_summary(void) { printf("MPU %10d kHz\n", diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index e060e5754e..4b4f0749db 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -384,12 +384,6 @@ unsigned int cm_get_l4_sp_clk_hz(void) return clock; }
-unsigned int cm_get_qspi_controller_clk_hz(void) -{ - return readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_BOOT_SCRATCH_COLD0); -} - unsigned int cm_get_spi_controller_clk_hz(void) { u32 clock = cm_get_l3_main_clk_hz(); diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 1f734bcd65..0f0cb230fa 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void); void cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void cm_print_clock_quick_summary(void); + +#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +unsigned int cm_get_qspi_controller_clk_hz(void); +#endif #endif
#if defined(CONFIG_TARGET_SOCFPGA_GEN5) diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index cb7923baef..98c3bf1b03 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -15,7 +15,6 @@ unsigned long cm_get_mpu_clk_hz(void); unsigned long cm_get_sdram_clk_hz(void); unsigned int cm_get_l4_sp_clk_hz(void); unsigned int cm_get_mmc_controller_clk_hz(void); -unsigned int cm_get_qspi_controller_clk_hz(void); unsigned int cm_get_spi_controller_clk_hz(void);
struct cm_config {
-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Monday, March 15, 2021 10:37 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
arch/arm/mach-socfpga/clock_manager.c | 15 ++++++++++++--- arch/arm/mach-socfpga/clock_manager_agilex.c | 6 ------ arch/arm/mach-socfpga/clock_manager_s10.c | 6 ------ arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 ++++ arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 - 5 files changed, 16 insertions(+), 16 deletions(-)
[...]
unsigned int cm_get_spi_controller_clk_hz(void) { u32 clock = cm_get_l3_main_clk_hz(); diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 1f734bcd65..0f0cb230fa 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void); void cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void cm_print_clock_quick_summary(void);
+#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +unsigned int cm_get_qspi_controller_clk_hz(void); +#endif #endif
If this is for soc64, move to _SOC64.h file?
Regards Ley Foon
Hi Ley Foon,
-----Original Message----- From: Tan, Ley Foon ley.foon.tan@intel.com Sent: Tuesday, March 23, 2021 6:34 PM To: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com; u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com Subject: RE: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Monday, March 15, 2021 10:37 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
arch/arm/mach-socfpga/clock_manager.c | 15 ++++++++++++--- arch/arm/mach-socfpga/clock_manager_agilex.c | 6 ------ arch/arm/mach-socfpga/clock_manager_s10.c | 6 ------ arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 ++++ arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 - 5 files changed, 16 insertions(+), 16 deletions(-)
[...]
unsigned int cm_get_spi_controller_clk_hz(void) { u32 clock = cm_get_l3_main_clk_hz(); diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 1f734bcd65..0f0cb230fa 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void); void cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void cm_print_clock_quick_summary(void);
+#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +unsigned int cm_get_qspi_controller_clk_hz(void); +#endif #endif
If this is for soc64, move to _SOC64.h file?
We do have clock_manager_soc64.h which shared by both stratix 10 and agilex.
clock_manager_s10.h if specific for CONFIG_TARGET_SOCFPGA_STRATIX10. clock_manager_s10.h includes clock_manager_soc64.h and it contains additional struct and macro for s10.
Regards Ley Foon
-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Wednesday, March 24, 2021 1:25 PM To: Tan, Ley Foon ley.foon.tan@intel.com; u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com Subject: RE: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Hi Ley Foon,
-----Original Message----- From: Tan, Ley Foon ley.foon.tan@intel.com Sent: Tuesday, March 23, 2021 6:34 PM To: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com; u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com Subject: RE: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Monday, March 15, 2021 10:37 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org;
Gan,
Yau Wai yau.wai.gan@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
arch/arm/mach-socfpga/clock_manager.c | 15 ++++++++++++--
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 ------ arch/arm/mach-socfpga/clock_manager_s10.c | 6 ------ arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 ++++ arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 - 5 files changed, 16 insertions(+), 16 deletions(-)
[...]
unsigned int cm_get_spi_controller_clk_hz(void) { u32 clock = cm_get_l3_main_clk_hz(); diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 1f734bcd65..0f0cb230fa 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void); void cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void cm_print_clock_quick_summary(void);
+#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +unsigned int cm_get_qspi_controller_clk_hz(void); +#endif #endif
If this is for soc64, move to _SOC64.h file?
We do have clock_manager_soc64.h which shared by both stratix 10 and agilex.
clock_manager_s10.h if specific for CONFIG_TARGET_SOCFPGA_STRATIX10. clock_manager_s10.h includes clock_manager_soc64.h and it contains additional struct and macro for s10.
cm_get_qspi_controller_clk_hz() is for cyclone 5 and Arria 10 too, can just function prototype in clock_manager.h and use for all devices.
Ley Foon
-----Original Message----- From: Tan, Ley Foon ley.foon.tan@intel.com Sent: Wednesday, March 24, 2021 4:11 PM To: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com; u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com Subject: RE: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Wednesday, March 24, 2021 1:25 PM To: Tan, Ley Foon ley.foon.tan@intel.com; u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com Subject: RE: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Hi Ley Foon,
-----Original Message----- From: Tan, Ley Foon ley.foon.tan@intel.com Sent: Tuesday, March 23, 2021 6:34 PM To: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com; u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org;
Gan,
Yau Wai yau.wai.gan@intel.com Subject: RE: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Monday, March 15, 2021 10:37 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org;
Gan,
Yau Wai yau.wai.gan@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
arch/arm/mach-socfpga/clock_manager.c | 15
++++++++++++--
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 ------ arch/arm/mach-socfpga/clock_manager_s10.c | 6 ------ arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 ++++ arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 - 5 files changed, 16 insertions(+), 16 deletions(-)
[...]
unsigned int cm_get_spi_controller_clk_hz(void) { u32 clock = cm_get_l3_main_clk_hz(); diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 1f734bcd65..0f0cb230fa 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void); void cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void cm_print_clock_quick_summary(void);
+#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +unsigned int cm_get_qspi_controller_clk_hz(void); +#endif #endif
If this is for soc64, move to _SOC64.h file?
We do have clock_manager_soc64.h which shared by both stratix 10 and agilex.
clock_manager_s10.h if specific for CONFIG_TARGET_SOCFPGA_STRATIX10. clock_manager_s10.h includes clock_manager_soc64.h and it contains additional struct and macro for s10.
cm_get_qspi_controller_clk_hz() is for cyclone 5 and Arria 10 too, can just function prototype in clock_manager.h and use for all devices.
Noted, I will make the change and send 3rd version of patchset for review.
Ley Foon
Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex.
This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com --- arch/arm/mach-socfpga/clock_manager.c | 5 +-- .../include/mach/system_manager_soc64.h | 16 ++++++++- arch/arm/mach-socfpga/mailbox_s10.c | 40 +++++++++++++++++++--- include/configs/socfpga_soc64_common.h | 1 + 4 files changed, 55 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index be426a5cfb..2783b9d18d 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -67,8 +67,9 @@ int set_cpu_clk_info(void) #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) unsigned int cm_get_qspi_controller_clk_hz(void) { - return readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + return (readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD0) & + SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * CLOCK_1K; } #endif
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 1eb8e7a904..fc4e17821b 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 -/* store qspi ref clock */ +/* + * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit + * storing qspi ref clock (kHz) + */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 /* store osc1 clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 @@ -85,6 +88,17 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 #define SYSMGR_SOC64_IODELAY0 0x1400
+/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0 + * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit + * storing qspi ref clock (kHz) + */ +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 7dcdae8136..2a13fbb506 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -356,6 +356,38 @@ int mbox_qspi_close(void) 0, NULL, 0, 0, NULL); }
+int mbox_qspi_set_controller_clk_hz(int clk_hz) +{ + u32 reg; + u32 clk_khz; + + /* We are getting QSPI ref clock and set into sysmgr boot register */ + /* + * Only clock freq in kHz degree is accepted due to limited bits[27:0] + * is reserved for storing the QSPI clock freq into boot scratch cold0 + * register + */ + if (clk_hz < CLOCK_1K) + return -EINVAL; + + clk_khz = clk_hz / CLOCK_1K; + printf("QSPI: Reference clock at %d kHz\n", clk_khz); + + /* + * DDR retention bit, SHA comparison bit and reset type bits sharing the + * same scratch register in N5X, ensure the content inside register is + * not overwritten by QSPI ref clock (kHz) + */ + reg = (readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) & + ~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK); + + writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + + return 0; +} + int mbox_qspi_open(void) { int ret; @@ -384,10 +416,10 @@ int mbox_qspi_open(void) if (ret) goto error;
- /* We are getting QSPI ref clock and set into sysmgr boot register */ - printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]); - writel(resp_buf[0], - socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + /* Store QSPI controller ref clock frequency*/ + ret = mbox_qspi_set_controller_clk_hz(resp_buf[0]); + if (ret) + goto error;
return 0;
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 5afdb10454..6a157298ca 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -73,6 +73,7 @@
#ifndef __ASSEMBLY__ unsigned int cm_get_qspi_controller_clk_hz(void); +#define CLOCK_1K 1000 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif
-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Monday, March 15, 2021 10:37 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [v1 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz
Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex.
This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
arch/arm/mach-socfpga/clock_manager.c | 5 +-- .../include/mach/system_manager_soc64.h | 16 ++++++++- arch/arm/mach-socfpga/mailbox_s10.c | 40 +++++++++++++++++++--- include/configs/socfpga_soc64_common.h | 1 + 4 files changed, 55 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach- socfpga/clock_manager.c index be426a5cfb..2783b9d18d 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -67,8 +67,9 @@ int set_cpu_clk_info(void) #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) unsigned int cm_get_qspi_controller_clk_hz(void) {
- return readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
- return (readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) *CLOCK_1K; } #endif
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 1eb8e7a904..fc4e17821b 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 -/* store qspi ref clock */ +/*
- Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for
+SOC 64-bit
- storing qspi ref clock (kHz)
- */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 /* store osc1 clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 @@ -85,6 +88,17 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 #define SYSMGR_SOC64_IODELAY0 0x1400
+/*
- Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
- Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for
+SOC 64-bit
- storing qspi ref clock (kHz)
- */
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28
#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach- socfpga/mailbox_s10.c index 7dcdae8136..2a13fbb506 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -356,6 +356,38 @@ int mbox_qspi_close(void) 0, NULL, 0, 0, NULL); }
+int mbox_qspi_set_controller_clk_hz(int clk_hz) {
This function nothing related to mailbox. Change to other name and move the function to the place read qspi clock. Then can remove define CLOCK_1K from socfpga_soc64_common.h.
- u32 reg;
- u32 clk_khz;
- /* We are getting QSPI ref clock and set into sysmgr boot register */
- /*
* Only clock freq in kHz degree is accepted due to limited bits[27:0]* is reserved for storing the QSPI clock freq into boot scratch cold0* register*/- if (clk_hz < CLOCK_1K)
return -EINVAL;- clk_khz = clk_hz / CLOCK_1K;
- printf("QSPI: Reference clock at %d kHz\n", clk_khz);
- /*
* DDR retention bit, SHA comparison bit and reset type bits sharingthe
* same scratch register in N5X, ensure the content inside register is* not overwritten by QSPI ref clock (kHz)*/
Comment doesn't need to mention about DDR retention. This is for N5X only. This just to clear the intended bits only.
- reg = (readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);- writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) |
reg,
socfpga_get_sysmgr_addr() +SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
- return 0;
+}
int mbox_qspi_open(void) { int ret; @@ -384,10 +416,10 @@ int mbox_qspi_open(void) if (ret) goto error;
- /* We are getting QSPI ref clock and set into sysmgr boot register */
- printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
- writel(resp_buf[0],
socfpga_get_sysmgr_addr() +SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
/* Store QSPI controller ref clock frequency*/
ret = mbox_qspi_set_controller_clk_hz(resp_buf[0]);
if (ret)
goto error;return 0;
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 5afdb10454..6a157298ca 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -73,6 +73,7 @@
#ifndef __ASSEMBLY__ unsigned int cm_get_qspi_controller_clk_hz(void); +#define CLOCK_1K 1000 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif
-- 2.13.0
Hi Ley Foon,
-----Original Message----- From: Tan, Ley Foon ley.foon.tan@intel.com Sent: Tuesday, March 23, 2021 6:49 PM To: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com; u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com Subject: RE: [v1 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz
-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Monday, March 15, 2021 10:37 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [v1 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz
Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex.
This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
arch/arm/mach-socfpga/clock_manager.c | 5 +-- .../include/mach/system_manager_soc64.h | 16 ++++++++- arch/arm/mach-socfpga/mailbox_s10.c | 40 +++++++++++++++++++--- include/configs/socfpga_soc64_common.h | 1 + 4 files changed, 55 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach- socfpga/clock_manager.c index be426a5cfb..2783b9d18d 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -67,8 +67,9 @@ int set_cpu_clk_info(void) #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) unsigned int cm_get_qspi_controller_clk_hz(void) {
- return readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
- return (readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) *CLOCK_1K; } #endif
diff --git a/arch/arm/mach-
socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 1eb8e7a904..fc4e17821b 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 -/* store qspi ref clock */ +/*
- Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved
+for SOC 64-bit
- storing qspi ref clock (kHz)
- */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 /* store osc1 clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 @@ -85,6 +88,17 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 #define SYSMGR_SOC64_IODELAY0 0x1400
+/*
- Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
- Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for
+SOC 64-bit
- storing qspi ref clock (kHz)
- */
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28
#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach- socfpga/mailbox_s10.c index 7dcdae8136..2a13fbb506 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -356,6 +356,38 @@ int mbox_qspi_close(void) 0, NULL, 0, 0, NULL); }
+int mbox_qspi_set_controller_clk_hz(int clk_hz) {
This function nothing related to mailbox. Change to other name and move the function to the place read qspi clock. Then can remove define CLOCK_1K from socfpga_soc64_common.h.
Noted, I will rename this function to ' cm_set_qspi_controller_clk_hz ' and move to clock_manager.c.
- u32 reg;
- u32 clk_khz;
- /* We are getting QSPI ref clock and set into sysmgr boot register */
- /*
* Only clock freq in kHz degree is accepted due to limited bits[27:0]* is reserved for storing the QSPI clock freq into boot scratch cold0* register*/- if (clk_hz < CLOCK_1K)
return -EINVAL;- clk_khz = clk_hz / CLOCK_1K;
- printf("QSPI: Reference clock at %d kHz\n", clk_khz);
- /*
* DDR retention bit, SHA comparison bit and reset type bits sharingthe
* same scratch register in N5X, ensure the content inside register is* not overwritten by QSPI ref clock (kHz)*/Comment doesn't need to mention about DDR retention. This is for N5X only. This just to clear the intended bits only.
- reg = (readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);- writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) |
reg,
socfpga_get_sysmgr_addr() +SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
- return 0;
+}
int mbox_qspi_open(void) { int ret; @@ -384,10 +416,10 @@ int mbox_qspi_open(void) if (ret) goto error;
- /* We are getting QSPI ref clock and set into sysmgr boot register */
- printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
- writel(resp_buf[0],
socfpga_get_sysmgr_addr() +SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
/* Store QSPI controller ref clock frequency*/
ret = mbox_qspi_set_controller_clk_hz(resp_buf[0]);
if (ret)
goto error;return 0;
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 5afdb10454..6a157298ca 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -73,6 +73,7 @@
#ifndef __ASSEMBLY__ unsigned int cm_get_qspi_controller_clk_hz(void); +#define CLOCK_1K 1000 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif
-- 2.13.0
participants (3)
-
Lim, Elly Siew Chin -
Siew Chin Lim
-
Tan, Ley Foon