On 03/04/2014 08:01, Tim Harvey wrote:

We only need to read in the size of struct image_header and thus don't need to know the page size of the nand device.

Signed-off-by: Tim Harvey tharvey@gateworks.com

common/spl/spl_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 9da0218..062461b 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -76,7 +76,7 @@ void spl_nand_load_image(void) #endif /* Load u-boot */ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,

• CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
  

• sizeof(*header), (void *)header);
  

  spl_parse_image_header(header); nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, spl_image.size, (void *)spl_image.load_addr);

Acked-by: Stefano Babic sbabic@denx.de

Best regards, Stefano Babic

On Thu, 2014-04-17 at 07:18 -0700, Tim Harvey wrote:

On Mon, Apr 14, 2014 at 4:38 AM, Stefano Babic sbabic@denx.de wrote:

...

On 03/04/2014 08:01, Tim Harvey wrote:

...

We only need to read in the size of struct image_header and thus don't need to know the page size of the nand device.

Signed-off-by: Tim Harvey tharvey@gateworks.com

common/spl/spl_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 9da0218..062461b 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -76,7 +76,7 @@ void spl_nand_load_image(void) #endif /* Load u-boot */ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,

•         CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
  

•         sizeof(*header), (void *)header);
  spl_parse_image_header(header);
  nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
          spl_image.size, (void *)spl_image.load_addr);
  
  

Acked-by: Stefano Babic sbabic@denx.de

Best regards, Stefano Babic

Scott,

This should have been addressed to you in the first place as its NAND and not IMX specific. It's been +1'd and ack'd, so if you agree with it and commit it I'll remove it from my next patch series regarding IMX6 SPL NAND support.

I suppose it's not worse than what's already there, but I really don't like the way nand_spl_load_image takes a pointer and a size, but can write more bytes to the pointer than the size that was given (it rounds up to the block -- not page -- size).

That said, Acked-by: Scott Wood scottwood@freescale.com ...and feel free to leave it in with the rest of the patchset.

-Scott

Hi Tim,

sorry for late review.

On 03/04/2014 08:01, Tim Harvey wrote:

This utilizes existing nand support, including the mtd layer to provide a a method to load an image off nand for SPL. It is somewhat bulky but avoids duplicating code.

This will need to be split out and re-based on top of Tom's recent patch to add MTD NAND support which is needed here.

Signed-off-by: Tim Harvey tharvey@gateworks.com

drivers/mtd/Makefile | 11 ++++++++++ drivers/mtd/nand/Makefile | 9 ++++++++ drivers/mtd/nand/mxs_nand_spl.c | 46 +++++++++++++++++++++++++++++++++++++++++ spl/Makefile | 1 + 4 files changed, 67 insertions(+) create mode 100644 drivers/mtd/nand/mxs_nand_spl.c

diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 5467a95..10ec470 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -5,6 +5,15 @@ # SPDX-License-Identifier: GPL-2.0+ #

+ifdef CONFIG_SPL_BUILD

+ifdef CONFIG_SPL_NAND_MXS +obj-y += mtdcore.o +obj-y += mtdpart.o +endif

This is usually:

obj-$(CONFIG_SPL_NAND_MXS) += mtdcore.o mtdpart.o

+else # not spl

ifneq (,$(findstring y,$(CONFIG_MTD_DEVICE)$(CONFIG_CMD_NAND)$(CONFIG_CMD_ONENAND))) obj-y += mtdcore.o endif @@ -18,3 +27,5 @@ obj-$(CONFIG_FTSMC020) += ftsmc020.o obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o obj-$(CONFIG_ST_SMI) += st_smi.o

+endif diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 02b149c..8b1a37a 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -19,6 +19,14 @@ obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o

+ifdef CONFIG_SPL_NAND_MXS +obj-y += mxs_nand_spl.o +obj-y += nand_bbt.o +obj-y += nand_ids.o +obj-y += nand_util.o +obj-y += nand_ecc.o +endif

Ditto.

else # not spl

NORMAL_DRIVERS=y @@ -65,5 +73,6 @@ else # minimal SPL drivers obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o +obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o

endif # drivers diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c new file mode 100644 index 0000000..ec07eb1 --- /dev/null +++ b/drivers/mtd/nand/mxs_nand_spl.c @@ -0,0 +1,46 @@ +/*

• • (C) Copyright 2014
• • Tim Harvey, Gateworks Corporation, tharvey@gateworks.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <nand.h>

+static nand_info_t mtd; +static struct nand_chip nand_chip;

+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) +{

• size_t sz, actual;
• debug("%s offset:0x%08x len:%d\n", __func__, offs, size);
• sz = size;
• nand_read_skip_bad(&mtd, (loff_t) offs, &sz, &actual, size, dst);
• debug("read %d/%d bytes\n", sz, actual);
• return 0;

+}

+void nand_init(void) +{

• int ret;
• board_nand_init(&nand_chip);
• mtd.priv = &nand_chip;
• if (nand_chip.select_chip)

• nand_chip.select_chip(&mtd, 0);
  

• ret = nand_scan(&mtd, 1);
• if (!ret)

• ret = nand_scan_tail(&mtd);
  

• debug("oobsize=%d pagesize=%d\n", mtd.oobsize, mtd.writesize);
• printf("NAND: %llu MiB\n", (mtd.size / (1024 * 1024)));

+}

+void nand_deselect(void) +{

• if (nand_chip.select_chip)

• nand_chip.select_chip(&mtd, -1);
  

+} diff --git a/spl/Makefile b/spl/Makefile index 346d0aa..6a2c80f 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -103,6 +103,7 @@ libs-y += fs/ libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/ libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/ libs-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/ +libs-$(CONFIG_SPL_NAND_MXS) += drivers/mtd/ libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/ libs-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/ libs-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/

The main issue (I read also Scott's answer for Patch 4/11) is due to the fact that you link a lot of MTD code, increasing the footprint. This becomes an exception, because only a restricted number of function were introduces for other SOCs (see mxc_nand_spl.c or code in omap_gpmc.c). Sure that we cannot get rid of it ?

Best regards, Stefano Babic

On Wed, Apr 9, 2014 at 7:55 AM, Nikita Kiryanov nikita@compulab.co.il wrote:

Hi Tim,

On 04/03/2014 09:01 AM, Tim Harvey wrote:> Add a common header which can hopefully be shared among imx6 SPL users

...

Signed-off-by: Tim Harvey tharvey@gateworks.com

include/configs/imx6_spl.h | 64

++++++++++++++++++++++++++++++++++++++++++++++

...

1 file changed, 64 insertions(+) create mode 100644 include/configs/imx6_spl.h

diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h new file mode 100644 index 0000000..f9bdf55 --- /dev/null +++ b/include/configs/imx6_spl.h @@ -0,0 +1,64 @@ +/*

• • Author: Tim Harvey tharvey@gateworks.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __IMX6_SPL_CONFIG_H +#define __IMX6_SPL_CONFIG_H

+#ifdef CONFIG_SPL

+#define CONFIG_SPL_FRAMEWORK

+/*

• • IMX6 OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF

That's not true for all IMX6 SoCs. On i.MX6 Solo and DualLite it's 0x00907000 to 0x0091FFFF.

...

• • • we start at 0x00908000 so as to leave some room for IVT/DCD
• • • recommended stack (from IMX6DQRM Figure 8-3) is at 0x0093FFB8
• • • this leaves about 224K for SPL image and stack
• */

+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/mx6/u-boot-spl.lds" +#define CONFIG_SPL_TEXT_BASE 0x00908000 +#define CONFIG_SPL_MAX_SIZE (128 * 1024)

This should be a smaller value if we want this config to apply for i.MX6 Solo and DualLite, which have a 68KB OCRAM free area.

Hi Nikita,

Agreed - I just discovered this yesterday. I had tested on an IMX6DL/SOLO via boot from OTG, but I had not tested those combinations when booting from flash and indeed they failed.

The 68KB OCRAM free area also assumes that you start at 0x00907000 and as we start at 0x00908000 to leave room for the IVT+DCD this becomes 65KB

...

+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7" +#define CONFIG_SPL_STACK 0x0093FFB8

For i.MX6 Solo and DualLite this address should be lower (recommended address is 0x0091FFB8).

Agreed

...

+#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT

+/* NAND support */ +#if defined(CONFIG_SPL_NAND_SUPPORT) +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_DMA_SUPPORT +#endif

-- Regards, Nikita.

This presents another challenge for SPL NAND as currently my SPL is ~70K. There is a lot of unnecessary code in the mtd nand layer that I'm including because that layer includes support for both read and write (I don't need write for SPL) as well as various NAND types (and I only need BCH).

I'm not sure yet what the best approach is to resolve that. I can either: a) add a lot of ifdef's around functions in drivers/mtd/nand/{nand_base.c,nand_bbt.c} to remove NAND write and non BCH support for CONFIG_SPL_BUILD b) re-write the necessary functionality (code duplication) into drivers/mtd/nand/mxs_nand_spl.c

Thanks for the review!

Tim

Hi Tim,

On 03/04/2014 08:01, Tim Harvey wrote:

Add enums, #defines, and helper functions needed for SPL images to describe and detect IMX6 boot device.

Signed-off-by: Tim Harvey tharvey@gateworks.com

arch/arm/cpu/armv7/mx6/soc.c | 56 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/spl.h | 26 ++++++++++++++ arch/arm/include/asm/imx-common/boot_mode.h | 17 +++++++++ 3 files changed, 99 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx6/spl.h

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 1725279..4ee62c7 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -305,6 +305,62 @@ const struct boot_mode soc_boot_modes[] = { {NULL, 0}, };

+/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */ +enum boot_device get_boot_device(void) +{

• enum boot_device boot_dev;
• uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); /* SRC_SBMR1 */

Use structure to access internal registers. The structure is already defined in imx-regs.h.

• /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
• switch ((soc_sbmr & 0x000000FF) >> 4) {

• /* EIM: See 8.5.1, Table 8-9 */
  

• case 0x0:

• /* BOOT_CFG1[3]: NOR/OneNAND Selection */
  

• if ((soc_sbmr & 0x00000008) >> 3)
  

• 	boot_dev = MX6_ONE_NAND_BOOT;
  

• else
  

• 	boot_dev = MX6_WEIM_NOR_BOOT;
  

• break;
  

• /* SATA: See 8.5.4, Table 8-20 */
• case 0x2:

Can we use #defines for that ?

• boot_dev = MX6_SATA_BOOT;
  

• break;
  

• /* Serial ROM: See 8.5.5.1, Table 8-22 */
• case 0x3:

• /* BOOT_CFG4[2:0] */
  

• switch ((soc_sbmr & 0x07000000) >> 24) {
  

• case 0x0 ... 0x4:
  

• 	boot_dev = MX6_SPI_NOR_BOOT;
  

• 	break;
  

• case 0x5 ... 0x7:
  

• 	boot_dev = MX6_I2C_BOOT;
  

• 	break;
  

• }
  

• break;
  

• /* SD/eSD: 8.5.3, Table 8-15 */
• case 0x4:
• case 0x5:

• boot_dev = MX6_SD_BOOT;
  

• break;
  

• /* MMC/eMMC: 8.5.3 */
• case 0x6:
• case 0x7:

• boot_dev = MX6_MMC_BOOT;
  

• break;
  

• /* NAND Flash: 8.5.2 */
• case 0x8 ... 0xf:

• boot_dev = MX6_NAND_BOOT;
  

• break;
  

• default:

• boot_dev = MX6_UNKNOWN_BOOT;
  

• break;
  

• }

The function can be used as well for MX5 SOCs. Move it into imx-common, and use constants without SOC names. Instead of MX6_NAND_BOOT, IMX_NAND_BOOT (or whatever you find makes sense..)

• return boot_dev;

+}

void s_init(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; diff --git a/arch/arm/include/asm/arch-mx6/spl.h b/arch/arm/include/asm/arch-mx6/spl.h new file mode 100644 index 0000000..5611c71 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/spl.h @@ -0,0 +1,26 @@ +/*

• • Copyright (C) 2013 TechNexion Ltd.
• • Author: Richard Hu linuxfae@technexion.com
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• */

+#ifndef __ASM_ARCH_SPL_H__ +#define __ASM_ARCH_SPL_H__

+#define BOOT_DEVICE_MMC1 0 +#define BOOT_DEVICE_MMC2 1 +#define BOOT_DEVICE_MMC2_2 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_SATA 4 +#define BOOT_DEVICE_USBETH 5 +#define BOOT_DEVICE_NONE 6

They are only defines and are not yet related to i.MX6 anymnore, because you have already mapped them. What about to move this defines into imx-common ?

+#endif /* __ASM_ARCH_SPL_H__ */ diff --git a/arch/arm/include/asm/imx-common/boot_mode.h b/arch/arm/include/asm/imx-common/boot_mode.h index de0205c..3686367 100644 --- a/arch/arm/include/asm/imx-common/boot_mode.h +++ b/arch/arm/include/asm/imx-common/boot_mode.h @@ -17,4 +17,21 @@ struct boot_mode { void add_board_boot_modes(const struct boot_mode *p); void boot_mode_apply(unsigned cfg_val); extern const struct boot_mode soc_boot_modes[];

+/* boot devices */ +enum boot_device {

• MX6_SD_BOOT,
• MX6_MMC_BOOT,
• MX6_NAND_BOOT,
• MX6_SATA_BOOT,
• MX6_WEIM_NOR_BOOT,
• MX6_ONE_NAND_BOOT,
• MX6_PATA_BOOT,
• MX6_I2C_BOOT,
• MX6_SPI_NOR_BOOT,
• MX6_UNKNOWN_BOOT,
• MX6_BOOT_DEV_NUM = MX6_UNKNOWN_BOOT,

+};

See my remark before.

+enum boot_device get_boot_device(void);

#endif

Best regards, Stefano Babic

Hi Tim,

On 17/04/2014 08:16, Tim Harvey wrote:

...

...

•         boot_dev = MX6_SATA_BOOT;
  

•         break;
  

• /* Serial ROM: See 8.5.5.1, Table 8-22 */
  

• case 0x3:
  

•         /* BOOT_CFG4[2:0] */
  

•         switch ((soc_sbmr & 0x07000000) >> 24) {
  

•         case 0x0 ... 0x4:
  

•                 boot_dev = MX6_SPI_NOR_BOOT;
  

•                 break;
  

•         case 0x5 ... 0x7:
  

•                 boot_dev = MX6_I2C_BOOT;
  

•                 break;
  

•         }
  

•         break;
  

• /* SD/eSD: 8.5.3, Table 8-15  */
  

• case 0x4:
  

• case 0x5:
  

•         boot_dev = MX6_SD_BOOT;
  

•         break;
  

• /* MMC/eMMC: 8.5.3 */
  

• case 0x6:
  

• case 0x7:
  

•         boot_dev = MX6_MMC_BOOT;
  

•         break;
  

• /* NAND Flash: 8.5.2 */
  

• case 0x8 ... 0xf:
  

•         boot_dev = MX6_NAND_BOOT;
  

•         break;
  

• default:
  

•         boot_dev = MX6_UNKNOWN_BOOT;
  

•         break;
  

• }
  

The function can be used as well for MX5 SOCs. Move it into imx-common, and use constants without SOC names. Instead of MX6_NAND_BOOT, IMX_NAND_BOOT (or whatever you find makes sense..)

Are you saying the i.MX5's have the same register and meaning? I figured the sbmr is different.

The register is the same, and mostly with the same meaning. You do not need to care about it. Just put it into imx-common, and when someone will add support for MX5, this function will be analyzed and modified instead of adding a new one.

...

...

• return boot_dev;
  

+}

void s_init(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; diff --git a/arch/arm/include/asm/arch-mx6/spl.h b/arch/arm/include/asm/arch-mx6/spl.h new file mode 100644 index 0000000..5611c71 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/spl.h @@ -0,0 +1,26 @@ +/*

• • Copyright (C) 2013 TechNexion Ltd.
• • Author: Richard Hu linuxfae@technexion.com
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• */

+#ifndef __ASM_ARCH_SPL_H__ +#define __ASM_ARCH_SPL_H__

+#define BOOT_DEVICE_MMC1 0 +#define BOOT_DEVICE_MMC2 1 +#define BOOT_DEVICE_MMC2_2 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_SATA 4 +#define BOOT_DEVICE_USBETH 5 +#define BOOT_DEVICE_NONE 6

They are only defines and are not yet related to i.MX6 anymnore, because you have already mapped them. What about to move this defines into imx-common ?

ok

Masahiro has sent this week a patch to consolidate names, that are duplicated for all architecture: http://patchwork.ozlabs.org/patch/339438/

I think it is a very good idea to follow his approach.

I hope to have a v2 posted soon.

Please only wait until I send my remark regarding the patches with pinmux.

Best regards, Stefano Babic

Hi Tim,

On 04/03/2014 09:01 AM, Tim Harvey wrote:

This can be used to pass info between the SPL and u-boot.

Signed-off-by: Tim Harvey tharvey@gateworks.com

arch/arm/include/asm/arch-mx6/sys_proto.h | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 38851a1..f43e09c 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -39,4 +39,9 @@ int mxs_wait_mask_set(struct mxs_register_32 *reg, int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned int timeout);

+struct mx6_spl_data {

• uint8_t boot_mode_idx;
• uint32_t mem_dram_size;

+}; #endif

While I'm in favor of having some way for SPL to pass data to U-Boot, I don't think this patch achieves this as long as we don't have a common mechanism that makes use of this struct. At the very least I would've expected to see a #define that is shared by SPL and U-Boot that defines the address for this struct (if we were to use the ventana implementation).

On Wed, Apr 9, 2014 at 7:56 AM, Nikita Kiryanov nikita@compulab.co.il wrote:

Hi Tim,

On 04/03/2014 09:01 AM, Tim Harvey wrote:

...

Add new function that can take an array of iomux configs, an index, and a stride to allow a multi-dimentional array of pinmux values to be used to define pinmux values per cpu-type.

This takes a different approach to previously proposed solutions which used multiple arrays of pad lists. The goal is to eliminate having these multiple arrays such as 'mx6q_uart1_pads' and 'mx6dl_uart1_pads' which are almost identical copies of each other except for the MX6Q/MX6DL prefix on the PAD.

I like this approach, but I think you should also define the IOMUX, SETUP_PAD, and SETUP_PADS macros from patch 10 in this file, as they (macros and function) are clearly meant to be used together.

I agree with this. Do the macro names IOMUX, SETUP_PAD, SETUP_PADS make sense?

...

Signed-off-by: Tim Harvey tharvey@gateworks.com

arch/arm/imx-common/iomux-v3.c | 19 +++++++++++++++---- arch/arm/include/asm/imx-common/iomux-v3.h | 5 ++++- 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index b59b802..d3e1e30 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -46,12 +46,23 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #endif }

-void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,

•                                 unsigned count)
  

+/* configures a list of pads within an array of lists */ +void imx_iomux_v3_setup_multiple_pads_array(iomux_v3_cfg_t const *pad_list,

•                                       unsigned count, unsigned list,
  

•                                       unsigned stride)
  

  { iomux_v3_cfg_t const *p = pad_list; int i;

•   for (i = 0; i < count; i++)
  

•           imx_iomux_v3_setup_pad(*p++);
  

•   p += list;
  

•   for (i = 0; i < count; i++) {
  

•           imx_iomux_v3_setup_pad(*p);
  

•           p += stride;
  

•   }
  

+}

+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,

•                                 unsigned count)
  

+{

•   imx_iomux_v3_setup_multiple_pads_array(pad_list, count, 0, 1);
  

  }

diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dec11a1..c8cc45b 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -167,7 +167,10 @@ typedef u64 iomux_v3_cfg_t; #define GPIO_PORTF (5 << GPIO_PORT_SHIFT)

void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); +void imx_iomux_v3_setup_multiple_pads_array(iomux_v3_cfg_t const *pad_list,

•                                       unsigned count, unsigned list,
  

•                                       unsigned stride);
  

  void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,

•                                unsigned count);
  

•                                 unsigned count);
  

The above change is a cleanup and should not be in this patch.

If there appears to be general agreement on this approach, I'll submit a new 2-patch series just for this patch and pull it out of my overall series.

Regards,

Tim

...

#endif /* __MACH_IOMUX_V3_H__*/

-- Regards, Nikita.

On 03/04/2014 08:01, Tim Harvey wrote:

use the new iomux function and a macro to create a multi-dimensional array of iomux values without duplicating the defintions.

Signed-off-by: Tim Harvey tharvey@gateworks.com

board/gateworks/gw_ventana/gw_ventana.c | 497 ++++++++++++++++++++------------ 1 file changed, 316 insertions(+), 181 deletions(-)

diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 2113740..ebf7e7d 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -40,6 +40,17 @@

DECLARE_GLOBAL_DATA_PTR;

+#define IOMUX(x) (MX6Q_##x), (MX6DL_##x) +#define SETUP_PAD(def) \ +if (is_cpu_type(MXC_CPU_MX6Q)) { \

• imx_iomux_v3_setup_pad(MX6Q_##def); \

+} else { \

• imx_iomux_v3_setup_pad(MX6DL_##def); \

+}

This macro should be available for other boards, too.

+#define SETUP_PADS(x) \

• imx_iomux_v3_setup_multiple_pads_array(x, \
• ARRAY_SIZE(x)/2, is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1, 2)

/* GPIO's common to all baseboards */ #define GP_PHY_RST IMX_GPIO_NR(1, 30) #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) @@ -94,109 +105,145 @@ int board_type;

/* UART1: Function varies per baseboard */ iomux_v3_cfg_t const uart1_pads[] = {

• MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
• MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

• IOMUX(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
• IOMUX(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),

};

/* UART2: Serial Console */ iomux_v3_cfg_t const uart2_pads[] = {

• MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
• MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

• IOMUX(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
• IOMUX(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),

};

#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

/* I2C1: GSC */ -struct i2c_pads_info i2c_pad_info0 = { +struct i2c_pads_info mx6q_i2c_pad_info0 = { .scl = {

• .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  

• .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  

• .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
  

• .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
  

What have you changed here ?

.gp = IMX_GPIO_NR(3, 21)

}, .sda = {

• .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  

• .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  

• .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
  

• .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
  

• .gp = IMX_GPIO_NR(3, 28)
  

• }

+}; +struct i2c_pads_info mx6dl_i2c_pad_info0 = {

• .scl = {

• .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
  

• .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
  

• .gp = IMX_GPIO_NR(3, 21)
  

• },
• .sda = {

• .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
  

• .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
  

  .gp = IMX_GPIO_NR(3, 28) }

};

/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ -struct i2c_pads_info i2c_pad_info1 = { +struct i2c_pads_info mx6q_i2c_pad_info1 = {

• .scl = {

• .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
  

• .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
  

• .gp = IMX_GPIO_NR(4, 12)
  

• },
• .sda = {

• .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
  

• .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  

• .gp = IMX_GPIO_NR(4, 13)
  

• }

+}; +struct i2c_pads_info mx6dl_i2c_pad_info1 = { .scl = {

• .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
  

• .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
  

• .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
  

• .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
  

  .gp = IMX_GPIO_NR(4, 12) }, .sda = {

• .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  

• .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  

• .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
  

• .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  

  .gp = IMX_GPIO_NR(4, 13) }

};

/* I2C3: Misc/Expansion */ -struct i2c_pads_info i2c_pad_info2 = { +struct i2c_pads_info mx6q_i2c_pad_info2 = { .scl = {

• .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
  

• .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
  

• .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
  

• .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
  

  .gp = IMX_GPIO_NR(1, 3) }, .sda = {

• .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
  

• .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
  

• .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
  

• .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
  

• .gp = IMX_GPIO_NR(1, 6)
  

• }

+};

It seems you have already tried but you have not found a solution for this. Anyway, repeating the same structure for all variants looks bad. The solution with SETUP_PADS() and IOMUX is pretty better.

+struct i2c_pads_info mx6dl_i2c_pad_info2 = {

• .scl = {

• .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
  

• .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
  

• .gp = IMX_GPIO_NR(1, 3)
  

• },
• .sda = {

• .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
  

• .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
  

  .gp = IMX_GPIO_NR(1, 6) }

};

/* MMC */ iomux_v3_cfg_t const usdhc3_pads[] = {

• MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */

• IOMUX(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
• IOMUX(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
• IOMUX(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
• IOMUX(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
• IOMUX(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
• IOMUX(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
• IOMUX(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */

};

/* ENET */ iomux_v3_cfg_t const enet_pads[] = {

• MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

• IOMUX(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
• IOMUX(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), /* PHY nRST */

• MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),

};

/* NAND */ iomux_v3_cfg_t const nfc_pads[] = {

• MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
• IOMUX(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),

};

#ifdef CONFIG_CMD_NAND @@ -205,7 +252,7 @@ static void setup_gpmi_nand(void) struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

/* config gpmi nand iomux */

• imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));

• SETUP_PADS(nfc_pads);

I will only suggest to use another name for the macro. SETUP_PADS seems too generic and could conflict in future with other SOCs. IMX6_SETUP_PADS ?

/* config gpmi and bch clock to 100 MHz */ clrsetbits_le32(&mxc_ccm->cs2cdr, @@ -231,7 +278,7 @@ static void setup_gpmi_nand(void)

static void setup_iomux_enet(void) {

• imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));

• SETUP_PADS(enet_pads);

  /* toggle PHY_RST# */ gpio_direction_output(GP_PHY_RST, 0);

@@ -241,35 +288,34 @@ static void setup_iomux_enet(void)

static void setup_iomux_uart(void) {

• imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
• imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));

• SETUP_PADS(uart1_pads);
• SETUP_PADS(uart2_pads);

}

#ifdef CONFIG_USB_EHCI_MX6 iomux_v3_cfg_t const usb_pads[] = {

• MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL),
• MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL),
• MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */

• IOMUX(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL)),
• IOMUX(PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL)),
• /* OTG PWR */
• IOMUX(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL)),

};

int board_ehci_hcd_init(int port) { struct ventana_board_info *info = &ventana_info;

• imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));

• SETUP_PADS(usb_pads);

  /* Reset USB HUB (present on GW54xx/GW53xx) */ switch (info->model[3]) { case '3': /* GW53xx */

• imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09|
  

• 		       MUX_PAD_CTRL(NO_PAD_CTRL));
  

• SETUP_PAD(PAD_GPIO_9__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL));
  

  gpio_direction_output(IMX_GPIO_NR(1, 9), 0); mdelay(2); gpio_set_value(IMX_GPIO_NR(1, 9), 1); break; case '4': /* GW54xx */

• imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 |
  

• 		       MUX_PAD_CTRL(NO_PAD_CTRL));
  

• SETUP_PAD(PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL));
  

  gpio_direction_output(IMX_GPIO_NR(1, 16), 0); mdelay(2); gpio_set_value(IMX_GPIO_NR(1, 16), 1);

@@ -301,7 +347,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { /* Only one USDHC controller on Ventana */

• imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));

• SETUP_PADS(usdhc3_pads); usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg.max_bus_width = 4;

@@ -312,17 +358,16 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */

• MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
• MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
• MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
• MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

• IOMUX(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
• IOMUX(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
• IOMUX(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
• IOMUX(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),

};

static void setup_spi(void) { gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);

• imx_iomux_v3_setup_multiple_pads(ecspi1_pads,

• 			 ARRAY_SIZE(ecspi1_pads));
  

• SETUP_PADS(ecspi1_pads);

} #endif

@@ -453,118 +498,118 @@ read_eeprom(void) /* common to add baseboards */ static iomux_v3_cfg_t const gw_gpio_pads[] = { /* MSATA_EN */

• MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RS232_EN# */

• MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),

};

/* prototype */ static iomux_v3_cfg_t const gwproto_gpio_pads[] = { /* PANLEDG# */

• MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* PANLEDR# */

• MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* LOCLED# */

• MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RS485_EN */

• MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* IOEXP_PWREN# */

• MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* IOEXP_IRQ# */

• MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* VID_EN */

• MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DIOI2C_DIS# */

• MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* PCICK_SSON */

• MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* PCI_RST# */

• MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),

};

static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { /* PANLEDG# */

• MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* PANLEDR# */

• MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* IOEXP_PWREN# */

• MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* IOEXP_IRQ# */

• MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),

  /* GPS_SHDN */

• MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* VID_PWR */

• MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* PCI_RST# */

• MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),

};

static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { /* PANLEDG# */

• MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* PANLEDR# */

• MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* IOEXP_PWREN# */

• MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* IOEXP_IRQ# */

• MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),

  /* MX6_LOCLED# */

• MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* GPS_SHDN */

• MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* USBOTG_SEL */

• MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* VID_PWR */

• MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* PCI_RST# */

• MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),

};

static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { /* PANLEDG# */

• MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* PANLEDR# */

• MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* IOEXP_PWREN# */

• MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* IOEXP_IRQ# */

• MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),

  /* MX6_LOCLED# */

• MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* GPS_SHDN */

• MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* VID_EN */

• MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* PCI_RST# */

• MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),

};

static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { /* PANLEDG# */

• MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* PANLEDR# */

• MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* MX6_LOCLED# */

• MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* MIPI_DIO */

• MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RS485_EN */

• MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* IOEXP_PWREN# */

• MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* IOEXP_IRQ# */

• MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DIOI2C_DIS# */

• MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DIOI2C_DIS# */

• MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* PCICK_SSON */

• MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* PCI_RST# */

• MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),

• IOMUX(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),

};

/* @@ -572,9 +617,9 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {

• be pinmuxed as a GPIO or in some cases a PWM

*/ struct dio_cfg {

• iomux_v3_cfg_t gpio_padmux;

• iomux_v3_cfg_t gpio_padmux[2]; unsigned gpio_param;

• iomux_v3_cfg_t pwm_padmux;

• iomux_v3_cfg_t pwm_padmux[2]; unsigned pwm_param;

};

@@ -601,16 +646,32 @@ struct ventana gpio_cfg[] = { /* GW5400proto */ { .gpio_pads = gw54xx_gpio_pads,

• .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
  

• .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
  

  .dio_cfg = {

• 	{ MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
  

• 	  MX6_PAD_GPIO_9__PWM1_OUT, 1 },
  

• 	{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
  

• 	  MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
  

• 	{ MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
  

• 	  MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
  

• 	{ MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
  

• 	  MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
  

• 	{
  

• 		{ IOMUX(PAD_GPIO_9__GPIO1_IO09) },
  

• 		IMX_GPIO_NR(1, 9),
  

• 		{ IOMUX(PAD_GPIO_9__PWM1_OUT) },
  

• 		1
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD1_DAT2__GPIO1_IO19) },
  

• 		IMX_GPIO_NR(1, 19),
  

• 		{ IOMUX(PAD_SD1_DAT2__PWM2_OUT) },
  

• 		2
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD4_DAT1__GPIO2_IO09) },
  

• 		IMX_GPIO_NR(2, 9),
  

• 		{ IOMUX(PAD_SD4_DAT1__PWM3_OUT) },
  

• 		3
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD4_DAT2__GPIO2_IO10) },
  

• 		IMX_GPIO_NR(2, 10),
  

• 		{ IOMUX(PAD_SD4_DAT2__PWM4_OUT) },
  

• 		4
  

• 	},
  

  }, .leds = { IMX_GPIO_NR(4, 6),

@@ -628,16 +689,32 @@ struct ventana gpio_cfg[] = { /* GW51xx */ { .gpio_pads = gw51xx_gpio_pads,

• .num_pads = ARRAY_SIZE(gw51xx_gpio_pads),
  

• .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
  

  .dio_cfg = {

• 	{ MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
  

• 	  0, 0 },
  

• 	{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
  

• 	  MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
  

• 	{ MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
  

• 	  MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
  

• 	{ MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18),
  

• 	  MX6_PAD_SD1_CMD__PWM4_OUT, 4 },
  

• 	{
  

• 		{ IOMUX(PAD_SD1_DAT0__GPIO1_IO16) },
  

• 		IMX_GPIO_NR(1, 16),
  

• 		{ 0, 0 },
  

• 		0
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD1_DAT2__GPIO1_IO19) },
  

• 		IMX_GPIO_NR(1, 19),
  

• 		{ IOMUX(PAD_SD1_DAT2__PWM2_OUT) },
  

• 		2
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD1_DAT1__GPIO1_IO17) },
  

• 		IMX_GPIO_NR(1, 17),
  

• 		{ IOMUX(PAD_SD1_DAT1__PWM3_OUT) },
  

• 		3
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD1_CMD__GPIO1_IO18) },
  

• 		IMX_GPIO_NR(1, 18),
  

• 		{ IOMUX(PAD_SD1_CMD__PWM4_OUT) },
  

• 		4
  

• 	},
  

  }, .leds = { IMX_GPIO_NR(4, 6),

@@ -653,16 +730,32 @@ struct ventana gpio_cfg[] = { /* GW52xx */ { .gpio_pads = gw52xx_gpio_pads,

• .num_pads = ARRAY_SIZE(gw52xx_gpio_pads),
  

• .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
  

  .dio_cfg = {

• 	{ MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
  

• 	  0, 0 },
  

• 	{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
  

• 	  MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
  

• 	{ MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
  

• 	  MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
  

• 	{ MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
  

• 	  0, 0 },
  

• 	{
  

• 		{ IOMUX(PAD_SD1_DAT0__GPIO1_IO16) },
  

• 		IMX_GPIO_NR(1, 16),
  

• 		{ 0, 0 },
  

• 		0
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD1_DAT2__GPIO1_IO19) },
  

• 		IMX_GPIO_NR(1, 19),
  

• 		{ IOMUX(PAD_SD1_DAT2__PWM2_OUT) },
  

• 		2
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD1_DAT1__GPIO1_IO17) },
  

• 		IMX_GPIO_NR(1, 17),
  

• 		{ IOMUX(PAD_SD1_DAT1__PWM3_OUT) },
  

• 		3
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD1_CLK__GPIO1_IO20) },
  

• 		IMX_GPIO_NR(1, 20),
  

• 		{ 0, 0 },
  

• 		0
  

• 	},
  

  }, .leds = { IMX_GPIO_NR(4, 6),

@@ -680,16 +773,32 @@ struct ventana gpio_cfg[] = { /* GW53xx */ { .gpio_pads = gw53xx_gpio_pads,

• .num_pads = ARRAY_SIZE(gw53xx_gpio_pads),
  

• .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
  

  .dio_cfg = {

• 	{ MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
  

• 	  0, 0 },
  

• 	{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
  

• 	  MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
  

• 	{ MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
  

• 	  MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
  

• 	{ MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
  

• 	  0, 0 },
  

• 	{
  

• 		{ IOMUX(PAD_SD1_DAT0__GPIO1_IO16) },
  

• 		IMX_GPIO_NR(1, 16),
  

• 		{ 0, 0 },
  

• 		0
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD1_DAT2__GPIO1_IO19) },
  

• 		IMX_GPIO_NR(1, 19),
  

• 		{ IOMUX(PAD_SD1_DAT2__PWM2_OUT) },
  

• 		2
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD1_DAT1__GPIO1_IO17) },
  

• 		IMX_GPIO_NR(1, 17),
  

• 		{ IOMUX(PAD_SD1_DAT1__PWM3_OUT) },
  

• 		3
  

• 	},
  

• 	{
  

• 		{IOMUX(PAD_SD1_CLK__GPIO1_IO20) },
  

• 		IMX_GPIO_NR(1, 20),
  

• 		{ 0, 0 },
  

• 		0
  

• 	},
  

  }, .leds = { IMX_GPIO_NR(4, 6),

@@ -706,16 +815,32 @@ struct ventana gpio_cfg[] = { /* GW54xx */ { .gpio_pads = gw54xx_gpio_pads,

• .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
  

• .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
  

  .dio_cfg = {

• 	{ MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
  

• 	  MX6_PAD_GPIO_9__PWM1_OUT, 1 },
  

• 	{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
  

• 	  MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
  

• 	{ MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
  

• 	  MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
  

• 	{ MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
  

• 	  MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
  

• 	{
  

• 		{ IOMUX(PAD_GPIO_9__GPIO1_IO09) },
  

• 		IMX_GPIO_NR(1, 9),
  

• 		{ IOMUX(PAD_GPIO_9__PWM1_OUT) },
  

• 		1
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD1_DAT2__GPIO1_IO19) },
  

• 		IMX_GPIO_NR(1, 19),
  

• 		{ IOMUX(PAD_SD1_DAT2__PWM2_OUT) },
  

• 		2
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD4_DAT1__GPIO2_IO09) },
  

• 		IMX_GPIO_NR(2, 9),
  

• 		{ IOMUX(PAD_SD4_DAT1__PWM3_OUT) },
  

• 		3
  

• 	},
  

• 	{
  

• 		{ IOMUX(PAD_SD4_DAT2__GPIO2_IO10) },
  

• 		IMX_GPIO_NR(2, 10),
  

• 		{ IOMUX(PAD_SD4_DAT2__PWM4_OUT) },
  

• 		4
  

• 	},
  

  }, .leds = { IMX_GPIO_NR(4, 6),

@@ -805,6 +930,7 @@ static void setup_board_gpio(int board) for (i = 0; i < 4; i++) { struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; unsigned ctrl = DIO_PAD_CTRL;

• unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
  
  

  sprintf(arg, "dio%d", i); if (!hwconfig(arg))

@@ -819,14 +945,14 @@ static void setup_board_gpio(int board) cfg->gpio_param%32, cfg->gpio_param); }

• 	imx_iomux_v3_setup_pad(cfg->gpio_padmux |
  

• 	imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
  		       MUX_PAD_CTRL(ctrl));
  gpio_direction_input(cfg->gpio_param);
  

  } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && cfg->pwm_padmux) { if (!quiet) printf("DIO%d: pwm%d\n", i, cfg->pwm_param);

• 	imx_iomux_v3_setup_pad(cfg->pwm_padmux |
  

• 	imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
  		       MUX_PAD_CTRL(ctrl));
  

  } }

@@ -846,9 +972,10 @@ static void setup_board_gpio(int board) int imx6_pcie_toggle_reset(void) { if (board_type < GW_UNKNOWN) {

• gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0);
  

• uint pin = gpio_cfg[board_type].pcie_rst;
  

• gpio_direction_output(pin, 0);
  

  mdelay(50);

• gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1);
  

• gpio_direction_output(pin, 1);
  

  } return 0;

} @@ -916,9 +1043,15 @@ int board_init(void) #ifdef CONFIG_MXC_SPI setup_spi(); #endif

• setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
• setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
• setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);

• if (is_cpu_type(MXC_CPU_MX6Q)) {

• setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
  

• setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
  

• setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
  

• } else {

• setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
  

• setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
  

• setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
  

• }

#ifdef CONFIG_CMD_SATA setup_sata(); @@ -927,11 +1060,13 @@ int board_init(void) board_type = read_eeprom();

/* board-specifc GPIO iomux */

• SETUP_PADS(gw_gpio_pads); if (board_type < GW_UNKNOWN) {

• imx_iomux_v3_setup_multiple_pads(gw_gpio_pads,
  

• 				 ARRAY_SIZE(gw_gpio_pads));
  

• imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads,
  

• 				 gpio_cfg[board_type].num_pads);
  

• iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
  

• int count = gpio_cfg[board_type].num_pads;
  

• unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
  

• imx_iomux_v3_setup_multiple_pads_array(p, count, cputype, 2);
  

  }

  return 0;

Best regards, Stefano Babic

Hi Tim,

On 03/04/2014 08:01, Tim Harvey wrote:

Switch to an SPL image. The SPL for Ventana does the following:

• setup i2c and read the factory programmed EEPROM to obtain DRAM config and model for board-specific calibration data
• configure DRAM per CPU/size/layout/devices/calibration
• load u-boot.img from NAND and jump to it

This allows for a single SPL+u-boot.img to replace the previous multiple board configurations.

Signed-off-by: Tim Harvey tharvey@gateworks.com

board/gateworks/gw_ventana/Makefile | 2 +- board/gateworks/gw_ventana/README | 91 +++--- board/gateworks/gw_ventana/gw_ventana.c | 5 +- board/gateworks/gw_ventana/gw_ventana.cfg | 15 - board/gateworks/gw_ventana/gw_ventana_spl.c | 394 ++++++++++++++++++++++++++ board/gateworks/gw_ventana/gw_ventana_spl.cfg | 29 ++ boards.cfg | 6 +- include/config/uboot.release | 1 + include/configs/gw_ventana.h | 13 +- 9 files changed, 500 insertions(+), 56 deletions(-) create mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c create mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.cfg create mode 100644 include/config/uboot.release

diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile index e8dab89..8b239ae 100644 --- a/board/gateworks/gw_ventana/Makefile +++ b/board/gateworks/gw_ventana/Makefile @@ -6,5 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-y := gw_ventana.o gsc.o +obj-y := gw_ventana.o gsc.o gw_ventana_spl.o

I think that gw_ventana_spl.o is always built. Should we use instead :

obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o

diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README index 9e697d6..c45d4b8 100644 --- a/board/gateworks/gw_ventana/README +++ b/board/gateworks/gw_ventana/README @@ -3,53 +3,80 @@ U-Boot for the Gateworks Ventana Product Family boards This file contains information for the port of U-Boot to the Gateworks Ventana Product family boards.

-1. Boot source, boot from NAND +1. Secondary Program Loader (SPL) +---------------------------------

+The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading +an executable image from various boot devices.

+The Gateworks Ventana board config uses an SPL build configuration. This +will build the following artifacts from u-boot source:

• • SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program

•     Loader) boots.  This detects CPU/DRAM configuration, configures
  

•     The DRAM controller, loads u-boot.img from the detected boot device,
  

•     and jumps to it.  As this is booted from the PPL, it has an IVT/DCD
  

•     table.
  

• • u-boot.img - The main u-boot core which is u-boot.bin with a image header.

+2. Build +--------

+To build U-Boot for the Gateworks Ventana product family:

• make gwventana_config
• make

+3. Boot source, boot from NAND

The i.MX6 BOOT ROM expects some structures that provide details of NAND layout and bad block information (referred to as 'bootstreams') which are replicated -multiple times in NAND. The number of replications is configurable through -board strapping options and eFUSE settings. The Freescale 'kobs-ng' -application from the Freescale LTIB BSP, which runs under Linux, must be used -to program the bootstream in order to setup the replicated headers correctly. +multiple times in NAND. The number of replications and their spacing (referred +to as search stride) is configurable through board strapping options and/or +eFUSE settings (BOOT_SEARCH_COUNT / Pages in block from BOOT_CFG2). In +addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two +copies of a bootloader in flash in the case that a bad block has corrupted one. The Freescale 'kobs-ng' application from the Freescale LTIB BSP, which runs

Line too long ?

+under Linux and operates on an MTD partition, must be used to program the +bootstream in order to setup this flash structure correctly.

The Gateworks Ventana boards with NAND flash have been factory programmed such that their eFUSE settings expect 2 copies of the boostream (this is specified by providing kobs-ng with the --search_exponent=1 argument). Once in -Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream +Linux with MTD support for the NAND on /dev/mtd0 you can program the SPL with:

-kobs-ng init -v -x --search_exponent=1 u-boot.imx +kobs-ng init -v -x --search_exponent=1 SPL

-The kobs-ng application uses an imximage (u-boot.imx) which contains the -Image Vector Table (IVT) and Device Configuration Data (DCD) structures that -the i.MX6 BOOT ROM requires to boot. The kobs-ng adds the Firmware -Configuration Block (FCB) and Discovered Bad Block Table (DBBT). +The kobs-ng application uses an imximage which contains the Image Vector Table +(IVT) and Device Configuration Data (DCD) structures that the i.MX6 BOOT ROM +requires to boot. The kobs-ng adds the Firmware Configuration Block (FCB) and +Discovered Bad Block Table (DBBT). The SPL build artifact from u-boot is +an imximage.

-This information is taken from:

• http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH

+The u-boot.img, which is the non SPL u-boot binary appended to a u-boot image +header must be programmed in the NAND flash boot device at an offset hard +coded in the SPL. For the Ventana boards, this has been chosen to be 14MB. +The image can be programmed from either u-boot or Linux:

-More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.

-2. Build

+u-boot: +Ventana > setenv mtdparts mtdparts=nand:14m(spl),2m(uboot),1m(env),-(rootfs) +Ventana > tftp ${loadaddr} u-boot.img && nand erase.part uboot && \

•      nand write ${loadaddr} uboot ${filesize}
  
  

-There are several Gateworks Ventana boards that share a simliar design but -vary based on CPU, Memory configuration, and subloaded devices. Although -the subloaded devices are handled dynamically in the bootloader using -factory configured EEPROM data to modify the device-tree, the CPU choice -(IMX6Q vs IMX6DL) and memory configurations are currently compile-time -options. +Linux: +nandwrite /dev/mtd1 u-boot.img

-The following Gateworks Ventana configurations exist:

• gwventanaq1gspi: MX6Q,1GB,SPI FLASH
• gwventanaq : MX6Q,512MB,NAND FLASH
• gwventanaq1g : MX6Q,1GB,NAND FLASH
• gwventanadl : MX6DL,512MB,NAND FLASH
• gwventanadl1g : MX6DL,1GB,NAND FLASH

+The above assumes the default Ventana partitioning scheme which is configured +via the mtdparts env var:

• • spl: 14MB
• • uboot: 2M
• • env: 1M
• • rootfs: the rest

-To build U-Boot for the MX6Q,1GB,NAND FLASH for example: +This information is taken from:

• http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH

• make gwventanaq1g_config
• make

+More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.

diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index ebf7e7d..7508141 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1019,8 +1019,9 @@ int board_early_init_f(void)

int dram_init(void) {

• gd->ram_size = get_ram_size((void *)PHYS_SDRAM,

• 		    CONFIG_DDR_MB*1024*1024);
  

• struct mx6_spl_data *data = (struct mx6_spl_data *)

• ((CONFIG_SPL_TEXT_BASE - sizeof(struct mx6_spl_data)) & ~0xf);
  

Ok, you have *data on the stack, you initialize to a magic number and then you do nothing with it.

• gd->ram_size = data->mem_dram_size;

We have already talked about it. A runtime detection is absolutely preferable, as suggested by Igor.

return 0; } diff --git a/board/gateworks/gw_ventana/gw_ventana.cfg b/board/gateworks/gw_ventana/gw_ventana.cfg index 27f0974..9ab95f5 100644 --- a/board/gateworks/gw_ventana/gw_ventana.cfg +++ b/board/gateworks/gw_ventana/gw_ventana.cfg @@ -24,21 +24,6 @@ BOOT_FROM nand

#define __ASSEMBLY__ #include <config.h> -#include "asm/arch/mx6-ddr.h" #include "asm/arch/iomux.h" #include "asm/arch/crm_regs.h"

-/* Memory configuration (size is overridden via eeprom config) */ -#include "../../boundary/nitrogen6x/ddr-setup.cfg" -#if defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 1024

• #include "../../boundary/nitrogen6x/1066mhz_4x128mx16.cfg"

-#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 1024

• #include "../../boundary/nitrogen6x/800mhz_4x128mx16.cfg"

-#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 512

• #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"

-#elif defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 512

• #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"

-#else

• #error "Unsupported CPU/Memory configuration"

-#endif #include "clocks.cfg"

Right - this is what I have expected for the .cfg file adding SPL.

diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c new file mode 100644 index 0000000..492c814 --- /dev/null +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -0,0 +1,394 @@ +/*

• • Author: Tim Harvey tharvey@gateworks.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6_ddr_regs.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#ifdef CONFIG_SPL +#include <spl.h> +#endif

+DECLARE_GLOBAL_DATA_PTR;

+#if defined(CONFIG_SPL_BUILD)

I will drop it from here and conditionally compile this file if SPL_BUILD is set.

+#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ +#define I2C_GSC 0 +#define GSC_EEPROM_ADDR 0x51 +#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */ +#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */ +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

• PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
• PAD_CTL_ODE | PAD_CTL_SRE_FAST)

+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define CONFIG_SYS_I2C_SPEED 100000

+/* I2C1: GSC */ +static struct i2c_pads_info mx6q_i2c_pad_info0 = {

• .scl = {

• .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
  

• .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
  

• .gp = IMX_GPIO_NR(3, 21)
  

• },
• .sda = {

• .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
  

• .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
  

• .gp = IMX_GPIO_NR(3, 28)
  

• }

+}; +static struct i2c_pads_info mx6dl_i2c_pad_info0 = {

• .scl = {

• .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
  

• .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
  

• .gp = IMX_GPIO_NR(3, 21)
  

• },
• .sda = {

• .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
  

• .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
  

• .gp = IMX_GPIO_NR(3, 28)
  

• }

+};

+static void i2c_setup_iomux(void) +{

• if (is_cpu_type(MXC_CPU_MX6Q))

• setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
  

• else

• setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
  

+}

+static u16 +read_eeprom(void)

+{

• u8 data[3];
• /*

• * On a board with a missing/depleted backup battery for GSC, the
  

• * board may be ready to probe the GSC before its firmware is
  

• * running.  We will wait here indefinately for the GSC/EEPROM.
  

• */
  

• while (1) {

• if (0 == i2c_set_bus_num(I2C_GSC) &&
  

•     0 == i2c_probe(GSC_EEPROM_ADDR))
  

• 	break;
  

• /* TODO: mdelay hangs at this point
  

• mdelay(1);
  

• */
  

• }
• i2c_read(GSC_EEPROM_ADDR, GSC_EEPROM_DDR_SIZE, 1, data, 3);
• return (data[0] << 8) | data[2];

+}

This is a simplified version of the same function in gw_ventana.c. By submitting the original patch, you convinced me that due to hardware issues the read can fails the first time and you add gsc_i2c_read(). Why do we have no problem with i2c in SPL ? It should be even worse.

+/* configure mx6 mmdc io registers */ +struct mx6_mmdc_ioregs mmdc_ioregs = {

• /* DDR3 */
• .mmdc_grp_ddr_type = 0x000c0000,
• /* disable DDR pullups */
• .mmdc_grp_ddrpke = 0x00000000,
• /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
• .mmdc_dram_sdclk_0 = 0x00020030,
• .mmdc_dram_sdclk_1 = 0x00020030,
• .mmdc_dram_cas = 0x00020030,
• .mmdc_dram_ras = 0x00020030,
• .mmdc_dram_reset = 0x00020030,
• /* ADDR[00:16], SDBA[0:1]: 40 ohm */
• .mmdc_grp_addds = 0x00000030,
• /* SDCKE[0:1]: 100k pull-up */
• .mmdc_dram_sdcke0 = 0x00003000,
• .mmdc_dram_sdcke1 = 0x00003000,
• /* SDBA2: pull-up disabled */
• .mmdc_dram_sdba2 = 0x00000000,
• /* SDODT[0:1]: 100k pull-up, 40 ohm */
• .mmdc_dram_sdodt0 = 0x00003030,
• .mmdc_dram_sdodt1 = 0x00003030,
• /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
• .mmdc_grp_ctlds = 0x00000030,
• /* SDQS[0:7]: Differential input, 40 ohm */
• .mmdc_ddrmode_ctl = 0x00020000,
• .mmdc_dram_sdqs0 = 0x00000030,
• .mmdc_dram_sdqs1 = 0x00000030,
• .mmdc_dram_sdqs2 = 0x00000030,
• .mmdc_dram_sdqs3 = 0x00000030,
• .mmdc_dram_sdqs4 = 0x00000030,
• .mmdc_dram_sdqs5 = 0x00000030,
• .mmdc_dram_sdqs6 = 0x00000030,
• .mmdc_dram_sdqs7 = 0x00000030,
• /* DATA[00:63]: Differential input, 40 ohm */
• .mmdc_grp_ddrmode = 0x00020000,
• .mmdc_grp_b0ds = 0x00000030,
• .mmdc_grp_b1ds = 0x00000030,
• .mmdc_grp_b2ds = 0x00000030,
• .mmdc_grp_b3ds = 0x00000030,
• .mmdc_grp_b4ds = 0x00000030,
• .mmdc_grp_b5ds = 0x00000030,
• .mmdc_grp_b6ds = 0x00000030,
• .mmdc_grp_b7ds = 0x00000030,
• /* DQM[0:7]: Differential input, 40 ohm */
• .mmdc_dram_dqm0 = 0x00020030,
• .mmdc_dram_dqm1 = 0x00020030,
• .mmdc_dram_dqm2 = 0x00020030,
• .mmdc_dram_dqm3 = 0x00020030,
• .mmdc_dram_dqm4 = 0x00020030,
• .mmdc_dram_dqm5 = 0x00020030,
• .mmdc_dram_dqm6 = 0x00020030,
• .mmdc_dram_dqm7 = 0x00020030,

+};

I will suggest you move these structure in a separate file. It is then easier for a board developer to understand what is very board specific.

+/* MT41K128M16JT-125 */ +static struct mx6_ddr3_cfg mt41k128m16jt_125 = {

• .mem_speed = 1600,
• .density = 2,
• .width = 16,
• .banks = 8,
• .rowaddr = 14,
• .coladdr = 10,
• .pagesz = 2,
• .trcd = 1375,
• .trcmin = 4875,
• .trasmin = 3500,

+};

+/* GW54xx specific calibration */ +static struct mx6_mmdc_calibration gw54xx_mmdc_calibration = {

• /* write leveling calibration determine */
• .mmdc_p0_mpwldectrl0 = 0x00210021,
• .mmdc_p0_mpwldectrl1 = 0x00284024,
• .mmdc_p1_mpwldectrl0 = 0x0018002b,
• .mmdc_p1_mpwldectrl1 = 0x000c801f,
• /* Read DQS Gating calibration */
• .mmdc_p0_mpdgctrl0 = 0x43430354,
• .mmdc_p0_mpdgctrl1 = 0x034e0344,
• .mmdc_p1_mpdgctrl0 = 0x43500359,
• .mmdc_p1_mpdgctrl1 = 0x034b031c,
• /* Read Calibration: DQS delay relative to DQ read access */
• .mmdc_p0_mprddlctl = 0x3e363abe,
• .mmdc_p1_mprddlctl = 0x35b23040,
• /* Write Calibration: DQ/DM delay relative to DQS write access */
• .mmdc_p0_mpwrdlctl = 0x3839403c,
• .mmdc_p1_mpwrdlctl = 0x45b6483c,

+};

+/* GW53xx specific calibration */ +static struct mx6_mmdc_calibration gw53xx_mmdc_calibration = {

• /* write leveling calibration determine */
• .mmdc_p0_mpwldectrl0 = 0x007c007e,
• .mmdc_p0_mpwldectrl1 = 0x003b007c,
• .mmdc_p1_mpwldectrl0 = 0x001f002b,
• .mmdc_p1_mpwldectrl1 = 0x003f003f,
• /* Read DQS Gating calibration */
• .mmdc_p0_mpdgctrl0 = 0x42550254,
• .mmdc_p0_mpdgctrl1 = 0x023d023d,
• .mmdc_p1_mpdgctrl0 = 0x423c027e,
• .mmdc_p1_mpdgctrl1 = 0x021c0238,
• /* Read Calibration: DQS delay relative to DQ read access */
• .mmdc_p0_mprddlctl = 0x484a4e4b,
• .mmdc_p1_mprddlctl = 0x4b4d4e4b,
• /* Write Calibration: DQ/DM delay relative to DQS write access */
• .mmdc_p0_mpwrdlctl = 0x37342f32,
• .mmdc_p1_mpwrdlctl = 0x3f33372b,

+};

+/* GW52xx specific calibration */ +static struct mx6_mmdc_calibration gw52xx_mmdc_calibration = {

• /* write leveling calibration determine */
• .mmdc_p0_mpwldectrl0 = 0x0040003C,
• .mmdc_p0_mpwldectrl1 = 0x0032003E,
• /* Read DQS Gating calibration */
• .mmdc_p0_mpdgctrl0 = 0x42350231,
• .mmdc_p0_mpdgctrl1 = 0x021A0218,
• /* Read Calibration: DQS delay relative to DQ read access */
• .mmdc_p0_mprddlctl = 0x4B4B4E49,
• /* Write Calibration: DQ/DM delay relative to DQS write access */
• .mmdc_p0_mpwrdlctl = 0x3F3F3035,

+};

+/* GW51xx specific calibration */ +static struct mx6_mmdc_calibration gw51xx_mmdc_calibration = {

• /* write leveling calibration determine */
• .mmdc_p0_mpwldectrl0 = 0x0040003C,
• .mmdc_p0_mpwldectrl1 = 0x0032003E,
• /* Read DQS Gating calibration */
• .mmdc_p0_mpdgctrl0 = 0x42350231,
• .mmdc_p0_mpdgctrl1 = 0x021A0218,
• /* Read Calibration: DQS delay relative to DQ read access */
• .mmdc_p0_mprddlctl = 0x4B4B4E49,
• /* Write Calibration: DQ/DM delay relative to DQS write access */
• .mmdc_p0_mpwrdlctl = 0x3F3F3035,

+};

+static void spl_dram_init(int ddr_cfg) +{

• struct mx6_spl_data *data = (struct mx6_spl_data *)

• ((CONFIG_SPL_TEXT_BASE - sizeof(struct mx6_spl_data)) & ~0xf);
  

• u32 cpurev, imxtype;
• int width, size;
• struct mx6_ddr3_cfg *mem = &mt41k128m16jt_125;
• struct mx6_mmdc_calibration *calib;
• struct mx6_ddr_sysinfo sysinfo = {

• .dsize = (8 << (ddr_cfg & 0xff))/32,
  

• .cs_density = (16 << (ddr_cfg>>8))/128,
  

• /* single chip select */
  

• .ncs = 1,
  

• .cs1_mirror = 0,
  

• .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
  

+#ifdef RTT_NOM_120OHM

• .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
  

+#else

• .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
  

+#endif

• .walat = 1,	/* Write additional latency */
  

• .ralat = 5,	/* Read additional latency */
  

• .mif3_mode = 3,	/* Command prediction working mode */
  

• .bi_on = 1,	/* Bank interleaving enabled */
  

• .sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
  

• .rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
  

• };
• u8 model[16];
• i2c_read(GSC_EEPROM_ADDR, 0x30, 1, model, 16);
• debug("model:%s\n", model);
• /*

• * MMDC Calibration requires the following data:
  

• *   mx6_mmdc_calibration - board-specific calibration (routing delays)
  

• *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
  

• *   mx6_ddr_cfg - chip specific timing/layout details
  

• */
  

• switch (model[3]) {
• case '1':

• calib = &gw51xx_mmdc_calibration;
  

• break;
  

• case '2':

• calib = &gw52xx_mmdc_calibration;
  

• break;
  

• case '3':

• calib = &gw53xx_mmdc_calibration;
  

• break;
  

• default:
• case '4':

• calib = &gw54xx_mmdc_calibration;
  

• break;
  

• }
• cpurev = get_cpu_rev();
• imxtype = (cpurev & 0xFF000) >> 12;
• size = (16 << (ddr_cfg >> 8));
• width = (8 << (ddr_cfg & 0xff));

• data->mem_dram_size = size * 1024 * 1024;

• get_imx_type(imxtype);
• switch (imxtype) {
• case MXC_CPU_MX6Q:

• mx6_dram_iocfg(width, &mx6dq_ctrl, &mmdc_ioregs);
  

• mx6_dram_cfg(&sysinfo, &mx6_ddrcfg, calib, mem);
  

• break;
  

• case MXC_CPU_MX6DL:
• default:

• mx6_dram_iocfg(width, &mx6sdl_ctrl, &mmdc_ioregs);
  

• mx6_dram_cfg(&sysinfo, &mx6_ddrcfg, calib, mem);
  

• break;
  

• }

+}

+/*

• • called from C runtime startup code (arch/arm/lib/crt0.S:_main)
• • • we have a stack and a place to store GD, both in SRAM
• • • no variable global data is available
• */

+void board_init_f(ulong dummy) +{

• int ddrcfg;
• /* iomux and setup of i2c */
• i2c_setup_iomux();
• /* TODO: possible to get console support at this point for debugging? */
• timer_init();
• ddrcfg = read_eeprom();
• spl_dram_init(ddrcfg);
• arch_cpu_init();
• /* Clear the BSS. */
• memset(__bss_start, 0, __bss_end - __bss_start);
• /* Set global data pointer. */
• gd = &gdata;
• board_early_init_f();
• preloader_console_init();
• if (is_cpu_type(MXC_CPU_MX6Q))

• puts("CPU: IMX6Q\n");
  

• else if (is_cpu_type(MXC_CPU_MX6DL))

• puts("CPU: IMX6DL\n");
  

• else

• puts("CPU: unsupported\n");
  

• printf("SDRAM: %dMB %dbit\n", (16 << (ddrcfg>>8)),

•       (8 << (ddrcfg & 0xff)));
  

Really do we need this in SPL ? Is not enough in U-Boot ?

• board_init_r(NULL, 0);

+}

Mmhhh...apart the access to the eeprom to get the ram size, this function should be common.

+/* called from board_init_r() to decide what spl_*_load_image() to call */ +u32 spl_boot_device(void) +{

• puts("Boot Device: ");
• switch (get_boot_device()) {
• case MX6_MMC_BOOT:

• printf("uSD\n");
  

• return BOOT_DEVICE_MMC1;
  

• case MX6_NAND_BOOT:

• printf("NAND\n");
  

• return BOOT_DEVICE_NAND;
  

• case MX6_SATA_BOOT:

• printf("SATA\n");
  

• return BOOT_DEVICE_SATA;
  

• default:

• printf("UNKNOWN\n");
  

• return BOOT_DEVICE_NONE;
  

• }

+}

This function (without unneeded printf) should be made common. Feel free to add a spl.c file inside ./arch/arm/imx-common

+#if defined(CONFIG_SPL_MMC_SUPPORT) +/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ +u32 spl_boot_mode(void) +{

• switch (get_boot_device()) {
• /* for MMC return either RAW or FAT mode */
• case BOOT_DEVICE_MMC1:

+#ifdef CONFIG_SPL_FAT_SUPPORT

• return MMCSD_MODE_FAT;
  

+#else

• return MMCSD_MODE_RAW;
  

+#endif

• break;
  

• default:

• puts("spl: ERROR:  unsupported device\n");
  

• hang();
  

• }

+} +#endif

+void reset_cpu(ulong addr) +{ +} +#endif

Ditto

diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.cfg b/board/gateworks/gw_ventana/gw_ventana_spl.cfg new file mode 100644 index 0000000..9ab95f5 --- /dev/null +++ b/board/gateworks/gw_ventana/gw_ventana_spl.cfg @@ -0,0 +1,29 @@ +/*

• • Copyright (C) 2013 Gateworks Corporation
• • SPDX-License-Identifier: GPL-2.0+
• • Refer doc/README.imximage for more details about how-to configure
• • and create imximage boot image
• • The syntax is taken as close as possible with the kwbimage
• */

+/* image version */ +IMAGE_VERSION 2

+/*

• • Boot Device : one of
• • spi, sd, nand, sata
• */

+#ifdef CONFIG_SPI_FLASH +BOOT_FROM spi +#else +BOOT_FROM nand +#endif

+#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" +#include "clocks.cfg"

Mmhhh...which is the reason to have gw_ventana.cfg and gw_ventana_spl.cfg ?

You need the .cfg file to generate the IVT header only for SPL. It is not required for U-Boot, because the boot ROM has already processed the first i.MX header.

diff --git a/boards.cfg b/boards.cfg index a7be5a3..aa48f89 100644 --- a/boards.cfg +++ b/boards.cfg @@ -320,11 +320,7 @@ Active arm armv7 mx6 freescale mx6qsabreauto Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam fabio.estevam@freescale.com Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam fabio.estevam@freescale.com Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam fabio.estevam@freescale.com -Active arm armv7 mx6 gateworks gw_ventana gwventanadl gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512 Tim Harvey tharvey@gateworks.com -Active arm armv7 mx6 gateworks gw_ventana gwventanadl1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024 Tim Harvey tharvey@gateworks.com -Active arm armv7 mx6 gateworks gw_ventana gwventanaq gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512 Tim Harvey tharvey@gateworks.com -Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey tharvey@gateworks.com -Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey tharvey@gateworks.com +Active arm armv7 mx6 gateworks gw_ventana gwventana gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL,SPL Tim Harvey tharvey@gateworks.com

Nice, only one entry for all of your boards.

Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton jon.nettleton@gmail.com Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman sakoman@gmail.com Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas notasas@gmail.com diff --git a/include/config/uboot.release b/include/config/uboot.release new file mode 100644 index 0000000..0e37110 --- /dev/null +++ b/include/config/uboot.release @@ -0,0 +1 @@ +2014.04-rc1-00227-g1879963-dirty diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 3398390..f6dc52a 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -7,6 +7,17 @@ #ifndef __CONFIG_H #define __CONFIG_H

+/* SPL */ +#define CONFIG_SPL_NAND_SUPPORT +/* +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_SATA_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +*/ +/* Location in NAND to read U-Boot from */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024)

This is ok - it is your decision where to put it.

May I ask why do you need 14 MB at the beginning ? It seems you lose a lot of place. NAND is cheap nowadays, but...

+#include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" #define CONFIG_MX6 #define CONFIG_DISPLAY_CPUINFO /* display cpu info */ @@ -242,7 +253,7 @@ "mtdparts=nor:512k(uboot),64k(env),2m(kernel),-(rootfs)" #else #define MTDIDS_DEFAULT "nand0=nand" -#define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)" +#define MTDPARTS_DEFAULT "mtdparts=nand:14m(spl),2m(uboot),1m(env),-(rootfs)"

Best regards, Stefano Babic

Hi Tim,

On 24/04/2014 10:06, Tim Harvey wrote:

...

...

+/* configure mx6 mmdc io registers */ +struct mx6_mmdc_ioregs mmdc_ioregs = {

• /* DDR3 */
  

• .mmdc_grp_ddr_type = 0x000c0000,
  

• /* disable DDR pullups */
  

• .mmdc_grp_ddrpke = 0x00000000,
  

• /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  

• .mmdc_dram_sdclk_0 = 0x00020030,
  

• .mmdc_dram_sdclk_1 = 0x00020030,
  

• .mmdc_dram_cas = 0x00020030,
  

• .mmdc_dram_ras = 0x00020030,
  

• .mmdc_dram_reset = 0x00020030,
  

• /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  

• .mmdc_grp_addds = 0x00000030,
  

• /* SDCKE[0:1]: 100k pull-up */
  

• .mmdc_dram_sdcke0 = 0x00003000,
  

• .mmdc_dram_sdcke1 = 0x00003000,
  

• /* SDBA2: pull-up disabled */
  

• .mmdc_dram_sdba2 = 0x00000000,
  

• /* SDODT[0:1]: 100k pull-up, 40 ohm */
  

• .mmdc_dram_sdodt0 = 0x00003030,
  

• .mmdc_dram_sdodt1 = 0x00003030,
  

• /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  

• .mmdc_grp_ctlds = 0x00000030,
  

• /* SDQS[0:7]: Differential input, 40 ohm */
  

• .mmdc_ddrmode_ctl = 0x00020000,
  

• .mmdc_dram_sdqs0 = 0x00000030,
  

• .mmdc_dram_sdqs1 = 0x00000030,
  

• .mmdc_dram_sdqs2 = 0x00000030,
  

• .mmdc_dram_sdqs3 = 0x00000030,
  

• .mmdc_dram_sdqs4 = 0x00000030,
  

• .mmdc_dram_sdqs5 = 0x00000030,
  

• .mmdc_dram_sdqs6 = 0x00000030,
  

• .mmdc_dram_sdqs7 = 0x00000030,
  

• /* DATA[00:63]: Differential input, 40 ohm */
  

• .mmdc_grp_ddrmode = 0x00020000,
  

• .mmdc_grp_b0ds = 0x00000030,
  

• .mmdc_grp_b1ds = 0x00000030,
  

• .mmdc_grp_b2ds = 0x00000030,
  

• .mmdc_grp_b3ds = 0x00000030,
  

• .mmdc_grp_b4ds = 0x00000030,
  

• .mmdc_grp_b5ds = 0x00000030,
  

• .mmdc_grp_b6ds = 0x00000030,
  

• .mmdc_grp_b7ds = 0x00000030,
  

• /* DQM[0:7]: Differential input, 40 ohm */
  

• .mmdc_dram_dqm0 = 0x00020030,
  

• .mmdc_dram_dqm1 = 0x00020030,
  

• .mmdc_dram_dqm2 = 0x00020030,
  

• .mmdc_dram_dqm3 = 0x00020030,
  

• .mmdc_dram_dqm4 = 0x00020030,
  

• .mmdc_dram_dqm5 = 0x00020030,
  

• .mmdc_dram_dqm6 = 0x00020030,
  

• .mmdc_dram_dqm7 = 0x00020030,
  

+};

I will suggest you move these structure in a separate file. It is then easier for a board developer to understand what is very board specific.

hmmm... they are all very board specific but ok.

Well, I am noy saying to move it outside board/gateworks/gw_ventana. My proposal is more as to signalize how to add SPL support for a new board. Anyway, I agree it is a personal taste.

not needed - I used it mainly for debugging and will remove it.

...

...

• board_init_r(NULL, 0);
  

+}

Mmhhh...apart the access to the eeprom to get the ram size, this function should be common.

maybe, but I think we should wait to see what other boards come up with SPL support to see what actually ends up being common. An SPL that supports SPI or some of the other boot devices may need to do some additional things.

Agree, this makes sense. We can do it later.

yes... considering we currently have 4 baseboards (a fifth on the way), supporting both IMX6DL or IMX6Q on each, and have 2 memory densities (a third on the way) SPL is a must for my sanity to eliminate what would be something like 5*2*3 various build-time configurations.

The dynamic ddr configuration functionality I'm proposing helps out tremendously as well because the DDR3 calibration and testing I've done tells me that each board design (varied layout between SoC and DDR3) needs its own calibration values due to propagation delays and IMX6Q/D vs IMX6DL/SOLO need different calibration values on each board as well. This can all be handled with minimal tables and easily configured at runtime via baseboard detection, cpu detection, and memory density information.

Very nice.

...

...

+#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024)

This is ok - it is your decision where to put it.

May I ask why do you need 14 MB at the beginning ? It seems you lose a lot of place. NAND is cheap nowadays, but...

it was perhaps a poor decision I made early on when I was following too much of the reference design without understanding all the details. They used a 16MB area in NAND for the bootstreams so that is what I used as well. I worked through the calculation once and the 16MB wasn't all that crazy considering at the time I was wanting enough room to support a 1MB u-boot. When you add the blocks and redundant blocks for FCB/DBBT (default is to have 2 copies of these), then double the bootloader size (because IMX BOOT ROM supports 2 firmware images for redundancy), and factor in 20% headroom to allow for bad blocks, the 16MB wasn't all that crazy. Now that I'm talking about using 14MB for a <64KB SPL image, its overkill for sure.

I don't want to impose a partition layout change on our existing users that I want to update to the SPL bootloader (with all the improved DDR3 calibration values) so I figure we'll put u-boot.img in the last 2MB of the 16MB partition for the 'bootloader' and leave the first 14MB for SPL to be flashed according to the IMX6 BOOT ROM.

ok, thanks for explanation

...

...

+#include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" #define CONFIG_MX6 #define CONFIG_DISPLAY_CPUINFO /* display cpu info */ @@ -242,7 +253,7 @@ "mtdparts=nor:512k(uboot),64k(env),2m(kernel),-(rootfs)" #else #define MTDIDS_DEFAULT "nand0=nand" -#define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)" +#define MTDPARTS_DEFAULT "mtdparts=nand:14m(spl),2m(uboot),1m(env),-(rootfs)"

and I'll be reverting that last change as well and leaving the original 16M partition for the 'bootloader' meaning the 14MB area flashed by kobs-ng according to the IMX6 BOOT ROM requirements for NAND boot as well as the 2MB area I'm reserving for u-boot.img.

If I were to split the partitions like the above change, it will cause some grief for existing users that are using the 3.0.35 (non device-tree) vendor kernel that has the mtd partitions hard coded in the board support. Instead, I decided to patch the kobs-ng application used to flash the SPL so that it can be passed a max size to use within /dev/mtd0 and users that need to upgrade to the SPL bootloader will need to use that patched kobs-ng to flash the SPL to the first 14MB, then use std mtd utils to flash u-boot.img in the area between 14M and 16M.

Don't forget, at some point soon I hope to add some functionality to u-boot to flash the SPL portion to nand (the way kobs-ng does) so that you don't need to boot to linux and use kobs-ng or use our JTAG tool.

This will be a great improvement ! Thanks for working on this issue.

Best regards, Stefano