[U-Boot] [PATCH 1/2] stm32mp: cleanup cpu.c
Move all defines at the beginning of the file
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com --- This patch follow the initial serie: arm: stm32mp1: add initial support for STM32MP157 http://patchwork.ozlabs.org/patch/884385/
arch/arm/mach-stm32mp/cpu.c | 44 +++++++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 7c43dc1..34f4d60 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -8,16 +8,16 @@ #include <asm/io.h> #include <asm/arch/stm32.h>
-void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} +/* RCC register */ +#define RCC_TZCR (STM32_RCC_BASE + 0x00) +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) +#define RCC_BDCR (STM32_RCC_BASE + 0x0140) +#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_RTCSRC GENMASK(17, 16) +#define RCC_DBGCFGR_DBGCKEN BIT(8)
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) -/********************************************** - * Security init - *********************************************/ +/* Security register */ #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
@@ -30,13 +30,11 @@ void enable_caches(void) #define PWR_CR1 (STM32_PWR_BASE + 0x00) #define PWR_CR1_DBP BIT(8)
-#define RCC_TZCR (STM32_RCC_BASE + 0x00) -#define RCC_BDCR (STM32_RCC_BASE + 0x0140) -#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) - -#define RCC_BDCR_VSWRST BIT(31) -#define RCC_BDCR_RTCSRC GENMASK(17, 16) +/* DBGMCU register */ +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) +#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) static void security_init(void) { /* Disable the backup domain write protection */ @@ -93,15 +91,9 @@ static void security_init(void) writel(0x0, TAMP_CR1); }
-/********************************************** +/* * Debug init - *********************************************/ -#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) -#define RCC_DBGCFGR_DBGCKEN BIT(8) - -#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) -#define DBGMCU_APB4FZ1_IWDG2 BIT(2) - + */ static void dbgmcu_init(void) { setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); @@ -125,6 +117,12 @@ int arch_cpu_init(void) return 0; }
+void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) {
Add support of DBGMCU_IDC for cpu identifier and revision
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
arch/arm/mach-stm32mp/cpu.c | 48 +++++++++++++++++++++++++- arch/arm/mach-stm32mp/include/mach/sys_proto.h | 16 +++++++++ 2 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-stm32mp/include/mach/sys_proto.h
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 34f4d60..3e5ac15 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -7,6 +7,7 @@ #include <clk.h> #include <asm/io.h> #include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h>
/* RCC register */ #define RCC_TZCR (STM32_RCC_BASE + 0x00) @@ -31,8 +32,13 @@ #define PWR_CR1_DBP BIT(8)
/* DBGMCU register */ +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) #define DBGMCU_APB4FZ1_IWDG2 BIT(2) +#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) +#define DBGMCU_IDC_DEV_ID_SHIFT 0 +#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) +#define DBGMCU_IDC_REV_ID_SHIFT 16
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) static void security_init(void) @@ -123,10 +129,50 @@ void enable_caches(void) dcache_enable(); }
+static u32 read_idc(void) +{ + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + + return readl(DBGMCU_IDC); +} + +u32 get_cpu_rev(void) +{ + return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; +} + +u32 get_cpu_type(void) +{ + return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - printf("CPU: STM32MP15x\n"); + char *cpu_s, *cpu_r; + + switch (get_cpu_type()) { + case CPU_STMP32MP15x: + cpu_s = "15x"; + break; + default: + cpu_s = "?"; + break; + } + + switch (get_cpu_rev()) { + case CPU_REVA: + cpu_r = "A"; + break; + case CPU_REVB: + cpu_r = "B"; + break; + default: + cpu_r = "?"; + break; + } + + printf("CPU: STM32MP%s.%s\n", cpu_s, cpu_r);
return 0; } diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h new file mode 100644 index 0000000..a8c20d1 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#define CPU_STMP32MP15x 0x500 + +/* return CPU_STMP32MPxx constants */ +u32 get_cpu_type(void); + +#define CPU_REVA 0x1000 +#define CPU_REVB 0x2000 + +/* return CPU_REV constants */ +u32 get_cpu_rev(void);
On Mon, Mar 19, 2018 at 07:09:21PM +0100, Patrick Delaunay wrote:
Add support of DBGMCU_IDC for cpu identifier and revision
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Applied to u-boot/master, thanks!
On Mon, Mar 19, 2018 at 07:09:20PM +0100, Patrick Delaunay wrote:
Move all defines at the beginning of the file
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Applied to u-boot/master, thanks!
participants (2)
-
Patrick Delaunay -
Tom Rini