[U-Boot] [PATCH 1/2] 85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic number
Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle e500mc's 64-byte cacheline properly when it gets added.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- cpu/mpc85xx/start.S | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index fc3c336..f16d4c0 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -998,8 +998,8 @@ trap_reloc: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@l + lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h + ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l mfspr r4,L1CFG0 andi. r4,r4,0x1ff slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc.
* Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc85xx/release.S | 8 ++++++++ cpu/mpc85xx/start.S | 2 ++ include/asm-ppc/cache.h | 2 ++ 4 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index b8f9125..c780687 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -134,6 +134,10 @@ int checkcpu (void) puts("Unknown"); break; } + + if (PVR_MEM(pvr) == 0x03) + puts("MC"); + printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo); diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index ec5e4da..7c3e8a1 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -24,14 +24,18 @@ __secondary_start_page: /* First do some preliminary setup */ lis r3, HID0_EMCP@h /* enable machine check */ +#ifndef CONFIG_E500MC ori r3,r3,HID0_TBEN@l /* enable Timebase */ +#endif #ifdef CONFIG_PHYS_64BIT ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ #endif mtspr SPRN_HID0,r3
+#ifndef CONFIG_E500MC li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mtspr SPRN_HID1,r3 +#endif
/* Enable branch prediction */ li r3,0x201 @@ -64,7 +68,11 @@ __secondary_start_page:
/* r10 has the base address for the entry */ mfspr r0,SPRN_PIR +#ifdef CONFIG_E500MC + rlwinm r4,r0,27,27,31 +#else mr r4,r0 +#endif slwi r8,r4,5 add r10,r3,r8
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index f16d4c0..651ff1c 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -163,8 +163,10 @@ _start_e500: ori r0,r0,HID0_TBEN@l /* Enable Timebase */ mtspr HID0,r0
+#ifndef CONFIG_E500MC li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mtspr HID1,r0 +#endif
/* Enable Branch Prediction */ #if defined(CONFIG_BTB) diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 7252be7..53e8d05 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -12,6 +12,8 @@ #define L1_CACHE_SHIFT 4 #elif defined(CONFIG_PPC64BRIDGE) #define L1_CACHE_SHIFT 7 +#elif defined(CONFIG_E500MC) +#define L1_CACHE_SHIFT 6 #else #define L1_CACHE_SHIFT 5 #endif
On Oct 23, 2008, at 01:47, Kumar Gala wrote:
Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle e500mc's 64-byte cacheline properly when it gets added.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
Grabbed this one and the e500mc one, thanks
Andy
participants (2)
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Andy Fleming -
Kumar Gala