[U-Boot] [PATCH 1/1] arm: sunxi: Allwinner A10 SPI driver
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is adapted from mailine kernel (currently 4.15.0-rc1).
Signed-off-by: Stefan Mavrodiev stefan@olimex.com --- Tested with A20-OLinuXino-Lime2 with W25Q128 chip. The output is: => sspi
=> sf probe SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB, total 16 Mib
=> sf test 0 1000000 SPI flash test: 0 erase: 188398 ticks, 86 KiB/s 0.688 Mbps 1 check: 141504 ticks, 115 KiB/s 0.920 Mbps 2 write: 174697 ticks, 93 KiB/s 0.744 Mbps 3 read: 141312 ticks, 115 KiB/s 0.920 Mbps Test passed 0 erase: 188398 ticks, 86 KiB/s 0.688 Mbps 1 check: 141504 ticks, 115 KiB/s 0.920 Mbps 2 write: 174697 ticks, 93 KiB/s 0.744 Mbps 3 read: 141312 ticks, 115 KiB/s 0.920 Mbps
drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/sun4i_spi.c | 423 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 429 insertions(+) create mode 100644 drivers/spi/sun4i_spi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 88da9a4..d78253a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -132,6 +132,11 @@ config STM32_QSPI used to access the SPI NOR flash chips on platforms embedding this ST IP core.
+config SUN4I_SPI + bool "Allwinner A10 SoCs SPI controller" + help + SPI driver for Allwinner sun4i, sun5i and sun7i SoCs + config TEGRA114_SPI bool "nVidia Tegra114 SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index ad56203..04ba305 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o +obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c new file mode 100644 index 0000000..3ef1c68 --- /dev/null +++ b/drivers/spi/sun4i_spi.c @@ -0,0 +1,423 @@ +/* + * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V. + * S.J.R. van Schaik stephan@whiteboxsystems.nl + * M.B.W. Wajer merlijn@whiteboxsystems.nl + * + * (C) Copyright 2017 Olimex Ltd.. + * Stefan Mavrodiev stefan@olimex.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <spi.h> +#include <fdt_support.h> + +#include <asm/bitops.h> +#include <asm/gpio.h> +#include <asm/io.h> + +#include <asm/arch/clock.h> + +#define SUN4I_FIFO_DEPTH 64 + +#define SUN4I_RXDATA_REG 0x00 + +#define SUN4I_TXDATA_REG 0x04 + +#define SUN4I_CTL_REG 0x08 +#define SUN4I_CTL_ENABLE BIT(0) +#define SUN4I_CTL_MASTER BIT(1) +#define SUN4I_CTL_CPHA BIT(2) +#define SUN4I_CTL_CPOL BIT(3) +#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4) +#define SUN4I_CTL_LMTF BIT(6) +#define SUN4I_CTL_TF_RST BIT(8) +#define SUN4I_CTL_RF_RST BIT(9) +#define SUN4I_CTL_XCH BIT(10) +#define SUN4I_CTL_CS_MASK 0x3000 +#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK) +#define SUN4I_CTL_DHB BIT(15) +#define SUN4I_CTL_CS_MANUAL BIT(16) +#define SUN4I_CTL_CS_LEVEL BIT(17) +#define SUN4I_CTL_TP BIT(18) + +#define SUN4I_INT_CTL_REG 0x0c +#define SUN4I_INT_CTL_RF_F34 BIT(4) +#define SUN4I_INT_CTL_TF_E34 BIT(12) +#define SUN4I_INT_CTL_TC BIT(16) + +#define SUN4I_INT_STA_REG 0x10 + +#define SUN4I_DMA_CTL_REG 0x14 + +#define SUN4I_WAIT_REG 0x18 + +#define SUN4I_CLK_CTL_REG 0x1c +#define SUN4I_CLK_CTL_CDR2_MASK 0xff +#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK) +#define SUN4I_CLK_CTL_CDR1_MASK 0xf +#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8) +#define SUN4I_CLK_CTL_DRS BIT(12) + +#define SUN4I_MAX_XFER_SIZE 0xffffff + +#define SUN4I_BURST_CNT_REG 0x20 +#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) + +#define SUN4I_XMIT_CNT_REG 0x24 +#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) + +#define SUN4I_FIFO_STA_REG 0x28 +#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f +#define SUN4I_FIFO_STA_RF_CNT_BITS 0 +#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f +#define SUN4I_FIFO_STA_TF_CNT_BITS 16 + +#define SUN4I_SPI_MAX_RATE 24000000 +#define SUN4I_SPI_MIN_RATE 3000 +#define SUN4I_SPI_DEFAULT_RATE 1000000 +#define SUN4I_SPI_TIMEOUT_US 1000000 + +struct sun4i_spi_platdata { + u32 base_addr; + u32 freq; +}; + +struct sun4i_spi_priv { + u32 base_addr; + u32 freq; + u32 mode; + + const u8 *tx_buf; + u8 *rx_buf; +}; + +DECLARE_GLOBAL_DATA_PTR; + +static inline u32 sun4i_spi_read(struct sun4i_spi_priv *priv, u32 reg) +{ + return readl(priv->base_addr + reg); +} + +static inline void sun4i_spi_write(struct sun4i_spi_priv *priv, u32 reg, + u32 value) +{ + writel(value, priv->base_addr + reg); +} + +static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len) +{ + u8 byte; + + while (len--) { + byte = readb(priv->base_addr + SUN4I_RXDATA_REG); + *priv->rx_buf++ = byte; + } +} + +static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len) +{ + u8 byte; + + while (len--) { + byte = priv->tx_buf ? *priv->tx_buf++ : 0; + writeb(byte, priv->base_addr + SUN4I_TXDATA_REG); + } +} + +static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable) +{ + struct sun4i_spi_priv *priv = dev_get_priv(bus); + u32 reg; + + reg = sun4i_spi_read(priv, SUN4I_CTL_REG); + + reg &= ~SUN4I_CTL_CS_MASK; + reg |= SUN4I_CTL_CS(cs); + + /* We want to control the chip select manually */ + reg |= SUN4I_CTL_CS_MANUAL; + + if (enable) + reg |= SUN4I_CTL_CS_LEVEL; + else + reg &= ~SUN4I_CTL_CS_LEVEL; + + reg |= SUN4I_CTL_CS_ACTIVE_LOW; + + sun4i_spi_write(priv, SUN4I_CTL_REG, reg); +} + +static int sun4i_spi_parse_pins(struct udevice *dev) +{ + const void *fdt = gd->fdt_blob; + const char *pin_name; + const fdt32_t *list; + u32 phandle; + int drive, pull = 0, pin, i; + int offset; + int size; + + list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size); + if (!list) { + printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n"); + return -EINVAL; + } + + while (size) { + phandle = fdt32_to_cpu(*list++); + size -= sizeof(*list); + + offset = fdt_node_offset_by_phandle(fdt, phandle); + if (offset < 0) + return offset; + + drive = fdt_getprop_u32_default_node(fdt, offset, 0, + "drive-strength", 0); + if (drive) { + if (drive <= 10) + drive = 0; + else if (drive <= 20) + drive = 1; + else if (drive <= 30) + drive = 2; + else + drive = 3; + } else { + drive = fdt_getprop_u32_default_node(fdt, offset, 0, + "allwinner,drive", + 0); + drive = min(drive, 3); + } + + if (fdt_get_property(fdt, offset, "bias-disable", NULL)) + pull = 0; + else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL)) + pull = 1; + else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL)) + pull = 2; + else + pull = fdt_getprop_u32_default_node(fdt, offset, 0, + "allwinner,pull", + 0); + pull = min(pull, 2); + + for (i = 0; ; i++) { + pin_name = fdt_stringlist_get(fdt, offset, + "pins", i, NULL); + if (!pin_name) { + pin_name = fdt_stringlist_get(fdt, offset, + "allwinner,pins", + i, NULL); + if (!pin_name) + break; + } + + pin = name_to_gpio(pin_name); + if (pin < 0) + break; + + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0); + sunxi_gpio_set_drv(pin, drive); + sunxi_gpio_set_pull(pin, pull); + } + } + return 0; +} + +static inline void sun4i_spi_enable_clock(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *const)SUNXI_CCM_BASE; + + setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0)); + writel((1 << 31), &ccm->spi0_clk_cfg); +} + +static int sun4i_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct sun4i_spi_platdata *plat = dev_get_platdata(bus); + + plat->base_addr = devfdt_get_addr(bus); + plat->freq = SUN4I_SPI_DEFAULT_RATE; + + return 0; +} + +static int sun4i_spi_probe(struct udevice *bus) +{ + struct sun4i_spi_platdata *plat = dev_get_platdata(bus); + struct sun4i_spi_priv *priv = dev_get_priv(bus); + + sun4i_spi_enable_clock(); + sun4i_spi_parse_pins(bus); + + priv->base_addr = plat->base_addr; + priv->freq = plat->freq; + + return 0; +} + +static int sun4i_spi_claim_bus(struct udevice *dev) +{ + struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); + + sun4i_spi_write(priv, SUN4I_CTL_REG, + SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP); + return 0; +} + +static int sun4i_spi_release_bus(struct udevice *dev) +{ + struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); + u32 reg; + + reg = sun4i_spi_read(priv, SUN4I_CTL_REG); + reg &= ~SUN4I_CTL_ENABLE; + sun4i_spi_write(priv, SUN4I_CTL_REG, reg); + + return 0; +} + +static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct sun4i_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + + u32 len = bitlen / 8; + u32 reg; + u8 nbytes; + int timeout; + + priv->tx_buf = dout; + priv->rx_buf = din; + + if (bitlen % 8) { + debug("%s: non byte-aligned SPI transfer.\n", __func__); + return -ENAVAIL; + } + + if (flags & SPI_XFER_BEGIN) + sun4i_spi_set_cs(bus, slave_plat->cs, 0); + + reg = sun4i_spi_read(priv, SUN4I_CTL_REG); + + /* Reset FIFOs */ + sun4i_spi_write(priv, SUN4I_CTL_REG, + reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST); + + while (len) { + /* Setup the transfer now... */ + nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1)); + + /* Setup the counters */ + sun4i_spi_write(priv, SUN4I_BURST_CNT_REG, + SUN4I_BURST_CNT(nbytes)); + sun4i_spi_write(priv, SUN4I_XMIT_CNT_REG, + SUN4I_XMIT_CNT(nbytes)); + + /* Fill the TX FIFO */ + sun4i_spi_fill_fifo(priv, nbytes); + + /* Start the transfer */ + reg = sun4i_spi_read(priv, SUN4I_CTL_REG); + sun4i_spi_write(priv, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH); + + /* Wait transfer to complete */ + timeout = SUN4I_SPI_TIMEOUT_US; + while ((sun4i_spi_read(priv, SUN4I_CTL_REG) & SUN4I_CTL_XCH) && + timeout--) + udelay(1); + + if (timeout < 0) { + printf("ERROR: sun4i_spi: Timeout transferring data\n"); + sun4i_spi_set_cs(bus, slave_plat->cs, 1); + return -ETIMEDOUT; + } + + /* Drain the RX FIFO */ + sun4i_spi_drain_fifo(priv, nbytes); + + len -= nbytes; + } + + if (flags & SPI_XFER_END) + sun4i_spi_set_cs(bus, slave_plat->cs, 1); + + return 0; +} + +static int sun4i_spi_set_speed(struct udevice *dev, uint speed) +{ + struct sun4i_spi_priv *priv = dev_get_priv(dev); + unsigned int div; + u32 reg; + + speed = min(speed, (unsigned int)SUN4I_SPI_MAX_RATE); + speed = max((unsigned int)SUN4I_SPI_MIN_RATE, speed); + + div = SUN4I_SPI_MAX_RATE / (2 * speed); + + if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { + if (div > 0) + div--; + + reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; + } else { + div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed); + reg = SUN4I_CLK_CTL_CDR1(div); + } + + priv->freq = speed; + sun4i_spi_write(priv, SUN4I_CLK_CTL_REG, reg); + + return 0; +} + +static int sun4i_spi_set_mode(struct udevice *dev, uint mode) +{ + struct sun4i_spi_priv *priv = dev_get_priv(dev); + u32 reg; + + reg = sun4i_spi_read(priv, SUN4I_CTL_REG); + reg &= ~(SUN4I_CTL_CPOL | SUN4I_CTL_CPHA); + + if (mode & SPI_CPOL) + reg |= SUN4I_CTL_CPOL; + + if (mode & SPI_CPHA) + reg |= SUN4I_CTL_CPHA; + + priv->mode = mode; + sun4i_spi_write(priv, SUN4I_CTL_REG, reg); + + return 0; +} + +static const struct dm_spi_ops sun4i_spi_ops = { + .claim_bus = sun4i_spi_claim_bus, + .release_bus = sun4i_spi_release_bus, + .xfer = sun4i_spi_xfer, + .set_speed = sun4i_spi_set_speed, + .set_mode = sun4i_spi_set_mode, +}; + +static const struct udevice_id sun4i_spi_ids[] = { + { .compatible = "allwinner,sun4i-a10-spi" }, + { } +}; + +U_BOOT_DRIVER(sun4i_spi) = { + .name = "sun4i_spi", + .id = UCLASS_SPI, + .of_match = sun4i_spi_ids, + .ops = &sun4i_spi_ops, + .ofdata_to_platdata = sun4i_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct sun4i_spi_platdata), + .priv_auto_alloc_size = sizeof(struct sun4i_spi_priv), + .probe = sun4i_spi_probe, +};
Hi Stefan,
On Fri, Dec 01, 2017 at 10:27:12AM +0200, Stefan Mavrodiev wrote:
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is adapted from mailine kernel (currently 4.15.0-rc1).
Signed-off-by: Stefan Mavrodiev stefan@olimex.com
Tested with A20-OLinuXino-Lime2 with W25Q128 chip. The output is: => sspi
=> sf probe SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB, total 16 Mib
=> sf test 0 1000000 SPI flash test: 0 erase: 188398 ticks, 86 KiB/s 0.688 Mbps 1 check: 141504 ticks, 115 KiB/s 0.920 Mbps 2 write: 174697 ticks, 93 KiB/s 0.744 Mbps 3 read: 141312 ticks, 115 KiB/s 0.920 Mbps Test passed 0 erase: 188398 ticks, 86 KiB/s 0.688 Mbps 1 check: 141504 ticks, 115 KiB/s 0.920 Mbps 2 write: 174697 ticks, 93 KiB/s 0.744 Mbps 3 read: 141312 ticks, 115 KiB/s 0.920 Mbps
drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/sun4i_spi.c | 423 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 429 insertions(+) create mode 100644 drivers/spi/sun4i_spi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 88da9a4..d78253a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -132,6 +132,11 @@ config STM32_QSPI used to access the SPI NOR flash chips on platforms embedding this ST IP core.
+config SUN4I_SPI
- bool "Allwinner A10 SoCs SPI controller"
- help
SPI driver for Allwinner sun4i, sun5i and sun7i SoCsconfig TEGRA114_SPI bool "nVidia Tegra114 SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index ad56203..04ba305 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o +obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c new file mode 100644 index 0000000..3ef1c68 --- /dev/null +++ b/drivers/spi/sun4i_spi.c @@ -0,0 +1,423 @@ +/*
- (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
- S.J.R. van Schaik stephan@whiteboxsystems.nl
- M.B.W. Wajer merlijn@whiteboxsystems.nl
- (C) Copyright 2017 Olimex Ltd..
- Stefan Mavrodiev stefan@olimex.com
- SPDX-License-Identifier: GPL-2.0+
If you indeed based this on the kernel driver, you should keep the original copyrights holder.
It looks good otherwise, let's see what Jagan thinks about it.
Thanks! Maxime
On Fri, Dec 1, 2017 at 1:57 PM, Stefan Mavrodiev stefan@olimex.com wrote:
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is adapted from mailine kernel (currently 4.15.0-rc1).
Signed-off-by: Stefan Mavrodiev stefan@olimex.com
Tested with A20-OLinuXino-Lime2 with W25Q128 chip. The output is: => sspi
=> sf probe SF: Detected w25q128bv with page size 256 Bytes, erase size 4 KiB, total 16 Mib
=> sf test 0 1000000 SPI flash test: 0 erase: 188398 ticks, 86 KiB/s 0.688 Mbps 1 check: 141504 ticks, 115 KiB/s 0.920 Mbps 2 write: 174697 ticks, 93 KiB/s 0.744 Mbps 3 read: 141312 ticks, 115 KiB/s 0.920 Mbps Test passed 0 erase: 188398 ticks, 86 KiB/s 0.688 Mbps 1 check: 141504 ticks, 115 KiB/s 0.920 Mbps 2 write: 174697 ticks, 93 KiB/s 0.744 Mbps 3 read: 141312 ticks, 115 KiB/s 0.920 Mbps
drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/sun4i_spi.c | 423 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 429 insertions(+) create mode 100644 drivers/spi/sun4i_spi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 88da9a4..d78253a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -132,6 +132,11 @@ config STM32_QSPI used to access the SPI NOR flash chips on platforms embedding this ST IP core.
+config SUN4I_SPI
bool "Allwinner A10 SoCs SPI controller"helpSPI driver for Allwinner sun4i, sun5i and sun7i SoCsconfig TEGRA114_SPI bool "nVidia Tegra114 SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index ad56203..04ba305 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o +obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c new file mode 100644 index 0000000..3ef1c68 --- /dev/null +++ b/drivers/spi/sun4i_spi.c @@ -0,0 +1,423 @@ +/*
- (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
- S.J.R. van Schaik stephan@whiteboxsystems.nl
- M.B.W. Wajer merlijn@whiteboxsystems.nl
- (C) Copyright 2017 Olimex Ltd..
- Stefan Mavrodiev stefan@olimex.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <spi.h> +#include <fdt_support.h>
+#include <asm/bitops.h> +#include <asm/gpio.h> +#include <asm/io.h>
+#include <asm/arch/clock.h>
+#define SUN4I_FIFO_DEPTH 64
+#define SUN4I_RXDATA_REG 0x00
+#define SUN4I_TXDATA_REG 0x04
+#define SUN4I_CTL_REG 0x08 +#define SUN4I_CTL_ENABLE BIT(0) +#define SUN4I_CTL_MASTER BIT(1) +#define SUN4I_CTL_CPHA BIT(2) +#define SUN4I_CTL_CPOL BIT(3) +#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4) +#define SUN4I_CTL_LMTF BIT(6) +#define SUN4I_CTL_TF_RST BIT(8) +#define SUN4I_CTL_RF_RST BIT(9) +#define SUN4I_CTL_XCH BIT(10) +#define SUN4I_CTL_CS_MASK 0x3000 +#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK) +#define SUN4I_CTL_DHB BIT(15) +#define SUN4I_CTL_CS_MANUAL BIT(16) +#define SUN4I_CTL_CS_LEVEL BIT(17) +#define SUN4I_CTL_TP BIT(18)
+#define SUN4I_INT_CTL_REG 0x0c +#define SUN4I_INT_CTL_RF_F34 BIT(4) +#define SUN4I_INT_CTL_TF_E34 BIT(12) +#define SUN4I_INT_CTL_TC BIT(16)
+#define SUN4I_INT_STA_REG 0x10
+#define SUN4I_DMA_CTL_REG 0x14
+#define SUN4I_WAIT_REG 0x18
+#define SUN4I_CLK_CTL_REG 0x1c +#define SUN4I_CLK_CTL_CDR2_MASK 0xff +#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK) +#define SUN4I_CLK_CTL_CDR1_MASK 0xf +#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8) +#define SUN4I_CLK_CTL_DRS BIT(12)
+#define SUN4I_MAX_XFER_SIZE 0xffffff
+#define SUN4I_BURST_CNT_REG 0x20 +#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
+#define SUN4I_XMIT_CNT_REG 0x24 +#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
+#define SUN4I_FIFO_STA_REG 0x28 +#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f +#define SUN4I_FIFO_STA_RF_CNT_BITS 0 +#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f +#define SUN4I_FIFO_STA_TF_CNT_BITS 16
+#define SUN4I_SPI_MAX_RATE 24000000 +#define SUN4I_SPI_MIN_RATE 3000 +#define SUN4I_SPI_DEFAULT_RATE 1000000 +#define SUN4I_SPI_TIMEOUT_US 1000000
+struct sun4i_spi_platdata {
u32 base_addr;u32 freq;+};
+struct sun4i_spi_priv {
u32 base_addr;u32 freq;u32 mode;const u8 *tx_buf;u8 *rx_buf;+};
+DECLARE_GLOBAL_DATA_PTR;
+static inline u32 sun4i_spi_read(struct sun4i_spi_priv *priv, u32 reg) +{
return readl(priv->base_addr + reg);+}
+static inline void sun4i_spi_write(struct sun4i_spi_priv *priv, u32 reg,
u32 value)+{
writel(value, priv->base_addr + reg);+}
Understand this got syned from Linux, would be better to go with simple. like using direct ops.
+static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len) +{
u8 byte;while (len--) {byte = readb(priv->base_addr + SUN4I_RXDATA_REG);*priv->rx_buf++ = byte;}+}
+static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len) +{
u8 byte;while (len--) {byte = priv->tx_buf ? *priv->tx_buf++ : 0;writeb(byte, priv->base_addr + SUN4I_TXDATA_REG);}+}
+static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable) +{
struct sun4i_spi_priv *priv = dev_get_priv(bus);u32 reg;reg = sun4i_spi_read(priv, SUN4I_CTL_REG);reg &= ~SUN4I_CTL_CS_MASK;reg |= SUN4I_CTL_CS(cs);/* We want to control the chip select manually */reg |= SUN4I_CTL_CS_MANUAL;
This can be done during probe, not needed fr every time.
if (enable)reg |= SUN4I_CTL_CS_LEVEL;elsereg &= ~SUN4I_CTL_CS_LEVEL;reg |= SUN4I_CTL_CS_ACTIVE_LOW;
I think this is needed for idle level becuase of manual chip selection, can you try to do the same in probe?
sun4i_spi_write(priv, SUN4I_CTL_REG, reg);+}
+static int sun4i_spi_parse_pins(struct udevice *dev) +{
const void *fdt = gd->fdt_blob;const char *pin_name;const fdt32_t *list;u32 phandle;int drive, pull = 0, pin, i;int offset;int size;list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);if (!list) {printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");return -EINVAL;}while (size) {phandle = fdt32_to_cpu(*list++);size -= sizeof(*list);offset = fdt_node_offset_by_phandle(fdt, phandle);if (offset < 0)return offset;drive = fdt_getprop_u32_default_node(fdt, offset, 0,"drive-strength", 0);if (drive) {if (drive <= 10)drive = 0;else if (drive <= 20)drive = 1;else if (drive <= 30)drive = 2;elsedrive = 3;} else {drive = fdt_getprop_u32_default_node(fdt, offset, 0,"allwinner,drive",0);drive = min(drive, 3);}if (fdt_get_property(fdt, offset, "bias-disable", NULL))pull = 0;else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))pull = 1;else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))pull = 2;elsepull = fdt_getprop_u32_default_node(fdt, offset, 0,"allwinner,pull",0);pull = min(pull, 2);for (i = 0; ; i++) {pin_name = fdt_stringlist_get(fdt, offset,"pins", i, NULL);if (!pin_name) {pin_name = fdt_stringlist_get(fdt, offset,"allwinner,pins",i, NULL);if (!pin_name)break;}pin = name_to_gpio(pin_name);if (pin < 0)break;sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);sunxi_gpio_set_drv(pin, drive);sunxi_gpio_set_pull(pin, pull);}}return 0;+}
+static inline void sun4i_spi_enable_clock(void) +{
struct sunxi_ccm_reg *const ccm =(struct sunxi_ccm_reg *const)SUNXI_CCM_BASE;setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));writel((1 << 31), &ccm->spi0_clk_cfg);+}
+static int sun4i_spi_ofdata_to_platdata(struct udevice *bus) +{
struct sun4i_spi_platdata *plat = dev_get_platdata(bus);plat->base_addr = devfdt_get_addr(bus);plat->freq = SUN4I_SPI_DEFAULT_RATE;return 0;+}
+static int sun4i_spi_probe(struct udevice *bus) +{
struct sun4i_spi_platdata *plat = dev_get_platdata(bus);struct sun4i_spi_priv *priv = dev_get_priv(bus);sun4i_spi_enable_clock();sun4i_spi_parse_pins(bus);priv->base_addr = plat->base_addr;priv->freq = plat->freq;return 0;+}
+static int sun4i_spi_claim_bus(struct udevice *dev) +{
struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);sun4i_spi_write(priv, SUN4I_CTL_REG,SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);return 0;+}
+static int sun4i_spi_release_bus(struct udevice *dev) +{
struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);u32 reg;reg = sun4i_spi_read(priv, SUN4I_CTL_REG);reg &= ~SUN4I_CTL_ENABLE;sun4i_spi_write(priv, SUN4I_CTL_REG, reg);return 0;+}
+static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)+{
struct udevice *bus = dev->parent;struct sun4i_spi_priv *priv = dev_get_priv(bus);struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);u32 len = bitlen / 8;u32 reg;u8 nbytes;int timeout;priv->tx_buf = dout;priv->rx_buf = din;if (bitlen % 8) {debug("%s: non byte-aligned SPI transfer.\n", __func__);return -ENAVAIL;}if (flags & SPI_XFER_BEGIN)sun4i_spi_set_cs(bus, slave_plat->cs, 0);
false better than 0
reg = sun4i_spi_read(priv, SUN4I_CTL_REG);/* Reset FIFOs */sun4i_spi_write(priv, SUN4I_CTL_REG,reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);while (len) {/* Setup the transfer now... */nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1));/* Setup the counters */sun4i_spi_write(priv, SUN4I_BURST_CNT_REG,SUN4I_BURST_CNT(nbytes));sun4i_spi_write(priv, SUN4I_XMIT_CNT_REG,SUN4I_XMIT_CNT(nbytes));/* Fill the TX FIFO */sun4i_spi_fill_fifo(priv, nbytes);/* Start the transfer */reg = sun4i_spi_read(priv, SUN4I_CTL_REG);sun4i_spi_write(priv, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);/* Wait transfer to complete */timeout = SUN4I_SPI_TIMEOUT_US;while ((sun4i_spi_read(priv, SUN4I_CTL_REG) & SUN4I_CTL_XCH) &&timeout--)udelay(1);if (timeout < 0) {printf("ERROR: sun4i_spi: Timeout transferring data\n");sun4i_spi_set_cs(bus, slave_plat->cs, 1);return -ETIMEDOUT;}
Use wait_for_bit
/* Drain the RX FIFO */sun4i_spi_drain_fifo(priv, nbytes);len -= nbytes;}if (flags & SPI_XFER_END)sun4i_spi_set_cs(bus, slave_plat->cs, 1);
true better than 1
return 0;+}
+static int sun4i_spi_set_speed(struct udevice *dev, uint speed) +{
struct sun4i_spi_priv *priv = dev_get_priv(dev);unsigned int div;u32 reg;speed = min(speed, (unsigned int)SUN4I_SPI_MAX_RATE);
SUN4I_SPI_MAX_RATE can be add though 'spi-max-frequency' dt attribute
speed = max((unsigned int)SUN4I_SPI_MIN_RATE, speed);
re-assingment? why we need min?
Add divider calculation comments here.
div = SUN4I_SPI_MAX_RATE / (2 * speed);
What if speed is 0? may be though sf probe 0 0 0 better add default div if speed == 0
if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {if (div > 0)div--;reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;} else {div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed);reg = SUN4I_CLK_CTL_CDR1(div);}priv->freq = speed;sun4i_spi_write(priv, SUN4I_CLK_CTL_REG, reg);return 0;+}
+static int sun4i_spi_set_mode(struct udevice *dev, uint mode) +{
struct sun4i_spi_priv *priv = dev_get_priv(dev);u32 reg;reg = sun4i_spi_read(priv, SUN4I_CTL_REG);reg &= ~(SUN4I_CTL_CPOL | SUN4I_CTL_CPHA);if (mode & SPI_CPOL)reg |= SUN4I_CTL_CPOL;if (mode & SPI_CPHA)reg |= SUN4I_CTL_CPHA;priv->mode = mode;sun4i_spi_write(priv, SUN4I_CTL_REG, reg);
thanks!
participants (3)
-
Jagan Teki -
Maxime Ripard -
Stefan Mavrodiev