[U-Boot] [PATCH v1 1/4] mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled
From: Yangbo Lu yangbo.lu@nxp.com
u-boot is trying to make CONFIG_BLK as a hard requirement for DM_MMC. But now it's still not.
config BLK bool "Support block devices" depends on DM default y if DM_MMC
When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC without CONFIG_BLK enabled wasn't considered. This patch is to fix probe issue without CONFIG_BLK enabled.
Signed-off-by: Yangbo Lu yangbo.lu@nxp.com --- drivers/mmc/fsl_esdhc.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 9e34557d16..45516f807a 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -25,6 +25,10 @@ #include <asm-generic/gpio.h> #include <dm/pinctrl.h>
+#if !CONFIG_IS_ENABLED(BLK) +#include "mmc_private.h" +#endif + DECLARE_GLOBAL_DATA_PTR;
#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ @@ -1448,6 +1452,9 @@ static int fsl_esdhc_probe(struct udevice *dev) fdt_addr_t addr; unsigned int val; struct mmc *mmc; +#if !CONFIG_IS_ENABLED(BLK) + struct blk_desc *bdesc; +#endif int ret;
addr = dev_read_addr(dev); @@ -1576,6 +1583,26 @@ static int fsl_esdhc_probe(struct udevice *dev) mmc = &plat->mmc; mmc->cfg = &plat->cfg; mmc->dev = dev; +#if !CONFIG_IS_ENABLED(BLK) + mmc->priv = priv; + + /* Setup dsr related values */ + mmc->dsr_imp = 0; + mmc->dsr = 0xffffffff; + /* Setup the universal parts of the block interface just once */ + bdesc = mmc_get_blk_desc(mmc); + bdesc->if_type = IF_TYPE_MMC; + bdesc->removable = 1; + bdesc->devnum = mmc_get_next_devnum(); + bdesc->block_read = mmc_bread; + bdesc->block_write = mmc_bwrite; + bdesc->block_erase = mmc_berase; + + /* setup initial part type */ + bdesc->part_type = mmc->cfg->part_type; + mmc_list_add(mmc); +#endif + upriv->mmc = mmc;
return esdhc_init_common(priv, mmc);
From: Yangbo Lu yangbo.lu@nxp.com
Layerscape began to use two eSDHC controllers, for example, LS1028A. They were same IP block with same reference clock. This patch is to add clock support for the second eSDHC.
Signed-off-by: Yangbo Lu yangbo.lu@nxp.com Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 1 + arch/arm/include/asm/arch-fsl-layerscape/clock.h | 1 + 2 files changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index bc268e207c..7dbca1f06f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -214,6 +214,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: + case MXC_ESDHC2_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h index cf058d22a9..ac4194b9aa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -14,6 +14,7 @@ enum mxc_clock { MXC_BUS_CLK, MXC_UART_CLK, MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, MXC_I2C_CLK, MXC_DSPI_CLK, };
From: Meenakshi Aggarwal meenakshi.aggarwal@nxp.com
Mark BSS and Heap area of OCRAM as non-secure to perform DMA from non-secure SD controller.
Signed-off-by: Meenakshi Aggarwal meenakshi.aggarwal@nxp.com Signed-off-by: Yangbo Lu yangbo.lu@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 8 ++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 15 ++++++++++++++- scripts/config_whitelist.txt | 1 + 3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 3e53084b21..a6e0af05bf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP */
#include <common.h> @@ -74,6 +75,13 @@ void board_init_f(ulong dummy) #endif #ifdef CONFIG_VID init_func_vid(); +#endif +#ifdef CONFIG_TZPC_OCRAM_BSS_HEAP_NS + /* + * Mark BSS and HEAP area of OCRAM non-secure + * to support DMA mode in SD. + */ + out_le32(TZPCR0SIZE_BASE, OCRAM_NONSECURE_SIZE); #endif dram_init(); #ifdef CONFIG_SPL_FSL_LS_PPA diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index eb21c09e01..e7ec71a3da 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2016-2018 NXP * Copyright 2015, Freescale Semiconductor + * Copyright 2017-2018 NXP */
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ @@ -32,6 +32,19 @@ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
+/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) + /* DDR */ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 8c7c1592a5..61de7e0ca0 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4437,6 +4437,7 @@ CONFIG_TWL6030_POWER CONFIG_TWR CONFIG_TWR_P1025 CONFIG_TX_DESCR_NUM +CONFIG_TZPC_OCRAM_BSS_HEAP_NS CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_T_SH7706LSR CONFIG_UART_BR_PRELIM
From: Yangbo Lu yangbo.lu@nxp.com
Mark BSS and Heap area of OCRAM as non-secure to perform DMA from non-secure SD controller.
Signed-off-by: Yangbo Lu yangbo.lu@nxp.com Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com --- include/configs/ls1028a_common.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 10f2e88bfd..46d22154d1 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -183,6 +183,8 @@ #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 #define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_TZPC_OCRAM_BSS_HEAP_NS +#define OCRAM_NONSECURE_SIZE 0x00010000 #define CONFIG_ENV_SECT_SIZE 0x40000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
participants (1)
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Yinbo Zhu