[U-Boot] [PATCH v2 0/19] powerpc: Introduce device tree control and driver model
This series does a small amount of tweaking to support device tree control (CONFIG_OF_CONTROL) on PowerPC platforms. It also adds support for driver model. In both cases the main effort is to set things up correctly before calling board_init_f().
A new generic function, board_init_f_mem() is introduced. This does the various memory calculations in C code, since they are messy in assembler and every architecture should in fact be the same. A later series will adjust ARM and x86 to use this function.
As an example, the Canyonlands boards are converted over to use device tree control and driver model for their serial console. It should be fairly straightforward to convert over other boards.
Changes in v2: - Reduce reserved stack space for board_init_f_mem() to 64 bytes - Add SYS_MALLOC_F to Kconfig
Simon Glass (15): Introduce board_init_f_mem() to handle early memory layout powerpc: Permit device tree control of U-Boot (CONFIG_OF_CONTROL) powerpc: ppc4xx: canyonlands: config: Tidy up CONFIGs and config.mk powerpc: ppc4xx: Move CANYONLANDS/GLACIER/ARCHES to Kconfig powerpc: ppc4xx: Add ramboot config for glacier powerpc: ppc4xx: canyonlands: Move to generic board powerpc: ppc4xx: dts: Bring in canyonlands device tree files powerpc: ppc4xx: Call board_init_f_mem() for generic board powerpc: ppc4xx: Add a gpio.h header file powerpc: ppc4xx: Allow the end of u-boot.bin to be found powerpc: ppc4xx: Use CONFIG_OF_CONTROL for canyonlands boards ppc: amcc: Omit unneeded ns16550 CONFIG if using driver model powerpc: Add serial driver for driver model dm: powerpc: ppc4xx: Move glacier to use driver model for serial powerpc: Add linkage.h file
Stefan Roese (4): WIP: powerpc: ppc4xx: Somehow BSS is not cleared in RAMBOOT case powerpc: ppc4xx: Change from OF_SEPARATE to OF_EMBED powerpc: ppc4xx: Add defaults for DT based booting to really work powerpc: ppc4xx: Enable CONFIG_DISPLAY_BOARDINFO
arch/Kconfig | 1 + arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 8 + arch/powerpc/cpu/ppc4xx/config.mk | 5 +- arch/powerpc/cpu/ppc4xx/cpu_init.c | 2 + arch/powerpc/cpu/ppc4xx/start.S | 18 +- arch/powerpc/cpu/ppc4xx/u-boot.lds | 8 +- arch/powerpc/dts/Makefile | 11 + arch/powerpc/dts/arches.dts | 339 ++++++++++++++++ arch/powerpc/dts/canyonlands.dts | 561 +++++++++++++++++++++++++++ arch/powerpc/dts/glacier.dts | 582 ++++++++++++++++++++++++++++ arch/powerpc/include/asm/arch-ppc4xx/gpio.h | 7 + arch/powerpc/include/asm/linkage.h | 7 + arch/powerpc/include/asm/ppc460ex_gt.h | 2 + arch/powerpc/lib/board.c | 3 + board/amcc/canyonlands/Kconfig | 36 ++ board/amcc/canyonlands/MAINTAINERS | 1 + board/amcc/canyonlands/config.mk | 2 - board/amcc/canyonlands/u-boot-ram.lds | 85 ++++ common/board_f.c | 18 + common/board_r.c | 8 +- configs/arches_defconfig | 5 +- configs/canyonlands_defconfig | 5 +- configs/glacier_defconfig | 5 +- configs/glacier_ramboot_defconfig | 8 + drivers/serial/Makefile | 1 + drivers/serial/serial_ppc.c | 40 ++ include/configs/amcc-common.h | 2 + include/configs/canyonlands.h | 38 +- 28 files changed, 1778 insertions(+), 30 deletions(-) create mode 100644 arch/powerpc/dts/Makefile create mode 100644 arch/powerpc/dts/arches.dts create mode 100644 arch/powerpc/dts/canyonlands.dts create mode 100644 arch/powerpc/dts/glacier.dts create mode 100644 arch/powerpc/include/asm/arch-ppc4xx/gpio.h create mode 100644 arch/powerpc/include/asm/linkage.h create mode 100644 board/amcc/canyonlands/u-boot-ram.lds create mode 100644 configs/glacier_ramboot_defconfig create mode 100644 drivers/serial/serial_ppc.c
At present on some architectures we set up the following before calling board_init_f():
- global_data - stack - early malloc memory
Adding the code to support early malloc and global data setup to every arch's assembler start-up is a pain. Also this code is not actually architecture-specific. We can use common code for all architectures and with a bit of care we can write this code in C.
Add a new function to deal with this. It should be called after memory is available, with a pointer to the top of the area that should be used before relocation. The function will set things up and return the lowest memory address that it allocated/used. That can then be set as the top of the stack.
Note that on some archs this function will use the stack, so the stack pointer should be set to same value as is pased to board_init_f_mem(). A margin of 128 bytes will be left for this stack, so that it is not overwritten. This means that 64 bytes is wasted by this early call. This is not strictly necessary on several more modern archs, so we could remove this at the cost of some arch-dependent code.
With this function there is no-longer any need for the assembler code to zero global_data or set up the early malloc pointers.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Reduce reserved stack space for board_init_f_mem() to 64 bytes
common/board_f.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/common/board_f.c b/common/board_f.c index 7953137..07f5118 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -1075,4 +1075,22 @@ void board_init_f_r(void) /* NOTREACHED - board_init_r() does not return */ hang(); } +#else +ulong board_init_f_mem(ulong top) +{ + /* Leave space for the stack we are running with now */ + top -= 0x40; + + top -= sizeof(struct global_data); + top = ALIGN(top, 16); + gd = (struct global_data *)top; + memset((void *)gd, '\0', sizeof(*gd)); + +#ifdef CONFIG_SYS_MALLOC_F_LEN + top -= CONFIG_SYS_MALLOC_F_LEN; + gd->malloc_base = top; +#endif + + return top; +} #endif /* CONFIG_X86 */
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
At present on some architectures we set up the following before calling board_init_f():
- global_data
- stack
- early malloc memory
Adding the code to support early malloc and global data setup to every arch's assembler start-up is a pain. Also this code is not actually architecture-specific. We can use common code for all architectures and with a bit of care we can write this code in C.
Add a new function to deal with this. It should be called after memory is available, with a pointer to the top of the area that should be used before relocation. The function will set things up and return the lowest memory address that it allocated/used. That can then be set as the top of the stack.
Note that on some archs this function will use the stack, so the stack pointer should be set to same value as is pased to board_init_f_mem(). A margin of 128 bytes will be left for this stack, so that it is not overwritten. This means that 64 bytes is wasted by this early call. This is not strictly necessary on several more modern archs, so we could remove this at the cost of some arch-dependent code.
With this function there is no-longer any need for the assembler code to zero global_data or set up the early malloc pointers.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Reduce reserved stack space for board_init_f_mem() to 64 bytes
common/board_f.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
Applied to u-boot-dm.
Enable this in the Kconfig so that PowerPC boards can use device tree to configure U-Boot.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/Kconfig b/arch/Kconfig index f63cc5a..67e99e9 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -39,6 +39,7 @@ config OPENRISC config PPC bool "PowerPC architecture" select HAVE_PRIVATE_LIBGCC + select SUPPORT_OF_CONTROL
config SANDBOX bool "Sandbox"
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
Enable this in the Kconfig so that PowerPC boards can use device tree to configure U-Boot.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/Kconfig | 1 + 1 file changed, 1 insertion(+)
Applied to u-boot-dm.
Many CONFIG options have an unnecessary value of 1. CONFIG_440 is set in the various board config files. Also simplify the CONFIG_440 check in config.mk
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/powerpc/cpu/ppc4xx/config.mk | 5 +---- board/amcc/canyonlands/config.mk | 2 -- include/configs/canyonlands.h | 34 +++++++++++++++++----------------- 3 files changed, 18 insertions(+), 23 deletions(-)
diff --git a/arch/powerpc/cpu/ppc4xx/config.mk b/arch/powerpc/cpu/ppc4xx/config.mk index f87c9dc..9cb41bb 100644 --- a/arch/powerpc/cpu/ppc4xx/config.mk +++ b/arch/powerpc/cpu/ppc4xx/config.mk @@ -7,10 +7,7 @@
PLATFORM_CPPFLAGS += -mstring -msoft-float
-cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h -is440:=$(shell grep CONFIG_440 $(cfg)) - -ifneq (,$(findstring CONFIG_440,$(is440))) +ifneq (,$(CONFIG_440)) PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440 else PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405 diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk index 63b8973..5cc90d2 100644 --- a/board/amcc/canyonlands/config.mk +++ b/board/amcc/canyonlands/config.mk @@ -8,8 +8,6 @@ # AMCC 460EX/460GT Evaluation Board (Canyonlands) board #
-PLATFORM_CPPFLAGS += -DCONFIG_440=1 - ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG endif diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 8eeb15c..7b1f368 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -19,10 +19,10 @@ * and Arches dual (460GT) */ #ifdef CONFIG_CANYONLANDS -#define CONFIG_460EX 1 /* Specific PPC460EX */ +#define CONFIG_460EX /* Specific PPC460EX */ #define CONFIG_HOSTNAME canyonlands #else -#define CONFIG_460GT 1 /* Specific PPC460GT */ +#define CONFIG_460GT /* Specific PPC460GT */ #ifdef CONFIG_GLACIER #define CONFIG_HOSTNAME glacier #else @@ -32,7 +32,7 @@ #endif #endif
-#define CONFIG_440 1 +#define CONFIG_440
#ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF80000 @@ -45,10 +45,10 @@
#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r */ +#define CONFIG_BOARD_TYPES /* support board types */
/*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -134,7 +134,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -172,9 +172,9 @@ * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot * code. */ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/ -#define CONFIG_DDR_ECC 1 /* with ECC support */ +#define CONFIG_DDR_ECC /* with ECC support */ #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
#else /* defined(CONFIG_ARCHES) */ @@ -262,8 +262,8 @@ #define CONFIG_4xx_CONFIG_BLOCKSIZE 16
/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 /* use AD7414 */ #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ #define CONFIG_SYS_DTT_MAX_TEMP 70 #define CONFIG_SYS_DTT_LOW_TEMP -30 @@ -275,14 +275,14 @@
#if !defined(CONFIG_ARCHES) /* RTC configuration */ -#define CONFIG_RTC_M41T62 1 +#define CONFIG_RTC_M41T62 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #endif
/*----------------------------------------------------------------------- * Ethernet *----------------------------------------------------------------------*/ -#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_IBM_EMAC4_V4
#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 @@ -322,9 +322,9 @@ #define CONFIG_GPCS_PHY2_ADDR 0xC #endif /* !defined(CONFIG_ARCHES) */
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_PHY_DYNAMIC_ANEG 1 +#define CONFIG_PHY_RESET /* reset phy upon startup */ +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_DYNAMIC_ANEG
/*----------------------------------------------------------------------- * USB-OHCI
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
Many CONFIG options have an unnecessary value of 1. CONFIG_440 is set in the various board config files. Also simplify the CONFIG_440 check in config.mk
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/powerpc/cpu/ppc4xx/config.mk | 5 +---- board/amcc/canyonlands/config.mk | 2 -- include/configs/canyonlands.h | 34 +++++++++++++++++----------------- 3 files changed, 18 insertions(+), 23 deletions(-)
Applied to u-boot-dm.
Move these options to Kconfig and remove them from the CONFIG files.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
board/amcc/canyonlands/Kconfig | 20 ++++++++++++++++++++ configs/arches_defconfig | 2 +- configs/canyonlands_defconfig | 2 +- configs/glacier_defconfig | 2 +- include/configs/canyonlands.h | 2 ++ 5 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig index 530a6ef..0fc6877 100644 --- a/board/amcc/canyonlands/Kconfig +++ b/board/amcc/canyonlands/Kconfig @@ -9,4 +9,24 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "canyonlands"
+choice BOARD_TYPE + prompt "Select which board to build for" + +config CANYONLANDS + bool "Glacier" + help + Select this to build for the Canyonlands 460EX board. + +config GLACIER + bool "Glacier" + help + Select this to build for the Glacier 460GT board. + +config ARCHES + bool "Arches" + help + Select this to build for the Arches dual 460GT board. + +endchoice + endif diff --git a/configs/arches_defconfig b/configs/arches_defconfig index 18d0a14..60e6ef9 100644 --- a/configs/arches_defconfig +++ b/configs/arches_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="ARCHES" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CANYONLANDS=y +CONFIG_ARCHES=y diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig index 09b9ab9..37a2b4d 100644 --- a/configs/canyonlands_defconfig +++ b/configs/canyonlands_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CANYONLANDS" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CANYONLANDS=y +CONFIG_CANYONLANDS=y diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig index 2a66bfb..436b9f8 100644 --- a/configs/glacier_defconfig +++ b/configs/glacier_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="GLACIER" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CANYONLANDS=y +CONFIG_GLACIER=y diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 7b1f368..ed790cc 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -11,6 +11,8 @@ #ifndef __CONFIG_H #define __CONFIG_H
+#include <linux/kconfig.h> + /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
Move these options to Kconfig and remove them from the CONFIG files.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
board/amcc/canyonlands/Kconfig | 20 ++++++++++++++++++++ configs/arches_defconfig | 2 +- configs/canyonlands_defconfig | 2 +- configs/glacier_defconfig | 2 +- include/configs/canyonlands.h | 2 ++ 5 files changed, 25 insertions(+), 3 deletions(-)
Applied to u-boot-dm.
Add a new ramboot config for glacier so that it is possible to test U-Boot loaded over Ethernet instead of using JTAG.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 8 ++++ board/amcc/canyonlands/MAINTAINERS | 1 + board/amcc/canyonlands/u-boot-ram.lds | 79 ++++++++++++++++++++++++++++++++++ configs/glacier_ramboot_defconfig | 5 +++ 4 files changed, 93 insertions(+) create mode 100644 board/amcc/canyonlands/u-boot-ram.lds create mode 100644 configs/glacier_ramboot_defconfig
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 71bb9d7..7202c3f 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -424,6 +424,14 @@ phys_size_t initdram(int board_type) int write_recovery; phys_size_t dram_size = 0;
+ if (IS_ENABLED(CONFIG_SYS_RAMBOOT)) { + /* + * Reduce RAM size to avoid overwriting memory used by + * current stack? Not sure what is happening. + */ + return sdram_memsize() / 2; + } + num_dimm_banks = sizeof(iic0_dimm_addr);
/*------------------------------------------------------------------ diff --git a/board/amcc/canyonlands/MAINTAINERS b/board/amcc/canyonlands/MAINTAINERS index 52bf004..8be8a52 100644 --- a/board/amcc/canyonlands/MAINTAINERS +++ b/board/amcc/canyonlands/MAINTAINERS @@ -6,3 +6,4 @@ F: include/configs/canyonlands.h F: configs/arches_defconfig F: configs/canyonlands_defconfig F: configs/glacier_defconfig +F: configs/glacier_ramboot_defconfig diff --git a/board/amcc/canyonlands/u-boot-ram.lds b/board/amcc/canyonlands/u-boot-ram.lds new file mode 100644 index 0000000..6765256 --- /dev/null +++ b/board/amcc/canyonlands/u-boot-ram.lds @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .text : + { + arch/powerpc/cpu/ppc4xx/start.o (.text*) + board/amcc/canyonlands/init.o (.text*) + + *(.text*) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + KEEP(*(.got)) + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data*) + *(.sdata*) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.bss*) + *(.sbss*) + *(COMMON) + . = ALIGN(4); + } + + __bss_end = . ; + PROVIDE (end = .); +} diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig new file mode 100644 index 0000000..4fc2303 --- /dev/null +++ b/configs/glacier_ramboot_defconfig @@ -0,0 +1,5 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds" +CONFIG_PPC=y +CONFIG_4xx=y +CONFIG_TARGET_CANYONLANDS=y +CONFIG_GLACIER=y
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
Add a new ramboot config for glacier so that it is possible to test U-Boot loaded over Ethernet instead of using JTAG.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 8 ++++ board/amcc/canyonlands/MAINTAINERS | 1 + board/amcc/canyonlands/u-boot-ram.lds | 79 ++++++++++++++++++++++++++++++++++ configs/glacier_ramboot_defconfig | 5 +++ 4 files changed, 93 insertions(+) create mode 100644 board/amcc/canyonlands/u-boot-ram.lds create mode 100644 configs/glacier_ramboot_defconfig
Applied to u-boot-dm.
Switch to generic board so that this board will not be broken/removed.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/powerpc/cpu/ppc4xx/cpu_init.c | 2 ++ include/configs/canyonlands.h | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index e5a0e21..5f5c720 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -450,10 +450,12 @@ cpu_init_f (void) PLB4Ax_ACR_RDP_4DEEP); #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
+#ifndef CONFIG_SYS_GENERIC_BOARD gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */ memset((void *)gd, 0, sizeof(gd_t)); +#endif }
/* diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index ed790cc..7a1499d 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -13,6 +13,8 @@
#include <linux/kconfig.h>
+#define CONFIG_SYS_GENERIC_BOARD + /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
Switch to generic board so that this board will not be broken/removed.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/powerpc/cpu/ppc4xx/cpu_init.c | 2 ++ include/configs/canyonlands.h | 2 ++ 2 files changed, 4 insertions(+)
Applied to u-boot-dm.
From: Stefan Roese sr@denx.de
(NOT TO APPLY)
I'm really not sure why this doesn't work in the RAMBOOT case. But BSS is not cleared and because of this booting crashed / hangs at some stage later. Something with the GOT calculation / handling is incorrect.
To get this going for now, just clear the BSS again in the C code.
Signed-off-by: Stefan Roese sr@denx.de Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/powerpc/lib/board.c | 3 +++ common/board_r.c | 8 +++++++- 2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 91645d3..47654fa 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -108,6 +108,7 @@ DECLARE_GLOBAL_DATA_PTR; extern ulong __init_end; extern ulong __bss_end; ulong monitor_flash_len; +extern ulong __bss_start;
#if defined(CONFIG_CMD_BEDBUG) #include <bedbug/type.h> @@ -590,6 +591,8 @@ void board_init_r(gd_t *id, ulong dest_addr) /* The Malloc area is immediately below the monitor copy in DRAM */ malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+ memset(&__bss_start, 0, &__bss_end - &__bss_start); + #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) /* * The gd->arch.cpu pointer is set to an address in flash before diff --git a/common/board_r.c b/common/board_r.c index 68a9448..6900374 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -1,4 +1,4 @@ -/* + /* * Copyright (c) 2011 The Chromium OS Authors. * (C) Copyright 2002-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -870,6 +870,12 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) gd = new_gd; #endif
+#ifdef CONFIG_GLACIER + ulong bss_start = (ulong)&__bss_start; + ulong bss_end = (ulong)&__bss_end; + memset((void *)bss_start, 0, bss_end - bss_start); +#endif + #ifdef CONFIG_NEEDS_MANUAL_RELOC for (i = 0; i < ARRAY_SIZE(init_sequence_r); i++) init_sequence_r[i] += gd->reloc_off;
The canyonlands.h config file works with canyonlands, glacier and arches boards. Bring in the device tree files for these from Linux 3.17.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/powerpc/dts/Makefile | 11 + arch/powerpc/dts/arches.dts | 339 +++++++++++++++++++++++ arch/powerpc/dts/canyonlands.dts | 555 +++++++++++++++++++++++++++++++++++++ arch/powerpc/dts/glacier.dts | 579 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 1484 insertions(+) create mode 100644 arch/powerpc/dts/Makefile create mode 100644 arch/powerpc/dts/arches.dts create mode 100644 arch/powerpc/dts/canyonlands.dts create mode 100644 arch/powerpc/dts/glacier.dts
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile new file mode 100644 index 0000000..ad104b9 --- /dev/null +++ b/arch/powerpc/dts/Makefile @@ -0,0 +1,11 @@ +dtb-$(CONFIG_TARGET_CANYONLANDS) += arches.dtb canyonlands.dtb glacier.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/powerpc/dts/arches.dts b/arch/powerpc/dts/arches.dts new file mode 100644 index 0000000..bd5ebfd --- /dev/null +++ b/arch/powerpc/dts/arches.dts @@ -0,0 +1,339 @@ +/* + * Device Tree Source for AMCC Arches (dual 460GT board) + * + * (C) Copyright 2008 Applied Micro Circuits Corporation + * Victor Gallardo vgallardo@amcc.com + * Adam Graham agraham@amcc.com + * + * Based on the glacier.dts file + * Stefan Roese sr@denx.de + * Copyright 2008 DENX Software Engineering + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "amcc,arches"; + compatible = "amcc,arches"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + ethernet2 = &EMAC2; + serial0 = &UART0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,460GT"; + reg = <0x00000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + timebase-frequency = <0>; /* Filled in by U-Boot */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + next-level-cache = <&L2C0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0x0c0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0x0d0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC2: interrupt-controller2 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <2>; + dcr-reg = <0x0e0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC3: interrupt-controller3 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <3>; + dcr-reg = <0x0f0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-460gt"; + dcr-reg = <0x00e 0x002>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-460gt"; + dcr-reg = <0x00c 0x002>; + }; + + L2C0: l2c { + compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; + dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ + 0x030 0x008>; /* L2 cache DCR's */ + cache-line-size = <32>; /* 32 bytes */ + cache-size = <262144>; /* L2, 256K */ + interrupt-parent = <&UIC1>; + interrupts = <11 1>; + }; + + plb { + compatible = "ibm,plb-460gt", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by U-Boot */ + + SDRAM0: sdram { + compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; + dcr-reg = <0x010 0x002>; + }; + + CRYPTO: crypto@180000 { + compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto"; + reg = <4 0x00180000 0x80400>; + interrupt-parent = <&UIC0>; + interrupts = <0x1d 0x4>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; + dcr-reg = <0x180 0x062>; + num-tx-chans = <3>; + num-rx-chans = <24>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-parent = <&UIC2>; + interrupts = < /*TXEOB*/ 0x6 0x4 + /*RXEOB*/ 0x7 0x4 + /*SERR*/ 0x3 0x4 + /*TXDE*/ 0x4 0x4 + /*RXDE*/ 0x5 0x4>; + desc-base-addr-high = <0x8>; + }; + + POB0: opb { + compatible = "ibm,opb-460gt", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + + EBC0: ebc { + compatible = "ibm,ebc-460gt", "ibm,ebc"; + dcr-reg = <0x012 0x002>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by U-Boot */ + /* ranges property is supplied by U-Boot */ + interrupts = <0x6 0x4>; + interrupt-parent = <&UIC1>; + + nor_flash@0,0 { + compatible = "amd,s29gl256n", "cfi-flash"; + bank-width = <2>; + reg = <0x00000000 0x00000000 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x001e0000>; + }; + partition@1e0000 { + label = "dtb"; + reg = <0x001e0000 0x00020000>; + }; + partition@200000 { + label = "root"; + reg = <0x00200000 0x00200000>; + }; + partition@400000 { + label = "user"; + reg = <0x00400000 0x01b60000>; + }; + partition@1f60000 { + label = "env"; + reg = <0x01f60000 0x00040000>; + }; + partition@1fa0000 { + label = "u-boot"; + reg = <0x01fa0000 0x00060000>; + }; + }; + }; + + UART0: serial@ef600300 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC1>; + interrupts = <0x1 0x4>; + }; + + IIC0: i2c@ef600700 { + compatible = "ibm,iic-460gt", "ibm,iic"; + reg = <0xef600700 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x2 0x4>; + #address-cells = <1>; + #size-cells = <0>; + sttm@4a { + compatible = "ad,ad7414"; + reg = <0x4a>; + interrupt-parent = <&UIC1>; + interrupts = <0x0 0x8>; + }; + }; + + IIC1: i2c@ef600800 { + compatible = "ibm,iic-460gt", "ibm,iic"; + reg = <0xef600800 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x3 0x4>; + }; + + TAH0: emac-tah@ef601350 { + compatible = "ibm,tah-460gt", "ibm,tah"; + reg = <0xef601350 0x00000030>; + }; + + TAH1: emac-tah@ef601450 { + compatible = "ibm,tah-460gt", "ibm,tah"; + reg = <0xef601450 0x00000030>; + }; + + EMAC0: ethernet@ef600e00 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC0>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 + /*Wake*/ 0x1 &UIC2 0x14 0x4>; + reg = <0xef600e00 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + phy-mode = "sgmii"; + phy-map = <0xffffffff>; + gpcs-address = <0x0000000a>; + tah-device = <&TAH0>; + tah-channel = <0>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + }; + + EMAC1: ethernet@ef600f00 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC1>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 + /*Wake*/ 0x1 &UIC2 0x15 0x4>; + reg = <0xef600f00 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <1>; + mal-rx-channel = <8>; + cell-index = <1>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + phy-mode = "sgmii"; + phy-map = <0x00000000>; + gpcs-address = <0x0000000b>; + tah-device = <&TAH1>; + tah-channel = <1>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + mdio-device = <&EMAC0>; + }; + + EMAC2: ethernet@ef601100 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC2>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 + /*Wake*/ 0x1 &UIC2 0x16 0x4>; + reg = <0xef601100 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <2>; + mal-rx-channel = <16>; + cell-index = <2>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + tx-fifo-size-gige = <16384>; /* emac2&3 only */ + phy-mode = "sgmii"; + phy-map = <0x00000001>; + gpcs-address = <0x0000000C>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + mdio-device = <&EMAC0>; + }; + }; + }; +}; diff --git a/arch/powerpc/dts/canyonlands.dts b/arch/powerpc/dts/canyonlands.dts new file mode 100644 index 0000000..2ec9762 --- /dev/null +++ b/arch/powerpc/dts/canyonlands.dts @@ -0,0 +1,555 @@ +/* + * Device Tree Source for AMCC Canyonlands (460EX) + * + * Copyright 2008-2009 DENX Software Engineering, Stefan Roese sr@denx.de + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "amcc,canyonlands"; + compatible = "amcc,canyonlands"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + serial0 = &UART0; + serial1 = &UART1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,460EX"; + reg = <0x00000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + timebase-frequency = <0>; /* Filled in by U-Boot */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + next-level-cache = <&L2C0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-460ex","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0x0c0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-460ex","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0x0d0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC2: interrupt-controller2 { + compatible = "ibm,uic-460ex","ibm,uic"; + interrupt-controller; + cell-index = <2>; + dcr-reg = <0x0e0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC3: interrupt-controller3 { + compatible = "ibm,uic-460ex","ibm,uic"; + interrupt-controller; + cell-index = <3>; + dcr-reg = <0x0f0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-460ex"; + dcr-reg = <0x00e 0x002>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-460ex"; + dcr-reg = <0x00c 0x002>; + }; + + CPM0: cpm { + compatible = "ibm,cpm"; + dcr-access-method = "native"; + dcr-reg = <0x160 0x003>; + unused-units = <0x00000100>; + idle-doze = <0x02000000>; + standby = <0xfeff791d>; + }; + + L2C0: l2c { + compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; + dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ + 0x030 0x008>; /* L2 cache DCR's */ + cache-line-size = <32>; /* 32 bytes */ + cache-size = <262144>; /* L2, 256K */ + interrupt-parent = <&UIC1>; + interrupts = <11 1>; + }; + + plb { + compatible = "ibm,plb-460ex", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by U-Boot */ + + SDRAM0: sdram { + compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; + dcr-reg = <0x010 0x002>; + }; + + CRYPTO: crypto@180000 { + compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto"; + reg = <4 0x00180000 0x80400>; + interrupt-parent = <&UIC0>; + interrupts = <0x1d 0x4>; + }; + + HWRNG: hwrng@110000 { + compatible = "amcc,ppc460ex-rng", "ppc4xx-rng"; + reg = <4 0x00110000 0x50>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; + dcr-reg = <0x180 0x062>; + num-tx-chans = <2>; + num-rx-chans = <16>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-parent = <&UIC2>; + interrupts = < /*TXEOB*/ 0x6 0x4 + /*RXEOB*/ 0x7 0x4 + /*SERR*/ 0x3 0x4 + /*TXDE*/ 0x4 0x4 + /*RXDE*/ 0x5 0x4>; + }; + + USB0: ehci@bffd0400 { + compatible = "ibm,usb-ehci-460ex", "usb-ehci"; + interrupt-parent = <&UIC2>; + interrupts = <0x1d 4>; + reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>; + }; + + USB1: usb@bffd0000 { + compatible = "ohci-le"; + reg = <4 0xbffd0000 0x60>; + interrupt-parent = <&UIC2>; + interrupts = <0x1e 4>; + }; + + USBOTG0: usbotg@bff80000 { + compatible = "amcc,dwc-otg"; + reg = <0x4 0xbff80000 0x10000>; + interrupt-parent = <&USBOTG0>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupts = <0x0 0x1 0x2>; + interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4 + /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8 + /* DMA */ 0x2 &UIC0 0xc 0x4>; + }; + + SATA0: sata@bffd1000 { + compatible = "amcc,sata-460ex"; + reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>; + interrupt-parent = <&UIC3>; + interrupts = <0x0 0x4 /* SATA */ + 0x5 0x4>; /* AHBDMA */ + }; + + POB0: opb { + compatible = "ibm,opb-460ex", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + + EBC0: ebc { + compatible = "ibm,ebc-460ex", "ibm,ebc"; + dcr-reg = <0x012 0x002>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by U-Boot */ + /* ranges property is supplied by U-Boot */ + interrupts = <0x6 0x4>; + interrupt-parent = <&UIC1>; + + nor_flash@0,0 { + compatible = "amd,s29gl512n", "cfi-flash"; + bank-width = <2>; + reg = <0x00000000 0x00000000 0x04000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x001e0000>; + }; + partition@1e0000 { + label = "dtb"; + reg = <0x001e0000 0x00020000>; + }; + partition@200000 { + label = "ramdisk"; + reg = <0x00200000 0x01400000>; + }; + partition@1600000 { + label = "jffs2"; + reg = <0x01600000 0x00400000>; + }; + partition@1a00000 { + label = "user"; + reg = <0x01a00000 0x02560000>; + }; + partition@3f60000 { + label = "env"; + reg = <0x03f60000 0x00040000>; + }; + partition@3fa0000 { + label = "u-boot"; + reg = <0x03fa0000 0x00060000>; + }; + }; + + cpld@2,0 { + compatible = "amcc,ppc460ex-bcsr"; + reg = <2 0x0 0x9>; + }; + + ndfc@3,0 { + compatible = "ibm,ndfc"; + reg = <0x00000003 0x00000000 0x00002000>; + ccr = <0x00001000>; + bank-settings = <0x80002222>; + #address-cells = <1>; + #size-cells = <1>; + + nand { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x00100000>; + }; + partition@100000 { + label = "user"; + reg = <0x00000000 0x03f00000>; + }; + }; + }; + }; + + UART0: serial@ef600300 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC1>; + interrupts = <0x1 0x4>; + }; + + UART1: serial@ef600400 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC0>; + interrupts = <0x1 0x4>; + }; + + IIC0: i2c@ef600700 { + compatible = "ibm,iic-460ex", "ibm,iic"; + reg = <0xef600700 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x2 0x4>; + #address-cells = <1>; + #size-cells = <0>; + rtc@68 { + compatible = "stm,m41t80"; + reg = <0x68>; + interrupt-parent = <&UIC2>; + interrupts = <0x19 0x8>; + }; + sttm@48 { + compatible = "ad,ad7414"; + reg = <0x48>; + interrupt-parent = <&UIC1>; + interrupts = <0x14 0x8>; + }; + }; + + IIC1: i2c@ef600800 { + compatible = "ibm,iic-460ex", "ibm,iic"; + reg = <0xef600800 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x3 0x4>; + }; + + GPIO0: gpio@ef600b00 { + compatible = "ibm,ppc4xx-gpio"; + reg = <0xef600b00 0x00000048>; + gpio-controller; + }; + + ZMII0: emac-zmii@ef600d00 { + compatible = "ibm,zmii-460ex", "ibm,zmii"; + reg = <0xef600d00 0x0000000c>; + }; + + RGMII0: emac-rgmii@ef601500 { + compatible = "ibm,rgmii-460ex", "ibm,rgmii"; + reg = <0xef601500 0x00000008>; + has-mdio; + }; + + TAH0: emac-tah@ef601350 { + compatible = "ibm,tah-460ex", "ibm,tah"; + reg = <0xef601350 0x00000030>; + }; + + TAH1: emac-tah@ef601450 { + compatible = "ibm,tah-460ex", "ibm,tah"; + reg = <0xef601450 0x00000030>; + }; + + EMAC0: ethernet@ef600e00 { + device_type = "network"; + compatible = "ibm,emac-460ex", "ibm,emac4sync"; + interrupt-parent = <&EMAC0>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 + /*Wake*/ 0x1 &UIC2 0x14 0x4>; + reg = <0xef600e00 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + phy-mode = "rgmii"; + phy-map = <0x00000000>; + rgmii-device = <&RGMII0>; + rgmii-channel = <0>; + tah-device = <&TAH0>; + tah-channel = <0>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + }; + + EMAC1: ethernet@ef600f00 { + device_type = "network"; + compatible = "ibm,emac-460ex", "ibm,emac4sync"; + interrupt-parent = <&EMAC1>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 + /*Wake*/ 0x1 &UIC2 0x15 0x4>; + reg = <0xef600f00 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <1>; + mal-rx-channel = <8>; + cell-index = <1>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + phy-mode = "rgmii"; + phy-map = <0x00000000>; + rgmii-device = <&RGMII0>; + rgmii-channel = <1>; + tah-device = <&TAH1>; + tah-channel = <1>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + mdio-device = <&EMAC0>; + }; + }; + + PCIX0: pci@c0ec00000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; + primary; + large-inbound-windows; + enable-msi-hole; + reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ + 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ + 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 + 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 0 to 0x3f */ + bus-range = <0x0 0x3f>; + + /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; + }; + + PCIE0: pciex@d00000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; + primary; + port = <0x0>; /* port number */ + reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ + 0x0000000c 0x08010000 0x00001000>; /* Registers */ + dcr-reg = <0x100 0x020>; + sdr-base = <0x300>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 40 to 0x7f */ + bus-range = <0x40 0x7f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; + }; + + PCIE1: pciex@d20000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; + primary; + port = <0x1>; /* port number */ + reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ + 0x0000000c 0x08011000 0x00001000>; /* Registers */ + dcr-reg = <0x120 0x020>; + sdr-base = <0x340>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 80 to 0xbf */ + bus-range = <0x80 0xbf>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; + }; + + MSI: ppc4xx-msi@C10000000 { + compatible = "amcc,ppc4xx-msi", "ppc4xx-msi"; + reg = < 0xC 0x10000000 0x100>; + sdr-base = <0x36C>; + msi-data = <0x00000000>; + msi-mask = <0x44440000>; + interrupt-count = <3>; + interrupts = <0 1 2 3>; + interrupt-parent = <&UIC3>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &UIC3 0x18 1 + 1 &UIC3 0x19 1 + 2 &UIC3 0x1A 1 + 3 &UIC3 0x1B 1>; + }; + }; +}; diff --git a/arch/powerpc/dts/glacier.dts b/arch/powerpc/dts/glacier.dts new file mode 100644 index 0000000..3e7ce2c --- /dev/null +++ b/arch/powerpc/dts/glacier.dts @@ -0,0 +1,579 @@ +/* + * Device Tree Source for AMCC Glacier (460GT) + * + * Copyright 2008-2010 DENX Software Engineering, Stefan Roese sr@denx.de + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "amcc,glacier"; + compatible = "amcc,glacier"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + ethernet2 = &EMAC2; + ethernet3 = &EMAC3; + serial0 = &UART0; + serial1 = &UART1; + }; + + chosen { + stdout-path = &UART0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,460GT"; + reg = <0x00000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + timebase-frequency = <0>; /* Filled in by U-Boot */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + next-level-cache = <&L2C0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0x0c0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0x0d0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC2: interrupt-controller2 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <2>; + dcr-reg = <0x0e0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC3: interrupt-controller3 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <3>; + dcr-reg = <0x0f0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-460gt"; + dcr-reg = <0x00e 0x002>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-460gt"; + dcr-reg = <0x00c 0x002>; + }; + + L2C0: l2c { + compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; + dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ + 0x030 0x008>; /* L2 cache DCR's */ + cache-line-size = <32>; /* 32 bytes */ + cache-size = <262144>; /* L2, 256K */ + interrupt-parent = <&UIC1>; + interrupts = <11 1>; + }; + + plb { + compatible = "ibm,plb-460gt", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by U-Boot */ + + SDRAM0: sdram { + compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; + dcr-reg = <0x010 0x002>; + }; + + CRYPTO: crypto@180000 { + compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto", + "amcc,ppc4xx-crypto"; + reg = <4 0x00180000 0x80400>; + interrupt-parent = <&UIC0>; + interrupts = <0x1d 0x4>; + }; + + HWRNG: hwrng@110000 { + compatible = "amcc,ppc460ex-rng", "ppc4xx-rng"; + reg = <4 0x00110000 0x50>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; + dcr-reg = <0x180 0x062>; + num-tx-chans = <4>; + num-rx-chans = <32>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-parent = <&UIC2>; + interrupts = < /*TXEOB*/ 0x6 0x4 + /*RXEOB*/ 0x7 0x4 + /*SERR*/ 0x3 0x4 + /*TXDE*/ 0x4 0x4 + /*RXDE*/ 0x5 0x4>; + desc-base-addr-high = <0x8>; + }; + + POB0: opb { + compatible = "ibm,opb-460gt", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + + EBC0: ebc { + compatible = "ibm,ebc-460gt", "ibm,ebc"; + dcr-reg = <0x012 0x002>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by U-Boot */ + /* ranges property is supplied by U-Boot */ + interrupts = <0x6 0x4>; + interrupt-parent = <&UIC1>; + + nor_flash@0,0 { + compatible = "amd,s29gl512n", "cfi-flash"; + bank-width = <2>; + reg = <0x00000000 0x00000000 0x04000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x001e0000>; + }; + partition@1e0000 { + label = "dtb"; + reg = <0x001e0000 0x00020000>; + }; + partition@200000 { + label = "ramdisk"; + reg = <0x00200000 0x01400000>; + }; + partition@1600000 { + label = "jffs2"; + reg = <0x01600000 0x00400000>; + }; + partition@1a00000 { + label = "user"; + reg = <0x01a00000 0x02560000>; + }; + partition@3f60000 { + label = "env"; + reg = <0x03f60000 0x00040000>; + }; + partition@3fa0000 { + label = "u-boot"; + reg = <0x03fa0000 0x00060000>; + }; + }; + + ndfc@3,0 { + compatible = "ibm,ndfc"; + reg = <0x00000003 0x00000000 0x00002000>; + ccr = <0x00001000>; + bank-settings = <0x80002222>; + #address-cells = <1>; + #size-cells = <1>; + + nand { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x00100000>; + }; + partition@100000 { + label = "user"; + reg = <0x00000000 0x03f00000>; + }; + }; + }; + }; + + UART0: serial@ef600300 { + device_type = "serial"; + reg-shift = <0>; + compatible = "ns16550"; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC1>; + interrupts = <0x1 0x4>; + }; + + UART1: serial@ef600400 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC0>; + interrupts = <0x1 0x4>; + }; + + UART2: serial@ef600500 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC1>; + interrupts = <28 0x4>; + }; + + UART3: serial@ef600600 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC1>; + interrupts = <29 0x4>; + }; + + IIC0: i2c@ef600700 { + compatible = "ibm,iic-460gt", "ibm,iic"; + reg = <0xef600700 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x2 0x4>; + #address-cells = <1>; + #size-cells = <0>; + rtc@68 { + compatible = "stm,m41t80"; + reg = <0x68>; + interrupt-parent = <&UIC2>; + interrupts = <0x19 0x8>; + }; + sttm@48 { + compatible = "ad,ad7414"; + reg = <0x48>; + interrupt-parent = <&UIC1>; + interrupts = <0x14 0x8>; + }; + }; + + IIC1: i2c@ef600800 { + compatible = "ibm,iic-460gt", "ibm,iic"; + reg = <0xef600800 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x3 0x4>; + }; + + ZMII0: emac-zmii@ef600d00 { + compatible = "ibm,zmii-460gt", "ibm,zmii"; + reg = <0xef600d00 0x0000000c>; + }; + + RGMII0: emac-rgmii@ef601500 { + compatible = "ibm,rgmii-460gt", "ibm,rgmii"; + reg = <0xef601500 0x00000008>; + has-mdio; + }; + + RGMII1: emac-rgmii@ef601600 { + compatible = "ibm,rgmii-460gt", "ibm,rgmii"; + reg = <0xef601600 0x00000008>; + has-mdio; + }; + + TAH0: emac-tah@ef601350 { + compatible = "ibm,tah-460gt", "ibm,tah"; + reg = <0xef601350 0x00000030>; + }; + + TAH1: emac-tah@ef601450 { + compatible = "ibm,tah-460gt", "ibm,tah"; + reg = <0xef601450 0x00000030>; + }; + + EMAC0: ethernet@ef600e00 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC0>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 + /*Wake*/ 0x1 &UIC2 0x14 0x4>; + reg = <0xef600e00 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + phy-mode = "rgmii"; + phy-map = <0x00000000>; + rgmii-device = <&RGMII0>; + rgmii-channel = <0>; + tah-device = <&TAH0>; + tah-channel = <0>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + }; + + EMAC1: ethernet@ef600f00 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC1>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 + /*Wake*/ 0x1 &UIC2 0x15 0x4>; + reg = <0xef600f00 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <1>; + mal-rx-channel = <8>; + cell-index = <1>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + phy-mode = "rgmii"; + phy-map = <0x00000000>; + rgmii-device = <&RGMII0>; + rgmii-channel = <1>; + tah-device = <&TAH1>; + tah-channel = <1>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + mdio-device = <&EMAC0>; + }; + + EMAC2: ethernet@ef601100 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC2>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 + /*Wake*/ 0x1 &UIC2 0x16 0x4>; + reg = <0xef601100 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <2>; + mal-rx-channel = <16>; + cell-index = <2>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + tx-fifo-size-gige = <16384>; /* emac2&3 only */ + phy-mode = "rgmii"; + phy-map = <0x00000000>; + rgmii-device = <&RGMII1>; + rgmii-channel = <0>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + mdio-device = <&EMAC0>; + }; + + EMAC3: ethernet@ef601200 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC3>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4 + /*Wake*/ 0x1 &UIC2 0x17 0x4>; + reg = <0xef601200 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <3>; + mal-rx-channel = <24>; + cell-index = <3>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + tx-fifo-size-gige = <16384>; /* emac2&3 only */ + phy-mode = "rgmii"; + phy-map = <0x00000000>; + rgmii-device = <&RGMII1>; + rgmii-channel = <1>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + mdio-device = <&EMAC0>; + }; + }; + + PCIX0: pci@c0ec00000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix"; + primary; + large-inbound-windows; + enable-msi-hole; + reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ + 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ + 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 + 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 0 to 0x3f */ + bus-range = <0x0 0x3f>; + + /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; + }; + + PCIE0: pciex@d00000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; + primary; + port = <0x0>; /* port number */ + reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ + 0x0000000c 0x08010000 0x00001000>; /* Registers */ + dcr-reg = <0x100 0x020>; + sdr-base = <0x300>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 40 to 0x7f */ + bus-range = <0x40 0x7f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; + }; + + PCIE1: pciex@d20000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; + primary; + port = <0x1>; /* port number */ + reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ + 0x0000000c 0x08011000 0x00001000>; /* Registers */ + dcr-reg = <0x120 0x020>; + sdr-base = <0x340>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 80 to 0xbf */ + bus-range = <0x80 0xbf>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; + }; + }; +};
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
The canyonlands.h config file works with canyonlands, glacier and arches boards. Bring in the device tree files for these from Linux 3.17.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/powerpc/dts/Makefile | 11 + arch/powerpc/dts/arches.dts | 339 +++++++++++++++++++++++ arch/powerpc/dts/canyonlands.dts | 555 +++++++++++++++++++++++++++++++++++++ arch/powerpc/dts/glacier.dts | 579 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 1484 insertions(+) create mode 100644 arch/powerpc/dts/Makefile create mode 100644 arch/powerpc/dts/arches.dts create mode 100644 arch/powerpc/dts/canyonlands.dts create mode 100644 arch/powerpc/dts/glacier.dts
Applied to u-boot-dm.
Call this function to set up our early memory.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/powerpc/cpu/ppc4xx/start.S | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 09a02d7..7a0f0d2 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -760,6 +760,15 @@ _start: #endif
bl cpu_init_f /* run low-level CPU init code (from Flash) */ +#ifdef CONFIG_SYS_GENERIC_BOARD + mr r3, r1 + bl board_init_f_mem + mr r1, r3 + li r0,0 + stwu r0, -4(r1) + stwu r0, -4(r1) +#endif + li r3, 0 bl board_init_f /* NOTREACHED - board_init_f() does not return */
@@ -1027,7 +1036,14 @@ _start: GET_GOT /* initialize GOT access */
bl cpu_init_f /* run low-level CPU init code (from Flash) */ - +#ifdef CONFIG_SYS_GENERIC_BOARD + mr r3, r1 + bl board_init_f_mem + mr r1, r3 + stwu r0, -4(r1) + stwu r0, -4(r1) +#endif + li r3, 0 bl board_init_f /* run first part of init code (from Flash) */ /* NOTREACHED - board_init_f() does not return */
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
Call this function to set up our early memory.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/powerpc/cpu/ppc4xx/start.S | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
Applied to u-boot-dm.
This is required at present for device tree control. The ppc4xx does support GPIOs but does not seem to have a proper driver. So this file is empty.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/powerpc/include/asm/arch-ppc4xx/gpio.h | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 arch/powerpc/include/asm/arch-ppc4xx/gpio.h
diff --git a/arch/powerpc/include/asm/arch-ppc4xx/gpio.h b/arch/powerpc/include/asm/arch-ppc4xx/gpio.h new file mode 100644 index 0000000..3d960c3 --- /dev/null +++ b/arch/powerpc/include/asm/arch-ppc4xx/gpio.h @@ -0,0 +1,7 @@ +/* + * (C) Copyright 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* This is empty for now as we don't support the generic GPIO interface */
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
This is required at present for device tree control. The ppc4xx does support GPIOs but does not seem to have a proper driver. So this file is empty.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/powerpc/include/asm/arch-ppc4xx/gpio.h | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 arch/powerpc/include/asm/arch-ppc4xx/gpio.h
Applied to u-boot-dm.
Define an _end symbol indicating the end of u-boot.bin. Also add some dummy words into the link script to ensure that u-boot.bin will always extend that far. There may be a better way of doing this.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/powerpc/cpu/ppc4xx/u-boot.lds | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds index 8773178..1980508 100644 --- a/arch/powerpc/cpu/ppc4xx/u-boot.lds +++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds @@ -76,9 +76,13 @@ SECTIONS . = ALIGN(256); __init_begin = .; .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); + .data.init : { + *(.data.init) + . = ALIGN(256); + LONG(0) LONG(0) /* Extend u-boot.bin to here */ + } __init_end = .; + _end = .;
#ifndef CONFIG_SPL #ifdef CONFIG_440
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
Define an _end symbol indicating the end of u-boot.bin. Also add some dummy words into the link script to ensure that u-boot.bin will always extend that far. There may be a better way of doing this.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/powerpc/cpu/ppc4xx/u-boot.lds | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
Applied to u-boot-dm.
Enable CONFIG_OF_CONTROL so that U-Boot on these three boards uses a device tree for its configuration.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
board/amcc/canyonlands/u-boot-ram.lds | 10 ++++++++-- configs/arches_defconfig | 3 +++ configs/canyonlands_defconfig | 3 +++ configs/glacier_defconfig | 3 +++ configs/glacier_ramboot_defconfig | 3 +++ 5 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/board/amcc/canyonlands/u-boot-ram.lds b/board/amcc/canyonlands/u-boot-ram.lds index 6765256..1750c74 100644 --- a/board/amcc/canyonlands/u-boot-ram.lds +++ b/board/amcc/canyonlands/u-boot-ram.lds @@ -12,6 +12,7 @@ SECTIONS . = + SIZEOF_HEADERS; .text : { + _image_copy_start = .; arch/powerpc/cpu/ppc4xx/start.o (.text*) board/amcc/canyonlands/init.o (.text*)
@@ -61,9 +62,14 @@ SECTIONS . = ALIGN(256); __init_begin = .; .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); + .data.init : { + *(.data.init) + . = ALIGN(256); + LONG(0) LONG(0) /* Extend u-boot.bin to here */ + } __init_end = .; + _end = .; + _image_binary_end = .;
__bss_start = .; .bss (NOLOAD) : diff --git a/configs/arches_defconfig b/configs/arches_defconfig index 60e6ef9..30c6932 100644 --- a/configs/arches_defconfig +++ b/configs/arches_defconfig @@ -2,3 +2,6 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CANYONLANDS=y CONFIG_ARCHES=y +CONFIG_DEFAULT_DEVICE_TREE="arches" +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig index 37a2b4d..6f6cf14 100644 --- a/configs/canyonlands_defconfig +++ b/configs/canyonlands_defconfig @@ -2,3 +2,6 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CANYONLANDS=y CONFIG_CANYONLANDS=y +CONFIG_DEFAULT_DEVICE_TREE="canyonlands" +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig index 436b9f8..e67fa32 100644 --- a/configs/glacier_defconfig +++ b/configs/glacier_defconfig @@ -2,3 +2,6 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CANYONLANDS=y CONFIG_GLACIER=y +CONFIG_DEFAULT_DEVICE_TREE="glacier" +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig index 4fc2303..e5b402e 100644 --- a/configs/glacier_ramboot_defconfig +++ b/configs/glacier_ramboot_defconfig @@ -3,3 +3,6 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CANYONLANDS=y CONFIG_GLACIER=y +CONFIG_DEFAULT_DEVICE_TREE="glacier" +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
Enable CONFIG_OF_CONTROL so that U-Boot on these three boards uses a device tree for its configuration.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
board/amcc/canyonlands/u-boot-ram.lds | 10 ++++++++-- configs/arches_defconfig | 3 +++ configs/canyonlands_defconfig | 3 +++ configs/glacier_defconfig | 3 +++ configs/glacier_ramboot_defconfig | 3 +++ 5 files changed, 20 insertions(+), 2 deletions(-)
Applied to u-boot-dm.
This comes from the device tree or a call to get_uart_clock().
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/powerpc/include/asm/ppc460ex_gt.h | 2 ++ include/configs/amcc-common.h | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h b/arch/powerpc/include/asm/ppc460ex_gt.h index f41df0d..ea019aa 100644 --- a/arch/powerpc/include/asm/ppc460ex_gt.h +++ b/arch/powerpc/include/asm/ppc460ex_gt.h @@ -19,10 +19,12 @@ /* Memory mapped registers */ #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
+#ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600) +#endif
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) #define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 2aea899..73e1b0a 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -20,8 +20,10 @@ */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
This comes from the device tree or a call to get_uart_clock().
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/powerpc/include/asm/ppc460ex_gt.h | 2 ++ include/configs/amcc-common.h | 2 ++ 2 files changed, 4 insertions(+)
Applied to u-boot-dm.
This uses the ns16550 driver but sets up the clock at run-time. It does not seem to be available in the device tree.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
drivers/serial/Makefile | 1 + drivers/serial/serial_ppc.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 drivers/serial/serial_ppc.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 4cc00cd..63b0cbf 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -8,6 +8,7 @@ ifdef CONFIG_DM_SERIAL obj-y += serial-uclass.o obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o +obj-$(CONFIG_PPC) += serial_ppc.o else obj-y += serial.o obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o diff --git a/drivers/serial/serial_ppc.c b/drivers/serial/serial_ppc.c new file mode 100644 index 0000000..47141c6 --- /dev/null +++ b/drivers/serial/serial_ppc.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <ns16550.h> +#include <serial.h> + +static const struct udevice_id ppc_serial_ids[] = { + { .compatible = "ns16550" }, + { } +}; + +static int ppc_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev_get_platdata(dev); + int ret; + + ret = ns16550_serial_ofdata_to_platdata(dev); + if (ret) + return ret; + plat->clock = get_serial_clock(); + + return 0; +} + +U_BOOT_DRIVER(serial_ns16550) = { + .name = "serial_ppc", + .id = UCLASS_SERIAL, + .of_match = ppc_serial_ids, + .ofdata_to_platdata = ppc_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +};
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
This uses the ns16550 driver but sets up the clock at run-time. It does not seem to be available in the device tree.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
drivers/serial/Makefile | 1 + drivers/serial/serial_ppc.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 drivers/serial/serial_ppc.c
Applied to u-boot-dm.
Adjust Kconfig to default to driver model for glacier, canyonlands and arches.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add SYS_MALLOC_F to Kconfig
board/amcc/canyonlands/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig index 0fc6877..1617d95 100644 --- a/board/amcc/canyonlands/Kconfig +++ b/board/amcc/canyonlands/Kconfig @@ -29,4 +29,16 @@ config ARCHES
endchoice
+config DM + default y + +config DM_SERIAL + default y + +config SYS_MALLOC_F + default y + +config SYS_MALLOC_F_LEN + default 0x400 + endif
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
Adjust Kconfig to default to driver model for glacier, canyonlands and arches.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Add SYS_MALLOC_F to Kconfig
board/amcc/canyonlands/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+)
Applied to u-boot-dm.
This permits us to use linux/linkage.h on PowerPC machines.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/powerpc/include/asm/linkage.h | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 arch/powerpc/include/asm/linkage.h
diff --git a/arch/powerpc/include/asm/linkage.h b/arch/powerpc/include/asm/linkage.h new file mode 100644 index 0000000..559b42e --- /dev/null +++ b/arch/powerpc/include/asm/linkage.h @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* We don't need anything here at present */
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
This permits us to use linux/linkage.h on PowerPC machines.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/powerpc/include/asm/linkage.h | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 arch/powerpc/include/asm/linkage.h
Applied to u-boot-dm.
From: Stefan Roese sr@denx.de
This is necessary, as ppc4xx has the reset vector located at the end of the U-Boot image. This needs to be flashed to the end of the NOR flash. Adding the dtb to the main U-Boot image will break booting on ppc4xx. This patch now embeds the dtb in the U-Boot image instead.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
configs/canyonlands_defconfig | 2 +- configs/glacier_defconfig | 2 +- configs/glacier_ramboot_defconfig | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig index 6f6cf14..44d4fbd 100644 --- a/configs/canyonlands_defconfig +++ b/configs/canyonlands_defconfig @@ -4,4 +4,4 @@ CONFIG_TARGET_CANYONLANDS=y CONFIG_CANYONLANDS=y CONFIG_DEFAULT_DEVICE_TREE="canyonlands" CONFIG_OF_CONTROL=y -CONFIG_OF_SEPARATE=y +CONFIG_OF_EMBED=y diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig index e67fa32..d318f82 100644 --- a/configs/glacier_defconfig +++ b/configs/glacier_defconfig @@ -4,4 +4,4 @@ CONFIG_TARGET_CANYONLANDS=y CONFIG_GLACIER=y CONFIG_DEFAULT_DEVICE_TREE="glacier" CONFIG_OF_CONTROL=y -CONFIG_OF_SEPARATE=y +CONFIG_OF_EMBED=y diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig index e5b402e..f8363b2 100644 --- a/configs/glacier_ramboot_defconfig +++ b/configs/glacier_ramboot_defconfig @@ -5,4 +5,4 @@ CONFIG_TARGET_CANYONLANDS=y CONFIG_GLACIER=y CONFIG_DEFAULT_DEVICE_TREE="glacier" CONFIG_OF_CONTROL=y -CONFIG_OF_SEPARATE=y +CONFIG_OF_EMBED=y
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
From: Stefan Roese sr@denx.de
This is necessary, as ppc4xx has the reset vector located at the end of the U-Boot image. This needs to be flashed to the end of the NOR flash. Adding the dtb to the main U-Boot image will break booting on ppc4xx. This patch now embeds the dtb in the U-Boot image instead.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
configs/canyonlands_defconfig | 2 +- configs/glacier_defconfig | 2 +- configs/glacier_ramboot_defconfig | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
Applied to u-boot-dm, thanks!
Hi,
On Sat, 7 Feb 2015 11:51:50 -0700 Simon Glass sjg@chromium.org wrote:
From: Stefan Roese sr@denx.de
This is necessary, as ppc4xx has the reset vector located at the end of the U-Boot image. This needs to be flashed to the end of the NOR flash. Adding the dtb to the main U-Boot image will break booting on ppc4xx. This patch now embeds the dtb in the U-Boot image instead.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Simon Glass sjg@chromium.org
It this a common requirement for PowerPC architecture? If so, does it make sense to change default value only for PowerPC?
choice prompt "Provider of DTB for DT control" depends on OF_CONTROL default OF_EMBED if PPC
Or, introduce OF_SEPARATE_TOP ?? I do not know...
Best Regards Masahiro Yamada
On 19.02.2015 11:45, Masahiro Yamada wrote:
On Sat, 7 Feb 2015 11:51:50 -0700 Simon Glass sjg@chromium.org wrote:
From: Stefan Roese sr@denx.de
This is necessary, as ppc4xx has the reset vector located at the end of the U-Boot image. This needs to be flashed to the end of the NOR flash. Adding the dtb to the main U-Boot image will break booting on ppc4xx. This patch now embeds the dtb in the U-Boot image instead.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Simon Glass sjg@chromium.org
It this a common requirement for PowerPC architecture?
No. Its specific to PPC4xx, and perhaps some other PPC variants. But not generally for PowerPC.
If so, does it make sense to change default value only for PowerPC?
Might make sense. Or perhaps even for PPC4xx?
choice prompt "Provider of DTB for DT control" depends on OF_CONTROL default OF_EMBED if PPC
default OF_EMBED if 4xx
Does this work?
Thanks, Stefan
From: Stefan Roese sr@denx.de
These additional nodes need to be provided to get U-Boot to boot correctly on the Canyonlands / Glacier board:
- chosen path to the console-uart - reg-shift set to 0 in the uart device nodes
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
arch/powerpc/dts/canyonlands.dts | 6 ++++++ arch/powerpc/dts/glacier.dts | 3 +++ 2 files changed, 9 insertions(+)
diff --git a/arch/powerpc/dts/canyonlands.dts b/arch/powerpc/dts/canyonlands.dts index 2ec9762..0a2f5d7 100644 --- a/arch/powerpc/dts/canyonlands.dts +++ b/arch/powerpc/dts/canyonlands.dts @@ -22,6 +22,10 @@ serial1 = &UART1; };
+ chosen { + stdout-path = &UART0; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -280,6 +284,7 @@
UART0: serial@ef600300 { device_type = "serial"; + reg-shift = <0>; compatible = "ns16550"; reg = <0xef600300 0x00000008>; virtual-reg = <0xef600300>; @@ -291,6 +296,7 @@
UART1: serial@ef600400 { device_type = "serial"; + reg-shift = <0>; compatible = "ns16550"; reg = <0xef600400 0x00000008>; virtual-reg = <0xef600400>; diff --git a/arch/powerpc/dts/glacier.dts b/arch/powerpc/dts/glacier.dts index 3e7ce2c..bb4e819 100644 --- a/arch/powerpc/dts/glacier.dts +++ b/arch/powerpc/dts/glacier.dts @@ -251,6 +251,7 @@
UART1: serial@ef600400 { device_type = "serial"; + reg-shift = <0>; compatible = "ns16550"; reg = <0xef600400 0x00000008>; virtual-reg = <0xef600400>; @@ -262,6 +263,7 @@
UART2: serial@ef600500 { device_type = "serial"; + reg-shift = <0>; compatible = "ns16550"; reg = <0xef600500 0x00000008>; virtual-reg = <0xef600500>; @@ -273,6 +275,7 @@
UART3: serial@ef600600 { device_type = "serial"; + reg-shift = <0>; compatible = "ns16550"; reg = <0xef600600 0x00000008>; virtual-reg = <0xef600600>;
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
From: Stefan Roese sr@denx.de
These additional nodes need to be provided to get U-Boot to boot correctly on the Canyonlands / Glacier board:
- chosen path to the console-uart
- reg-shift set to 0 in the uart device nodes
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/powerpc/dts/canyonlands.dts | 6 ++++++ arch/powerpc/dts/glacier.dts | 3 +++ 2 files changed, 9 insertions(+)
Applied to u-boot-dm, thanks!
From: Stefan Roese sr@denx.de
This also displays the "Board:" line in the bootup text with the generic board support code.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
board/amcc/canyonlands/Kconfig | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig index 1617d95..ba1411c 100644 --- a/board/amcc/canyonlands/Kconfig +++ b/board/amcc/canyonlands/Kconfig @@ -29,6 +29,10 @@ config ARCHES
endchoice
+config DISPLAY_BOARDINFO + bool + default y + config DM default y
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
From: Stefan Roese sr@denx.de
This also displays the "Board:" line in the bootup text with the generic board support code.
Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2: None
board/amcc/canyonlands/Kconfig | 4 ++++ 1 file changed, 4 insertions(+)
Applied to u-boot-dm, thanks!
Hi,
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
This series does a small amount of tweaking to support device tree control (CONFIG_OF_CONTROL) on PowerPC platforms. It also adds support for driver model. In both cases the main effort is to set things up correctly before calling board_init_f().
A new generic function, board_init_f_mem() is introduced. This does the various memory calculations in C code, since they are messy in assembler and every architecture should in fact be the same. A later series will adjust ARM and x86 to use this function.
As an example, the Canyonlands boards are converted over to use device tree control and driver model for their serial console. It should be fairly straightforward to convert over other boards.
Changes in v2:
- Reduce reserved stack space for board_init_f_mem() to 64 bytes
- Add SYS_MALLOC_F to Kconfig
I'm trying to catch up on a few things I haven't got to.
If it suits I can apply this to u-boot-dm since it is a driver-model-enablement series and Stefan has tested it.
Regards, Simon
Hi,
On 7 February 2015 at 11:53, Simon Glass sjg@chromium.org wrote:
Hi,
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
This series does a small amount of tweaking to support device tree control (CONFIG_OF_CONTROL) on PowerPC platforms. It also adds support for driver model. In both cases the main effort is to set things up correctly before calling board_init_f().
A new generic function, board_init_f_mem() is introduced. This does the various memory calculations in C code, since they are messy in assembler and every architecture should in fact be the same. A later series will adjust ARM and x86 to use this function.
As an example, the Canyonlands boards are converted over to use device tree control and driver model for their serial console. It should be fairly straightforward to convert over other boards.
Changes in v2:
- Reduce reserved stack space for board_init_f_mem() to 64 bytes
- Add SYS_MALLOC_F to Kconfig
I'm trying to catch up on a few things I haven't got to.
If it suits I can apply this to u-boot-dm since it is a driver-model-enablement series and Stefan has tested it.
OK unless I hear any screams I'm going ahead with that plan this week.
Regards, Simon
Hi Simon,
On 10.02.2015 17:35, Simon Glass wrote:
On 7 February 2015 at 11:51, Simon Glass sjg@chromium.org wrote:
This series does a small amount of tweaking to support device tree control (CONFIG_OF_CONTROL) on PowerPC platforms. It also adds support for driver model. In both cases the main effort is to set things up correctly before calling board_init_f().
A new generic function, board_init_f_mem() is introduced. This does the various memory calculations in C code, since they are messy in assembler and every architecture should in fact be the same. A later series will adjust ARM and x86 to use this function.
As an example, the Canyonlands boards are converted over to use device tree control and driver model for their serial console. It should be fairly straightforward to convert over other boards.
Changes in v2:
- Reduce reserved stack space for board_init_f_mem() to 64 bytes
- Add SYS_MALLOC_F to Kconfig
I'm trying to catch up on a few things I haven't got to.
If it suits I can apply this to u-boot-dm since it is a driver-model-enablement series and Stefan has tested it.
OK unless I hear any screams I'm going ahead with that plan this week.
Yes, please go ahead. Lazy people (like me) tend to only scream when really forced to test the "latest and greatest" stuff. ;)
Thanks, Stefan
participants (3)
-
Masahiro Yamada -
Simon Glass -
Stefan Roese