The 8572 DDR erratum1: DDR controller may enter an illegal state when operating in 32-bit bus mode with 4-beat bursts.

Description: When operating with a 32-bit bus, it is recommended that DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used. This forces the DDR controller to use 4-beat bursts when communicating to the DRAMs. However, an issue exists that could lead to data corruption when the DDR controller is in 32-bit bus mode while using 4-beat bursts.

Projected Impact: If the DDR controller is operating in 32-bit bus mode with 4-beat bursts, then the controller may enter into a bad state. All subsequent reads from memory is corrupted. Four-beat bursts with a 32-bit bus only is used with DDR2 memories. Therefore, this erratum does not affect DDR3 mode.

Work Arounds: To work around this issue, software must set DEBUG_1[31] in DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2).

Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register.

Signed-off-by: Dave Liu daveliu@freescale.com --- cpu/mpc85xx/ddr-gen3.c | 9 ++++++--- 1 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index e0654bb..a2b45c5 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -79,15 +79,18 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);

/* - * 32-bit workaround for DDR2 - * 32_BE + * For 8572 DDR1 erratum - DDR controller may enter illegal state + * when operatiing in 32-bit bus mode with 4-beat bursts, + * This erratum does not affect DDR3 mode, only for DDR2 mode. */ +#ifdef CONFIG_MPC8572 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) - && in_be32(&ddr->sdram_cfg_2) & 0x80000) { + && in_be32(&ddr->sdram_cfg) & 0x80000) { /* set DEBUG_1[31] */ u32 temp = in_be32(&ddr->debug_1); out_be32(&ddr->debug_1, temp | 1); } +#endif

/* * 200 painful micro-seconds must elapse between