Add the base address for watchdog and firewall.

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h index 2c6e412..1f549d7 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -6,9 +6,11 @@ #ifndef _SOCFPGA_S10_BASE_HARDWARE_H_ #define _SOCFPGA_S10_BASE_HARDWARE_H_

+#define SOCFPGA_CCU_ADDRESS 0xf7000000 #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 @@ -17,12 +19,21 @@ #define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100 #define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000 #define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200 +#define SOCFPGA_L4WD1_ADDRESS 0xffd00300 +#define SOCFPGA_L4WD2_ADDRESS 0xffd00400 +#define SOCFPGA_L4WD3_ADDRESS 0xffd00500 #define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000 #define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000 #define SOCFPGA_CLKMGR_ADDRESS 0xffd10000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 +#define SOCFPGA_FIREWALL_L4_PER 0xffd21000 +#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100 +#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 +#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 +#define SOCFPGA_FIREWALL_TCU 0xffd21400 #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 #define SOCFPGA_OCRAM_ADDRESS 0xffe00000

Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 + .../mach-socfpga/include/mach/reset_manager_s10.h | 116 ++++++++++++++++ arch/arm/mach-socfpga/reset_manager.c | 13 ++ arch/arm/mach-socfpga/reset_manager_s10.c | 140 ++++++++++++++++++++ 5 files changed, 272 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 6ee8ce6..69bdb84 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -30,6 +30,7 @@ endif

ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += reset_manager_s10.o obj-y += wrap_pll_config_s10.o endif ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 7cfed7d..075da07 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -44,6 +44,8 @@ void socfpga_per_reset_all(void); #include <asm/arch/reset_manager_gen5.h> #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include <asm/arch/reset_manager_arria10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include <asm/arch/reset_manager_s10.h> #endif

#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h new file mode 100644 index 0000000..6182d5f --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#ifndef _RESET_MANAGER_S10_ +#define _RESET_MANAGER_S10_ + +void reset_cpu(ulong addr); +void reset_deassert_peripherals_handoff(void); + +void socfpga_bridges_reset(int enable); + +void socfpga_per_reset(u32 reset, int set); +void socfpga_per_reset_all(void); + +struct socfpga_reset_manager { + u32 status; + u32 mpu_rst_stat; + u32 misc_stat; + u32 padding1; + u32 hdsk_en; + u32 hdsk_req; + u32 hdsk_ack; + u32 hdsk_stall; + u32 mpumodrst; + u32 per0modrst; + u32 per1modrst; + u32 brgmodrst; + u32 padding2; + u32 cold_mod_reset; + u32 padding3; + u32 dbg_mod_reset; + u32 tap_mod_reset; + u32 padding4; + u32 padding5; + u32 brg_warm_mask; + u32 padding6[3]; + u32 tst_stat; + u32 padding7; + u32 hdsk_timeout; + u32 mpul2flushtimeout; + u32 dbghdsktimeout; +}; + +#define RSTMGR_MPUMODRST_CORE0 0 +#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 +#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 + +/* + * Define a reset identifier, from which a permodrst bank ID + * and reset ID can be extracted using the subsequent macros + * RSTMGR_RESET() and RSTMGR_BANK(). + */ +#define RSTMGR_BANK_OFFSET 8 +#define RSTMGR_BANK_MASK 0x7 +#define RSTMGR_RESET_OFFSET 0 +#define RSTMGR_RESET_MASK 0x1f +#define RSTMGR_DEFINE(_bank, _offset) \ + ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) + +/* Extract reset ID from the reset identifier. */ +#define RSTMGR_RESET(_reset) \ + (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) + +/* Extract bank ID from the reset identifier. */ +#define RSTMGR_BANK(_reset) \ + (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) + +/* + * SocFPGA Stratix10 reset IDs, bank mapping is as follows: + * 0 ... mpumodrst + * 1 ... per0modrst + * 2 ... per1modrst + * 3 ... brgmodrst + */ +#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) +#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) +#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3) +#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 5) +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) +#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8) +#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9) +#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10) +#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11) +#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12) +#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13) +#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15) +#define RSTMGR_DMA RSTMGR_DEFINE(1, 16) +#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) +#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) +#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) +#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) +#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2) +#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3) +#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4) +#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8) +#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9) +#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10) +#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11) +#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12) +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) +#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) +#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24) +#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25) +#define RSTMGR_SDR RSTMGR_DEFINE(3, 6) + +void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state); + +/* Create a human-readable reference to SoCFPGA reset. */ +#define SOCFPGA_RESET(_name) RSTMGR_##_name + +#endif /* _RESET_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index 1389c82..e0a01ed 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -8,8 +8,16 @@ #include <asm/io.h> #include <asm/arch/reset_manager.h>

+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include <asm/arch/mailbox_s10.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10) static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS; +#endif

/* * Write the reset manager register to cause reset @@ -17,8 +25,13 @@ static const struct socfpga_reset_manager *reset_manager_base = void reset_cpu(ulong addr) { /* request a warm reset */ +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) + puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); + mbox_reset_cold(); +#else writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); +#endif /* * infinite loop here as watchdog will trigger and reset * the processor diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c new file mode 100644 index 0000000..5cc8336 --- /dev/null +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <dt-bindings/reset/altr,rst-mgr-s10.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; +static const struct socfpga_system_manager *system_manager_base = + (void *)SOCFPGA_SYSMGR_ADDRESS; + +/* Assert or de-assert SoCFPGA reset manager reset. */ +void socfpga_per_reset(u32 reset, int set) +{ + const void *reg; + + if (RSTMGR_BANK(reset) == 0) + reg = &reset_manager_base->mpumodrst; + else if (RSTMGR_BANK(reset) == 1) + reg = &reset_manager_base->per0modrst; + else if (RSTMGR_BANK(reset) == 2) + reg = &reset_manager_base->per1modrst; + else if (RSTMGR_BANK(reset) == 3) + reg = &reset_manager_base->brgmodrst; + else /* Invalid reset register, do nothing */ + return; + + if (set) + setbits_le32(reg, 1 << RSTMGR_RESET(reset)); + else + clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); +} + +/* + * Assert reset on every peripheral but L4WD0. + * Watchdog must be kept intact to prevent glitches + * and/or hangs. + */ +void socfpga_per_reset_all(void) +{ + const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); + + /* disable all except OCP and l4wd0. OCP disable later */ + writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK), + &reset_manager_base->per0modrst); + writel(~l4wd0, &reset_manager_base->per0modrst); + writel(0xffffffff, &reset_manager_base->per1modrst); +} + +void socfpga_bridges_reset(int enable) +{ + if (enable) { + /* clear idle request to all bridges */ + setbits_le32(&system_manager_base->noc_idlereq_clr, ~0); + + /* Release bridges from reset state per handoff value */ + clrbits_le32(&reset_manager_base->brgmodrst, ~0); + + /* Poll until all idleack to 0 */ + while (readl(&system_manager_base->noc_idleack)) + ; + } else { + /* set idle request to all bridges */ + writel(~0, &system_manager_base->noc_idlereq_set); + + /* Enable the NOC timeout */ + writel(1, &system_manager_base->noc_timeout); + + /* Poll until all idleack to 1 */ + while ((readl(&system_manager_base->noc_idleack) ^ + (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) + ; + + /* Poll until all idlestatus to 1 */ + while ((readl(&system_manager_base->noc_idlestatus) ^ + (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) + ; + + /* Put all bridges (except NOR DDR scheduler) into reset */ + setbits_le32(&reset_manager_base->brgmodrst, + ~RSTMGR_BRGMODRST_DDRSCH_MASK); + + /* Disable NOC timeout */ + writel(0, &system_manager_base->noc_timeout); + } +} + +/* of_reset_id: emac reset id + * state: 0 - disable reset, !0 - enable reset + */ +void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state) +{ + u32 reset_emac; + u32 reset_emacocp; + + /* hardcode this now */ + switch (of_reset_id) { + case EMAC0_RESET: + reset_emac = SOCFPGA_RESET(EMAC0); + reset_emacocp = SOCFPGA_RESET(EMAC0_OCP); + break; + case EMAC1_RESET: + reset_emac = SOCFPGA_RESET(EMAC1); + reset_emacocp = SOCFPGA_RESET(EMAC1_OCP); + break; + case EMAC2_RESET: + reset_emac = SOCFPGA_RESET(EMAC2); + reset_emacocp = SOCFPGA_RESET(EMAC2_OCP); + break; + default: + printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); + hang(); + break; + } + + /* Reset ECC OCP first */ + socfpga_per_reset(reset_emacocp, state); + + /* Release the EMAC controller from reset */ + socfpga_per_reset(reset_emac, state); +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per1modrst); + /* Enable OCP first */ + writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst); + writel(0, &reset_manager_base->per0modrst); +}

Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch conditional build in order this file can by shared across other SOCFPGAs.

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/misc.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 5c27f19..8ec0917 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -22,8 +22,10 @@

DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +#endif

struct bsel bsel_str[] = { { "rsvd", "Reserved", }, @@ -52,6 +54,7 @@ void enable_caches(void) #endif }

+#ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_enable(void) { /* Disable the L2 cache */ @@ -72,6 +75,7 @@ void v7_outer_cache_disable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } +#endif

#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)

Move bridge command to misc common driver, in preparation to used by other platforms.

Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/include/mach/misc.h | 2 + arch/arm/mach-socfpga/misc.c | 31 +++++++++++++++++++++++++++++ arch/arm/mach-socfpga/misc_gen5.c | 26 ++--------------------- 3 files changed, 36 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 197f09a..7fe77ac 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -27,4 +27,6 @@ unsigned int shared_uart_com_port(const void *blob); unsigned int uart_com_port(const void *blob); #endif

+void do_bridge_reset(int enable); + #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 8ec0917..6e0f9a2 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -139,3 +139,34 @@ int arch_cpu_init(void)

return 0; } + +#ifndef CONFIG_SPL_BUILD +static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + + argv++; + + switch (*argv[0]) { + case 'e': /* Enable */ + do_bridge_reset(1); + break; + case 'd': /* Disable */ + do_bridge_reset(0); + break; + default: + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + bridge, 2, 1, do_bridge, + "SoCFPGA HPS FPGA bridge control", + "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "" +); +#endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index b9db3ae..84759a1 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -322,40 +322,20 @@ static void socfpga_sdram_apply_static_cfg(void) : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc"); }

-static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +void do_bridge_reset(int enable) { - if (argc != 2) - return CMD_RET_USAGE; - - argv++; - - switch (*argv[0]) { - case 'e': /* Enable */ + if (enable) { writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); socfpga_sdram_apply_static_cfg(); writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); writel(iswgrp_handoff[1], &nic301_regs->remap); - break; - case 'd': /* Disable */ + } else { writel(0, &sysmgr_regs->fpgaintfgrp_module); writel(0, &sdr_ctrl->fpgaport_rst); socfpga_sdram_apply_static_cfg(); writel(0, &reset_manager_base->brg_mod_reset); writel(1, &nic301_regs->remap); - break; - default: - return CMD_RET_USAGE; } - - return 0; } - -U_BOOT_CMD( - bridge, 2, 1, do_bridge, - "SoCFPGA HPS FPGA bridge control", - "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "" -); #endif

Add misc support such as EMAC and cpu info printout for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/misc_s10.c | 133 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 134 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-socfpga/misc_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 61f5778..c74fec2 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -30,6 +30,7 @@ endif

ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += misc_s10.o obj-y += reset_manager_s10.o obj-y += system_manager_s10.o obj-y += wrap_pinmux_config_s10.o diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c new file mode 100644 index 0000000..918baac --- /dev/null +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#include <altera.h> +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/misc.h> +#include <asm/pl310.h> +#include <linux/libfdt.h> + +#include <dt-bindings/reset/altr,rst-mgr-s10.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* + * DesignWare Ethernet initialization + */ +#ifdef CONFIG_ETH_DESIGNWARE + +static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode) +{ + u32 modereg; + + if (!phymode) + return -EINVAL; + + if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + else if (!strcmp(phymode, "rgmii")) + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + else if (!strcmp(phymode, "rmii")) + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + else + return -EINVAL; + + clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, + modereg); + + return 0; +} + +static int socfpga_set_phymode(void) +{ + const void *fdt = gd->fdt_blob; + struct fdtdec_phandle_args args; + const char *phy_mode; + u32 gmac_index; + int nodes[2]; /* Max. 3 GMACs */ + int ret, count; + int i, node; + + count = fdtdec_find_aliases_for_id(fdt, "ethernet", + COMPAT_ALTERA_SOCFPGA_DWMAC, + nodes, ARRAY_SIZE(nodes)); + for (i = 0; i < count; i++) { + node = nodes[i]; + if (node <= 0) + continue; + + ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", + "#reset-cells", 1, 0, + &args); + if (ret || args.args_count != 1) { + debug("GMAC%i: Failed to parse DT 'resets'!\n", i); + continue; + } + + gmac_index = args.args[0] - EMAC0_RESET; + + phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); + ret = socfpga_phymode_setup(gmac_index, phy_mode); + if (ret) { + debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); + continue; + } + } + + return 0; +} +#else +static int socfpga_set_phymode(void) +{ + return 0; +}; +#endif + +/* + * Print CPU information + */ +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n"); + + return 0; +} +#endif + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + char qspi_string[13]; + + sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); + env_set("qspi_clock", qspi_string); + + socfpga_set_phymode(); + return 0; +} +#endif + +int arch_early_init_r(void) +{ + return 0; +} + +void do_bridge_reset(int enable) +{ + socfpga_bridges_reset(enable); +}

Add mailbox support for Stratix SoC

Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Chin Liang See chin.liang.see@intel.com --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 144 ++++++++ arch/arm/mach-socfpga/mailbox_s10.c | 380 ++++++++++++++++++++++ 3 files changed, 525 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index c74fec2..5c22cc2 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -30,6 +30,7 @@ endif

ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += reset_manager_s10.o obj-y += system_manager_s10.o diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h new file mode 100644 index 0000000..81a609d --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> + * + */ + +#ifndef _MAILBOX_S10_H_ +#define _MAILBOX_S10_H_ + +/* user define Uboot ID */ +#define MBOX_CLIENT_ID_UBOOT 0xB +#define MBOX_ID_UBOOT 0x1 + +#define MBOX_CMD_DIRECT 0 +#define MBOX_CMD_INDIRECT 1 + +#define MBOX_MAX_CMD_INDEX 2047 +#define MBOX_CMD_BUFFER_SIZE 32 +#define MBOX_RESP_BUFFER_SIZE 16 + +#define MBOX_HDR_CMD_LSB 0 +#define MBOX_HDR_CMD_MSK (BIT(11) - 1) +#define MBOX_HDR_I_LSB 11 +#define MBOX_HDR_I_MSK BIT(11) +#define MBOX_HDR_LEN_LSB 12 +#define MBOX_HDR_LEN_MSK 0x007FF000 +#define MBOX_HDR_ID_LSB 24 +#define MBOX_HDR_ID_MSK 0x0F000000 +#define MBOX_HDR_CLIENT_LSB 28 +#define MBOX_HDR_CLIENT_MSK 0xF0000000 + +/* Interrupt flags */ +#define MBOX_FLAGS_INT_COE BIT(0) /* COUT update interrupt enable */ +#define MBOX_FLAGS_INT_RIE BIT(1) /* RIN update interrupt enable */ +#define MBOX_FLAGS_INT_UAE BIT(8) /* Urgent ACK interrupt enable */ +#define MBOX_ALL_INTRS (MBOX_FLAGS_INT_COE | \ + MBOX_FLAGS_INT_RIE | \ + MBOX_FLAGS_INT_UAE) + +/* Status */ +#define MBOX_STATUS_UA_MSK BIT(8) + +#define MBOX_CMD_HEADER(client, id, len, indirect, cmd) \ + ((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \ + (((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \ + (((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \ + (((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK) | \ + (((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK)) + +#define MBOX_RESP_ERR_GET(resp) \ + (((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB) +#define MBOX_RESP_LEN_GET(resp) \ + (((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB) +#define MBOX_RESP_ID_GET(resp) \ + (((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB) +#define MBOX_RESP_CLIENT_GET(resp) \ + (((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB) + +/* Response error list */ +enum ALT_SDM_MBOX_RESP_CODE { + /* CMD completed successfully, but check resp ARGS for any errors */ + MBOX_RESP_STATOK = 0, + /* CMD is incorrectly formatted in some way */ + MBOX_RESP_INVALID_COMMAND = 1, + /* BootROM Command code not undesrtood */ + MBOX_RESP_UNKNOWN_BR = 2, + /* CMD code not recognized by firmware */ + MBOX_RESP_UNKNOWN = 3, + /* Indicates that the device is not configured */ + MBOX_RESP_NOT_CONFIGURED = 256, + /* Indicates that the device is busy */ + MBOX_RESP_DEVICE_BUSY = 0x1FF, + /* Indicates that there is no valid response available */ + MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF, + /* General Error */ + MBOX_RESP_ERROR = 0x3FF, +}; + +/* Mailbox command list */ +#define MBOX_RESTART 2 +#define MBOX_CONFIG_STATUS 4 +#define MBOX_RECONFIG 6 +#define MBOX_RECONFIG_MSEL 7 +#define MBOX_RECONFIG_DATA 8 +#define MBOX_RECONFIG_STATUS 9 +#define MBOX_QSPI_OPEN 50 +#define MBOX_QSPI_CLOSE 51 +#define MBOX_QSPI_DIRECT 59 +#define MBOX_REBOOT_HPS 71 + +/* Mailbox registers */ +#define MBOX_CIN 0 /* command valid offset */ +#define MBOX_ROUT 4 /* response output offset */ +#define MBOX_URG 8 /* urgent command */ +#define MBOX_FLAGS 0x0c /* interrupt enables */ +#define MBOX_COUT 0x20 /* command free offset */ +#define MBOX_RIN 0x24 /* respond valid offset */ +#define MBOX_STATUS 0x2c /* mailbox status */ +#define MBOX_CMD_BUF 0x40 /* circular command buffer */ +#define MBOX_RESP_BUF 0xc0 /* circular response buffer */ +#define MBOX_DOORBELL_TO_SDM 0x400 /* Doorbell to SDM */ +#define MBOX_DOORBELL_FROM_SDM 0x480 /* Doorbell from SDM */ + +/* Status and bit information returned by RECONFIG_STATUS */ +#define RECONFIG_STATUS_RESPONSE_LEN 6 +#define RECONFIG_STATUS_STATE 0 +#define RECONFIG_STATUS_PIN_STATUS 2 +#define RECONFIG_STATUS_SOFTFUNC_STATUS 3 + +#define MBOX_CFGSTAT_STATE_IDLE 0x00000000 +#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 +#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 +#define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001 +#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002 +#define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003 +#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004 +#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005 +#define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006 +#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 +#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 + +#define RCF_SOFTFUNC_STATUS_CONF_DONE BIT(0) +#define RCF_SOFTFUNC_STATUS_INIT_DONE BIT(1) +#define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3) +#define RCF_PIN_STATUS_NSTATUS BIT(31) + +int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, + u32 *resp_buf_len, u32 *resp_buf); +int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, + u8 urgent, u32 *resp_buf_len, u32 *resp_buf); +int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg); +int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg); +int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len); +int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len); +int mbox_init(void); + +#ifdef CONFIG_CADENCE_QSPI +int mbox_qspi_close(void); +int mbox_qspi_open(void); +#endif + +int mbox_reset_cold(void); + +#endif /* _MAILBOX_S10_H_ */ diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c new file mode 100644 index 0000000..cccd1a4 --- /dev/null +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <wait_bit.h> +#include <asm/io.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/system_manager.h> +#include <asm/secure.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MBOX_READL(reg) \ + readl(SOCFPGA_MAILBOX_ADDRESS + (reg)) + +#define MBOX_WRITEL(data, reg) \ + writel(data, SOCFPGA_MAILBOX_ADDRESS + (reg)) + +#define MBOX_READ_RESP_BUF(rout) \ + MBOX_READL(MBOX_RESP_BUF + ((rout) * sizeof(u32))) + +#define MBOX_WRITE_CMD_BUF(data, cin) \ + MBOX_WRITEL(data, MBOX_CMD_BUF + ((cin) * sizeof(u32))) + +static __always_inline int mbox_polling_resp(u32 rout) +{ + u32 rin; + unsigned long i = ~0; + + while (i) { + rin = MBOX_READL(MBOX_RIN); + if (rout != rin) + return 0; + + i--; + } + + return -ETIMEDOUT; +} + +/* Check for available slot and write to circular buffer. + * It also update command valid offset (cin) register. + */ +static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len, + u32 *arg) +{ + u32 cin; + u32 cout; + u32 i; + + cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE; + cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE; + + /* if command buffer is full or not enough free space + * to fit the data + */ + if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout || + ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) % + MBOX_CMD_BUFFER_SIZE) < len) + return -ENOMEM; + + /* write header to circular buffer */ + MBOX_WRITE_CMD_BUF(header, cin++); + /* wrapping around when it reach the buffer size */ + cin %= MBOX_CMD_BUFFER_SIZE; + + /* write arguments */ + for (i = 0; i < len; i++) { + MBOX_WRITE_CMD_BUF(arg[i], cin++); + /* wrapping around when it reach the buffer size */ + cin %= MBOX_CMD_BUFFER_SIZE; + } + + /* write command valid offset */ + MBOX_WRITEL(cin, MBOX_CIN); + + return 0; +} + +/* Check the command and fill it into circular buffer */ +static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd, + u8 is_indirect, u32 len, + u32 *arg) +{ + u32 header; + int ret; + + /* Total length is command + argument length */ + if ((len + 1) > MBOX_CMD_BUFFER_SIZE) + return -EINVAL; + + if (cmd > MBOX_MAX_CMD_INDEX) + return -EINVAL; + + header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len, + (is_indirect) ? 1 : 0, cmd); + + ret = mbox_fill_cmd_circular_buff(header, len, arg); + + return ret; +} + +/* Send command only without waiting for responses from SDM */ +static __always_inline int mbox_send_cmd_only_common(u8 id, u32 cmd, + u8 is_indirect, u32 len, + u32 *arg) +{ + int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg); + /* write doorbell */ + MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM); + + return ret; +} + +/* Return number of responses received in buffer */ +static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len) +{ + u32 rin; + u32 rout; + u32 resp_len = 0; + + /* clear doorbell from SDM if it was SET */ + if (MBOX_READL(MBOX_DOORBELL_FROM_SDM) & 1) + MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM); + + /* read current response offset */ + rout = MBOX_READL(MBOX_ROUT); + /* read response valid offset */ + rin = MBOX_READL(MBOX_RIN); + + while (rin != rout && (resp_len < resp_buf_max_len)) { + /* Response received */ + if (resp_buf) + resp_buf[resp_len++] = MBOX_READ_RESP_BUF(rout); + + rout++; + /* wrapping around when it reach the buffer size */ + rout %= MBOX_RESP_BUFFER_SIZE; + /* update next ROUT */ + MBOX_WRITEL(rout, MBOX_ROUT); + } + + return resp_len; +} + +/* Support one command and up to 31 words argument length only */ +static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect, + u32 len, u32 *arg, u8 urgent, + u32 *resp_buf_len, + u32 *resp_buf) +{ + u32 rin; + u32 resp; + u32 rout; + u32 status; + u32 resp_len; + u32 buf_len; + int ret; + + ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg); + if (ret) + return ret; + + if (urgent) { + /* Read status because it is toggled */ + status = MBOX_READL(MBOX_STATUS) & MBOX_STATUS_UA_MSK; + /* Send command as urgent command */ + MBOX_WRITEL(1, MBOX_URG); + } + + /* write doorbell */ + MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM); + + while (1) { + ret = ~0; + + /* Wait for doorbell from SDM */ + while (!MBOX_READL(MBOX_DOORBELL_FROM_SDM) && ret--) + ; + if (!ret) + return -ETIMEDOUT; + + /* clear interrupt */ + MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM); + + if (urgent) { + u32 new_status = MBOX_READL(MBOX_STATUS); + /* urgent command doesn't have response */ + MBOX_WRITEL(0, MBOX_URG); + /* Urgent ACK is toggled */ + if ((new_status & MBOX_STATUS_UA_MSK) ^ status) + return 0; + + return -ECOMM; + } + + /* read current response offset */ + rout = MBOX_READL(MBOX_ROUT); + + /* read response valid offset */ + rin = MBOX_READL(MBOX_RIN); + + if (rout != rin) { + /* Response received */ + resp = MBOX_READ_RESP_BUF(rout); + rout++; + /* wrapping around when it reach the buffer size */ + rout %= MBOX_RESP_BUFFER_SIZE; + /* update next ROUT */ + MBOX_WRITEL(rout, MBOX_ROUT); + + /* check client ID and ID */ + if ((MBOX_RESP_CLIENT_GET(resp) == + MBOX_CLIENT_ID_UBOOT) && + (MBOX_RESP_ID_GET(resp) == id)) { + ret = MBOX_RESP_ERR_GET(resp); + if (ret) + return ret; + + if (resp_buf_len) { + buf_len = *resp_buf_len; + *resp_buf_len = 0; + } else { + buf_len = 0; + } + + resp_len = MBOX_RESP_LEN_GET(resp); + while (resp_len) { + ret = mbox_polling_resp(rout); + if (ret) + return ret; + /* we need to process response buffer + * even caller doesn't need it + */ + resp = MBOX_READ_RESP_BUF(rout); + rout++; + resp_len--; + rout %= MBOX_RESP_BUFFER_SIZE; + MBOX_WRITEL(rout, MBOX_ROUT); + if (buf_len) { + /* copy response to buffer */ + resp_buf[*resp_buf_len] = resp; + (*resp_buf_len)++; + buf_len--; + } + } + return ret; + } + } + }; + + return -EIO; +} + +int mbox_init(void) +{ + int ret; + + /* enable mailbox interrupts */ + MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS); + + /* Ensure urgent request is cleared */ + MBOX_WRITEL(0, MBOX_URG); + + /* Ensure the Doorbell Interrupt is cleared */ + MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM); + + ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0, + NULL, 1, 0, NULL); + if (ret) + return ret; + + /* Renable mailbox interrupts after MBOX_RESTART */ + MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS); + + return 0; +} + +#ifdef CONFIG_CADENCE_QSPI +int mbox_qspi_close(void) +{ + return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT, + 0, NULL, 0, 0, NULL); +} + +int mbox_qspi_open(void) +{ + static const struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + + int ret; + u32 resp_buf[1]; + u32 resp_buf_len; + + ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT, + 0, NULL, 0, 0, NULL); + if (ret) { + /* retry again by closing and reopen the QSPI again */ + ret = mbox_qspi_close(); + if (ret) + return ret; + + ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, + MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL); + if (ret) + return ret; + } + + /* HPS will directly control the QSPI controller, no longer mailbox */ + resp_buf_len = 1; + ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT, + 0, NULL, 0, (u32 *)&resp_buf_len, + (u32 *)&resp_buf); + if (ret) + goto error; + + /* We are getting QSPI ref clock and set into sysmgr boot register */ + printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]); + writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0); + + return 0; + +error: + mbox_qspi_close(); + + return ret; +} +#endif /* CONFIG_CADENCE_QSPI */ + +int mbox_reset_cold(void) +{ + int ret; + + ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT, + 0, NULL, 0, 0, NULL); + if (ret) { + /* mailbox sent failure, wait for watchdog to kick in */ + hang(); + } + return 0; +} + +int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, + u8 urgent, u32 *resp_buf_len, u32 *resp_buf) +{ + return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent, + resp_buf_len, resp_buf); +} + +int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, + u32 *arg, u8 urgent, u32 *resp_buf_len, + u32 *resp_buf) +{ + return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent, + resp_buf_len, resp_buf); +} + +int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) +{ + return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg); +} + +int __secure mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, + u32 *arg) +{ + return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg); +} + +int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len) +{ + return __mbox_rcv_resp(resp_buf, resp_buf_max_len); +} + +int __secure mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len) +{ + return __mbox_rcv_resp(resp_buf, resp_buf_max_len); +}

Add MMU memory mapping table for Stratix SoC.

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Acked-by: Marek Vasut marex@denx.de --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 5c22cc2..478afe2 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -32,6 +32,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o obj-y += mailbox_s10.o obj-y += misc_s10.o +obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-y += system_manager_s10.o obj-y += wrap_pinmux_config_s10.o diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c new file mode 100644 index 0000000..670ceb9 --- /dev/null +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct mm_region socfpga_stratix10_mem_map[] = { + { + /* MEM 2GB*/ + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* FPGA 1.5GB */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x60000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* DEVICE 142MB */ + .virt = 0xF7000000UL, + .phys = 0xF7000000UL, + .size = 0x08E00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* OCRAM 1MB but available 256KB */ + .virt = 0xFFE00000UL, + .phys = 0xFFE00000UL, + .size = 0x00100000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* DEVICE 32KB */ + .virt = 0xFFFC0000UL, + .phys = 0xFFFC0000UL, + .size = 0x00008000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* MEM 124GB */ + .virt = 0x0100000000UL, + .phys = 0x0100000000UL, + .size = 0x1F00000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* DEVICE 4GB */ + .virt = 0x2000000000UL, + .phys = 0x2000000000UL, + .size = 0x0100000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* List terminator */ + }, +}; + +struct mm_region *mem_map = socfpga_stratix10_mem_map;

Restructure the SPL so each devices such as CV, A10 and S10 will have their own dedicated SPL file. SPL file determine the HW initialization flow which is device specific

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/Makefile | 5 +- arch/arm/mach-socfpga/spl_a10.c | 105 +++++++++++++++++++++++++++ arch/arm/mach-socfpga/{spl.c => spl_gen5.c} | 57 +++------------ 3 files changed, 120 insertions(+), 47 deletions(-) create mode 100644 arch/arm/mach-socfpga/spl_a10.c rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (82%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 478afe2..e8a1c0f 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -39,13 +39,16 @@ obj-y += wrap_pinmux_config_s10.o obj-y += wrap_pll_config_s10.o endif ifdef CONFIG_SPL_BUILD -obj-y += spl.o ifdef CONFIG_TARGET_SOCFPGA_GEN5 +obj-y += spl_gen5.o obj-y += freeze_controller.o obj-y += wrap_iocsr_config.o obj-y += wrap_pinmux_config.o obj-y += wrap_sdram_config.o endif +ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +obj-y += spl_a10.o +endif endif

ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c new file mode 100644 index 0000000..e6fc766 --- /dev/null +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/pl310.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <image.h> +#include <asm/arch/reset_manager.h> +#include <spl.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/freeze_controller.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/scan_manager.h> +#include <asm/arch/sdram.h> +#include <asm/arch/scu.h> +#include <asm/arch/nic301.h> +#include <asm/sections.h> +#include <fdtdec.h> +#include <watchdog.h> +#include <asm/arch/pinmux.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +u32 spl_boot_device(void) +{ + const u32 bsel = readl(&sysmgr_regs->bootinfo); + + switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { + case 0x1: /* FPGA (HPS2FPGA Bridge) */ + return BOOT_DEVICE_RAM; + case 0x2: /* NAND Flash (1.8V) */ + case 0x3: /* NAND Flash (3.0V) */ + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); + return BOOT_DEVICE_NAND; + case 0x4: /* SD/MMC External Transceiver (1.8V) */ + case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ + socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); + socfpga_per_reset(SOCFPGA_RESET(DMA), 0); + return BOOT_DEVICE_MMC1; + case 0x6: /* QSPI Flash (1.8V) */ + case 0x7: /* QSPI Flash (3.0V) */ + socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); + return BOOT_DEVICE_SPI; + default: + printf("Invalid boot device (bsel=%08x)!\n", bsel); + hang(); + } +} + +#ifdef CONFIG_SPL_MMC_SUPPORT +u32 spl_boot_mode(const u32 boot_device) +{ +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) + return MMCSD_MODE_FS; +#else + return MMCSD_MODE_RAW; +#endif +} +#endif + +void spl_board_init(void) +{ + /* configuring the clock based on handoff */ + cm_basic_init(gd->fdt_blob); + WATCHDOG_RESET(); + + config_dedicated_pins(gd->fdt_blob); + WATCHDOG_RESET(); + + /* Release UART from reset */ + socfpga_reset_uart(0); + + /* enable console uart printing */ + preloader_console_init(); +} + +void board_init_f(ulong dummy) +{ + /* + * Configure Clock Manager to use intosc clock instead external osc to + * ensure success watchdog operation. We do it as early as possible. + */ + cm_use_intosc(); + + socfpga_watchdog_disable(); + + arch_early_init_r(); + +#ifdef CONFIG_HW_WATCHDOG + /* release osc1 watchdog timer 0 from reset */ + socfpga_reset_deassert_osc1wd0(); + + /* reconfigure and enable the watchdog */ + hw_watchdog_init(); + WATCHDOG_RESET(); +#endif /* CONFIG_HW_WATCHDOG */ +} diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl_gen5.c similarity index 82% rename from arch/arm/mach-socfpga/spl.c rename to arch/arm/mach-socfpga/spl_gen5.c index 4b86ead..9df7927 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -21,21 +21,15 @@ #include <asm/sections.h> #include <fdtdec.h> #include <watchdog.h> -#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#include <asm/arch/pinmux.h> -#endif

DECLARE_GLOBAL_DATA_PTR;

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -#endif - static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

@@ -65,7 +59,17 @@ u32 spl_boot_device(void) } }

-#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#ifdef CONFIG_SPL_MMC_SUPPORT +u32 spl_boot_mode(const u32 boot_device) +{ +#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) + return MMCSD_MODE_FS; +#else + return MMCSD_MODE_RAW; +#endif +} +#endif + static void socfpga_nic301_slave_ns(void) { writel(0x1, &nic301_regs->lwhps2fpgaregs); @@ -181,42 +185,3 @@ void board_init_f(ulong dummy) /* Configure simple malloc base pointer into RAM. */ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); } -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -void spl_board_init(void) -{ - /* configuring the clock based on handoff */ - cm_basic_init(gd->fdt_blob); - WATCHDOG_RESET(); - - config_dedicated_pins(gd->fdt_blob); - WATCHDOG_RESET(); - - /* Release UART from reset */ - socfpga_reset_uart(0); - - /* enable console uart printing */ - preloader_console_init(); -} - -void board_init_f(ulong dummy) -{ - /* - * Configure Clock Manager to use intosc clock instead external osc to - * ensure success watchdog operation. We do it as early as possible. - */ - cm_use_intosc(); - - socfpga_watchdog_disable(); - - arch_early_init_r(); - -#ifdef CONFIG_HW_WATCHDOG - /* release osc1 watchdog timer 0 from reset */ - socfpga_reset_deassert_osc1wd0(); - - /* reconfigure and enable the watchdog */ - hw_watchdog_init(); - WATCHDOG_RESET(); -#endif /* CONFIG_HW_WATCHDOG */ -} -#endif

Add timer support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/Makefile | 4 +++- arch/arm/mach-socfpga/timer_s10.c | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-socfpga/timer_s10.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 3131949..654999c 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -9,7 +9,6 @@ obj-y += board.o obj-y += clock_manager.o obj-y += misc.o obj-y += reset_manager.o -obj-y += timer.o

ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += clock_manager_gen5.o @@ -17,6 +16,7 @@ obj-y += misc_gen5.o obj-y += reset_manager_gen5.o obj-y += scan_manager.o obj-y += system_manager_gen5.o +obj-y += timer.o obj-y += wrap_pll_config.o obj-y += fpga_manager.o endif @@ -26,6 +26,7 @@ obj-y += clock_manager_arria10.o obj-y += misc_arria10.o obj-y += pinmux_arria10.o obj-y += reset_manager_arria10.o +obj-y += timer.o endif

ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 @@ -35,6 +36,7 @@ obj-y += misc_s10.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-y += system_manager_s10.o +obj-y += timer_s10.o obj-y += wrap_pinmux_config_s10.o obj-y += wrap_pll_config_s10.o endif diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c new file mode 100644 index 0000000..5723789 --- /dev/null +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/timer.h> + +/* + * Timer initialization + */ +int timer_init(void) +{ + int enable = 0x3; /* timer enable + output signal masked */ + int loadval = ~0; + + /* enable system counter */ + writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS); + /* enable processor pysical counter */ + asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable)); + asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval)); + + return 0; +}

Add DDR support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/include/mach/sdram_s10.h | 183 +++++++++++ arch/arm/mach-socfpga/misc.c | 11 +- drivers/ddr/altera/Makefile | 1 + drivers/ddr/altera/sdram_s10.c | 388 ++++++++++++++++++++++++ 4 files changed, 577 insertions(+), 6 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h create mode 100644 drivers/ddr/altera/sdram_s10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h new file mode 100644 index 0000000..91bfc0e --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> + * + */ + +#ifndef _SDRAM_S10_H_ +#define _SDRAM_S10_H_ + +unsigned long sdram_calculate_size(void); +int sdram_mmr_init_full(unsigned int sdr_phy_reg); +int sdram_calibration_full(void); + +#define DDR_TWR 15 +#define DDR_READ_LATENCY_DELAY 40 +#define DDR_ACTIVATE_FAWBANK 0x1 + +/* ECC HMC registers */ +#define DDRIOCTRL 0x8 +#define DDRCALSTAT 0xc +#define DRAMADDRWIDTH 0xe0 +#define ECCCTRL1 0x100 +#define ECCCTRL2 0x104 +#define ERRINTEN 0x110 +#define INTMODE 0x11c +#define INTSTAT 0x120 +#define AUTOWB_CORRADDR 0x138 +#define ECC_REG2WRECCDATABUS 0x144 +#define ECC_DIAGON 0x150 +#define ECC_DECSTAT 0x154 +#define HPSINTFCSEL 0x210 +#define RSTHANDSHAKECTRL 0x214 +#define RSTHANDSHAKESTAT 0x218 + +#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 +#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) +#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) +#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) +#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0) +#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8) +#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0) +#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16) +#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0) +#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0) +#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1) +#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0) +#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) +#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) +#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) +#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff +#define DDR_HMC_CORE2SEQ_INT_REQ 0xF +#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) +#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f + +/* NOC DDR scheduler */ +#define DDR_SCH_ID_COREID 0 +#define DDR_SCH_ID_REVID 0x4 +#define DDR_SCH_DDRCONF 0x8 +#define DDR_SCH_DDRTIMING 0xc +#define DDR_SCH_DDRMODE 0x10 +#define DDR_SCH_READ_LATENCY 0x14 +#define DDR_SCH_ACTIVATE 0x38 +#define DDR_SCH_DEVTODEV 0x3c +#define DDR_SCH_DDR4TIMING 0x40 + +#define DDR_SCH_DDRTIMING_ACTTOACT_OFF 0 +#define DDR_SCH_DDRTIMING_RDTOMISS_OFF 6 +#define DDR_SCH_DDRTIMING_WRTOMISS_OFF 12 +#define DDR_SCH_DDRTIMING_BURSTLEN_OFF 18 +#define DDR_SCH_DDRTIMING_RDTOWR_OFF 21 +#define DDR_SCH_DDRTIMING_WRTORD_OFF 26 +#define DDR_SCH_DDRTIMING_BWRATIO_OFF 31 +#define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF 1 +#define DDR_SCH_ACTIVATE_RRD_OFF 0 +#define DDR_SCH_ACTIVATE_FAW_OFF 4 +#define DDR_SCH_ACTIVATE_FAWBANK_OFF 10 +#define DDR_SCH_DEVTODEV_BUSRDTORD_OFF 0 +#define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2 +#define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4 + +/* HMC MMR IO48 registers */ +#define CTRLCFG0 0x28 +#define CTRLCFG1 0x2c +#define DRAMTIMING0 0x50 +#define CALTIMING0 0x7c +#define CALTIMING1 0x80 +#define CALTIMING2 0x84 +#define CALTIMING3 0x88 +#define CALTIMING4 0x8c +#define CALTIMING9 0xa0 +#define DRAMADDRW 0xa8 +#define DRAMSTS 0xec +#define NIOSRESERVED0 0x110 +#define NIOSRESERVED1 0x114 +#define NIOSRESERVED2 0x118 + +#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ + (((x) >> 0) & 0x1F) +#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ + (((x) >> 5) & 0x1F) +#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ + (((x) >> 10) & 0xF) +#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \ + (((x) >> 14) & 0x3) +#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \ + (((x) >> 16) & 0x7) + +#define CTRLCFG0_CFG_MEMTYPE(x) \ + (((x) >> 0) & 0xF) +#define CTRLCFG0_CFG_DIMM_TYPE(x) \ + (((x) >> 4) & 0x7) +#define CTRLCFG0_CFG_AC_POS(x) \ + (((x) >> 7) & 0x3) +#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \ + (((x) >> 9) & 0x1F) + +#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ + (((x) >> 0) & 0x1F) +#define CTRLCFG1_CFG_ADDR_ORDER(x) \ + (((x) >> 5) & 0x3) +#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ + (((x) >> 7) & 0x1) + +#define DRAMTIMING0_CFG_TCL(x) \ + (((x) >> 0) & 0x7F) + +#define CALTIMING0_CFG_ACT_TO_RDWR(x) \ + (((x) >> 0) & 0x3F) +#define CALTIMING0_CFG_ACT_TO_PCH(x) \ + (((x) >> 6) & 0x3F) +#define CALTIMING0_CFG_ACT_TO_ACT(x) \ + (((x) >> 12) & 0x3F) +#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \ + (((x) >> 18) & 0x3F) + +#define CALTIMING1_CFG_RD_TO_RD(x) \ + (((x) >> 0) & 0x3F) +#define CALTIMING1_CFG_RD_TO_RD_DC(x) \ + (((x) >> 6) & 0x3F) +#define CALTIMING1_CFG_RD_TO_RD_DB(x) \ + (((x) >> 12) & 0x3F) +#define CALTIMING1_CFG_RD_TO_WR(x) \ + (((x) >> 18) & 0x3F) +#define CALTIMING1_CFG_RD_TO_WR_DC(x) \ + (((x) >> 24) & 0x3F) + +#define CALTIMING2_CFG_RD_TO_WR_DB(x) \ + (((x) >> 0) & 0x3F) +#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ + (((x) >> 6) & 0x3F) +#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ + (((x) >> 12) & 0x3F) +#define CALTIMING2_CFG_WR_TO_WR(x) \ + (((x) >> 18) & 0x3F) +#define CALTIMING2_CFG_WR_TO_WR_DC(x) \ + (((x) >> 24) & 0x3F) + +#define CALTIMING3_CFG_WR_TO_WR_DB(x) \ + (((x) >> 0) & 0x3F) +#define CALTIMING3_CFG_WR_TO_RD(x) \ + (((x) >> 6) & 0x3F) +#define CALTIMING3_CFG_WR_TO_RD_DC(x) \ + (((x) >> 12) & 0x3F) +#define CALTIMING3_CFG_WR_TO_RD_DB(x) \ + (((x) >> 18) & 0x3F) +#define CALTIMING3_CFG_WR_TO_PCH(x) \ + (((x) >> 24) & 0x3F) + +#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ + (((x) >> 0) & 0x3F) +#define CALTIMING4_CFG_PCH_TO_VALID(x) \ + (((x) >> 6) & 0x3F) +#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ + (((x) >> 12) & 0x3F) +#define CALTIMING4_CFG_ARF_TO_VALID(x) \ + (((x) >> 18) & 0xFF) +#define CALTIMING4_CFG_PDN_TO_VALID(x) \ + (((x) >> 26) & 0x3F) + +#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ + (((x) >> 0) & 0xFF) + +#endif /* _SDRAM_S10_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 6e0f9a2..bb88f30 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -162,11 +162,10 @@ static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; }

-U_BOOT_CMD( - bridge, 2, 1, do_bridge, - "SoCFPGA HPS FPGA bridge control", - "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "" +U_BOOT_CMD(bridge, 2, 1, do_bridge, + "SoCFPGA HPS FPGA bridge control", + "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "" ); #endif diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index d42fd44..34e50a3 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -8,4 +8,5 @@

ifdef CONFIG_ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o endif diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c new file mode 100644 index 0000000..48f4f47 --- /dev/null +++ b/drivers/ddr/altera/sdram_s10.c @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <errno.h> +#include <div64.h> +#include <asm/io.h> +#include <wait_bit.h> +#include <asm/arch/firewall_s10.h> +#include <asm/arch/sdram_s10.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/reset_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_system_manager *sysmgr_regs = + (void *)SOCFPGA_SYSMGR_ADDRESS; + +#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) + +/* The followring are the supported configurations */ +u32 ddr_config[] = { + /* DDR_CONFIG(Address order,Bank,Column,Row) */ + /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */ + DDR_CONFIG(0, 3, 10, 12), + DDR_CONFIG(0, 3, 9, 13), + DDR_CONFIG(0, 3, 10, 13), + DDR_CONFIG(0, 3, 9, 14), + DDR_CONFIG(0, 3, 10, 14), + DDR_CONFIG(0, 3, 10, 15), + DDR_CONFIG(0, 3, 11, 14), + DDR_CONFIG(0, 3, 11, 15), + DDR_CONFIG(0, 3, 10, 16), + DDR_CONFIG(0, 3, 11, 16), + DDR_CONFIG(0, 3, 12, 15), /* 0xa */ + /* List for DDR4 only (pinout order > chip, bank, row, column) */ + DDR_CONFIG(1, 3, 10, 14), + DDR_CONFIG(1, 4, 10, 14), + DDR_CONFIG(1, 3, 10, 15), + DDR_CONFIG(1, 4, 10, 15), + DDR_CONFIG(1, 3, 10, 16), + DDR_CONFIG(1, 4, 10, 16), + DDR_CONFIG(1, 3, 10, 17), + DDR_CONFIG(1, 4, 10, 17), +}; + +static u32 hmc_readl(u32 reg) +{ + return readl(((void __iomem *)SOCFPGA_HMC_MMR_IO48_ADDRESS + (reg))); +} + +static u32 hmc_ecc_readl(u32 reg) +{ + return readl((void __iomem *)SOCFPGA_SDR_ADDRESS + (reg)); +} + +static u32 hmc_ecc_writel(u32 data, u32 reg) +{ + return writel(data, (void __iomem *)SOCFPGA_SDR_ADDRESS + (reg)); +} + +static u32 ddr_sch_writel(u32 data, u32 reg) +{ + return writel(data, + (void __iomem *)SOCFPGA_SDR_SCHEDULER_ADDRESS + (reg)); +} + +int match_ddr_conf(u32 ddr_conf) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ddr_config); i++) { + if (ddr_conf == ddr_config[i]) + return i; + } + return 0; +} + +static int emif_clear(void) +{ + hmc_ecc_writel(0, RSTHANDSHAKECTRL); + + return wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + + RSTHANDSHAKESTAT), + DDR_HMC_RSTHANDSHAKE_MASK, + false, 1000, false); +} + +static int emif_reset(void) +{ + u32 c2s, s2c, ret; + + c2s = hmc_ecc_readl(RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK; + s2c = hmc_ecc_readl(RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK; + + debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", + c2s, s2c, hmc_readl(NIOSRESERVED0), hmc_readl(NIOSRESERVED1), + hmc_readl(NIOSRESERVED2), hmc_readl(DRAMSTS)); + + if (s2c && emif_clear()) { + printf("DDR: emif_clear() failed\n"); + return -1; + } + + debug("DDR: Triggerring emif reset\n"); + hmc_ecc_writel(DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); + + /* if seq2core[3] = 0, we are good */ + ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + + RSTHANDSHAKESTAT), + DDR_HMC_SEQ2CORE_INT_RESP_MASK, + false, 1000, false); + if (ret) { + printf("DDR: failed to get ack from EMIF\n"); + return ret; + } + + ret = emif_clear(); + if (ret) { + printf("DDR: emif_clear() failed\n"); + return ret; + } + + debug("DDR: %s triggered successly\n", __func__); + return 0; +} + +static int poll_hmc_clock_status(void) +{ + return wait_for_bit_le32(&sysmgr_regs->hmc_clk, + SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); +} + +/** + * sdram_mmr_init_full() - Function to initialize SDRAM MMR + * + * Initialize the SDRAM MMR. + */ +int sdram_mmr_init_full(unsigned int unused) +{ + u32 update_value, io48_value, ddrioctl; + u32 i; + int ret; + + /* Enable access to DDR from CPU master */ + clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E), + CCU_ADBASE_DI_MASK); + + /* Enable access to DDR from IO master */ + clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E), + CCU_ADBASE_DI_MASK); + + /* this enables nonsecure access to DDR */ + /* mpuregion0addr_limit */ + FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT); + FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT); + + /* nonmpuregion0addr_limit */ + FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, + FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); + FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT); + + /* Enable mpuregion0enable and nonmpuregion0enable */ + FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE, + FW_MPU_DDR_SCR_EN_SET); + + /* Ensure HMC clock is running */ + if (poll_hmc_clock_status()) { + puts("DDR: Error as HMC clock not running\n"); + return -1; + } + + /* release DDR scheduler from reset */ + socfpga_per_reset(SOCFPGA_RESET(SDR), 0); + + /* Try 3 times to do a calibration */ + for (i = 0; i < 3; i++) { + ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + + DDRCALSTAT), + DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000, + false); + if (!ret) + break; + + emif_reset(); + } + + if (ret) { + puts("DDR: Error as SDRAM calibration failed\n"); + return -1; + } + debug("DDR: Calibration success\n"); + + u32 ctrlcfg0 = hmc_readl(CTRLCFG0); + u32 ctrlcfg1 = hmc_readl(CTRLCFG1); + u32 dramaddrw = hmc_readl(DRAMADDRW); + u32 dramtim0 = hmc_readl(DRAMTIMING0); + u32 caltim0 = hmc_readl(CALTIMING0); + u32 caltim1 = hmc_readl(CALTIMING1); + u32 caltim2 = hmc_readl(CALTIMING2); + u32 caltim3 = hmc_readl(CALTIMING3); + u32 caltim4 = hmc_readl(CALTIMING4); + u32 caltim9 = hmc_readl(CALTIMING9); + + /* + * Configure the DDR IO size [0xFFCFB008] + * niosreserve0: Used to indicate DDR width & + * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit) + * bit[8] = 1 if user-mode OCT is present + * bit[9] = 1 if warm reset compiled into EMIF Cal Code + * bit[10] = 1 if warm reset is on during generation in EMIF Cal + * niosreserve1: IP ADCDS version encoded as 16 bit value + * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, + * 3=EAP, 4-6 are reserved) + * bit[5:3] = Service Pack # (e.g. 1) + * bit[9:6] = Minor Release # + * bit[14:10] = Major Release # + */ + update_value = hmc_readl(NIOSRESERVED0); + hmc_ecc_writel(((update_value & 0xFF) >> 5), DDRIOCTRL); + ddrioctl = hmc_ecc_readl(DDRIOCTRL); + + /* enable HPS interface to HMC */ + hmc_ecc_writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL); + + /* Set the DDR Configuration */ + io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1), + (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)), + DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw), + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw)); + + update_value = match_ddr_conf(io48_value); + if (update_value) + ddr_sch_writel(update_value, DDR_SCH_DDRCONF); + + /* Configure HMC dramaddrw */ + hmc_ecc_writel(hmc_readl(DRAMADDRW), DRAMADDRWIDTH); + + /* + * Configure DDR timing + * RDTOMISS = tRTP + tRP + tRCD - BL/2 + * WRTOMISS = WL + tWR + tRP + tRCD and + * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so... + * First part of equation is in memory clock units so divide by 2 + * for HMC clock units. 1066MHz is close to 1ns so use 15 directly. + * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD + */ + u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0); + + update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) + + CALTIMING4_CFG_PCH_TO_VALID(caltim4) + + CALTIMING0_CFG_ACT_TO_RDWR(caltim0) - + (burst_len >> 2); + io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR + + (burst_len >> 1)) >> 1) - + /* Up to here was in memory cycles so divide by 2 */ + CALTIMING1_CFG_RD_TO_WR(caltim1) + + CALTIMING0_CFG_ACT_TO_RDWR(caltim0) + + CALTIMING4_CFG_PCH_TO_VALID(caltim4)); + + ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT(caltim0) << + DDR_SCH_DDRTIMING_ACTTOACT_OFF) | + (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) | + (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) | + ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) | + (CALTIMING1_CFG_RD_TO_WR(caltim1) << + DDR_SCH_DDRTIMING_RDTOWR_OFF) | + (CALTIMING3_CFG_WR_TO_RD(caltim3) << + DDR_SCH_DDRTIMING_WRTORD_OFF) | + (((ddrioctl == 1) ? 1 : 0) << + DDR_SCH_DDRTIMING_BWRATIO_OFF)), + DDR_SCH_DDRTIMING); + + /* Configure DDR mode [precharge = 0] */ + ddr_sch_writel(((ddrioctl ? 0 : 1) << + DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF), + DDR_SCH_DDRMODE); + + /* Configure the read latency */ + ddr_sch_writel((DRAMTIMING0_CFG_TCL(dramtim0) >> 1) + + DDR_READ_LATENCY_DELAY, + DDR_SCH_READ_LATENCY); + + /* + * Configuring timing values concerning activate commands + * [FAWBANK alway 1 because always 4 bank DDR] + */ + ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) << + DDR_SCH_ACTIVATE_RRD_OFF) | + (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) << + DDR_SCH_ACTIVATE_FAW_OFF) | + (DDR_ACTIVATE_FAWBANK << + DDR_SCH_ACTIVATE_FAWBANK_OFF)), + DDR_SCH_ACTIVATE); + + /* + * Configuring timing values concerning device to device data bus + * ownership change + */ + ddr_sch_writel(((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) << + DDR_SCH_DEVTODEV_BUSRDTORD_OFF) | + (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) << + DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) | + (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) << + DDR_SCH_DEVTODEV_BUSWRTORD_OFF)), + DDR_SCH_DEVTODEV); + + /* assigning the SDRAM size */ + unsigned long long size = sdram_calculate_size(); + /* If the size is invalid, use default Config size */ + if (size <= 0) + gd->ram_size = PHYS_SDRAM_1_SIZE; + else + gd->ram_size = size; + + /* Enable or disable the SDRAM ECC */ + if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) { + setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK)); + setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2, + (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | + DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); + } else { + clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2, + (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | + DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); + } + + debug("DDR: HMC init success\n"); + return 0; +} + +/** + * sdram_calculate_size() - Calculate SDRAM size + * + * Calculate SDRAM device size based on SDRAM controller parameters. + * Size is specified in bytes. + */ +unsigned long sdram_calculate_size(void) +{ + u32 dramaddrw = hmc_readl(DRAMADDRW); + + u32 size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); + + size *= (2 << (hmc_ecc_readl(DDRIOCTRL) & + DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); + + return size; +}

Update dtsi and dts files for resets, phy node and other properties.

Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/dts/socfpga_stratix10.dtsi | 22 +++++++++++++++++----- arch/arm/dts/socfpga_stratix10_socdk.dts | 3 +++ 2 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index db8eb7c..ccd3f32 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -80,6 +80,7 @@ device_type = "soc"; interrupt-parent = <&intc>; ranges = <0 0 0 0xffffffff>; + u-boot,dm-pre-reloc;

clkmgr@ffd1000 { compatible = "altr,clk-mgr"; @@ -92,7 +93,7 @@ interrupts = <0 90 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC0_RESET>; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; reset-names = "stmmaceth"; status = "disabled"; }; @@ -103,7 +104,7 @@ interrupts = <0 91 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC1_RESET>; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; reset-names = "stmmaceth"; status = "disabled"; }; @@ -114,7 +115,7 @@ interrupts = <0 92 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC2_RESET>; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; reset-names = "stmmaceth"; status = "disabled"; }; @@ -136,6 +137,7 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = <0 110 4>; + bank-name = "porta"; }; };

@@ -156,6 +158,7 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = <0 111 4>; + bank-name = "portb"; }; };

@@ -166,6 +169,7 @@ reg = <0xffc02800 0x100>; interrupts = <0 103 4>; resets = <&rst I2C0_RESET>; + reset-names = "i2c"; status = "disabled"; };

@@ -176,6 +180,7 @@ reg = <0xffc02900 0x100>; interrupts = <0 104 4>; resets = <&rst I2C1_RESET>; + reset-names = "i2c"; status = "disabled"; };

@@ -186,6 +191,7 @@ reg = <0xffc02a00 0x100>; interrupts = <0 105 4>; resets = <&rst I2C2_RESET>; + reset-names = "i2c"; status = "disabled"; };

@@ -196,6 +202,7 @@ reg = <0xffc02b00 0x100>; interrupts = <0 106 4>; resets = <&rst I2C3_RESET>; + reset-names = "i2c"; status = "disabled"; };

@@ -206,6 +213,7 @@ reg = <0xffc02c00 0x100>; interrupts = <0 107 4>; resets = <&rst I2C4_RESET>; + reset-names = "i2c"; status = "disabled"; };

@@ -216,8 +224,8 @@ reg = <0xff808000 0x1000>; interrupts = <0 96 4>; fifo-depth = <0x400>; - resets = <&rst SDMMC_RESET>; - reset-names = "reset"; + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; + u-boot,dm-pre-reloc; status = "disabled"; };

@@ -231,6 +239,7 @@ compatible = "altr,rst-mgr"; reg = <0xffd11000 0x1000>; altr,modrst-offset = <0x20>; + u-boot,dm-pre-reloc; };

spi0: spi@ffda4000 { @@ -304,6 +313,8 @@ reg-shift = <2>; reg-io-width = <4>; resets = <&rst UART0_RESET>; + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; status = "disabled"; };

@@ -350,6 +361,7 @@ reg = <0xffd00200 0x100>; interrupts = <0 117 4>; resets = <&rst WATCHDOG0_RESET>; + u-boot,dm-pre-reloc; status = "disabled"; };

diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index d5f43a2..c6ab0ae 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -78,8 +78,11 @@ &mmc { status = "okay"; cap-sd-highspeed; + cap-mmc-highspeed; broken-cd; bus-width = <4>; + drvsel = <3>; + smplsel = <0>; };

&uart0 {

Add build support for Stratix SoC

Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/Kconfig | 9 +- arch/arm/mach-socfpga/Kconfig | 16 ++ configs/socfpga_stratix10_defconfig | 58 ++++++++ include/configs/socfpga_stratix10_socdk.h | 222 +++++++++++++++++++++++++++++ 4 files changed, 301 insertions(+), 4 deletions(-) create mode 100644 configs/socfpga_stratix10_defconfig create mode 100644 include/configs/socfpga_stratix10_socdk.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c9d6e0a..f8d13a5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -733,22 +733,23 @@ config ARCH_SNAPDRAGON

config ARCH_SOCFPGA bool "Altera SOCFPGA family" - select CPU_V7A + select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select ARM64 if TARGET_SOCFPGA_STRATIX10 select SUPPORT_SPL select OF_CONTROL select SPL_OF_CONTROL select DM - select ENABLE_ARM_SOC_BOOT0_HOOK + select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select ARCH_EARLY_INIT_R select ARCH_MISC_INIT - select SYS_THUMB_BUILD + select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 imply CMD_MTDPARTS imply CRC32_VERIFY imply DM_SPI imply DM_SPI_FLASH imply FAT_WRITE - imply HW_WATCHDOG imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10

config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index afc38d5..0caad36 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -15,6 +15,9 @@ config SPL_MMC_SUPPORT config SPL_NAND_SUPPORT default y if SPL_NAND_DENALI

+config SPL_RESET_SUPPORT + default y + config SPL_SERIAL_SUPPORT default y

@@ -49,6 +52,12 @@ config TARGET_SOCFPGA_GEN5 bool select ALTERA_SDRAM

+config TARGET_SOCFPGA_STRATIX10 + bool + select ARMV8_MULTIENTRY + select ARMV8_SPIN_TABLE + select ARMV8_SET_SMPEN + choice prompt "Altera SOCFPGA board select" optional @@ -90,6 +99,10 @@ config TARGET_SOCFPGA_SR1500 bool "SR1500 (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5

+config TARGET_SOCFPGA_STRATIX10_SOCDK + bool "Intel SOCFPGA SoCDK (Stratix 10)" + select TARGET_SOCFPGA_STRATIX10 + config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -121,12 +134,14 @@ config SYS_BOARD default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 + default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA

config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES @@ -152,6 +167,7 @@ config SYS_CONFIG_NAME default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 + default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA

endif diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig new file mode 100644 index 0000000..c54bd01 --- /dev/null +++ b/configs/socfpga_stratix10_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_SPL=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" +CONFIG_BOOTDELAY=5 +CONFIG_SPL_SPI_LOAD=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DM_GPIO=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_USE_TINY_PRINTF=y diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h new file mode 100644 index 0000000..e63fe29 --- /dev/null +++ b/include/configs/socfpga_stratix10_socdk.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> + * + */ + +#ifndef __CONFIG_SOCFGPA_STRATIX10_H__ +#define __CONFIG_SOCFGPA_STRATIX10_H__ + +#include <asm/arch/base_addr_s10.h> +#include <asm/arch/handoff_s10.h> + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_LOADADDR 0x2000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_REMAKE_ELF +/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ +#define CPU_RELEASE_ADDR 0xFFD12210 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */ + +/* + * U-Boot console configurations + */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) + +/* + * U-Boot run time memory configurations + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ + + CONFIG_SYS_INIT_RAM_SIZE \ + - S10_HANDOFF_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + +/* + * U-Boot environment configurations + */ +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + +/* + * QSPI support + */ + #ifdef CONFIG_CADENCE_QSPI +/* Enable it if you want to use dual-stacked mode */ +#undef CONFIG_SF_DUAL_FLASH +/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ + +/* Flash device info */ +#define CONFIG_SF_DEFAULT_SPEED (50000000) +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_3 | SPI_RX_QUAD) +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 + +/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/ +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +#undef CONFIG_ENV_OFFSET +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET 0x710000 +#define CONFIG_ENV_SIZE (4 * 1024) +#define CONFIG_ENV_SECT_SIZE (4 * 1024) +#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" +#endif /* CONFIG_SPL_BUILD */ + +#ifndef __ASSEMBLY__ +unsigned int cm_get_qspi_controller_clk_hz(void); +#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() +#endif + +#endif /* CONFIG_CADENCE_QSPI */ + +/* + * Boot arguments passed to the boot command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will override also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "earlycon" +#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \ + "run mmcboot" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=Image\0" \ + "fdt_addr=8000000\0" \ + "fdtimage=socfpga_stratix10_socdk.dtb\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "booti ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootfile};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@ff8d2000 status okay;" \ + "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \ + " ${qspi_clock}; fi; \0" \ + "scriptaddr=0x02100000\0" \ + "scriptfile=u-boot.scr\0" \ + "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ + "then source ${scriptaddr}; fi\0" + +/* + * Generic Interrupt Controller Definitions + */ +#define CONFIG_GICV2 + +/* + * External memory configurations + */ +#define PHYS_SDRAM_1 0x0 +#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_MEMTEST_START 0 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000 + +/* + * SDRAM controller + */ +#define CONFIG_ALTERA_SDRAM + +/* + * Serial / UART configurations + */ +#define CONFIG_SYS_NS16550_CLK 100000000 +#define CONFIG_SYS_NS16550_MEM32 + +/* + * Timer & watchdog configurations + */ +#define COUNTER_FREQUENCY 400000000 + +/* + * SDMMC configurations + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +#endif +/* + * Flash configurations + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_MII +#endif /* CONFIG_CMD_NET */ + +/* + * L4 Watchdog + */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_HW_WATCHDOG +#define CONFIG_DESIGNWARE_WATCHDOG +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS +#ifndef __ASSEMBLY__ +unsigned int cm_get_l4_sys_free_clk_hz(void); +#define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) +#endif +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000 +#endif + +/* + * SPL memory layout + * + * On chip RAM + * 0xFFE0_0000 ...... Start of OCRAM + * SPL code, rwdata + * empty space + * 0xFFEx_xxxx ...... Top of stack (grows down) + * 0xFFEy_yyyy ...... Global Data + * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN) + * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB) + * 0xFFE3_FFFF ...... End of OCRAM + * + * SDRAM + * 0x0000_0000 ...... Start of SDRAM_1 + * unused / empty space for image loading + * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE) + * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE) + * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) + * + */ +#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \ + - CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ + - CONFIG_SYS_SPL_MALLOC_SIZE) +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x3C00000 + +/* SPL SDMMC boot support */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" + +#endif /* __CONFIG_H */